Chapter 1
Properties of silicon
Markku Tilli and Atte Haapalinna
Okmetic Oy, Vantaa, Finland
1.1 Properties of silicon
Silicon is an abundant element found in the Earth’s crust in
various compounds. Worldwide polysilicon production in
2017 was around 445,000 t with a market size of US$ 6.5
billion. Most of the silicon is used for photovoltaic applica-
tions and the quality is lower than that required in the
semiconductor industry. The semiconductor grade silicon
production usable for semiconductor and microelectrome-
chanical systems (MEMS) applications was around
70,000 t. Today most of the silicon used is either N- or
P-type, doped with antimony, arsenic, phosphorus (N-type),
or boron (P-type); the dopant concentration ranges between
1013 and 1020 dopant atoms/cm3 Si. Intrinsic (no intentional
doping) or very slightly doped high resistivity silicon above
1 kΩ cm is used in small amounts especially in radio fre-
quency (RF) applications. Statistics pertaining to silicon
can be found, for example, in the US Geological Survey
2018 Minerals Yearbook [1,2].
Quartz, or silicon dioxide, is the most common start-
ing raw material for purified silicon for semiconductor
and sensor applications, and the Siemens process is the
most commonly used in semiconductor-grade silicon pro-
duction. In the classical Siemens process, metallurgical-
grade silicon, made first in an electric arc furnace by
reducing quartz with coke, is turned to silicon-hydrogen-
chloride compounds in fluidized bed reactors, and those
compounds are converted to TCS (trichlorosilane or
SiHCl3). TCS is purified by distillation, during which
concentrations of impurity compounds having either a
lower or higher temperature of volatility than TCS
(38.4
C) are reduced. Purified TCS is fed together with
hydrogen into a reactor. In the reactor, TCS decomposes
onto hot silicon filaments forming a pure polysilicon rod.
This rod is then used as a raw material for crystal growth,
either in rod form or in crushed pieces. There are alterna-
tive, newer techniques for purifying silicon; one variant is
similar to the Siemens process but uses silane (SiH4) as a
precursor. In some processes, heated silicon filaments are
Handbook of Silicon Based MEMS Materials and Technologies. DOI: https://doi.org/10.1016/B978-0-12-817786-0.00001-3
Copyright © 2020 Elsevier Inc. All rights reserved.
replaced by silicon particles floating in fluidized bed reac-
tors; these processes yield granular polysilicon.
The result of the purification process is high-purity sil-
icon containing very small amounts of foreign dissolved
atoms. If the single crystals are manufactured by a
Czochralski (CZ) technique, which is most commonly
used (c90% of the crystals), the impurity level increases,
as the growth is made from a quartz crucible having some
impurities. The result is, however, still acceptable.
Typically, most of the contamination of the silicon takes
place during actual device manufacturing. Of impurities,
metals are generally harmful, with rare exceptions, and
their concentration should be as low as possible, typically
much less than 1012 atoms/cm3 Si. Oxygen coming from
the CZ-crystal growth step as an impurity has a dual role:
it has beneficial effects (strengthening of the silicon lat-
tice at high temperatures, gettering effect in semiconduc-
tor use) but also has detrimental effects (donor formation,
defect generation). Nitrogen is a second example of an
impurity, and it can be used in small quantities to enhance
silicon properties, especially in integrated circuit (IC)
applications.
The current high demand for low-cost solar-grade sili-
con encourages the exploitation of alternative sources and
new purification techniques. Currently, these methods are
not able to produce semiconductor-grade silicon pure
enough for MEMS applications, although in solar applica-
tions, these new methods already show promising results.
Woditsch and Koch [3] and Istratov et al. [4] list some of
the available solar silicon purification techniques.
Silicon is an ideal material for various MEMS applica-
tions. Silicon is a semiconductor whose resistivity can be
adjusted by doping from sub-mΩ cm to several kΩ cm; it
is quite inert in a normal environment, hard, transparent
in an infrared regime, and elastic at room temperature
with no plastic deformation and with high fracture
strength. Finally, a protective stable silicon dioxide can
be grown. Silicon crystal has anisotropic properties—
mechanical, chemical, and electrical—which can be
3
4 PART | I Silicon as MEMS Material

TABLE 1.1 Basic parameters of silicon.

Atomic number of Si 14
Atomic mass of Si 28 (92.23%) 29 (4.67%),
30 (3.1%)
Crystal structure Diamond
Lattice constant 0.5431 nm
Si atoms 5 3 10 22
Atoms/cm3
Melting point 1687 K
Specific density 2.329 g/cm3 at
298K
Specific density (liquid) 2.57 g/cm3
Thermal conductivity 149 W/(m K)
26
Coefficient of thermal 2.56 3 10 m21/K (at
expansion 298K)
FIGURE 1.1 The silicon lattice unit cell. Gray silicon atoms in the lat-
Specific heat capacity 19.79 J/(mol K) tice are in the fcc position, and light color atoms are shifted from fcc
0.705 J/(g K) positions toward the [1 1 1] direction by 1/4 unit cell length. fcc, Face
centered cubic.
Young’s modulus 150 GPa
Speed of sound 8433 m/s
Other elements, such as germanium, in periodic
Hardness 7 Mohs table group IV typically have the same structure. The unit
Hardness 850 kg/mm2 cell contains eight atoms, and the atoms follow a face-
(Knoop centered cubic (fcc) Bravais lattice. In each fcc lattice
hardness) point, there are two atoms (motif): one in the lattice point
Volumetric compression 1.02 3 1028 kPa21 and the second displaced by 1/4 of the unit cell length
coefficient toward the [1 1 1] direction. The unit cell length at room
Index of refraction (varies B3.54B3.48 λ 1.1 μm, temperature is 0.5431 nm. Actually, this value is one of
with temperature and λ) RTλ 2 μm, RT the most precisely known among elements, since silicon
crystal can be grown almost perfectly, and the lattice
parameter can be measured precisely according to Martin
et al. [8] with an uncertainty of about 3. . .6 3 1028. Thus
exploited in MEMS component designs. Very large sili- silicon is a good candidate for various references, for
con single crystals in various crystal orientations can be instance, in determining Avogadro’s constant. The density
made with relative ease. These unique combinations of of packing of silicon in this lattice is approximately 34%.
properties have placed silicon as the number 1 material in The packing density is quite loose compared with that of
MEMS manufacturing, although it took almost 30 years fcc lattices (some metals, such as copper, have this struc-
after the invention of the silicon transistor until the poten- ture), whose packing density is 74%, and that of a body-
tial of silicon as a micromechanical material was widely centered cubic structure (for instance, pure iron at room
realized; see Petersen [5]. Table 1.1 lists some basic para- temperature), whose packing density is 68%. The largest
meters of silicon. Some of the parameters depend on dop- empty space in the diamond cubic lattice is the octahedral
ing level as well as temperature and have an effect on hole that can occupy an atom 41% of the size of the host
MEMS device function. atom. Atoms dissolved in the lattice in empty spaces are
A more comprehensive treatise on basic silicon prop- called interstitial atoms; the solubility is called interstitial
erties can be found, for instance, in a handbook edited by solubility. The most typical interstitially dissolved (impu-
Hull [6] or in LandoltBörnstein Group III Condensed rity) atom is oxygen. The maximum oxygen equilibrium
Matter [7]. content at crystal growing in the interstitial state can in
practice be almost up to 20 ppm, which corresponds to up
to 1018 atoms/cm3 Si. Carbon is the second most common
1.1.1 Crystallography of silicon interstitial impurity in silicon; in practice the concentra-
Silicon crystallizes into a diamond cubic crystal structure tion is less than 0.3 ppm in semiconductor-grade material.
(Fig. 1.1) in which the atoms are covalently bonded. Dopant atoms, of which boron, antimony, arsenic, and

phosphorus are commonly used, are in substitutional lat-
tice sites (i.e., replacing silicon atoms), with the exception
of very high doping levels (meaning high concentrations
above 1018 atoms/cm3 Si), at which a small fraction of the
doping elements are electrically inactive and in interstitial
places. The maximum substitutional solubility depends on
the atom size and some other factors; typically, it is less
than 1021 atoms/cm3. Germanium is an exception; it is
completely miscible.
1.1.1.1 Miller index (h k l) system
A convenient way to describe atomic planes and directions
in the crystal lattice is to use Miller indexes. When the lat-
tice has maximum symmetry, or is cubic (as the silicon lat-
tice is)—that is, the lattice axes are orthogonal and the
lattice parameters in all directions x,y,z are identical—the
Miller notation is easy to use and is described later.
Let us consider an orthogonal coordinate system, with
axes x, y, and z, with equal unit vector size, a (Fig. 1.2).
In Fig. 1.2A the plane intercepts the x-axis at a distance a
from the origin and is parallel to the y- and z-axes, or
intercepts them at N. The intercept points in each axis
are thus a,N,N. Miller indexes (h k l) are constructed in
such a way that reciprocals of the intersect points are
taken. Thus in the case of Fig. 1.2A, the Miller indexes
(A) (B)
z z
a y
a/2
a –a
a,0,0
a
x x
(D) (E)
z z
a y
a a
x x
FIGURE 1.2 Miller indexes.
Properties of silicon Chapter | 1 5
(h k l) are a/a, a/N, a/N or (1 0 0). If the plane intercept
points would be 1/2 a,N,N, Miller indexes of that plane
would be (2 0 0). A plane intersecting axis y at a and the
x and z axes at N, respectively, is (0 1 0). If the plane
would intersect axis y at 2 a, and the x and z axes at N,
it is (0 2 1 0) or ð0 l 0Þ in Miller notation, where the
negative sign is above the index number.
A plane (1 1 0) means that plane intersect points are
a,0,0, 0,a,0, and 0,0,N; with (1 1 1), plane intersect
points are, in a similar way, a,0,0, 0,a,0, and 0,0,a.
Correspondingly, the (3 2 1) plane is a plane with inter-
sects at points a/3,0,0, 0,a/2,0, and 0,0,a (Fig. 1.2F). The
convention is that when the plane is marked as (h k l), it
means that the plane is only that. If the marking is
{h k l}, all planes in the same family are included, and in
a cubic lattice it means that {k h l} includes all eight
identical planes (h k l), ðh k lÞ; ðh k lÞ; ðh k lÞ; ðh k lÞ;
ðh k lÞ; ðh k lÞ, and ðh k lÞ. Indexes for directions are
expressed in square brackets as [h k l]. The direction is
perpendicular to the plane. Finally, the family of direc-
tions is expressed as hh k li, and again in cubic
lattice

it

includes

all identical

eight

directions

h h k l i; h k l ;
h k l ; h k l ; h k l ; h k l ; h k l , and hh k li.
Those who would like to have a comprehensive picture
of Miller indexes should consult, for instance, Cullity
and Stock [9].
(C)
z
y y
x
(F)
z
a y y
a/3
a/2
x
6 PART | I Silicon as MEMS Material
1.1.1.2 Stereographic projection
Stereographic projection in crystallography is a helpful
and illustrative tool when investigating atomic planes or
directions and visualizing various orientation-dependent
phenomena. In stereographic projection, crystal directions
are projected onto a plane. Construction of stereographic
projection is made as follows: the crystal lattice is placed
in the center point of the sphere, and crystallographic
directions are projected onto the sphere’s surface. A plane
touching the sphere in point S is drawn. A line connecting
points N and the projection point of the crystallographic
direction on the sphere P* is drawn. This line intersects
the plane in point P. When all crystallographic low index
directions intersecting the sphere in the southern hemi-
sphere are drawn and projected to plane, a stereographic
projection is constructed. This kind of projection preserves
angles (but not areas), so it is possible to measure angles
between crystallographic directions. This can be done man-
ually using a Wulff net. Silicon-based MEMS technology
uses commonly (1 0 0) oriented silicon wafers, that is, the
(1 0 0) crystallographic plane is the surface of the wafer.
Less often, wafers with (1 1 1) or (1 1 0) are used. Some
special applications may use off-oriented wafers, for
instance, where the angle between (1 1 1) plane and water
surface is 45
. Below are stereographic projections of cubic
crystals in (1 0 0), (1 1 1), and (1 1 0) orientations con-
structed in such a way that the wafer orientation mark (a
flat or notch) is facing downward and is of h0 1 li type.
There are useful commercial and free software for the
construction of stereographic projections and calculation
of angles between directions and planes [10]. A compre-
hensive presentation about stereographic projections and
their use can be found, for example, in Cullity and Stock
[9] (Figs. 1.31.7).
1.1.2 Defects in silicon lattice
Although single crystalline silicon is almost perfect to a
degree where it can be used as a standard to define
Avogadro’s constant, in reality, single crystals made
N at higher temperatures the applied stress may generate
S P*
P
FIGURE 1.3 Construction of a stereographic projection.
either with CZ or float zone (FZ) growing methods
contain defects, some of which are characteristic to the par-
ticular growing method. Furthermore, defects are formed
intentionally or unintentionally during the processing of
silicon wafers to final components. These defects can be
classified as (1) point defects (or their agglomerates), (2)
linear defects, (3) planar defects, or (4) volume defects.
Silicon crystals are grown from the melt. Because of
the low diffusivity of the point defects—vacancies and
self-interstitials—many of the defects thermodynamically
at equilibrium concentration at the freezing point are “fro-
zen in” the crystal during the cooling phase. Depending
on the temperature gradient close to the freezing interface
and the time at high temperatures, point defect agglomer-
ates can be formed, too. In IC technology, crystal origi-
nated particles (COPs) (or large vacancy agglomerates)
have a great impact on thin gate oxide integrity, for
instance. Crystals grown with the CZ method also contain
foreign atoms, such as oxygen and carbon. Initially, they
are like point defects or clusters of a few atoms in the
crystal at equilibrium in freezing temperature, and at nor-
mal device processing temperatures, they are supersatu-
rated, eventually generating volume defects (precipitates)
and/or secondary linear or planar defects. A growing
oxide precipitate can nucleate stacking fault or dislocation
loops around the precipitate. Oxygen can also form elec-
trically or optically active defects, donors, which are dis-
cussed later in Section 3.6. Therefore it is essential to
control these defects not only in device manufacturing but
also in the crystal growing step. As the relationship of the
growth in defects in the crystals and defects in finished
devices is complex and depends on the thermal processing
steps, it is beneficial for the crystal grower to know, in as
detailed manner as possible, the device manufacturing
steps to optimize the behavior of the silicon. Reviews of
Falster et al. [11,12] give an overview of intrinsic point
defects in CZ silicon.
Linear defects are called dislocations (see Section 11.2).
In silicon single crystals grown by CZ or FZ methods, or in
wafers cut from these crystals, the dislocation density is
practically zero. During the processing of the silicon wafer
dislocations. The origin of these stresses can be thermal gra-
dients during temperature transients in heat treatment steps
or mismatch stresses caused by thin films or heavily doped
areas in combination with high temperatures. Movement of
dislocations through the crystal lattice causes permanent
deformation. Dislocations in silicon move on {1 1 1} planes
along h1 1 0i directions. This deformation can be seen
visually as slip lines. If the deformation is heavy, the wafer
warpage may increase. In general, dislocations in silicon
wafers have adverse effects on device performance, and in
the worst case, dislocations may even prevent the device
from functioning. Dislocations attract impurities, and the
 Properties of silicon Chapter | 1 7

– – –
– 023 011 032 –
– 012 021
013 –
031
–
– 133 –
123 – 132
– 122 010
001 – –
113 – – – 131
112 – 233 – 121
223 232
– –
103 – 111 – 130
213 – – 231
–– – 323 332 – 031
013 102 – – 120
– 212 322 221 –
203 – 331 230
–– –– 313 – – – 131
012 113 – 312 211 321 110 021
–– 101
– 231
–– –– 213 –– – 311 320 121
302 –
023 –– 112 313 201 – 210
331
132
032
123 –– –– 221
212 ––
223 –– 312 301 310 321 332 232
323
–– –– –– –– –– –– –– –– 100 011
011 133 122 233 111 322 211 311 311 211 322 111 233 122 133
–– –– –– 323
–
–– 232 332–– 321 310 301 312 223
132 221 – 201 212 123
–– –– –– 210
032 121 331 – – 302 313 112 023
–– 320 311 213
231 –
–– 110 – – – 101
021 –– 321 211 312 113 012
131 – – – – 203
230 331 – 322 313
–– – 221 – –
102
031 120 – 332 – 212 – 013
– 231 – 323 213 103
130 111
– –
– 232 223 –
– 121 – 112
233 –
131 113
–– –
010 – 122 –
132 123 001
–
133
–
– 013
031 – –
021 – – 012
032 – 023
011

FIGURE 1.4 Stereographic projection of (1 0 0)-oriented crystal.

result can be that moving dislocations leave precipitate col-
onies behind. Dislocations can also match together two
parts of silicon lattices having slightly different lattice con-
stants. This happens when an epitaxial layer is grown on a
substrate and their doping levels differ substantially (see
Fig. 5.12.). These dislocations are called misfit dislocations,
and normally they are confined in the interface. In MEMS
applications where silicon is etched, areas containing dislo-
cations generally have a nonuniform etch result because of
the stress field around the dislocation core. A further conse-
quence of the presence of dislocations is a reduction of
yield strength at higher temperatures. The yield strength of
zero dislocation silicon is higher than silicon having dislo-
cations in temperatures where plastic deformation can
occur. This means that once slip has occurred, silicon
wafers are more susceptible to additional slip in following
thermal treatments. However, dislocation locking by impu-
rity atoms diffusing to the dislocation core or strained area
increases resistance to additional slip.
Planar defects are called stacking faults. In silicon
stacking, faults are along (1 1 1) atomic planes, and they
are surrounded by partial dislocation. A silicon lattice
may contain an extra atomic place; this stacking fault is
called extrinsic. If an atomic plane is missing, the stack-
ing fault is intrinsic. Most stacking faults in silicon are of
the extrinsic type. Extrinsic stacking faults are formed by
excess silicon interstitials; oxidation-induced stacking
faults or stacking faults around growing oxide precipitates
are typical examples. A large oxygen precipitate may
generate stacking fault(s) to reduce misfit stresses. Wet
oxidation of silicon wafer also may induce stacking faults.
Intrinsic stacking faults can be found, for instance, in epi-
taxial layers. Although the largest stacking faults in
wafers can extend over several hundred micrometers, typ-
ically the diameter is less than 100 μm.
Volume defects in silicon are precipitates. They can
be coherent (the lattice of the precipitate is aligned with
the host silicon lattice), or noncoherent, when there is a
8 PART | I Silicon as MEMS Material

–
– 011
– –
123 132
– – – –
112 123 – 121
032
–
– 122 – – –
– 223 – – 021 – – 231
213 233 132 131
–
– – – 031
– – 111 232 –
313 212 323 – 121
– 131 – –
– – 332 – –
101 322 – – 130 120 230 110
– 221 231 010
312 – –
211 – 331 130
– 321
302 230 120 – –
– – 231
– 311 110 031 131 331
201 131 –
–– 320 231 – –
312 – 021 121 221 321
301 210 331 121 – – –
310 221
321 332 232 132 032 132 232 332
–– –– – – – – –
211 311 100 311 211 322 111 233 122 133 011 133 122 233 111 322 –
211
312 323 223 –
123 023 – –
– 301 212 123 223 323
–– 310 313 112 – – –
321 201 012 112
302 213 113 212 312
–
210 – 101 013 – – –
311 113 213 313
– – 203
320 – 312 – 102
211 313 103
– –
321 – 212 – 001
–
–
110 322 – 213 103 – –
102 203 –
323 – 101
– – – 113
331 221 – – – 112
332 111 223 –
013
– – ––
– – 233 123 – 113
231 232 – 012 ––
122 213
– – –
121 133 023
––
– 112
132 ––
–
011 123

FIGURE 1.5 Stereographic projection of a (1 1 1)-oriented crystal.

mismatch in lattice alignment. Small precipitates are often
coherent, and when they grow, they turn first semicoher-
ent, and then noncoherent. Precipitates are normally com-
pounds of silicon:silicates or silicon dioxide.
CZ-grown silicon contains dissolved oxygen, which is
supersaturated at wafer processing temperatures, unless a
special low oxygen content material is used. Extended
thermal treatments grow oxygen precipitates. Also, there
can be a redistribution of precipitates, in which large pre-
cipitates are grown at the expense of small ones. This
phenomenon is called Ostwald ripening process. At a
given temperature there is a critical size of precipitates;
larger precipitates are grown, provided that there is
enough supersaturation at that temperature, and smaller
precipitates are dissolved. Using this phenomenon, it is
possible to tune both the distribution and the size of the
precipitates, first by designing a proper lower temperature
nucleation step to adjust the size distribution and density
of nuclei, and then, at higher temperatures, growing preci-
pitates which exceed the critical size at that temperature.
At the same time, it is also possible to form a precipitate-
free zone below the wafer surface. The precipitate nucle-
ation process depends especially on the properties and
thermal history of the grown crystal; therefore silicon
wafers from different sources behave differently.
However, if, following thermal cycles, the crystal grower
knows to which subsequent manufacturing steps the sili-
con wafers are exposed, it is also possible to adjust the
crystal growth process and crystal properties in such a
way that desired results are obtained. If wafers are used in
IC manufacturing, the objective normally is to have pre-
cipitation on the bulk; the surface area remains defect
free, to get the maximum effect out of internal gettering.
On the other hand, some MEMS manufacturing processes
yield optimum results only if the bulk of the wafer
remains essentially precipitate free.
COP, a cluster of vacancies, is also a volume defect.
The size and density of this defect depend on the crystal
growth process; the average size can be from tens of
nanometer to less than 200 nm. COP has mostly an effect
 Properties of silicon Chapter | 1 9

–
110 –
331 –
– – 221 –
– – 331 332
– – 221
332 – –
– – 230 – 111
– – 231 231
111 – – –
232 – 232
– – 120 – –
– – – – 121 121 – 223
223 233 – 233
– – 130 –
– – 131 131 – – –
– – 122 – – 122 112
112 132 132
– – – – – –
123 133 133 123
– –
– – – 021– 031 010 031 021 113
113 – 032 032
011 011
– 023
– 023 –
012 – – 131 130 131 132 012
– 133 132 – 133
013 013
– – 121 120 121
123 122 – – 231 – 122 123
233 232 230 231 232 233
– – – – – – – –
001 113 112 223 111 332 221 331 110 331221 332 111 223 112 113 001
– – – 323
– 323 322 321 320 321 322
–
213
212
– – 211 212 213
103 – 211 210 103
– – 313
–
102
313 312
311 310 311 312 102
– 203
203 –
101 – – 101
302 201 – 201 302
–– 301 100 301 –
113 –– – 113
213 –– – 213
313 313
–– – –
–– –– 312 –– – 312 –
112 212 212 112
311 – 311
–– –– 310 – –
–– 323 211 211 323 –
223 – – 223
–– 210 322
322
–– –– –
321 – 321
111 320 –
111
––
332 –– –
221 ––
331 – – 332
110 – 221
331
FIGURE 1.6 Stereographic projection of a (1 1 0)-oriented crystal.

on the gate oxide quality in CMOS devices. Because the

COP originates from the crystal growth process involving
melt, epitaxial layers are free from COPs (Fig. 1.8).
“Defect Engineering” can be used successfully in sili-
con technologies to maximize a device yield; however, it
should be remembered that conventional approaches used
in IC manufacturing are not necessarily successful in
MEMS technology. Reviews by Borghesi et al. [13] on
oxygen precipitation in silicon, Bergholz and Gilles [14]
on defects in general in silicon, and Sinno et al. [15] on
defect engineering in CZ silicon give a good overview of
how defects affect the IC manufacturing.

1.1.3 Mechanical properties of silicon

FIGURE 1.7 Wulff net used in the measurement of angles in stereo-
graphic projection.
Silicon is a hard, brittle material, and at room temperature
under stress silicon single crystal elongates elastically
until fracture appears without significant plastic deforma-
tion. Therefore defects (scratches, dents, mechanical
10 PART | I Silicon as MEMS Material
(E)
(C)
(A)
(F)
(B)
(D)
(G)
FIGURE 1.8 Defects in primitive cubic lattice: (A) vacancy, (B) sub-
stitutional atom, (C) interstitial atom (can be foreign atom or self-inter-
stitial), (D) dislocation (edge), (E) intrinsic stacking fault, (F) extrinsic
stacking fault, and (G) noncoherent precipitate.
damage, etc.) on the surface or periphery of the silicon
wafer can cause premature cracking under stress because
of the notch effect. Silicon wafers having a rough surface
or residual damage left on the wafer surface (cut wafer,
lapped wafer, or ground wafer without stress relief) are
more prone to break compared with polished wafers. The
ideal, “strong” wafer is double-side polished, and the wafer
edge is polished and round, also. Samuels and Roberts [16]
used precracked bar-shaped single-crystal specimens in
four-point bending tests and found a brittleductile transi-
tion temperature of 545
C at ambient pressure. At room
temperature, they measured a fracture stress of 270 MPa.
Under 1.5 GPa confining pressure, the brittleductile tran-
sition temperature can be lowered to 275
C, after Rabier
and Demenet [17]. For a comparison, Vedde and Gravesen
[18] give, for median fracture strength (at 50% probability
level) when using a double-ring bending test method,
1.18 GPa for polished CZ wafer, and 1.011.12 GPa for
FZ wafer (different growth processes), compared with an
as-cut state from 180 to 220 MPa or 270 to 330 MPa in an
as-lapped state. However, these values are here only as indi-
cators, since, in practice testing conditions, the starting
material quality, wafer manufacturing processes, and possi-
ble post-treatments of the wafers have an influence on the
fracture tendency.
At elevated temperatures, silicon starts to show plastic
deformation. Once the upper yield strength (also called
upper yield point) is achieved, dislocations start to gener-
ate, multiply, and move on slip planes, the stress lowers
to the lower yield strength (point), and plastic deforma-
tion proceeds. When the dislocation density is increasing,
dislocations reach each other, slip is prevented, the lattice
hardens, and stress required for further deformation is
increased, until fracture occurs. Silicon single crystals
made with CZ or FZ techniques have similarly shaped
τ
τuy
τly
ε
FIGURE 1.9 Schematics of stressstrain behavior of dislocation-free
silicon single crystal at elevated temperatures. τ uy 5 upper yield strength,
τ ly 5 lower yield strength, ε 5 strain.
–1
1000/T (K )
0.5 1 1.5 2
10,000
1000
τ (MPa) 100
10
1
0.1
FIGURE 1.10 Lower yield strength of silicon versus deformation tem-
perature. Reprinted with permission from Phys. Status Solidi B, r2000
John Wiley.
stressstrain curves, provided that the crystals are ini-
tially dislocation free [19,20] (Fig. 1.9).
The value of lower yield strength varies with the tem-
perature, according to Fig. 1.10 [17]. At 900
C the critical
shear stress on the (1 1 1) plane required to move disloca-
tions is about 8 MPa.
Oxygen-containing CZ silicon has, in practice, a high-
er tolerance against slip compared with oxygen-free FZ
silicon. The difference is that when the deformation stops,
in oxygen-containing CZ, silicon dislocations are locked
rapidly by diffusing oxygen to dislocations, while in
oxygen-free FZ silicon, this locking does not take place
and dislocations can move easily. Once deformed, CZ
material shows again an upper yield point considerably
higher compared with the stress required to move disloca-
tions, while FZ silicon starts to deform at a stress level
required to move dislocations in constant deformation
(Fig. 1.11) [20]. FZ silicon can be “hardened” by adding
oxygen or nitrogen, but, in general, FZ is more prone to
slip, which has to be taken into account when designing
thermal treatment steps.
Oxygen concentration in dislocated silicon crystals has
a significant effect on upper yield strength. Fig. 1.12
shows an upper yield strength dependence on oxygen
 Properties of silicon Chapter | 1 11

4 radial stresses in wafers are highest) are more susceptible

T = 900°C , ε̇~1.1 × 10–4 s–1 to further slip with increasing initial dislocation content.
N0~106 cm–2
Resolved shear stress (107 N/m2)

It should be noted that silicon wafers in the as-received

3 state typically do not have dislocations; exceptions are some
CZ- Si
(O)~ 8 ×1017 cm–3 epi wafer types with thick epitaxial layers. In these epi
wafers, specifications allow some maximum amount of slip.
2 The oxygen-related bulk microdefect density has to be
O-treated FZ-Si
(O)~1017 cm–3 minimized in some MEMS processes; this is done by
minimizing the initial oxygen content in silicon wafers.
1 O-treated FZ-Si The adverse effect is that when such wafers are used,
FZ-Si more attention has to be paid to controlling stresses in
FZ-Si CZ-Si
wafers during thermal processes at temperatures at which
τeff
0
silicon is still plastic.
10 20 30 40 50
Shear strain (%) 1.1.4 Electrical properties
FIGURE 1.11 Actual result of stressstrain behavior of silicon single
crystals having initial dislocation density of 106/cm2 deformed at 900
C.
Silicon is a group IV element in the periodic table and is
Oxygen-free FZ-silicon does not have an upper yield point. FZ with a semiconductor with a bandgap of 1.12 eV, which means
added oxygen, as well as standard CZ-silicon, has an upper yield point. that pure silicon at room temperature is almost an insula-
CZ, Czochralski; FZ, float zone. Reprinted with permission from K. tor. By doping with group III or group V elements the
Sumino, I. Yonenaga, A. Yuasa, Mechanical strength of oxygen doped resistivity of silicon can be varied over a wide range.
float-zone silicon crystals, Jpn. J. Appl. Phys. 19 (1980) L763L766, r
1980, Japan Society of Applied Physics.
1.1.4.1 Introduction—dopants and impurities
in silicon
Semiconductors are solid materials that have electrical
6 N0(cm–2)
conductivities in between those of conductors and those
2× 105
of insulators. The physical reason causing a material to
1× 106
5 behave as a conductor, semiconductor, or insulator lies in
the availability or lack, thereof, of free current carriers in
the material. Semiconductors are characterized by the nar-
4
row bandgap between the valence bands, occupied by
τuy (107N/m2)

3 move freely according to applied electrical fields.
2
1 electrically active impurities can totally alter the electrical
0
0 5
Co
FIGURE 1.12 Upper yield strength versus oxygen content of dislo-
cated CZ-silicon at 800
C and 900
C. Silicon crystal with a higher dislo-
cation content has lower strength (τ is the effective stress on the (1 1 1)
slip plane). CZ, Czochralski. Reprinted with permission from J. Appl.
Phys., r1984, American Institute of Physics.
concentration at 800
C and 900
C, with two different ini-
tial dislocation densities [21]. When the initial dislocation
density increases, the effect of oxygen diminishes and the
upper yield strength falls. Thus slipped wafers in thermal
treatments (and especially in the cooling phase, where
T =800°C
electrons, and the conduction band, in which electrons
Intrinsic (i.e., pure) semiconductors act as insulators at
room temperatures, but their behavior changes dramati-
cally with temperature, and, more to the point, with small
impurities present in the crystal. Very small amounts of
T =900°C
properties of semiconductors such as silicon. This is
because the electrically active impurities either easily
10 donate valence electrons (donors) or accept them, creating
,1017cm–3
holes (acceptors). These electrons or holes are free (i.e.,
not bound to individual atoms). Their movement due to
applied electrical fields carries electrical currents, giving
rise to the term charge carriers used to denote them.
The electrical properties of semiconductor materials
such as single-crystal silicon are thus defined by the
impurity concentrations present in the silicon lattice.
Impurities are introduced into the starting materials during
crystal growth and modified during device processing by
additional doping of the silicon material with electrically
active impurities. In intentional doping of silicon, impu-
rity atoms from group III (acceptors) and group V
(donors) are used. The dopants used in crystal pulling,
12 PART | I Silicon as MEMS Material
and the conductivities reached with specific impurity con-
centrations, are described in more detail in Sections 3.1
and 3.3, Dopants and impurities in silicon crystals.
Manipulation of the electrical properties in the struc-
tures created during MEMS device manufacturing follows
practices established in semiconductor device manufactur-
ing. Techniques used include both very traditional meth-
ods, such as deep diffusions of dopants, which have been
abandoned in mainstream semiconductor processes, and
current standard techniques such as ion implantation and
epitaxial deposition. While semiconductor-grade starting
materials are largely free of other electrically active impu-
rities, the incorporation of unintentional contamination
into silicon during processing can have significant effects
on the electrical properties of the manufactured devices.
Unintentional doping of silicon includes the introduc-
tion of unwanted donors or acceptors to the crystal lattice
from the processing environment. These impurities can be
either group III/V-type atoms misplaced, or other con-
taminants, such as some transition metals.
The generation of electrically active donors also takes
place within the single-crystal CZ silicon itself, without
the introduction of additional impurities. CZ silicon
always includes a few parts per million atoms of intersti-
tial oxygen atoms, originating from the quartz crucible
used to hold the melt during crystal pulling (see also
Chapter 3: Properties of silicon crystals). At certain tem-
peratures, ranging from 400
C to 550
C, these interstitial
atoms create conglomerates of several oxygen atoms
within the lattice. Such siliconoxygen microclusters are
known as thermal donors (TDs), as they donate free elec-
trons to the conduction band, influencing the electrical
properties accordingly [22,23]. The concentration is, how-
ever, usually below 1015 3 cm23 and thus has only very
marginal effects on other than high-resistivity silicon.
These donors are not stable at temperatures above 600
C,
and even for applications requiring high-resistivity sili-
con, their effect can be suppressed by quick cooling down
over the generation temperature range. This method is
called TD anneal, and while it is effective, it does not pre-
vent the generation of new TD if temperatures in the criti-
cal range are used later in the device processing. For
further details, see Section 3.6.
The use of semiconductors is based on the fact that
the charge carrier concentrations are also influenced by
any electric fields that are present. This can take place
intentionally, as, for example, in transistors, but also due
to electric fields generated by surface effects such as
charging. These effects are more pronounced in high-
resistivity silicon, but they bear consideration in general.
In the vast majority of cases the electronics required
for the realization of a MEMS-based sensor consist of the
basic building blocks of semiconductor electronics used
since the birth of the silicon-based semiconductor industry
and described in the basic handbooks of the industry,
such as Sze [24]. In MEMS applications requiring very
high resistivity, in fields such as RF and optical, special
considerations apply. The very high resistivity materials
used are obviously strongly affected by even the smallest
concentrations of unintended charge carriers. These unin-
tended charge carriers can be introduced into the material
by methods such as TD generation (described earlier),
oxidation, and contamination of the surface if the donors/
acceptors are not subsequently evaporated. In very high
resistivity silicon, these effects can be severe, in some
cases even leading to type reversal.
1.1.4.2 Piezoresistive effect in silicon
General piezoresistive effect
The change in the resistance of metal devices due to an
applied mechanical load was first discovered by Lord
Kelvin in 1857. With the large-scale use of single-crystal
silicon for semiconductor circuits, a much stronger piezo-
resistive effect was discovered in silicon [25]. This dis-
covery forms the basis for practically all piezoresistive
MEMS applications.
Strain
When a sample is subjected to physical force, the force
yields a change in length, dL, that follows the well-known
Hooke’s law F 5 kΔL, where k is a material constant.
The stress is defined as the applied force per unit area.
Stress (σ) is thus given by
F kΔL kLΔL kεL L
σ5 5 5 or (1.1)
A A AL A
where εL denotes the differential deformation, ΔL/L,
known as strain. Most solids exhibit elastic behavior for
small stress loads. In elastic deformation the strain is pro-
portional to the applied stress and the material follows
Hooke’s law, which, in the simple case of uniaxial stress,
can be written as
σ 5 YεL (1.2)
where the scalar Y stands for the modulus of elasticity,
also known as Young’s modulus. This material parameter
for crystalline materials such as silicon is not omnidirec-
tional but varies according to crystal planes.
For strains above certain thresholds, Hooke’s law is
no longer valid. This is caused by nonelastic or irrevers-
ible (i.e., plastic) deformation.
The piezoresistive effect is quantified using the gauge
factor G, describing the relationship between the applied
strain and the change in resistivity. The piezoresistive
effect, and thus also the gauge factor of semiconductor
materials, is several magnitudes larger than the geometri-
cal effect observed in metals. The effect is observed in
 Properties of silicon Chapter | 1 13

several semiconductor materials, such as germanium, Because the relative change in resistivity is proportional
polycrystalline silicon, and single-crystal silicon. to strain, it can be written as:
The large piezoresistive effect in silicon is due to the
Δρ
fact that, instead of a stress-dependent change in geome- 5 YπL εL (1.5)
try, the effect is first and foremost due to the stress- ρ
dependent resistivity of the material. The strain applied to For strained anisotropic material the resistivity is thus
the lattice causes the anisotropic band structure to deform, no longer scalar and is described through tensor mathe-
giving rise to an anisotropic change in the mobility of the matics, similar to the mathematics described earlier for
current carriers. stresses in anisotropic material. Thus the dependence of
the current density J on the electric field E is denoted as
Stress in anisotropic materials 2 3 2 32 3
Ex ρxx ρxy ρxz Jx
The elastic behavior of isotropic materials can be defined 4 Ey 5 5 4 ρxy ρyy ρyz 54 Jy 5 (1.6)
with just two elastic constants, commonly used para- Ez ρxz ρzy ρzz Jz
meters being the Young’s modulus Y and Poisson’s ratio
ν, but modified constants known as bulk modulus K and Details of the tensor mathematics explaining the aniso-
shear modulus G are also sometimes used. In the general tropic resistivity are described in, for example, Thomsen
anisotropic case the stress state of the material is defined and Richter [26].
by a matrix known as the stress tensor, a 3 3 3 matrix in In typical applications the MEMS devices are con-
three dimensions. structed in such a way that the current in the piezoresistors
Crystallographic symmetry allows the reduction of is either parallel or perpendicular to the direction of the
stress tensors in silicon to six-vector notation. In static stress. Also, the vast majority of applications are made on
equilibrium the situation is further simplified to just six (1 0 0) silicon wafer substrates, with the substrate oriented
independent variables, and the stress tensor can be written in such a way that the resistors are aligned on the [1 1 0]
as [26]: direction on P-type and the [1 0 0] direction in N-type, as
2 3 depicted in Fig. 1.13. These directions yield the maximum
σxx σxy σxz positive and negative piezo coefficients (i.e., the maximum
σ 5 4 σxy σyy σyz 5 (1.3) relative resistivity change for a given applied force).
σxz σyz σzz For a system in which the coordinates are chosen to
Typically, the geometries used in MEMS applications coincide with the crystallographic axes, the relationship
reduce the situation, as in the case of a piezoresistive between the stress tensor and the anisotropic change in
sensing layer, created on a relatively thick silicon sub- resistivity simplifies due to crystallographic symmetries
strate. For such a layer the vertical (z) stresses can be of silicon and can be defined as:
equated to zero, and the stress is reduced to: 2 3 2 32 3
@ρ11 Π11 Π12 Π12 0 0 0 @σ11
2 3 6 @ρ22 7 6 Π12 Π11 Π12 0 0 7 6 7
σxx σxy 0 6 7 6 0 76 @σ22 7
6 7 6
1 6 @ρ33 7 6 Π12 Π12 Π11 0 0 76 @σ33 7
7 6
σlayer 5 4 σxy σyy 0 5 (1.4) 56
0 7
6 7
ρ 6 @ρ23 7 6 0 0 Π44 0 0 7 6 7
0 0 0 0 76 @σ23 7
4 @ρ 5 4 0 0 0 0 Π44 0 5 4 @σ13 5
13
This expression can be further simplified if we limit @ρ12 0 0 0 0 0 Π44 @σ12
our discussion to stresses parallel, and stresses perpendic- (1.7)
ular, to the direction of current. For practical sensor sys-
tems, this limitation can easily be applied. where Π11, Π12, and Π44 represent three independent
Thus the forces can be denoted as σl (parallel stress) piezo coefficients, listed in Table 1.2.
and σt (perpendicular or transverse stress).
(A) (B) (C)
Strain effect on resistivity
In metals the conduction/valence bands are partially filled
with charge carriers, and small changes in band shape do
not affect most of the carriers. In semiconductors the
shape and dimension of the bandgap have a much larger
effect, and shifts in energy bands due to applied stress FIGURE 1.13 Typical piezoresistor alignments used on MEMS-
standard (1 0 0) silicon wafers, aligned to utilize maximum piezo coeffi-
affect the mobility of charge carriers. The result is resis- cients for rectangular membranes of the type used in pressure sensors.
tivity change due to applied stress and gauge factors up to (A) P-type silicon, dicing along h1 1 0i, (B) P-type silicon, dicing along
two magnitudes larger than those observed in metals. h1 0 0i, (C) N-type silicon, dicing along h1 0 0i.
14 PART | I Silicon as MEMS Material

described by the examples depicted in Fig. 1.13. The

TABLE 1.2 Independent piezo coefficients for choices of resistor direction, dicing direction, and anisotro-
crystalline bulk silicon [25,27]. pic etching are determined by the crystal orientations. In
addition, the specification of the crystallographic location
10211 N-Si P-SiNA P-SiNA P-SiNA
1/Pa ND 5 4 3 1014 2 3 1015 1 3 1018 1 3 1019
of the substrate wafer flat is based on the chosen crystal
[25] [25] [27] [27]
alignment. The primary flat has historically been located at
the h1 1 0i direction, and dicing along and perpendicular to
Π11 2102 16.6
the primary flat is depicted in Fig. 1.13A and C.
Π12 153 21.1
Π44 214 1138 1103 181 Linearity
In comparison to many other physical phenomena the
piezoresistive effect is a fairly linear effect. To be exact
In most applications the change in resistivity is limited the linear equations for piezo coefficients should, how-
to stresses parallel and perpendicular to the resistive path. In ever, be replaced with higher order polynomials. For
such cases the situation is greatly simplified [28]. The tensor resistors aligned on the h1 1 0i crystal axis, for maximum
element becomes a scalar equation and can be written as: piezoresistive effect in P-type silicon, a quadratic correc-
@ρ tion to the transversal piezoresistive coefficient is suffi-
5 πl σl 1 πt σt (1.8) cient for a wide range of doping concentrations and
ρ
applied stresses. The quadratic correction for P-type sili-
where the common notions of longitudinal piezo coeffi- con along the h1 1 0i crystal axis is of the form [28]:
cient πl and transversal piezo coefficient πt are used. As
@ρ  
an example of a common situation, let us consider the 5 πl σl 1 πt σt 1 2 6:6610210 σt 1=pa (1.13)
case of a P-type piezoresistor constructed to utilize the ρ
maximum piezo sensitivity as described in Fig. 1.13A. yielding a quadratic correction of less than 1% for stresses
For such a resistor, which is uniaxially stressed and lying up to 10 Mpa.
in the (1 1 0) direction, the shear strain is zero and the
longitudinal piezo coefficient is simplified to:
Effect of temperature and doping
1
πl 5 ½π11 1 π12 1 π44  (1.9) In addition to the piezoresistive effect the silicon resistors
2 exhibit strong temperature dependence. For piezoresistors
The corresponding transversal piezo coefficient then with low to moderate doping the resistivity changes can
becomes reach one magnitude for every 100
C. Change in offset is
1 caused by leakage currents, which are strongly dependent
πt 5 ½π11 1 π12 2 π44  (1.10) on temperature according to Laermer [29]. While in some
2
cases the temperature dependence can be utilized or
For piezoresistors in the h1 0 0i plane of an N-silicon
ignored, in the vast majority of cases this must be com-
substrate, the maximum piezo coefficient is found along
pensated for. Combined with the effect of doping on the
the (1 0 0) crystal axis, and the piezo coefficients are
piezoresistive effect, the temperature effect can be cor-
reduced to:
rected with the piezoresistance correction factor P(N,T).
πl 5 π11 (1.11) Generally, a higher dopant concentration in silicon
and reduces the temperature effect, whereas the higher the
temperature, the lower is the effect of doping level. Thus
πt 5 π12 (1.12) designing of the resistor requires a trade-off between sen-
It is immediately observed that for both N- and P-type sitivity and temperature stability (Fig. 1.14).
piezoresistors, uniaxially stressed at respective optimum The modern IC technology can provide a mathematical
locations for sensitivity, the longitudinal and transverse solution to the compensation of the piezoresistors, by intro-
piezo coefficients have opposite signs. The advantages ducing signal conditioning of the linearity and temperature
offered by this fact in a Wheatstone bridge have contrib- effect to the sensing setup. This approach provides addi-
uted to the dominance of bridge circuits in piezoresistive tional accuracy and flexibility at the cost of some cost
sensing based on silicon. and complexity. While the approach is commonly used to
The alignment of piezoresistors to be constructed is gov- improve nonidealities in surface micromachined sensors,
erned by the piezoresistive coefficients listed in Table 1.2. the performance of sensing elements manufactured from
Almost universally, the optimal solution is to align the sens- bulk, single-crystal silicon is usually close to ideal when
ing resistors according to maximum piezoresistive effect, as temperature effects are accounted for.

1.6
T = –73 °C
Piezo correction factor P(N,T)
n-Si
1.4
T = –25°C
1.2
1.0 T = 25°C
T = 75°C
0.8 T = 125°C
T = 175°C
0.6
0.4
0.2
1E16 1E17 1E18 1E19
ND1/cm3
FIGURE 1.14 Piezo correction factor P(N,T) in N-Si as a function of
doping level, for various temperatures. Redrawn and modified from Y.
Kanda, Graphical representation of the piezoresistance coefficients in
silicon, IEEE Trans. Electron Devices 29 (1982) 6470 [30].
Basic solutions for correcting for temperature varia-
tions include the use of a reference (i.e., a nonstrained
resistor which is at the same temperature). The difference
of signal between the strained and nonstrained sensors
provides the desired signal due to strain only. The other
basic technique is to utilize a temperature-independent
circuit—in practice, a bridge circuit.
In a Wheatstone bridge circuit application the four
resistors are doped to the silicon and arranged in such a
way on the sensing membrane that they react to strain in
pairs. In addition to having the advantages in sensitivity,
discussed earlier, the bridge circuit can be used to com-
pensate for temperature effects. The standard setup of a
Wheatstone bridge in (1 0 0) silicon substrate consists of
one pair of resistors aligned to give maximum positive
change in resistivity (longitudinally stressed if P-type,
transversely stressed if N-type), while the other pair yields
the maximum negative change (a perpendicular alignment
with respect to the first pair of resistors). This bridge cir-
cuit provides an output signal that is independent of tem-
perature, assuming that the whole membrane is subjected
to equal temperature changes. The circuit output is thus,
to a first-degree approximation, directly proportional to
the change in resistivity due to the applied stress. The
main disadvantage of piezoresistive gauging using bridge
circuits lies in the current requirements in the milliampere
range, which cause limitations in the use of these circuits
in power-sensitive applications.
Example of a piezoresistive sensor design
Pressure sensing has utilized piezoresistive sensing based
on MEMS technology for years and is the first widely
adopted application of the technology. This is due to the
fact that thin micromachined silicon membranes with a
piezoresistor bridge implemented on top of them provide
a rather ideal solution to the common problem of sensing
Properties of silicon Chapter | 1 15
1017
Concentration in cm–3
1016
1015
1014
1013
1E20
1012
0.00 0.50 1.00 1.50 2.00 2.50
Depth in µM
FIGURE 1.15 Basic diffused piezoresistor dopant depth profile. The
wafer surface is to the left, and the piezoresistor is hatched. The transi-
tion zone under the piezoresistor acts as the electrical isolation. The
hatched line (   ) on the left denotes free hole concentration, and
the hatched line (—  —) on the right side of the transition denotes free
electron density, approaching the starting material ND density in the
depth of the wafer. The graph is calculated using IC-simulation software
ICECREM 4.3 for WINDOWSt by Fraunhofer Gesellschaft for
Integrated Systems and Device Technology (IISB), Erlangen, Germany
[31], and the carrier concentrations refer to zero bias.
pressure over a known, rather limited range of pressures,
over long periods of time and countless cycles of pressure
changes, for low cost and no maintenance.
A very basic sensing setup is as follows:
Starting point:
Silicon substrate, N-type, (1 0 0) orientation, device
dicing along h1 1 0i direction.
Membrane defined by etching, using an alkali etchant
from the backside of the wafer. The long etching is
carried out in concentrated KOH or TMAH, requiring
a thick protective layer of oxide, or nitride. The tradi-
tional bulk micromachining has utilized backside pat-
terning for these cavity-etching processes.
Cavity sealed through wafer bonding. The sealing
options range from glues and glass frits to fusion
bonding of silicon wafers.
Piezoresistors are boron implanted on top of the wafer,
at the edges of the membrane, where the stress max-
ims are located when the cavity pressure differs from
the outside pressure. Boron implantation of the ohmic
contacts can usually also be performed at this stage.
The basic device is finished with one or two layers of
metals.
The dopant profile of a simple implanted and diffused
piezoresistor of the type described is illustrated in
Fig. 1.15. The denuded zone responsible for the elec-
trical isolation is shown without bias; with reverse
bias, it can be extended to meet the requirements.
16 PART | I Silicon as MEMS Material
FIGURE 1.16 Basic MEMS-based sensor application using piezoresistors in h1 0 0i silicon. (A) Side view (cross section along the h1 1 0i plane).
(B) Top view, with the piezoresistors located in a Wheatstone bridge, along the (1 1 0) direction on the top of the silicon membrane.
The basic device outlined earlier follows the geometry
outlined in Fig. 1.16. This device has the piezoresis-
tors located at the stress maximums of the rectangular
membrane and along the crystal axis yielding greatest
change in resistivity for a given stress. Also, the shear
stresses of the membrane are minimized, theoretically
to zero, at the locations of the resistors.
Surface effects
In many cases the carrier concentration depth profile of
the piezoresistor can be very important. Especially in
accelerometers, the piezoresistive MEMS-sensor is often
loaded so as to cause compressive strain on one side of
the membrane and tensile strain on the other. In such a
case the effective piezo coefficient, and thus the sensitiv-
ity, is very strongly influenced by the ratio of carrier con-
centrations between the membrane surfaces. Also, those
piezoresistors whose stress is purely compressive or ten-
sile are affected by the vertical carrier profiles, as the
greatest strains are located at the very surfaces of the
membrane. On the other hand, the carrier concentrations
tend to change more rapidly the closer they are to the sur-
face. Because the carrier concentrations near the device
surfaces can also be affected by charging of the dielectric
layers used to isolate and seal the micromachined struc-
tures, a careful consideration of the design principles used
in analog transistor design is necessary to ensure the reli-
able operation of the piezoresistive element.
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