"International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and

Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

MATLAB MODELED FOR REAL TIME PROCESSING OF PARTIAL

DISCHARGE DETECTION USING FPGA TECHNOLOGY WITH GIGA
HERTZ DATA ACQUISITION
Emilliano, Chandan Kumar Chakrabarty, Ahmad Basri, Agileswari K. Ramasamy, Sanjay Devkumar,
Goh Chin Hock, Muhammad Hadi Badjian
Department of Electronic and Communication Engineering, College of Engineering (COE)
Universiti Tenaga Nasional
Km.7, Jln.Kajang-Puchong,43009, Selangor Darul Ehsan, Malaysia
emilliano@uniten.edu.my, Chandan@uniten.edu.my

Abstract-This paper is purely a model to determine the
method to advance Partial Discharge (PD) detection. The
research shall involve matlab and Verilog High
Development Language (VHDL) programming to
evaluate the use of Field Programming Gate Array
(FPGA) for the detection and counting of partial
discharge signals.
Keyword- Partial Discharge Detection, Magnitude Field,
FPGA Technology, Peak Detector, Real Time
Processing, Underground Cable, Portable Detector,
VHDL Programming.
I. INTRODUCTION
Fig. 1 Comparison between existing system
A Partial Discharge (PD) is a flow of electrons and
ions which occurs in a gas over a small volume of
the total insulation system. This short duration
series of events emit acoustic, optical, electrical
and electromagnetic energy. PDs can be detected
by measuring any of this radiation energy. Fig.1
shows the typical method for detecting and
monitoring PD.
present the system that is required for PD detection
is quite extensive as many high cost equipment are
used to monitor real time PD events.
As for the sake of comparison, the brand VLF-0.1
Hz system, needs outage, cable shielded sensor,
and its effective range is 4 km for PD detection and
2 km for PD location. This system costs
RM600,000. The brand OWTS-200 Hz system,
also needs outage, cable shielded sensor, and its
effective range is 4 km for PD detection and 2 km
for PD location and this system costs RM700,000.
The typical 50Hz On-line system, does not need
outage, the sensor is clamped on cable earth, and its
effective range is 5 km for PD detection and 2.5 km
for PD location. However this system costs
RM220,000 for sensor and RM180,000 for the
scope. The Magnetic Probe [1] system does not
need outage; the sensor is a magnetic probe, and its
effective range is unlimited for PD detection. This
system detects from above the ground as shown in
Fig. 2 and costs RM2.40 for the sensor and less
than RM50,000 for the proposed processor as will
be designed in this project. The functional approach
of the processor will be dealth in this paper.

The work in this paper primarily involve modeling,

which comprises of a matlab simulink approach
whereby partial discharge signals will be processed
and counted using peak detector and FPGA
technology. In the next stage ,this method will be
implemented on a lab simulation scale for testing
and validation. With this method of PD detection,
real PD signals can be detected and displayed for Fig.2 System PD Detection

readout easily, without the need of oscilloscope and

other associated costly measuring equipment. At The physics of PD generation is very extensive and
is not dealt in this work.

1
 "International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and
Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

FPGA
VIRTEX 5
Band Pass ADC
Gaussian Filter 3GSPS
Pulse LNA WITH FPGA

DISPLAY
Peak
Detector
LCD

Fig. 3 Block Diagram Hardware Setup of Partial Discharge Detector

 i 2 and  i 3
In short a PD gives rise to voltage and current where voff stands for the offset voltage, AV is the
pulses with time durations in the range of a few voltage gain, and are the second and
nanosecond (ns), travelling at velocities of
third order intercept point[4].
electromagnetic waves. Due to the high
sensitivities of magnetic probes, the shape of the The model of the LNA design is described
pulse is preserved with very high integrity. [2] comprehensively in ref [5]. It should be noted that
the input parameters plus the power consumption
II. DESIGN BLOCK OF THE PD DETECTION used for the circuit dimensioning are the same as in
equation (1).
Fig. 3 shows the functional approach of the
processing layout to count the PD signals. The
shape of the PD signal that will be fed into the
modeled system is a Gaussian pulse having a pulse
width of 1-10nsec. Each of the blocks in the figure
will be describe as follows:

A. Block LNA (Low Noise Amplifier):

The function of this block is to amplify small

signals [3] that are fed into it. In reality the actual
signals levels of the PD are extremely low about -
70dBm for measurement conducted at several ten’s
of meters away from the PD source. Hence the
need of the LNA in the model is very critical for
Fig. 4 Simulation in SIMULINK MATLAB Block (LNA) -Low
the accuracy of the detection. Noise Amplifier System

There are two kinds of amplifiers included in the
toolbox of matlab and they are LNA (Low Noise
Amplifiers) and PGA (Programmable Gain
Amplifiers). The non-linear function is modeled by
It is noted that the model in equation (1) can be
easily implemented by using simulink elementary
library blocks as shown in Fig. 4. However, this
implementation causes the matlab interpreter to be
called at each time step, drastically slowing down

 4 vin2 
the following equation: the simulation time.

v0  voff  AV vin 1   
vin
  i 2 3 i3 2 

(1) This problem is aggravated for more complex
2
circuit. In order to overcome this problem, the
nonlinear characteristic has been codified using C-
coded S-functions.[6]

2
"International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and
Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

2 5
Input Signal Output PD Detection
PD Source Threshold Logic 1

cheby2
<=
In1 Out1
Peak Detector Convert 5V
Gaussian Pulse
PD Source LNA (Low Noise Amplifier) BPF
Block System Band Pass Filter

Output Signal Logic 0

Output Signal
LNA Block BPF Block

In1 Out1 0

Display PD Detector
Pulse Counter
PD Detection in 1 micro second

Fig 5. Simulation Model of PD Detection Block with LNA Block, BPF Block (Chebyshev II Method), Peak Detector and
Impulse Counter using Matlab Simulink .

For this purpose, simulink provides different S- In this simulation, BPF block has an upper
function templates which can accommodate the C- bandedge frequency of 1 GHz and lower
coded computation model of different systems.[7] bandedge frequency of 125 MHz. stopband
Detail of simulation model of PD detection with attenuation is 60 dB in elliptic method, and 40 dB
LNA block, BPF block, Peak detector block, and in Chebyshev II method.
Impulse counter block is shown in Fig.5.
C. The Peak Detector / Square Law Detector:
B. Block BPF (Band Pass Filter):
The function of this peak detector is to detect peak
The function of this BPF is to filter out noise and signals from BPF. In this simulation the peak
unwanted frequencies from LNA, because when detector is designed to have a 2 V threshold
PD signal has been amplified by LNA, the noise is voltage. It means that if the input signal is more
also amplified.[8]. Simulation model of BPF Block than 2 V, the output of the peak detector is logic 1
is shown in Fig.6. or 5 V and if input signal is less than 2 V, the
output peak detector is logic 0 or 0 V. Detail of
simulation model of Peak detector is shown in
Input Signal
PD Source
Fig.7.
cheby2

In1 Out1 2
Input Signal
Gaussian Impulse Output PD Detection Threshold
LNA (Low Noise Amplifier) Analog PD Source
Block System Filter Design

ellip
Fig. 6 Band Pass Filter (BPF) Block with Chebyshev II method <=
In1 Out1
Peak Detector Output PD Detection
Gaussian Impulse
There are five methods for designing BPF in LNA (Low Noise Amplifier) BPF
matlab simulink that are Butterworth, Chebyshev I, Block System Band Pass Filter

Chebyshev II, Elliptic, and Bessels. The methods of

choice for the simulation are Butterworth, Output Signal
Output Signal
BPF Block
Chebyshev II and Elliptic function filters as they LNA Block

are quite commonly used in high frequency circuits Fig. 7 Peak Detector Block with 2 V Threshold
due to their easy in implementation.

3
"International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and
Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

D. The Analogue to Digital Converter (ADC) IV. TEST SIMULATION OF PD DETECTION

and Pulse Counter from FPGA :
A. Test of Low Noise Amplifier (LNA) Block
The function of ADC is to convert analog signals to
digital signals by sampling time, and digitize signal Input Signal
PD Source

[9]. FPGA with ADC is used as the real board

integrates these two components. In1 Out1

Gaussian Impulse Output PD Detection

The specifications for the actual FPGA board are LNA (Low Noise Amplifier)
Block System

shown in Table 1.[10] Fig.9 Design LNA Block with Gaussian Signal

TABLE I Fig. 9 shows the block diagram of the LNA. The

Spec. of FPGA Virtex 4 with ADC 3GSPS input of the LNA is a Gaussian signal. The signal is
Resolution 8 Bits shown in Fig. 10. And the expected output from the
Max Conversion Rate 3 Gsps (min) LNA with voltage gain of 2.5 is shown in Fig. 11.
Code Error Rate 10 -18 (typ) The signal is shown to be preserved quite well even
ENOB @ 748 MHz Input 7.1 Bits (typ) after being sent into the LNA, however the
SNR @ 748 MHz 44.9 dB (typ) amplitude is too low for it to be sent to the FPGA.
Full Power Bandwidth 3 GHz (typ) Hence the voltage gain is increased to 500. The
output is shown in Fig. 12. The signal integrity is
These real specifications are used as a reference to shown to be maintained and the output voltage
the model FPGA in this work. The purpose of the level has increased to 4 V. At this level, it is now
FPGA and the ADC converter is for counting the sufficient to be processed by the digital processor
amount of PD signals from ADC signal in the of the FPGA.
-3
Data INPUT
FPGA and then perform the computation of the real 8
x 10

time data using intelligence algorithm in VHDL

6
Programming. The model result from the
computation is displayed in the LCD of the FPGA 4

block. The data from ADC of FPGA block is 2

A/mm

transfered to the FPGA for further processes and to 0

show the graphed data in LCD graph color. Detail
-2
of simulation model of Impulse counter block is
shown in Fig.8. -4

0 2 4 6 8 10 12 14 16 18 20
Time (ns) -9
x 10

Fig. 10 Input Data of LNA Block from PD Signal

Input Clock -3
Data INPUT
x 10

1 Clk Cnt In1 Out1 1

5
In1 Up Out1
Rst Hit Latch
0
Counter

-5
0 0.5 1 1.5 2 2.5 3 3.5 4
-8
NOT x 10
Data OUTPUT
Pulse Reference in Logical Input Reference
1 micro second Operator
0.01
Fig. 8 Impulse COUNTER Block in PD Detection using
SIMULINK MATLAB 0

-0.01
In this simulation, impulse counter is designed to 0 0.5 1 1.5 2 2.5 3 3.5 4
-8
x 10
count the amount of pulses each 1µs because the
Fig. 11 Compare Input and Ouput Data of LNA Block
pulse to be measured is in the order of With AV=2.5
nanoseconds. This problem is due to the matlab
interpreter is called at each time step and hence
will drastically slow down the simulation time.

4
"International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and
Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

Data OUTPUT -3
Data INPUT
x 10
4

3
5

A/mm
0
2

-5
1
A/mm

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Time (ns) -8
x 10
0 Data OUTPUT

-1 2

A/mm
-2
0

0 2 4 6 8 10 12 14 16 18
Time (ns) -9 -2
x 10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Fig.12 Ouput Data of LNA Block Time (ns)
x 10
-8

With AV=500 Fig.14 Input PD Source and Output Data of BPF Block
With Butterworth methode
B. Test of Band Pass Filter (BPF) Block

B.1. Chebyshev II Method B.3. Elliptic Method

The similar traces as in the Butterworth filter is
seen in Fig. 15 in this filtering method and hence it
The output from the LNA with voltage gain of
is not suitable to be apart of the counting circuit.
500 is now fed into the BPF using Chebyshev
II method. Fig. 13 shows the signals output x 10
-3
Data INPUT

from the filter. It is shown that the signal has

5
narrowed down within the passband. This is
A/mm

necessary for the counting circuit to resolve the 0

pulses and in the event perform more accurate -5

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
counting. Time (ns)
x 10
-8

Data OUTPUT

2
-3
x 10 Data INPUT
A/mm

10
0

5
A/mm

-2
0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (ns) -8
x 10
-5
0 1 2 3 4 5 6 Fig.15 Input PD Source and Output Data of BPF Block
Time (ns) -8
x 10 With Elliptic methode
Data OUTPUT
4

2
C. Test of Peak Detector Block Simulator
A/mm

Data OUTPUT BPF (Band Pass Filter) methode Eliptics

0 2.5

2
-2
1.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Time (ns) -8
1
x 10
A/mm

0.5
Fig.13 Input PD Source and Output Data of BPF Block
0
With Chebyshev II methode
-0.5

-1

-1.5
0 0.5 1 1.5 2 2.5 3
B.2. Butterworth Method Time (ns)
x 10
-8

Data OUTPUT Partial Discharge Detector

5

4.5

When the Butterworth filter is used instead, its is 4

3.5
shown in Fig. 14 that the stopband frequency is 3
Volt Output

accentuated and the pulse is now distorted to the 2.5

extent that two pulses are seen for one pulse in the 1.5

input and these can contribute to significant errors 0.5

0
in the counting circuit. 0 0.5 1 1.5 2
Time (ns)
2.5 3 3.5 4
-8
x 10

Fig. 16 Input Data and Output Data of PEAK Detector Block

In 2 V Threshold

5
"International Conference on Electronics and Electrical Engineering" World Congress Science Engineering and
Technology (WCSET), in Penang, Malaysia, 25-27 February 2009.

The output of the BPF is fed into the peak detector [2] A. Morgado, V.J. Rivas, R. del Rio, R. Castro-Lopez,
block. Fig. 16 shows the output from the peak F. Fernandez and J.M de la Rosa, ”Behavioral
detector. The amplitude is large enough to be fed to Modeling, Simulation and Synthesis of Multi-
standard Wireless Receivers in
the FPGA block. The number of pulses is now
MATLAB/SIMULINK” VLSI Journal 2008, Vol.41.
accurately reflected in the output of the peak
detector as clear logic signals are produced [3] Bill Schwartz, Michael Carfore, and Dr. Robert Qiu,
“Ultra Wideband Transmitter & Receiver Design,” in
D. Test of Impulse Counter Block Simulator The REU Program of Tennessee Technological
University, July 27, 2005.
Data Output :
[4] Benjamin Nicolle, Mourad Zarour, William Tatinian,
Gilles Jacquemod, “System Design Oriented Low
In this simulation, the counter is set to 100 impulse Noise Amplifier Modeling” in IEEE 2007
per 1µs. Fig. 17 shows the counter will reset each
[5] S. Braun, F. Krug, and P. Russer, “A novel automatic
1µs, and the data output will be hold by a latch for digital quasi-peak 60detector for a time domain
display purpose. The data will be updated to measurement system,” in 2004 IEEE
display each 1µs in simulink. For constant impulse InternationalSymposium On Electromagnetic
Compatibility Digest, August 9–14, Santa Clara,
signal rate, there will be 108 Impulse in 1 s. USA, 2004.

[6] CISPR16-1, Specification for radio disturbance and

Data INPUT COUNTER immunity measuring apparatus and methods Part 1:
5 Volt (logic 1)

4 Radio disturbance and immunity measuring

2 apparatus. International Electrotechnical ommission,
0 1999.
0 2 4 6 8 10 12 14 16 18 20
Time (ns) -7
x 10
Data RESET [7] L. Cohen, “Time-Frequency Distributions - A
5 Volt (logic 1)

1
Review,” in Proceeding of the IEEE, vol. 77, no. 7,
0.5 pp. 941–981, 1989.[4] A. V. Oppenheim and R. W.
0 Schafer, Discrete–Time Signal Processing.ISBN 0-
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns) -6
13-214107-8, Prentice-Hall, 1999.
x 10
Data Latch
5 Volt (logic 1)

1
[8] M. S. Chong, “Partial Discharge Mapping of
0.5 Medium Voltage Cables – TNB’s Experience”,
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
CIRED 2001, 18-21 June 2001, Conference
Time (ns) -6
x 10 Publication No. 482 © IEEE 2001

[9] F.H Kreuger, “Discharge Detection in High Voltage

In1 Out1 100 Equipment”, A Heywood Book, Temple Press Book
Ltd, London 1964.
Display PD Detector
Pulse Counter
PD Detection in 1 micro second [10] Datasheet National Semiconductor ADC08B3000,
“ADC08B3000 - 8-Bit, 3 GSPS, High Performance,
Fig. 17 Input and Output Data Impulse Counter Block
Simulation Low Power A/D Converter with 4K Buffer from the
PowerWise® Family,” in Copyright 2008© National
Semiconductor Corporation, Information as of 4-Jan-
V. CONCLUSSION 2009.
A set of matlab simulink blocks has been proposed
for modeling, simulation and synthesis of PD
detection. The simulation scheme is shown to be
operational in FPGA technology. Hence bandpass
filter (BPF), peak detector and impulse counter
which are shown to be essential components and
can be easily realized by FPGA . The validation
and verification of the model will be conducted in
the next phase of this work.

VII. REFERENCE

[1] Ahmad Basri bin Abdul Ghani, “Detection of Partial

Discharge in Underground Cable Using Magnetic
Probe,” in 2008 Doctoral Thesis in University
Tenaga Nasional, Malaysia, 2008.