Professional Documents
Culture Documents
%/&PSGO(MEKVEQ
D
AMD CLOCK GENERATOR D
Up to 2GB DDRII
PAGE 9 10
LED&SW&TOUCHPAD
LVDS & INV PAGE 5 6 7 8 PAGE 50
H.T 800 MHz
PAGE 22
1600MT/s
MINI-PCIE FAN + SENSOR
CRT PCIE *1
PAGE 21
TV Card
PAGE 23
ATI PCIE *16 ATI PCIE *1
PAGE 40
TV OUT PCIE *1 DISCHARGE CIRCUIT
PAGE 23
M76-M RS690M PCIE *1 PAGE 52
JMB360
DVI e-SATA
PAGE 11 12 13 14
PAGE 49 SYSTEM PWR
PAGE 24
ALINK
C
4LANE MINI PCIE
C
CIR
WLAN BAT & CHARGER
PAGE 37
PAGE 26
SUPER I/O
SIR
ITEIT8712F_IX LPC
PAGE 37
33MHz USB NEW CARD
PAGE 37 ATI USB PAGE 27
Azalia
SB600
EC IT8511E PCI 33MHz
KEYPAD
MATRIX CardBus 1394
PAGE 29 PAGE 17 18 19 20 R5C833 PAGE 39
PAGE 28 29
PAGE 38 MMC/SD
INSTANT KEY USB 4 in 1
Memory
CARD READER
PAGE 50 Stick/MS PRO
PAGE 39
USB 2.0 XD
B LED B
CON X5
PAGE 50 MDC Conn SATA HDD PAGE 36
ISA (RJ11) PCI LAN
ROM (8MB) PAGE 34 PAGE 35
PAGE 29
PAGE 25
Bluetooth
Azalia Codec USB
AMPLIFIER HDD
ALC 660 PAGE 36
PAGE 31
PAGE 30 PAGE 35
Camera
SPEAKER or ODD
MIC AND LINE IN DSP SPDIF USB
PHONE JACK
PAGE 35 PAGE 22
PAGE 31 PAGE 32 PAGE 33 PAGE 31
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Block Diagram 20
Date: 14 2007 Sheet 1 of 69
5 4 3 2 1
5 4 3 2 1
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Table of Contents 20
Date: 14 2007 Sheet 2 of 69
5 4 3 2 1
5 4 3 2 1
+1.2VS
15
+1.5VS LDT_RESET#
PM_SUSC# SUSB_EC1#
+1.8VS
+2.5VS
+3VS
SB600
+5VS
+12VS
7 RS690M
8 (South Bridge) HT_CPU_STOP#
B CPU_VRON From B
EC
11 (North Bridge)
+VCORE
(MAX8760ETL)
9 PWRGD
CPUPWR_GD
To EC
13
A_RST#
HTVDD_EN
+1.2VS_HT
14
10 PCIRST# PCI Device
VLDT_PWRGD (RICOH R5C833)
A A
SYS PWRGD
11 13
PWRGD Logic PWRGD
PCIE, LPC Device Title : A7K
A_RST#
(Minicard, ASUSTECH CO LTD Engineer: Endy Zhang
Newcard, PCIE LAN, Size Project Name Rev
LPC devices) Custom Power Budget 20
Date: 14 2007 Sheet 3 of 69
5 4 3 2 1
5 4 3 2 1
D D
HTREFCLK
66MHZ
ATI NB - RS690M PCI_CLK_CB
24.576MHZ XTAL INPUT
R5C833
NB_OSC 33MHZ
14.318MHZ
TOP SO-DIMM BOT SO-DIMM
PCI_CLK_LAN
33MHZ PCI LAN
HTTCLK0 FS2
NBGFX_CLK_P
SRCLKT1
NBGFX_CLK_N ATI SB
100MHZ LPC_CLK_EC 32.768KHZ XTAL INPUT
EC IT8511E
NBLINK_CLKP SB600 33MHZ TPAD_CLK
NBLINK_CLKN TOUCHPAD
SRCLKT6
100MHZ
CPU_CLK_H
TURION S1g1 CPU CPU_CLK_L GFX_CLK_P LPC_CLK_DEBUG
GFX_CLK_N
200MHZ SRCLKT4 M76-M 33MHZ NEWCARD FOR DEBUG
LGA638 PACKAGE 100MHZ
(CLKREQ#B)
C C
GPP0_CLK_P LPC_CLK_SIO
GPP0_CLK_N
SRCLKT2 MINI PCIE TV 33MHZ SUPER IO
100MHZ
SIO_CLK IT8712F
48MHZ
GPP3_CLK_P
GPP3_CLK_N
SRCLKT7 E-SATA
100MHZ
CODEC_BCLK
ALC660
GPP1_CLK_P
SRCLKT3 GPP1_CLK_N
(CLKREQ#A) 100MHZ MINI PCI-E WLAN
GPP2_CLK_P MDC_BCLK
GPP2_CLK_N
SRCLKT0 MDC
100MHZ NEW CARD
(CLKREQ#C)
SBLINK_CLKP
SBLINK_CLKN
SRCLKT5
100MHZ
B B
FS0 CLK_14M_SB
14.318MHZ
48MHZ_0 CLK_48M_USB
48MHZ
SIO_CLK
48MHZ_1
48MHZ
14.31818MHz
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Clock Distribution 20
Date: 14 2007 Sheet 4 of 69
5 4 3 2 1
5 4 3 2 1
D D
U500A
HT_CPU_TX_CLK_H1 J5 Y4 HT_CPU_RX_CLK_H1
11 HT_CPU_TX_CLK_H1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CPU_RX_CLK_H1 11
HT_CPU_TX_CLK_L1 K5 Y3 HT_CPU_RX_CLK_L1
11 HT_CPU_TX_CLK_L1 L0_CLKIN_L1 L0_CLKOUT_L1 HT_CPU_RX_CLK_L1 11
+1 2VS_HT HT_CPU_TX_CLK_H0 J3 Y1 HT_CPU_RX_CLK_H0
11 HT_CPU_TX_CLK_H0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CPU_RX_CLK_H0 11
HT_CPU_TX_CLK_L0 J2 W1 HT_CPU_RX_CLK_L0
11 HT_CPU_TX_CLK_L0 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_RX_CLK_L0 11
R500 1 2 49 9Ohm HT_CPU_TX_CTL_H1 P3 T5
R501 1 HT_CPU_TX_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1
2 49 9Ohm P4
L0_CTLIN_L1 L0_CTLOUT_L1
R5
HT_CPU_TX_CTL_H0 N1 R2 HT_CPU_RX_CTL_H0
11 HT_CPU_TX_CTL_H0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CPU_RX_CTL_H0 11
HT_CPU_TX_CTL_L0 P1 R3 HT_CPU_RX_CTL_L0
11 HT_CPU_TX_CTL_L0 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CPU_RX_CTL_L0 11
HT_CPU_TX_CAD_H15 N5 T4 HT_CPU_RX_CAD_H15
HT_CPU_TX_CAD_L15 L0_CAD N_H15 L0_CADOUT_H15 HT_CPU_RX_CAD_L15
LAYOUT: PLACE NEAR CPU P5
L0_CAD N_L15 L0_CADOUT_L15
T3
HT_CPU_TX_CAD_H14 M3 V5 HT_CPU_RX_CAD_H14
STUFF WHEN CONFIGURED AS HT_CPU_TX_CAD_L14 M4
L0_CAD N_H14 L0_CADOUT_H14
U5 HT_CPU_RX_CAD_L14
16-BIT LINK HT_CPU_TX_CAD_H13 L0_CAD N_L14 L0_CADOUT_L14 HT_CPU_RX_CAD_H13
L5 V4 HT_CPU_RX_CAD_L[0 15] 11
HT_CPU_TX_CAD_L13 L0_CAD N_H13 L0_CADOUT_H13 HT_CPU_RX_CAD_L13
M5 V3
HT_CPU_TX_CAD_H12 L0_CAD N_L13 L0_CADOUT_L13 HT_CPU_RX_CAD_H12
K3 Y5
HT_CPU_TX_CAD_L12 L0_CAD N_H12 L0_CADOUT_H12 HT_CPU_RX_CAD_L12
K4 W5 HT_CPU_RX_CAD_H[0 15] 11
HT_CPU_TX_CAD_H11 L0_CAD N_L12 L0_CADOUT_L12 HT_CPU_RX_CAD_H11
H3 AB5
HT_CPU_TX_CAD_L11 L0_CAD N_H11 L0_CADOUT_H11 HT_CPU_RX_CAD_L11
H4 AA5
HT_CPU_TX_CAD_H10 L0_CAD N_L11 L0_CADOUT_L11 HT_CPU_RX_CAD_H10
G5 AB4
HT_CPU_TX_CAD_L10 L0_CAD N_H10 L0_CADOUT_H10 HT_CPU_RX_CAD_L10
H5 AB3
HT_CPU_TX_CAD_H9 L0_CAD N_L10 L0_CADOUT_L10 HT_CPU_RX_CAD_H9
11 HT_CPU_TX_CAD_L[0 15] F3 AD5
HT_CPU_TX_CAD_L9 L0_CAD N_H9 L0_CADOUT_H9 HT_CPU_RX_CAD_L9
F4 AC5
HT_CPU_TX_CAD_H8 L0_CAD N_L9 L0_CADOUT_L9 HT_CPU_RX_CAD_H8
E5 AD4
C HT_CPU_TX_CAD_L8 L0_CAD N_H8 L0_CADOUT_H8 HT_CPU_RX_CAD_L8 C
11 HT_CPU_TX_CAD_H[0 15] F5 AD3
L0_CAD N_L8 L0_CADOUT_L8
HYPERTRANSPORT
HT_CPU_TX_CAD_H7 N3 T1 HT_CPU_RX_CAD_H7
HT_CPU_TX_CAD_L7 L0_CAD N_H7 L0_CADOUT_H7 HT_CPU_RX_CAD_L7
N2 R1
HT_CPU_TX_CAD_H6 L0_CAD N_L7 L0_CADOUT_L7 HT_CPU_RX_CAD_H6
L1 U2
HT_CPU_TX_CAD_L6 L0_CAD N_H6 L0_CADOUT_H6 HT_CPU_RX_CAD_L6
M1 U3
HT_CPU_TX_CAD_H5 L0_CAD N_L6 L0_CADOUT_L6 HT_CPU_RX_CAD_H5
L3 V1
HT_CPU_TX_CAD_L5 L0_CAD N_H5 L0_CADOUT_H5 HT_CPU_RX_CAD_L5
L2 U1
HT_CPU_TX_CAD_H4 L0_CAD N_L5 L0_CADOUT_L5 HT_CPU_RX_CAD_H4
J1 W2
HT_CPU_TX_CAD_L4 L0_CAD N_H4 L0_CADOUT_H4 HT_CPU_RX_CAD_L4
K1 W3
HT_CPU_TX_CAD_H3 L0_CAD N_L4 L0_CADOUT_L4 HT_CPU_RX_CAD_H3
G1 AA2
HT_CPU_TX_CAD_L3 L0_CAD N_H3 L0_CADOUT_H3 HT_CPU_RX_CAD_L3
H1 AA3
HT_CPU_TX_CAD_H2 L0_CAD N_L3 L0_CADOUT_L3 HT_CPU_RX_CAD_H2
G3 AB1
HT_CPU_TX_CAD_L2 L0_CAD N_H2 L0_CADOUT_H2 HT_CPU_RX_CAD_L2
G2 AA1
HT_CPU_TX_CAD_H1 L0_CAD N_L2 L0_CADOUT_L2 HT_CPU_RX_CAD_H1
E1 AC2
HT_CPU_TX_CAD_L1 L0_CAD N_H1 L0_CADOUT_H1 HT_CPU_RX_CAD_L1
F1 AC3
HT_CPU_TX_CAD_H0 L0_CAD N_L1 L0_CADOUT_L1 HT_CPU_RX_CAD_H0
E3 L0_CAD N_H0 L0_CADOUT_H0 AD1
HT_CPU_TX_CAD_L0 E2 AC1 HT_CPU_RX_CAD_L0
L0_CAD N_L0 L0_CADOUT_L0
SOCKET638
U500E
A1 A26
P20 H16 T5021 N/A TPC28T
RSVD_MA0_CLK_H3 RSVD_MA_RESET_L T503 N/A TPC28T
P19 B18
B RSVD_MA0_CLK_L3 RSVD_MB_RESET_L B
N20
RSVD_MA0_CLK_H0
N19 B3
RSVD_MA0_CLK_L0 RSVD_V DSTRB1
C1
RSVD_V DSTRB0
RSVD_VDDNB_FB_H
H6 TURION S1g1
G6
RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
D5 uPGA638
MISC
NTERNAL FREE5
R24
W18
Top View
FREE6
R26 R23
RSVD_MB0_CLK_H3 FREE4
R25 AA8
RSVD_MB0_CLK_L3 FREE1
P22 H18
RSVD_MB0_CLK_H0 FREE2
R22 RSVD_MB0_CLK_L0 FREE3 H19
AF1
SOCKET638
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Turion HT I/F 20
Date: 14 2007 Sheet 5 of 69
5 4 3 2 1
5 4 3 2 1
MEM_MA0_CLK_H2 MEM_MB0_CLK_H2
9 MEM_MA0_CLK_H2 9 MEM_MB0_CLK_H2
C600 C601
MEM_MA0_CLK_L2 the cap close to cpu less than 1200mil MEM_MB0_CLK_L2
9 MEM_MA0_CLK_L2 9 MEM_MB0_CLK_L2
1 5PF/50V max neckdown to & from caps is 500mil 1 5PF/50V
MEM_MA0_CLK_H1 MEM_MB0_CLK_H1
9 MEM_MA0_CLK_H1 9 MEM_MB0_CLK_H1
D C602 C603 D
MEM_MA0_CLK_L1 MEM_MB0_CLK_L1
9 MEM_MA0_CLK_L1 9 MEM_MB0_CLK_L1
1 5PF/50V 1 5PF/50V
U500B U500C
MEM_MA_DATA[0 63] 9 MEM_MB_DATA[0 63] 9
MEM_MA0_CLK_H2 Y16 MEM_MB0_CLK_H2 AF18
MEM_MA0_CLK_L2 MA0_CLK_H2 MEM_MB0_CLK_L2 MB0_CLK_H2
AA16 MA0_CLK_L2 AF17 MB0_CLK_L2
MEM_MA0_CLK_H1 E16 AA12 MEM_MA_DATA63 MEM_MB0_CLK_H1 A17 AD11 MEM_MB_DATA63
MEM_MA0_CLK_L1 MA0_CLK_H1 MA_DATA63 MEM_MA_DATA62 MEM_MB0_CLK_L1 MB0_CLK_H1 MB_DATA63 MEM_MB_DATA62
9 10 MEM_MA0_CS_L[0 3] F16 AB12 9 10 MEM_MB0_CS_L[0 3] A18 AF11
MA0_CLK_L1 MA_DATA62 MEM_MA_DATA61 MB0_CLK_L1 MB_DATA62 MEM_MB_DATA61
AA14 AF14
MEM_MA0_CS_L3 MA_DATA61 MEM_MA_DATA60 MEM_MB0_CS_L3 MB_DATA61 MEM_MB_DATA60
V19 AB14 Y26 AE14
MEM_MA0_CS_L2 MA0_CS_L3 MA_DATA60 MEM_MA_DATA59 MEM_MB0_CS_L2 MB0_CS_L3 MB_DATA60 MEM_MB_DATA59
J22 W11 J24 Y11
MEM_MA0_CS_L1 MA0_CS_L2 MA_DATA59 MEM_MA_DATA58 MEM_MB0_CS_L1 MB0_CS_L2 MB_DATA59 MEM_MB_DATA58
V22 Y12 W24 AB11
MEM_MA0_CS_L0 MA0_CS_L1 MA_DATA58 MEM_MA_DATA57 MEM_MB0_CS_L0 MB0_CS_L1 MB_DATA58 MEM_MB_DATA57
9 10 MEM_MA0_ODT[0 1] T19 AD13 9 10 MEM_MB0_ODT[0 1] U23 AC12
MA0_CS_L0 MA_DATA57 MEM_MA_DATA56 MB0_CS_L0 MB_DATA57 MEM_MB_DATA56
AB13 AF13
MEM_MA0_ODT1 MA_DATA56 MEM_MA_DATA55 MEM_MB0_ODT1 MB_DATA56 MEM_MB_DATA55
V20 AD15 W23 AF15
MEM_MA0_ODT0 MA0_ODT1 MA_DATA55 MEM_MA_DATA54 MEM_MB0_ODT0 MB0_ODT1 MB_DATA55 MEM_MB_DATA54
U19 AB15 W26 AF16
MA0_ODT0 MA_DATA54 MEM_MA_DATA53 MB0_ODT0 MB_DATA54 MEM_MB_DATA53
AB17 AC18
MEM_MA_CAS_L MA_DATA53 MEM_MA_DATA52 MEM_MB_CAS_L MB_DATA53 MEM_MB_DATA52
9 10 MEM_MA_CAS_L U20 Y17 9 10 MEM_MB_CAS_L V26 AF19
C MEM_MA_WE_L MA_CAS_L MA_DATA52 MEM_MA_DATA51 MEM_MB_WE_L MB_CAS_L MB_DATA52 MEM_MB_DATA51 C
9 10 MEM_MA_WE_L U21 Y14 9 10 MEM_MB_WE_L U22 AD14
MEM_MA_RAS_L MA_WE_L MA_DATA51 MEM_MA_DATA50 MEM_MB_RAS_L MB_WE_L MB_DATA51 MEM_MB_DATA50
9 10 MEM_MA_RAS_L T20 W14 9 10 MEM_MB_RAS_L U24 AC14
MA_RAS_L MA_DATA50 MEM_MA_DATA49 MB_RAS_L MB_DATA50 MEM_MB_DATA49
9 10 MEM_MA_BANK[0 2] W16 9 10 MEM_MB_BANK[0 2] AE18
MEM_MA_BANK2 MA_DATA49 MEM_MA_DATA48 MEM_MB_BANK2 MB_DATA49 MEM_MB_DATA48
K22 AD17 K26 AD18
MEM_MA_BANK1 MA_BANK2 MA_DATA48 MEM_MA_DATA47 MEM_MB_BANK1 MB_BANK2 MB_DATA48 MEM_MB_DATA47
R20 Y18 T26 AD20
MEM_MA_BANK0 MA_BANK1 MA_DATA47 MEM_MA_DATA46 MEM_MB_BANK0 MB_BANK1 MB_DATA47 MEM_MB_DATA46
9 10 MEM_MA_CKE[0 1] T22 AD19 9 10 MEM_MB_CKE[0 1] U26 AC20
MA_BANK0 MA_DATA46 MEM_MA_DATA45 MB_BANK0 MB_DATA46 MEM_MB_DATA45
AD21 AF23
MEM_MA_CKE1 MA_DATA45 MEM_MA_DATA44 MEM_MB_CKE1 MB_DATA45 MEM_MB_DATA44
J20 AB21 H26 AF24
MEM_MA_CKE0 MA_CKE1 MA_DATA44 MEM_MA_DATA43 MEM_MB_CKE0 MB_CKE1 MB_DATA44 MEM_MB_DATA43
9 10 MEM_MA_ADD[0 15] J21 AB18 9 10 MEM_MB_ADD[0 15] J23 AF20
MA_CKE0 MA_DATA43 MEM_MA_DATA42 MB_CKE0 MB_DATA43 MEM_MB_DATA42
AA18 AE20
MEM_MA_ADD15 MA_DATA42 MEM_MA_DATA41 MEM_MB_ADD15 MB_DATA42 MEM_MB_DATA41
K19 AA20 J25 AD22
MEM_MA_ADD14 MA_ADD15 MEMORY MA_DATA41 MEM_MA_DATA40 MEM_MB_ADD14 MB_ADD15 MEMORY MB_DATA41 MEM_MB_DATA40
K20 Y20 J26 AC22
MEM_MA_ADD13 MA_ADD14 MA_DATA40 MEM_MA_DATA39 MEM_MB_ADD13 MB_ADD14 MB_DATA40 MEM_MB_DATA39
V24 INTERFACE AA22 W25 INTERFACE MB_DATA39 AE25
MEM_MA_ADD12 MA_ADD13 MA_DATA39 MEM_MA_DATA38 MEM_MB_ADD12 MB_ADD13 MEM_MB_DATA38
K24 Y22 L23 AD26
MEM_MA_ADD11 MA_ADD12 MA_DATA38 MEM_MA_DATA37 MEM_MB_ADD11 MB_ADD12 MB_DATA38 MEM_MB_DATA37
L20 W21 L25 AA25
MEM_MA_ADD10 MA_ADD11 MA_DATA37 MEM_MA_DATA36 MEM_MB_ADD10 MB_ADD11 MB_DATA37 MEM_MB_DATA36
R19 W22 U25 AA26
MEM_MA_ADD9 MA_ADD10 MA_DATA36 MEM_MA_DATA35 MEM_MB_ADD9 MB_ADD10 MB_DATA36 MEM_MB_DATA35
L19 MA_ADD9 MA_DATA35 AA21 L24 MB_ADD9 MB_DATA35 AE24
MEM_MA_ADD8 L22 AB22 MEM_MA_DATA34 MEM_MB_ADD8 M26 AD24 MEM_MB_DATA34
MEM_MA_ADD7 MA_ADD8 MA_DATA34 MEM_MA_DATA33 MEM_MB_ADD7 MB_ADD8 MB_DATA34 MEM_MB_DATA33
L21 AB24 L26 AA23
MEM_MA_ADD6 MA_ADD7 MA_DATA33 MEM_MA_DATA32 MEM_MB_ADD6 MB_ADD7 MB_DATA33 MEM_MB_DATA32
M19 Y24 N23 AA24
MEM_MA_ADD5 MA_ADD6 MA_DATA32 MEM_MA_DATA31 MEM_MB_ADD5 MB_ADD6 MB_DATA32 MEM_MB_DATA31
M20 H22 N24 G24
MEM_MA_ADD4 MA_ADD5 MA_DATA31 MEM_MA_DATA30 MEM_MB_ADD4 MB_ADD5 MB_DATA31 MEM_MB_DATA30
M24 H20 N25 G23
MEM_MA_ADD3 MA_ADD4 MA_DATA30 MEM_MA_DATA29 MEM_MB_ADD3 MB_ADD4 MB_DATA30 MEM_MB_DATA29
M22 E22 N26 D26
MEM_MA_ADD2 MA_ADD3 MA_DATA29 MEM_MA_DATA28 MEM_MB_ADD2 MB_ADD3 MB_DATA29 MEM_MB_DATA28
N22 E21 P24 C26
MEM_MA_ADD1 MA_ADD2 MA_DATA28 MEM_MA_DATA27 MEM_MB_ADD1 MB_ADD2 MB_DATA28 MEM_MB_DATA27
N21 J19 P26 G26
MEM_MA_ADD0 MA_ADD1 MA_DATA27 MEM_MA_DATA26 MEM_MB_ADD0 MB_ADD1 MB_DATA27 MEM_MB_DATA26
R21 H24 T24 G25
MA_ADD0 MA_DATA26 MEM_MA_DATA25 MB_ADD0 MB_DATA26 MEM_MB_DATA25
F22 E24
MEM_MA_DQS_H7 MA_DATA25 MEM_MA_DATA24 MEM_MB_DQS_H7 MB_DATA25 MEM_MB_DATA24
W12 F20 AF12 E23
MEM_MA_DQS_L7 MA_DQS_H7 MA_DATA24 MEM_MA_DATA23 MEM_MB_DQS_L7 MB_DQS_H7 MB_DATA24 MEM_MB_DATA23
W13 C23 AE12 C24
MEM_MA_DQS_H6 MA_DQS_L7 MA_DATA23 MEM_MA_DATA22 MEM_MB_DQS_H6 MB_DQS_L7 MB_DATA23 MEM_MB_DATA22
9 MEM_MA_DQS_H[0 7] Y15 B22 9 MEM_MB_DQS_H[0 7] AE16 B24
MEM_MA_DQS_L6 MA_DQS_H6 MA_DATA22 MEM_MA_DATA21 MEM_MB_DQS_L6 MB_DQS_H6 MB_DATA22 MEM_MB_DATA21
W15 F18 AD16 C20
MEM_MA_DQS_H5 MA_DQS_L6 MA_DATA21 MEM_MA_DATA20 MEM_MB_DQS_H5 MB_DQS_L6 MB_DATA21 MEM_MB_DATA20
AB19 E18 AF21 B20
B MEM_MA_DQS_L5 MA_DQS_H5 MA_DATA20 MEM_MA_DATA19 MEM_MB_DQS_L5 MB_DQS_H5 MB_DATA20 MEM_MB_DATA19 B
9 MEM_MA_DQS_L[0 7] AB20 E20 9 MEM_MB_DQS_L[0 7] AF22 C25
MEM_MA_DQS_H4 MA_DQS_L5 MA_DATA19 MEM_MA_DATA18 MEM_MB_DQS_H4 MB_DQS_L5 MB_DATA19 MEM_MB_DATA18
AD23 D22 AC25 D24
MEM_MA_DQS_L4 MA_DQS_H4 MA_DATA18 MEM_MA_DATA17 MEM_MB_DQS_L4 MB_DQS_H4 MB_DATA18 MEM_MB_DATA17
AC23 C19 AC26 A21
MEM_MA_DQS_H3 MA_DQS_L4 MA_DATA17 MEM_MA_DATA16 MEM_MB_DQS_H3 MB_DQS_L4 MB_DATA17 MEM_MB_DATA16
G22 G18 F26 D20
MEM_MA_DQS_L3 MA_DQS_H3 MA_DATA16 MEM_MA_DATA15 MEM_MB_DQS_L3 MB_DQS_H3 MB_DATA16 MEM_MB_DATA15
G21 G17 E26 D18
MEM_MA_DQS_H2 MA_DQS_L3 MA_DATA15 MEM_MA_DATA14 MEM_MB_DQS_H2 MB_DQS_L3 MB_DATA15 MEM_MB_DATA14
C22 C17 A24 C18
MEM_MA_DQS_L2 MA_DQS_H2 MA_DATA14 MEM_MA_DATA13 MEM_MB_DQS_L2 MB_DQS_H2 MB_DATA14 MEM_MB_DATA13
C21 F14 A23 D14
MEM_MA_DQS_H1 MA_DQS_L2 MA_DATA13 MEM_MA_DATA12 MEM_MB_DQS_H1 MB_DQS_L2 MB_DATA13 MEM_MB_DATA12
G16 E14 D16 C14
MEM_MA_DQS_L1 MA_DQS_H1 MA_DATA12 MEM_MA_DATA11 MEM_MB_DQS_L1 MB_DQS_H1 MB_DATA12 MEM_MB_DATA11
G15 H17 C16 A20
MEM_MA_DQS_H0 MA_DQS_L1 MA_DATA11 MEM_MA_DATA10 MEM_MB_DQS_H0 MB_DQS_L1 MB_DATA11 MEM_MB_DATA10
G13 E17 C12 A19
MEM_MA_DQS_L0 MA_DQS_H0 MA_DATA10 MEM_MA_DATA9 MEM_MB_DQS_L0 MB_DQS_H0 MB_DATA10 MEM_MB_DATA9
9 MEM_MA_DM[0 7] H13 E15 9 MEM_MB_DM[0 7] B12 A16
MA_DQS_L0 MA_DATA9 MEM_MA_DATA8 MB_DQS_L0 MB_DATA9 MEM_MB_DATA8
H15 A15
MEM_MA_DM7 MA_DATA8 MEM_MA_DATA7 MEM_MB_DM7 MB_DATA8 MEM_MB_DATA7
Y13 E13 AD12 A13
MEM_MA_DM6 MA_DM7 MA_DATA7 MEM_MA_DATA6 MEM_MB_DM6 MB_DM7 MB_DATA7 MEM_MB_DATA6
AB16 MA_DM6 MA_DATA6 C13 AC16 MB_DM6 MB_DATA6 D12
MEM_MA_DM5 Y19 H12 MEM_MA_DATA5 MEM_MB_DM5 AE22 E11 MEM_MB_DATA5
MEM_MA_DM4 MA_DM5 MA_DATA5 MEM_MA_DATA4 MEM_MB_DM4 MB_DM5 MB_DATA5 MEM_MB_DATA4
AC24 H11 AB26 G11
MEM_MA_DM3 MA_DM4 MA_DATA4 MEM_MA_DATA3 MEM_MB_DM3 MB_DM4 MB_DATA4 MEM_MB_DATA3
F24 G14 E25 B14
MEM_MA_DM2 MA_DM3 MA_DATA3 MEM_MA_DATA2 MEM_MB_DM2 MB_DM3 MB_DATA3 MEM_MB_DATA2
E19 H14 A22 A14
MEM_MA_DM1 MA_DM2 MA_DATA2 MEM_MA_DATA1 MEM_MB_DM1 MB_DM2 MB_DATA2 MEM_MB_DATA1
C15 F12 B16 A11
MEM_MA_DM0 MA_DM1 MA_DATA1 MEM_MA_DATA0 MEM_MB_DM0 MB_DM1 MB_DATA1 MEM_MB_DATA0
E12 G12 A12 C11
MA_DM0 MA_DATA0 MB_DM0 MB_DATA0
SOCKET638 SOCKET638
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Turion DDR2 Memory I/F 20
Date: 14 2007 Sheet 6 of 69
5 4 3 2 1
5 4 3 2 1
+1 8V
B B
CPU_M_VREF
R724 15mil trace.20mil space
1KOhm shorter than 6 inches
1% CPU_PROCHOT# CPU_PROCHOT#
CPU_M_VREF 3 3
D D
From SB From EC
Q701 Q702
C706 C707 SB_THRO_CPU 11 THRO CPU 11
19 SB_THRO_CPU 2N7002 28 THRO_CPU 2N7002
R725 G G
1KOhm 2 S N/A 2 S
1% 1000PF/16V 0 1UF/16V R726 R727
10KOhm 10KOhm
N/A
GND GND
P700 +3VS
1 2 R730
NC GND1 4 7KOhm
3 DBREQ_L1 GND2 4
5 DBRDY1 GND3 6
CPU_DBREQ# 7 8 R729
CPU_DBRDY DBREQ_L2 GND4 R728 10KOhm CPU_PROCHOT#
9 DBRDY2 GND5 10
CPU_TCK 11 12 10KOhm /x
CPU_TMS DBREQ_L3 GND6 /DEBUG
13 DBRDY3 GND7 14
CPU_TDI 15 16 Q703 Q704A
A CPU_TRST# DBREQ_L4 GND8 UM6K1N A
17 DBRDY4 DBRDY7 18 2
CPU_TDO 19 20 /x
DBREQ_L5 DBREQ_L7 /DEBUG
21 DBRDY5 DBRDY6 22
+1 8V 23 24 C E LDT_RESET# 5 Q704B
DBREQ_L6 GND9 28 63 PWRLMT#
26 UM6K1N
GND10 /x
ASP_68200_07_K25
/X GND
PMBS3904 Title : A7K
/DEBUG GND Engineer: Endy Zhang
ASUSTECH CO LTD
Size Project Name Rev
Custom Turion CNRL/DEBUG/THERM 20
Date: 14 2007 Sheet 7 of 69
5 4 3 2 1
5 4 3 2 1
DRAM_VTT 0.9V
D D
Between the socket and DIMMs, as close as
C800
+VCORE possible to the socket
+VCORE
+1 2VS_HT U500H U500G +1 8V
U500F
D4 AE5 4 7UF 10V J15 M17 C801 C802 C803 C804
VLDT_A4 VLDT_B4 VDD47 VSS91 0 22UF/6 3V 0 22UF/6 3V 0 22UF/6 3V 0 22UF/6 3V
AC4 AA4 D3 AE4 K16 N4
VDD1 VSS1 VLDT_A3 VLDT_B3 VDD48 VSS92
AD2 AA11 D2 AE3 L15 N8
VDD2 VSS2 +0 9V VLDT_A2 VLDT_B2 +0 9V VDD49 VSS93
G4 AA13 D1 AE2 M16 N10
VDD3 VSS3 VLDT_A1 VLDT_B1 VDD50 VSS94
H2 AA15 P16 N16
VDD4 VSS4 VDD51 VSS95 +1 8V
J9 AA17 D10 AC10 T16 N18
VDD5 VSS5 VTT8 VTT4 VDD52 VSS96
J11 AA19 C10 AB10 U15 P2
VDD6 VSS6 VTT7 VTT3 VDD53 VSS97 C805 C806 C807 C808
J13 AB2 B10 AA10 V16 P7
VDD7 VSS7 VTT6 VTT2 VDD54 VSS98 4 7UF/6 3V 4 7UF 6 3V 4 7UF 6 3V 4 7UF/6 3V
K6 AB7 AD10 A10 P9
VDD8 VSS8 VTT5 VTT1 VSS99
K10 AB9 W10 P11
VDD9 VSS9 +1 8V VTT9 VSS100
K12 AB23 P17
VDD10 VSS10 VSS101
K14 AB25 H25 D19 R8
VDD11 VSS11 VDD O23 VSS47 VSS102
L4 AC11 J17 D21 R10
VDD12 VSS12 VDD O1 VSS48 VSS103 +1 8V
L7 VDD13 VSS13 AC13 K18 VDD O2 VSS49 D23 VSS104 R16
L9 AC15 K21 D25 R18
VDD14 VSS14 VDD O3 VSS50 VSS105 C809 C810 C811 C812
L11 AC17 K23 E4 VDD T7
VDD15 VSS15 VDD O4 VSS51 VSS106 0 01UF/16V 0 01UF/16V 180PF/50V 180PF/50V
L13 AC19 K25 F2 T9
VDD16 VSS16 VDD O5 VSS52 VSS107
M2 AC21 L17 F11 T11
VDD17 VSS17 VDD O6 VSS53 VSS108
M6 AD6 M18 F13 T13
VDD18 VSS18 VDD O7 VSS54 VSS109
M8 AD8 M21 F15 T15
VDD19 VSS19 VDD O8 VSS55 VSS110
M10 AD25 M23 F17 T17
VDD20 VSS20 VDD O9 VSS56 VSS111
N7 AE11 M25 F19 U4
VDD21 VSS21 VDD O10 I O VSS57 VSS112 +1 8V
N9
N11
VDD22
VDD
VSS22
AE13
AE15
N17
P18
VDD O11 POWER VSS58
F21
F23
VSS113
U6
U8
place under socket on bottom side
VDD23 VSS23 VDD O12 VSS59 VSS114
P8 AE17 P21 F25 U10
VDD24 VSS24 VDD O13 VSS60 VSS115
P10 AE19 P23 H7 U12
C VDD25 VSS25 VDD O14 VSS61 VSS116 C813 C814 C815 C816 C
R4 AE21 P25 H9 U14
VDD26 VSS26 VDD O15 VSS62 VSS117 22UF/6 3V 22UF/6 3V 0 22UF/6 3V 0 22UF/6 3V
R7 AE23 R17 H21 U16
VDD27 VSS27 VDD O16 VSS63 VSS118
R9 B4 T18 H23 U18
VDD28 VSS28 VDD O17 VSS64 VSS119
R11 B6 T21 J4 V2
VDD29 VSS29 VDD O18 VSS66 VSS120
T2 B8 T23 J6 V7
VDD30 VSS30 VDD O19 VSS67 VSS121
T6 B9 T25 J8 V9
VDD31 VSS31 VDD O20 VSS68 VSS122
T8 B11 U17 J10 V11
VDD32 VSS32 VDD O21 VSS69 VSS123
T10 B13 V18 J12 V13
VDD33 VSS33 VDD O22 VSS70 VSS124
T12
T14
VDD34 VSS34
B15
B17
V21
V23
VDD O24 VSS71
J14
J16
VSS125
V15
V17
Capacitors are placed between the socket and
VDD35 VSS35 VDD O25 VSS72 VSS126
U7
VDD36 VSS36
B19 V25
VDD O26 VSS73
J18
VSS130
W6 DIMMs, as close as possible to the socket
U9 B21 Y25 K2 Y21
VDD37 VSS37 VDD O27 VSS74 VSS131
U11 B23 K7 Y23
VDD38 VSS38 VSS75 VSS132 +0 9V
U13 B25 K9 N6
VDD39 VSS39 VSS76 VSS133
V6 D6 K11
VDD40 VSS40 VSS77 SOCKET638 C817 C818 C819 C820
V8 D8 K13
VDD41 VSS41 VSS78 4 7UF/6 3V 4 7UF 6 3V 4 7UF 6 3V 4 7UF/6 3V
V10 VDD42 VSS42 D9 VSS79 K15
V12 D11 K17
VDD43 VSS43 VSS80
V14 D13 L6
VDD44 VSS44 VSS81 +0 9V
W4 D15 L8
VDD45 VSS45 VSS82
Y2 D17 L10
VDD46 VSS46 VSS83 C821 C822 C823 C824
L12
SOCKET638 VSS84 0 22UF/6 3V 0 22UF/6 3V 0 22UF/6 3V 0 22UF/6 3V
L14
VSS85
L16
VSS86
L18
VSS87 +0 9V
M7
+VCORE place under socket on bottom side VSS88
M9
VSS89
M11
VSS90 C831 C832 C833 C834
SOCKET638
C825 C826 C827 C828 C829 C830 1000PF/16V 1000PF/16V 1000PF/16V 1000PF 16V
22UF/6 3V 22UF/6 3V 22UF/6 3V 22UF/6 3V 22UF/6 3V 22UF/6 3V
B +0 9V B
C846 C847
4 7UF/6 3V 4 7UF/6 3V
+1 2VS_HT
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Turion Power 20
Date: 14 2007 Sheet 8 of 69
5 4 3 2 1
5 4 3 2 1
6 10 MEM_MA_ADD[0 15]
MEM_MA_ADD0 102
U900A TOP 5 MEM_MA_DATA5
MEM_MA_DATA[0 63] 6 6 10 MEM_MB_ADD[0 15]
MEM_MB_ADD0 102
U901A BOTTOM 5 MEM_MB_DATA0
MEM_MB_DATA[0 63] 6
D
MEM_M_VREF
+1 8V
15mil trace.20mil space
shorter than 6 inches
R901 C902
1KOhm
1% 0 1UF 16V MEM_M_VREF
MEM_M_VREF
C903 C904
R902
A 0 1UF 16V 1000PF/16V A
1KOhm
1%
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom DDR2 SODIMM 20
Date: 14 2007 Sheet 9 of 69
5 4 3 2 1
5 4 3 2 1
+0 9V
+0 9V
7 8 RN1008D
6 9 MEM_MB0_CS_L0 47Ohm
3 4 RN1013B
6 9 MEM_MB0_CS_L1 47Ohm
3 4 RN1012B
6 9 MEM_MB0_CS_L2 47Ohm
1 2 RN1015A C1024 C1025 C1026 C1027 C1028 C1029 C1030 C1031
6 9 MEM_MB0_CS_L3 47Ohm
3 4 RN1015B 0 1UF/16V 0 1UF 16V 0 1UF/16V 0 1UF 16V 0 1UF/16V 0 1UF/16V 0 1UF 16V 0 1UF/16V
6 9 MEM_MB0_ODT0 47Ohm
1 2 RN1013A
6 9 MEM_MB0_ODT1 47Ohm
1 2 RN1006A
47Ohm
7 8 RN1012D
47Ohm
+1 8V
place behind DIMMs
5 4 3 2 1
D D
U1100A
RS690M HT_TXCALN
B B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom RS690M HT Link0 I/F 20
Date: 14 2007 Sheet 11 of 69
5 4 3 2 1
5 4 3 2 1
D D
U1100B
RS690M
B B
17 A_C_RXP[0 3] A_C_TXP[0 3] 17
17 A_C_RXN[0 3] A_C_TXN[0 3] 17
40 GPP_RXP0 GPP_C_TXP0 40
40 GPP_RXN0 GPP_C_TXN0 40
26 GPP_RXP1 GPP_C_TXP1 26
26 GPP_RXN1 GPP_C_TXN1 26
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom RS690M PCIE Link I/F 20
Date: 14 2007 Sheet 12 of 69
5 4 3 2 1
5 4 3 2 1
+3VS
L1300
+1 8VS AVDDQ 1 2
L1301
1 2 220Ohm/100Mhz C1301
+3VS Q1302
Q1301 R1313
A_RST# 1 A VCC 5
DFT_GPIO4 1 2 E C GPULV_EN 22
19 NB_SELV_EN 2 B
0Ohm PMBS3904
3 GND 4
R1317 Y RS485/RS690 RS690 only
NC7SZ00M5X_NL
10KOhm
DFT_GPIO0 DFT_GPIO1 DFT_GPIO[4:2] DFT_GPIO5
+3VS
PULL HIGH Memory Bypass the loading These pin straps are used to configure PCI E GPP mode: Enable debug bus via the memory
R1315 (internally side port of EEPROM straps DEFAULT
IO pads, if ava lable in the package
111: register defined (register default to Config E)
/x pulled not and use Hardware 110: 4 0 0 0 0 Config A
10KOhm
high) available default values 101: 4 4 Config B use default values DEFAULT
A D1300 DEFAULT A
100: 4 2 2 Config C
1 2 R_BMREQ# DEFAULT 011: 4 2 1 1 Config D
17 BMREQ#
1SS355 010: 4 1 1 1 1 Config E
C1320 PULL Memory I2C Master can others: register defined (register default to Config E) use the memory data bus
15PF/50V R1316
LOW side port load strap values to output the debug bus
1 2 0Ohm
available from EEPROM if
/x connected, or use
default values if Title : A7K
not connected Engineer: Endy Zhang
ASUSTECH CO LTD
Size Project Name Rev
Custom RS690M System I/F & CLKGEN 20
Date: 14 2007 Sheet 13 of 69
5 4 3 2 1
5 4 3 2 1
D D
U1100E
A25 M3
VSS1 VSSA1
F11
VSS2 PAR 5 OF 5 VSSA2
V12
NB_VDDA12 D23 V11
VSS3 VSSA3
E9 V14
+1 2VS_HT VSS4 VSSA4
G11 F3
U1100D VSS5 VSSA5
Y23 V15
VSS6 VSSA6
VDD_HT_1PART 4 OF 5
AE24 D1 P11 A1
VDDA_12_9 VSS7 VSSA7
AD24 G7 R24 H1
VDD_HT_2 VDDA_12_10 VSS8 VSSA8
AD22 E2 AE18 G3
C1400 C1402 C1403 C1404 C1405 C1401 C1406 VDD_HT_3 VDDA_12_11 C1407 C1408 C1417 C1409 C1410 C1411 VSS9 VSSA9
AB17 C1 M15 J2
VDD_HT_4 VDDA_12_12 VSS10 VSSA10
AE23 E3 J22 H3
10UF/10V 10UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF 10V 1UF/10V VDD_HT_5 VDDA_12_13 1UF 10V 1UF/10V 1UF/10V 1UF/10V 10UF/10V 10UF/10V VSS11 VSSA11
Y17 VDD_HT_6 VDDA_12_14 D2 G23 VSS12 VSSA12 AE10
W17 M9 J12 J6
VDD_HT_7 VDDA_12_15 VSS13 VSSA13
AC18 F4 L12 AE6
VDD_HT_8 VDDA_12_16 VSS14 VSSA14
AD21 B1 L14 F1
VDD_HT_9 VDDA_12_17 VSS15 VSSA15
AC19 D3 L20 L6
+1 8VS VDD18 VDD_HT_10 VDDA_12_18 VSS16 VSSA16
AC20 L9 L23 M2
L1400 VDD_HT_11 VDDA_12_19 +VDDC_NB VSS17 VSSA17
AB19 E6 M11 M6
VDD_HT_12 VDDA_12_20 VSS18 VSSA18
1 2 AD23
VDD_HT_13
M20
VSS19 VSSA19
J3
AA17 L11 M23 P6
220Ohm/100Mhz VDD_HT_14 VDD_CORE_1 VSS20 VSSA20
AE25 L13 M25 T1
C1418 C1412 VDD_HT_15 VDD_CORE_2 VSS21 VSSA21
L15 N12 N3
VDD_CORE_3 C1413 C1414 C1415 C1416 VSS22 VSSA22
J14 M12 N14 P9
NB_VDDA12 +1 2VS 1UF/10V 1UF/10V VDD_18_1 VDD_CORE_4 VSS23 VSSA23
J15 R15 B7 R6
C L1404 VDD_18_2 VDD_CORE_5 0 1UF/16V 0 1UF 16V 0 1UF/16V 10UF/10V VSS24 VSSA24 C
M14 L24 U2
VDD_CORE_6 VSS25 VSSA25
1 2 AE2
VDDA_12_1 VDD_CORE_7
N11 P13
VSS26 VSSA26
T3
AB3 N13 P20 U3
VDDA_12_2 VDD_CORE_8 VSS27 VSSA27
220Ohm/100Mhz U7 N15 P15 U6
VDDA_12_3 VDD_CORE_9 VSS28 VSSA28
W7 J11 R12 AC4
VDDA_12_4 VDD_CORE_10 VSS29 VSSA29
AB4 H11 R14 Y1
VDDA_12_5 VDD_CORE_11 VSS30 VSSA30
AC3 P12 R20 Y15
C1419 C1420 C1421 C1422 C1423 C1424 VDDA_12_6 VDD_CORE_12 VSS31 VSSA31
AD2 P14 W23 W6
VDDA_12_7 VDD_CORE_13 VSS32 VSSA32
AE1 R11 Y25 AC2
10UF/10V 10UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF 10V VDDA_12_8 VDD_CORE_14 VSS33 VSSA33
R13 AD25 Y3
VDD_CORE_15 VSS34 VSSA34
E11 A19 U20 Y9
VDDR3_1 VDD_CORE_16 VSS35 VSSA35
D11 B19 H25 Y11
VDDR3_2 VDD_CORE_17 VSS36 VSSA36
U11 W24 R9
VDD_CORE_18 C1426 C1427 C1428 C1429 VSS37 VSSA37
AC12 U14 Y22 AD1
+3VS VDDR3 VDDR_1 VDD_CORE_19 C1425 VSS38 VSSA38
AD12 P17 AC23 AC5
L1401 VDDR_2 VDD_CORE_20 0 1UF/16V 0 1UF 16V 0 1UF/16V 10UF/10V VSS39 VSSA39
AE12 L17 D25 AC6
VDDR_3 VDD_CORE_21 0 1UF/16V VSS40 VSSA40
1 2 VDD_CORE_22 J19 G24 VSS41 VSSA41 AC7
E7 D20 AC14 AD3
220Ohm/100Mhz VDD_PLL_1 VDD_CORE_23 VSS42 VSSA42
F7 G20 H12 AC9
C1430 VDD_PLL_2 VDD_CORE_24 VSS43 VSSA43
F9 A9 AC22 AC10
VSS_PLL_1 VDD_CORE_25 VSS44 VSSA44
G9 B9 R23 G6
2 2UF 10V VSS_PLL_2 VDD_CORE_26 VSS45 VSSA45
C9 C4 Y12
VDD_CORE_27 VSS46 VSSA46
D22 D9 AE22 Y14
+1 8VS VDDR VDD_HT_PKG VDD_CORE_28 VSS47 VSSA47
M1 A7 T23 AA3
L1402 VDDA_12_PKG_1 VDD_CORE_29 VSS48 VSSA48
AC11 A4 T25
VDDA_12_PKG_2 VDD_CORE_30 VSS49
1 2 U12 AE14
VDD_CORE_31 VSS50
U15 R17
220Ohm/100Mhz VDD_CORE_32 VSS51
H23
C1431 C1432 C1433 VSS52
RS690M M17
VSS53
A23
1UF/10V 1UF/10V 1UF 10V VSS54
AC15
VSS55
F17
B VSS56 B
D4
VSS57
AC16
VSS58
M13
VDDHT_PKG VDDA12_PKG1 VDDA12_PKG2 VSS59
+1 2VS VDDPLL
L1403 C1434 RS690M
1 2
0 1UF/16V
220Ohm/100Mhz
C1435 C1436
4 7UF 6 3V 1UF/10V
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom RS690M Power 20
Date: 14 2007 Sheet 14 of 69
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : A7KM
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom <Doc> 20
Date: 14 2007 Sheet 15 of 69
5 4 3 2 1
5 4 3 2 1
+3 3VS_CLK
D D
CS951462AGLFT GND
R1636 R1638 R1640 R1642 R1644 R1646 GND GNDGND GNDGND
R1635 R1637 R1639 R1641 R1643 R1645 R1647 R1648 R1649
10KOhm 10KOhm 10KOhm
CLK_NEWCARD_REQ# 27
CLK_NEWCARD_REQ#
G_CLKREQ#
B B
A
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom External Clock Generator 20
Date: 14 2007 Sheet 16 of 69
5 4 3 2 1
5 4 3 2 1
U1700A
1UF/10V 4 7UF/6 3V
LPC_AD[0 3] 27 28 37
32K_XOUT C1 X
X2 LPC_AD0
AG24
CPU_PWROK LAD0 LPC_AD1
7 CPU_PWROK AC26 AG25
+1 8VS CPU_PG/LDT_PG LAD1 LPC_AD2
W26 AH24
INTR/LINT0 LAD2 LPC_AD3 JRST1
W24 NM /LINT1 LAD3 AH25
W25 AF24 SGL_JUMP
INIT# LFRAME# LPC_FRAME# 27 28 37
AA24 AJ24 LPC_DRQ#0 37
R1718 ALLOW_LDTSTOP LDT STOP# SMI# LDRQ0#
2 1 1KOhm 7 13 LDT_STOP# AA23 AH26 1 T1708 TPC28T
T1709 SLP#/LDT_STP# LDRQ1#/GNT5#/GPIO68
1 TPC28T AA22
IGNNE#/SIC BMREQ# REQ5#/GPIO65
W22 BMREQ# 13
T1710 1 TPC28T AA26 AF23
A20M#/SID SERIRQ INT_SERIRQ 28 37 38
T1711 1 TPC28T Y27
FERR# RTCCLK T1700 TPC28T
13 ALLOW_LDTSTOP AA25 STPCLK#/ALLOW_LDTSTP RTCCLK D3 1
T1712 1 TPC28T AH9 F5 1 T1713 TPC28T
T1714 CPU_STP#/DPSLP_3V# RTC_IRQ#/GPIO69
1 TPC28T B24 +VCC_RTC
T1715 DPSLP_OD# GP O37
1 TPC28T W23 DPRSLPVR VBAT E1
AC25 D1 C1727
7 LDT_RESET# LDT_RST#/DPRSTP#/PROCHOT# RTC_GND
0 1UF 16V
SB600
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom SB600 PCIE/PCI/CPU/LPC 20
Date: 14 2007 Sheet 17 of 69
5 4 3 2 1
5 4 3 2 1
+3VSUS +3VSUS
R1825 R1827
R1800
1 2 SYS_RST#
PM_PWRBTN# KB_SCI#
10KOhm C1800
0 1UF 16V
U1700D
SB600
GND
/x Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom SB600 ACPI/GPIO/USB/AC97/AZA 20
Date: 14 2007 Sheet 18 of 69
5 4 3 2 1
5 4 3 2 1
U1700B
D D
C1900 2 0 01UF/16V SATA_TX0+
35 SATA_TXP0 1
C1903 2 0 01UF/16V SATA_TX0
AH21
AJ21
SATA_TX0+ SB600 SB 23x23mm AB29
35 SATA_TXN0 SATA_TX0 IDE_IORDY IDE_P ORDY 35
Part 2 of 4 IDE_IRQ
AA28 INT_IRQ14 35
C1901
1 2 0 01UF/16V SATA_RX0 AH20 AA29
35 SATA_RXN0 SATA_RX0 IDE_A0 IDE_PDA0 35
C1904
1 2 0 01UF/16V SATA_RX0+ AJ20 AB27
35 SATA_RXP0 SATA_RX0+ IDE_A1 IDE_PDA1 35
Y28 IDE_PDA2 35
IDE_A2
AH18 AB28 DE_PDDACK# 35
SATA_TX1+ DE_DACK#
AJ18 AC27 IDE_PDDREQ 35
SATA_TX1 IDE_DRQ
AC29 DE_PDIOR# 35
DE_IOR#
AH17 AC28 DE_PDIOW# 35
SATA_RX1 IDE_IOW#
AJ17 W28 DE_PDCS#1 35
SATA_RX1+ IDE_CS1#
W27 DE_PDCS#3 35
IDE_CS3#
AH13 IDE_PDD[15:0] 35
SATA_TX2+ IDE_PDD0
AH14 AD28
SATA_TX2 IDE_D0 GPIO15 IDE_PDD1 +3VS
AD26
IDE_D1 GPIO16 IDE_PDD2
AH16 AE29
SATA_RX2 IDE_D2 GPIO17 IDE_PDD3
AJ16 AF27
SATA_RX2+ IDE_D3 GPIO18 IDE_PDD4
AG29
IDE_D4 GPIO19 IDE_PDD5
AJ11 SATA_TX3+ IDE_D5 GPIO20 AH28
AH11 AJ28 IDE_PDD6 R1907 2 2KOhm
R1900 SATA_TX3 IDE_D6 GPIO21 IDE_PDD7 PANEL_ID0
AJ27 1 2 PANEL_ID0 22
IDE_D7 GPIO22 IDE_PDD8
1 2 AH12 AH27
SATA_RX3 IDE_D8 GPIO23 IDE_PDD9
AJ13 AG27
1KOhm 1% SATA_RX3+ IDE_D9 GPIO24 IDE_PDD10
AG28
SATA_CAL DE_D10/GPIO25 IDE_PDD11 R1908 2 2KOhm
GND AF12 AF28
SATA_CAL DE_D11/GPIO26 IDE_PDD12 PANEL_ID1
AF29 1 2 PANEL_ID1 22
SATA_X1 DE_D12/GPIO27 IDE_PDD13
AD16 AE28
R1901 SATA_X1 DE_D13/GPIO28 IDE_PDD14
AD25
SATA_X2 DE_D14/GPIO29 IDE_PDD15
2 1 AD18 AD29
SATA_X2 DE_D15/GPIO30
Rev 2.0 10MOhm AC12
C 50 SATA_LED# SATA_ACT#/GPIO67 GPU 2C_EN# C
X1900 AD14
1 2 PLLVDD_SATA PLLVDD_SATA_1
AJ10 J3
PLLVDD_SATA_2 SPI_DI GPIO12
J6 SB_THRO_CPU 7
25Mhz SPI_DO GPIO11
AC16 G3 NB_SELV_EN 13
C1905 C1902 XTLVDD_SATA XTLVDD_SATA SPI_CLK GPIO47
G2
10PF/50V 10PF/50V SPI_HOLD#/GPIO31
AE14 G6
AVDD_SATA AVDD_SATA_1 SPI_CS# GPIO32
AE16
AVDD_SATA_2 R1915
AE18 C23
AVDD_SATA_3 LAN_RST#/GPIO13 /A7K
AE19 G5
AVDD_SATA_4 ROM_RST#/GPIO14
AF19
AVDD_SATA_5 GPIO3 T1905 TPC28T 10KOhm
AF21 M4 1
AVDD_SATA_6 FANOUT0/GPIO3 GPIO48 T1906 TPC28T
AG22 T3 1
AVDD_SATA_7 FANOUT1/GPIO48 GPIO49 T1907 TPC28T
GND AG23 V4 1
+1 2VS PLLVDD_SATA AVDD_SATA_8 FANOUT2/GPIO49
AH22
L1900 AVDD_SATA_9 GPIO50 T1908 TPC28T
AH23 N3 1
AVDD_SATA_10 FANIN0 GPIO50 GPIO51 T1909 TPC28T
1 2 AJ12 AVDD_SATA_11 FANIN1 GPIO51 P2 1
AJ14 W4 GPIO52 1 T1910 TPC28T
220Ohm/100Mhz C1906 C1907 AVDD_SATA_12 FANIN2 GPIO52 +3VS +3VS +3VS
AJ19
AVDD_SATA_13 TEMP_COMM
AJ22 P5
1UF 10V 1UF/10V AVDD_SATA_14 TEMP_COMM GPIO61 T1912 TPC28T
AJ23 P7 1
AVDD_SATA_15 TEMPIN0 GPIO61 TEMPIN_NB
P8
TEMPIN1 GPIO62 GPIO63 T1911 TPC28T
AB14 T8 1
AVSS_SATA_1 TEMPIN2 GPIO63 PM_THERM#
AB16 T7 PM_THERM# 28
AVSS_SATA_2 TEMPIN3/TALERT#/GPIO64 R1914 R1913 R1909
AB18
+3VS XTLVDD_SATA AVSS_SATA_3 GPU_RST# A7K
AC14 V5 GPU_RST# 41
L1901 AVSS_SATA_4 VIN0 GPIO53 T1913 TPC28T
AC18 L7 1
AVSS_SATA_5 VIN1 GPIO54 GPU 2C_EN# 10KOhm 10KOhm 10KOhm
1 2 AC19
AVSS_SATA_6 VIN2 GPIO55
M8 GPUI2C_EN# 22
AD12 V6 PANEL_ID0
220Ohm/100Mhz C1909 AVSS_SATA_7 VIN3 GPIO56 PANEL_ID1
AD19 M6
AVSS_SATA_8 VIN4 GPIO57 EMA L_LED# BT_LED_EN# GPU_RST#
AD21 P4
1UF 10V AVSS_SATA_9 VIN5 GPIO58 BT_LED_EN#
AE12 M7 BT_LED_EN# 50
B AVSS_SATA_10 VIN6 GPIO59 EMA L_LED# B
AE21 V7 EMAIL_LED# 50
+1 2VS AVSS_SATA_11 VIN7 GPIO60 +3VS
AF11
AVDD_SATA AVSS_SATA_12
AF14
L1902 AVSS_SATA_13 L1903
AF16
AVSS_SATA_14 HWM AVDD
1 2 AF18
AVSS_SATA_15 AVDD
N1 1 2
AG11
AVSS_SATA_16 220Ohm/100Mhz
220Ohm/100Mhz AG12 M1
AVSS_SATA_17 AVSS
AG13
C1911 C1912 C1913 C1914 C1915 AVSS_SATA_18 C1916 C1917
AG14
22UF/6 3V AVSS_SATA_19 TEMPIN_NB R1902 1
AG16
AVSS_SATA_20 GND 2 0Ohm NB_THERMD_P 13
1UF/10V 1UF/10V 0 1UF/16V 0 1UF/16V AG17 0 1UF/16V 2 2UF 10V
AVSS_SATA_21
AG18
AVSS_SATA_22 C1908
AG19
AVSS_SATA_23 0 01UF/16V
AG20 AVSS_SATA_24 GND GND
AG21
AVSS_SATA_25
AH10
AVSS_SATA_26 TEMP_COMM R1903 1
AH19 2 0Ohm NB_THERMD_N 13
AVSS_SATA_27
SB600
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom SB60 SATA/IDE/HWM/SPI 20
Date: 14 2007 Sheet 19 of 69
5 4 3 2 1
5 4 3 2 1
+3VS
GND SB600
GND GND
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom SB600 Power & Decoupling 20
Date: 14 2007 Sheet 20 of 69
5 4 3 2 1
5 4 3 2 1
D D
+3VS
Route CPU_THRM_DA and
CPU_THRM_DC
on the same layer
------------------OTHER SIGNALS
15 mils
OS#_OC 1 2 ===============GND
R2104
10 mils
10KOhm =========H_THERMDA(10 mils)
+3VS_THM +3VS
ADDRESS:98H Max: 1mA R2101
10 mils
200Ohm =========H_THERMDC(10 mils)
U2100 2 1 10 mils
28 48 SMB1_CLK 8 1 =========GND
SCLK VCC
28 48 SMB1_DAT 7 2 CPU_THERMADA 7
SDA DXP 15 mils
6 3 CPU_THERMADC 7
ALERT# DXN OS#_OC
5
GND OVERT#
4 ---------------------OTHER SIGNALS
C2100 C2101
100PF/50V 100PF/50V MAX6657MSA C2102 Avoid FSB,Power
/x x 0 1UF 16V CPU_THERMADA
C2103
1000PF/16V
GND GND
C CPU_THERMADC C
c0402 2 3Q2102
R2103 +12V C2105
10KOhm APM2301BAC CON2100 2200PF/50V
r0402_h16 U2101 +5VS_FAN OLD1
1 W oB_CON_3P c0603
3 A+ + VCC 8 R2106 2
R2105 100KOhm 1 1 2 3
R2107 FAN_PWM# 1 2 2 A AO + OLD2
1 2 r0603_h24 330Ohm CE2001 D2101 GND
48 OS#_OC_GPU
5 B+ + C2107 100U 6 3V 1SS355
3 Q2103 C2106 BO 7
1KOhm D
4700PF 25V 6 B GND 4 0 1UF/16V
OS#_OC 11 LM358MX
G
2 S 2N7002 GND GND GND GND GND
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Thermal Fan Control 20
Date: 14 2007 Sheet 21 of 69
5 4 3 2 1
5 4 3 2 1
+3VS +12VS
+3VS R2215 1 2 0Ohm /A7U C_TXOUT_LN0 +3VS
13 NB_TXOUT_LN0
GPULV_EN R2217 1 2 0Ohm /A7U C_TXOUT_LP0
13 NB_TXOUT_LP0
R2203 Q2207A R2218 1 2 0Ohm /A7U C_TXOUT_LN1
13 NB_TXOUT_LN1
R2204 10KOhm 1 6 R2219 1 2 0Ohm /A7U C_TXOUT_LP1
42 FPVCC 13 NB_TXOUT_LP1
10KOhm r0402 C2200 C2201 UM6K1N U2200
r0402 Q2201 0.1UF/16V R2220 1 2 0Ohm /A7U C_TXOUT_LN2 1 48
13 NB_TXOUT_LN2 VDD1 0B1 TXOUT_L0- 42
1 6 c0402 0.01UF/16V GPULV_EN# /A7K R2221 1 2 0Ohm /A7U C_TXOUT_LP2 C_TXOUT_LN0 2 47
D 13 NB_TXOUT_LP2 A0 1B1 TXOUT_L0+ 42
2 5 3 46
3 Q2200 3 Q2202 S 4+3VSLCD R2222 1 GND1 GND17
D D 3 13 NB_TXCLK_LN 2 0Ohm /A7U C_TXCLK_LN C_TXOUT_LP0 4 45 NB_TXOUT_LN0 13
A1 0B2
G R2223 1 2 0Ohm /A7U C_TXCLK_LP 5 44
+3VS_LCD 13 NB_TXCLK_LP GND2 1B2 NB_TXOUT_LP0 13
SI3456BDV L2200 Q2207B 6 43
VDD2 GND16
LVDSPWR_EN 11 11 80Ohm/100Mhz GND
13 NB_LVDS_DIGON 4 3 7 42 TXOUT_L1- 42
C2202 C_TXOUT_UN0 C_TXOUT_LN1 GND3 2B1
G G 1 2 UM6K1N R2226 1 2 0Ohm /A7U 8 41
D 2 S 2N7002 2 S 13 NB_TXOUT_UN0 A2 3B1 TXOUT_L1+ 42 D
2N7002 1UF/25V C2203 R2229 1 2 0Ohm /A7U C_TXOUT_UP0 9 40
13 NB_TXOUT_UP0 GND4 GND15
0.1UF/16V C2206 /A7K C_TXOUT_LP1 10 39
A3 2B2 NB_TXOUT_LN1 13
R2205 c0402 C2204 C2205 0.1UF/16V R2224 1 2 0Ohm /A7U C_TXOUT_UN1
10KOhm
Rev 2.0 10UF/10V 1UF/10V c0402 /A7U
13 NB_TXOUT_UN1
R2225 1 2 0Ohm /A7U C_TXOUT_UP1
11
12
GND5 3B2
38
37
NB_TXOUT_LP1 13
13 NB_TXOUT_UP1 VDD3 GND14
r0402 c0805 c0402 R2200 1 2 0Ohm LVDSPWR_EN 13 36
R2209 GND6 VDD5
GND GND R2227 1 2 0Ohm /A7U C_TXOUT_UN2 14 35
13 NB_TXOUT_UN2 NC 4B1 TXOUT_L2- 42
2 1 GND R2228 1 2 0Ohm /A7U C_TXOUT_UP2 C_TXOUT_LN2 15 34
13 NB_TXOUT_UP2 A4 5B1 TXOUT_L2+ 42
16 33
GND 3 Q2208 R2230 1 GND7 GND13
D 13 NB_TXCLK_UN 2 0Ohm /A7U C_TXCLK_UN C_TXOUT_LP2 17 32 NB_TXOUT_LN2 13
33Ohm R2231 1 C_TXCLK_UP A5 4B2
13 NB_TXCLK_UP 2 0Ohm /A7U 18 31 NB_TXOUT_LP2 13
+3VS GND8 5B2
19 30
VDD4 GND12
11 20
GND9 6B1
29 TXCLK_L- 42
G GND C_TXCLK_LN 21 28
2 S 2N7002 A6 7B1 TXCLK_L+ 42
22 27
C_TXCLK_LP GND10 GND11
23 26 NB_TXCLK_LN 13
GPULV_EN# A7 6B2
24 25 NB_TXCLK_LP 13
/A7K R2234 GLVDS_DDCCLK R2238 1 SEL 7B2
2 0Ohm /A7K LVDS_I2C_CLK
GND 10KOhm GLVDS_DDCDAT R2241 1 2 0Ohm /A7K LVDS_I2C_DATA TS3DV416DGGR
GPULV_EN# r0402
+3VS
+3VS 3 Q2210
D
B /x B
Q2209B C2227 C2223 C2224 C2225 C2226
13 NB_LVDS_BLEN 4 3 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
UM6K1N
L2203
C2210 1 2
0.1UF/16V C2211
+3VS c0402 80Ohm/100Mhz
1UF/25V
+
C2212 CE2200
0.1UF/16V 100U/6.3V
D2201 RB717F R2210 c0402
1 100KOhm GND
50 LID_SW#
3 r0402 CON2201
2 L2204
1 2 80Ohm/100Mhz +VIN_INV 1 2 +5V_USB_CCD
17,25,35,38 PCIRST# 1 2
3 4 GND GND
3 4
LVDS_BLEN 1 5 6
BL_EN L2205 BL_EN_CON 5 6
3 1 2 120Ohm/100Mhz 7 8 USB_PN6 18
l0603 7 8
28 BACK_OFF# 2 9
9 10
10 USB_PP6 18
120Ohm/100Mhz 11 12 120Ohm/100Mhz N/A
D2202 RB717F 11 12 INV_DA_CON L2207 1
13 14 2 BRIGHT_PWM 28
L2206 MIC_INT_CON 13 14
33 MIC_INT_P 1 2 15
15 16
16
l0603 17 18
C2213 L2209 MIC_GND_CON 17 18
1 2 19 20
19 20
1000PF/16V l0603 21 22
c0402 120Ohm/100Mhz SIDE1 SIDE2 D2203 D2204
23 24
A NP_NC1 NP_NC2 A
33 MIC_INT_N
C2214 WTOB_CON_20P C2216 EGA10603V05A1 EGA10603V05A1
D2205 D2206 1000PF/16V 1000PF/16V
C2215 c0402 c0402 /X /X
0.1UF/16V
R2213 R2214
10KOhm 10KOhm /x
GND GND GND
SFI0402_050E330NP_LF SFI0402_050E330NP_LF
Title : A7K
ASUSTECH CO.,LTD. Engineer: Endy Zhang
GND GND GND GND GND GND GND GND Size Project Name Rev
Custom LVDS And Inverter 2.0
Date: , 14, 2007 Sheet 22 of 69
5 4 3 2 1
5 4 3 2 1
L change to 09G023472000!!!
JP42300 L2300 L2301
TV OUT CRT OUT RED
JP42303
1 2 RED_ 1
L2302
2 RED_L1
L2303
2 R_CON 1
CON2300
RED VCC
9
TV_COMP 1 2 TV_COMP_ 1 2TV_COMP
1 L 2 TV_COMP_CON
U2300 47NH 47NH
47NH 47NH HOTPLUG# 1 8
1 P_GND1 R2303 C2314 C2301 C2302
4
R2301 4
2
C2300 C2303 C2304 C2324 2 75Ohm 5PF/50V 6PF 50V 5PF/50V
75Ohm 47PF 50V 47PF/50V 47PF/50V 1000PF 16V
Rev 2.0 5
7
5 /x
c0402 TV_C_CON 7
6
6
3 9
3 P_GND2
R2328 33Ohm
CRT_SDA 1 2 CRT_SDA_CON 12
R2324 1 RED DATA
13 NB_R 2 0Ohm R2327 1 2 0Ohm G_RED 42
/A7U /A7K 16
C2320 SIDE_G16
17
R2329 1 GREEN SIDE_G17
13 NB_G 2 0Ohm R2330 1 2 0Ohm G_GREEN 42
47PF 50V
/A7U /A7K
/x
R2331 1 2 0Ohm BLUE R2332 1 2 0Ohm
13 NB_B G_BLUE 42
R2333 6 8KOhm GND
B B
/A7U /A7K 1 2
R2337 33Ohm
R2334 1 2 0Ohm HSYNC R2335 1 2 0Ohm CRT_SCL 1 2 CRT_SCL_CON 15
13 NB_H G_HSYNC 42 48 DCLK
/A7U /A7K
4 3 NB_DACSDA CRT_SDA 3 4
Title : A7K
42 GCRT_DDCDAT NB_DACSDA 13
ASUSTECH CO LTD Engineer: Endy Zhang
Q2304B Q2305B Size Project Name Rev
UM6K1N UM6K1N
/x
Custom CRT And TV Connector 20
Date: 14 2007 Sheet 23 of 69
5 4 3 2 1
5 4 3 2 1
+3VS
22 23 GPU 2C_EN
+3VS +3VS
Q9201B Q9202B
HDMI_SDA_CON UM6K1N UM6K1N
/X
3 0OHM 4 RN2402B
/A7U TMDS_TX0P_R
12 TMDS_TX0P
R2420
TMDS_TX2P_R 1 TMDS_TX1N_R
TMDS_TX2N_R TMSD_Data2+ 12 TMDS_TX1N
3 2
C /A7K TMSD_Data2 TMSD_Data2_Sh eld TMDS_TX1P_R C
5 4 1 0OHM 2 RN2403A
33Ohm R2404 TMDS_TX0P_R TMSD_Data1_Sh eld TMSD_Data1+ TMDS_TX1N_R
7 6
TMDS_TX0N_R TMSD_Data0+ TMSD_Data1
42 DVI_DETECT 2 1 9 8 /A7U
TMSD_Data0 TMSD_Data0_Sh eld TMDS_TXCP_R
11
TMSD_Clock_Shield TMSD_Clock+
10 3 0OHM 4 RN2404B
13 12 TMDS_TXCN_R
HDMI_SCL_CON CEC TMSD_C ock +5VS TMDS_TX2P_R
15 14 12 TMDS_TX2P /A7U
33Ohm R2405 R2406 SCL Reserved HDMI_SDA_CON D2401 F01J2E
17 16
DDC CEC_GND SDA
13 TMDS_HPD 2 1 TMDS HPD CON 2 1 19 18 +5VS_DVI 2 1
Hot_Plug_Detect +5_Power
20KOhm TMDS_TX2N_R
12 TMDS_TX2N
/A7U
+3VS C2400 1 2 RN2404A
0OHM
D2402 R2407 4700PF/25V
BAV99 /A7U
100KOhm 3 4 RN2405B
0OHM
R2422 +3VS
/A7U TMDS_TXCP_R
12 TMDS_TXCP
A7K 10KOhm GND
HOTPLUG# TMDS_TXCN_R
Q2410 12 TMDS_TXCN
GND GND
2N7002 3 1 2 RN2405A
D 0OHM
/A7U
TMDS_HPD_CON 11 HOTPLUG# 13 23
G
2 S 3 4 RN2406B
0OHM
/A7K
/A7K TMDS_TX0P_R
42 DVI_A_TX0+
GND R2408
B TMDS_TX0P_R /x R2409 B
2 1
2 1 TMDS_TX1P_R /x TMDS_TX0N_R
42 DVI_A_TX0
R2416 1 2 180Ohm
499OHM R2410 R2417 1 2 180Ohm 1 0OHM 2 RN2406A
TMDS_TX0N_R 499OHM R2411
2 1
+3VS Q2406 /A7U 2 1 TMDS_TX1N_R /A7K
2N7002 3 +3VS Q2407 /A7U
D 499OHM 1 0OHM 2 RN2407A
2N7002 3
D 499OHM
/A7K TMDS_TX1P_R
42 DVI_A_TX1+
11 /A7U
G 11 /A7U
2 S G
2 S TMDS_TX1N_R
42 DVI_A_TX1
3 0OHM 4 RN2407B
/A7U
GND /A7U /A7K
GND 3 4 RN2408B
0OHM
/A7K TMDS_TX2P_R
42 DVI_A_TX2+
TMDS_TX2N_R
42 DVI_A_TX2
R2412 /x R2413
2 1 TMDS_TX2P_R 2 1 TMDS_TXCP_R /x 1 2 RN2408A
0OHM
R2418 1 2 180Ohm R2419 1 2 180Ohm /A7K
499OHM R2414 499OHM R2415 3 0OHM 4 RN2409B
2 1 TMDS_TX2N_R 2 1 TMDS_TXCN_R
+3VS Q2408 /A7U +3VS Q2409 /A7U /A7K TMDS_TXCP_R
2N7002 3 2N7002 3 42 DVI_A_CLK+
A
D 499OHM D 499OHM A
11 /A7U 11 /A7U
42 DVI_A_CLK
TMDS_TXCN_R
G G
2 S 2 S 1 2 RN2409A
0OHM
/A7K
/A7U
GND
/A7U
GND
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom DVI 20
Date: 14 2007 Sheet 24 of 69
5 4 3 2 1
5 4 3 2 1
+3V
PCI_C/BE#0
PCI_C/BE#1
PCI_PAR 17 38 +3VSUS
+3VSUS_LAN
PCI_SERR# 17 38
PCI_PERR# 17 38
RN2500A
PCI_STOP# 17 38
PCI_DEVSEL# 17 38 10KOhm
PCI_TRDY# 17 38
N/A
+3VSUS R2515 1 2 R2501
PM_CLKRUN# 17 28 38
D 0Ohm RN2500B 10KOhm D
10KOhm
R2500
+3VSUS_LAN
3 6KOhm Q2500
U2303
EECS U2304
1 8
EESK CS VCC RTL8110SC_GR
2 7 GND 38 PCI_PME# E C PCI_PME#_SB 18
EEDI/AUX 3 SK DC C2500
6
EEDO DI ORG
4 5
DO GND 0 1UF/16V
AT93C46
PMBS3904
GND 1 2
CTRL18
L2501 /x 5 6KOhm
VDD15 1 2 +3VSUS_LAN
AVDD18
+3VSUS_LAN VDD15
27 28 66 67 SUSB_EC1#
GND GND
GND GND GND
+3VSUS +3VSUS_LAN
C2519 2 1 0 01UF/16V 2 1 MDI0+ AVDD33
R2507 2 1 49 9Ohm MDI0
/x R2508 /x 49 9Ohm
C2520 2 1 0 01UF/16V 2 1 MDI1+ 30 mil L2503 30 mil L2504
/x
R2510 2 1 49 9Ohm MDI1 1 2 1 2
/x R2509 /x 49 9Ohm
C2521 2 1 0 01UF/16V 2 x 1 MDI2+ 120Ohm/100Mhz 120Ohm/100Mhz
R2513 2 1 49 9Ohm MDI2
/x R2511 /x 49 9Ohm C2523 C2524 C2525 C2526 C2527 C2528 C2529 C2530 C2531 C2532
A C2522 MDI3+ A
2 1 0 01UF/16V 2 x 1 0 1UF/16V 10UF/10V 0 1UF/16V 0 1UF 16V 0 1UF/16V 0 1UF 16V 0 1UF/16V 0 1UF/16V 0 1UF/16V 0 1UF/16V
R2512 2 1 49 9Ohm MDI3
/x R2514 /x 49 9Ohm
/x
GND
AVDD18 R2600
1 2 V_DAC
1 0OHM 2 RN2600A
D LTRLM3 D
GND L2600
MDI3 2 23 TRLM3
25 MDI3 TD1+ MX1+ LTRLP3
1 24 CMT3
TCT1 MCT1
3 0OHM 4 RN2600B
MDI3+ 3 22 TRLP3
25 MDI3+ TD1 MX1 CON2600 MODULAR_JACK_12P
1 0OHM 2 RN2601A 4 L26031KOhm/100Mhz 1 17
MDI2 TRLM2 SIDE2 RJ11_RING_CON 1 RJ11_R NG 1 SIDE1
25 MDI2 5 20 2 2 2 15
TD2+ MX2+ LTRLM2 2 RJ11_TIP_CON 1 RJ11_TIP 2 P_GND1
1 2 3 13
CMT2 1 3 NP_NC1
4 21 3 4
TCT2 MCT2 SIDE1 L26 1KOhm/100Mhz
2 LTXP 4
5
MDI2+ TRLP2 LTXN 5
25 MDI2+ 6 19 6
TD2 MX2 LTRLP2 WTOB_CON_2P LRXP 6
7
LTRLP2 7
8
MDI1 RXN LTRLM2 8
25 MDI1 8
TD3+ MX3+
17 3 0OHM 4 RN2601B 9
9
LRXN 10 14
RXC LTRLP3 10 NP_NC2
7 TCT3 MCT3 18 11 11 P_GND2 16
LTRLM3 12 18
MDI1+ RXP 12 SIDE2
25 MD 1+ 9
TD3 MX3
16 1 0OHM 2 RN2602A
J2600
LRXN
MDI0 11 14 TXN GND
25 MDI0 TD4+ MX4+
10 15 CMT
TCT4 MCT4 LRXP
MDI0+ 12 13 TXP
25 MD 0+ TD4 MX4
3 0OHM 4 RN2602B
GSM5009
C 1 2 RN2603A C
0OHM
LTXN R2610
1 2
0Ohm
LTXP
3 0OHM 4 RN2603B
GND GND_LAN
CMT3 1 RN2604A
75Ohm 2
CMT2 5 RN2604C
75Ohm 6 C2604
RXC 3 RN2604B
75Ohm 4
CMT 7 RN2604D FGND1S R2611
75Ohm 8 2 1
1 2
1000PF/2KV
0Ohm
C2605
2 1
GND_LAN
+3VS
+3VAUX_MINI_PCIE
B CON2601 B
1 2 R2603 1 2 0Ohm +3VSUS
18 25 27 SB_WAKE# WAKE# 3 3V_1 +1 5VS
36 CoEX_DATA 3 4
Reserved1 GND7 R2604 1
36 CoEX_CLK 5 6 2 0Ohm +3V
R2612 1 Reserved2 1 5V_1
16 MINI_PC E_CLKREQ# 2 0Ohm 7
CLKREQ# UIM_PWR
8 C2606 C2608
9 10 0 1UF 16V 22UF/10V /x R2605
GND1 UIM_DATA +3VS MIN PCIE_RESET#
16 GPP1_CLK_N 11 12 13 17 27 28 37 40 41 49 A_RST# 1 2
REFCLK U M_CLK
16 GPP1_CLK_P 13 14
REFCLK+ UIM_RESET R2601 0Ohm
15 16
GND2 UIM_VPP
1 2
GND C2607
17 18 10KOhm 0 1UF/16V
Reserved/UIM_C8 GND8
19 20
Reserved/UIM_C4W_DISABLE# MINIPCIE_RESET# 3 /x /x
21 GND3 PERST# 22 D
R2602 1 2 0Ohm GPP_C_RXN1 23 24
12 GPP_RXN1 PERn0 +3 3Vaux
R2606 1 2 0Ohm GPP_C_RXP1 25 26 Q2600
12 GPP_RXP1 PERp0 GND9 11
27 28 0Ohm GND
GND4 1 5V_2 2N7002 MPCI_WLAN_ON/OFF# 52
29 30 R2607 1 2 S 2
G
GPP_TXN1 GND5 SMB_CLK SMBCLK_SYS 18 27
1 2 31 32 R2608 1 2 /x
12 GPP_C_TXN1 GPP_TXP1 PETn0 SMB_DATA SMBDAT_SYS 18 27
C2609 0 1UF/16V 1 2 33 34
12 GPP_C_TXP1 PETp0 GND10
C2610 0 1UF/16V 35 36 0Ohm CON2602
GND6 USB_D
37 Reserved3 USB_D+ 38 1 SIDE1 SIDE2 2
39 40 GND 5 6
Reserved4 GND11 T1920 R2609 NP_NC1 NP_NC2
41 Reserved5 LED_WWAN# 42 3 SIDE3 SIDE4 4
43 Reserved6 LED_WLAN# 44 1 1 2
45 46 TPC28T MINI_PCI_LATCH_4P
Reserved7 LED_WPAN# 0Ohm
47 Reserved8 1 5V_3 48
49 Reserved9 GND12 50
51 52 +3VS +1 5VS GND
Reserved10 3 3V_2 GND
53 GND13 NP_NC2 56
A A
54 GND14 NP_NC1 55
C2611 C2612 C2613 C2614 C2615 C2616 C2617
MINI_CARD_LATCH_52P 0 1UF 16V 0 1UF/16V 22UF/10V 0 1UF/16V 0 1UF/16V 0 1UF/16V 22UF/10V
GND
GND
GND GND Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Mini PCIE WLAN 20
Date: 14 2007 Sheet 26 of 69
5 4 3 2 1
5 4 3 2 1
+3VSUS
Rev 2.0
R2700
100KOhm
D D
DEBUG_EN#
CON2700 CLK_NEWCARD_REQ# /X 1 0OHM 2 RN2700A CLKREQ#_R
1 29 SB_WAKE# /X 5 6 RN2700C PE_WAKE#_R Q2700
GND1 P_GND1 0OHM
USB_PN7 2 31 SMBCLK_SYS /X 3 4 RN2700B SMBCLK_R
USB_D GND5 0OHM C2700
USB_PP7 3 27 SMBDAT_SYS /X 7 8 RN2700D SMBDATA_R R2703 D2700
USB_D+ NP_NC1 0OHM
CPUSB# 4 B 1 2 2 1 2 1 PERST#
LPC_FRAME#_R CPUSB# NEWCARD_PRSNT# R2702 1 NEWCARD_PRSNT#_R
5
RESERVED1 2 0Ohm
6 200KOhm 1SS355 1000PF/16V
SMBCLK_R RESERVED2
7 /x
SMBDATA_R SMBCLK C2701
8
SMBDATA U2700 R2705
+1 5VS_PE 9 0 47UF/16V
+1 5V_1 NEWCARD_PRSNT#_R PMBS3904
10 17 LPC_CLK_DEBUG 3 2 100KOhm
PE_WAKE#_R +1 5V_2 A0 C0 CLKREQ#_R
11 17 28 37 LPC_AD3 7 6
WAKE# A1 C1 PE_WAKE#_R
+3VSUS_PE 12 17 28 37 LPC_AD0 11 10
NEWCARS_RST PERST# +3 3VAUX A2 C2 SMBCLK_R
1 2 13
PERST# 17 28 37 LPC_AD1 17
A3 C3
16
14 21 20 SMBDATA_R
+3VS_PE +3 3V_1 17 28 37 LPC_AD2 A4 C4
R2701 4 7KOhm 15
CLKREQ#_R +3 3V_2 NEWCARD_PRSNT#
16 4 5
NEWCARD_PRSNT#_R CLKREQ# R2704 1 B0 D0
17 16 CLK_NEWCARD_REQ# 2 0Ohm 8 9
CPPE# R2706 1 B1 D1
16 GPP2_CLK_N 18
REFCLK 18 25 26 SB_WAKE# 2 0Ohm 14
B2 D2
15 17 28 37 LPC_FRAME#
16 GPP2_CLK_P 19 18 26 SMBCLK_SYS 18 19
REFCLK+ B3 D3
20 18 26 SMBDAT_SYS 22 23
R2707 GPP_C_RXN2 GND2 B4 D4
13 GPP_RXN2 2 1 0Ohm 21
PERn0
R2708 2 1 0Ohm GPP_C_RXP2 22 +5VSUS
13 GPP_RXP2 PERp0
1 2 GPP_TXN2
23
24
GND3
28 DEBUG_EN#
1
13
BE# VCC
24
12
Rev 2.0
13 GPP_C_TXN2 PETn0 NP_NC2 BX GND +3VS
C2702 0 1UF/16V 1 2 GPP_TXP2 25 32 !ExpressCard Standard 1.0:
13 GPP_C_TXP2 PETp0 GND6
C2703 0 1UF/16V 26 30 SN74CBT3383PWR C2704
C GND4 P_GND2 Change Pin7 from RESERVED to SMBCLK 0 1UF/16V U2701 C
Change Pin8 from SMBCLK to SMBDATA DEBUG_EN# 1
OE# VCC
5
EXPRESS_CARD_26P 2
+3VSUS Change Pin9 from SMBDATA to +1.5V A LPC_FRAME#_R
3 4
GND Y
74LVC1G125GV
R2709
10KOhm GND
U2702 T2700
D2701 1 19 1 TPC28T
25 28 66 67 SUSB_EC1# STBY# OC#
28 56 57 68 VSUS_ON 2 1 20 11 +1 5VS_PE
SHDN# 1 5VOUT_1
8 13
PERST# 1 5VOUT_2
1SS355
NEWCARS_RST +3VS
2 15 USB_PP7
+3VS 3 3VIN_1 AUXOUT +3VSUS_PE 18 USB_PP7
4 R2711 10KOhm
3 3VIN_2 CLK_NEWCARD_REQ#
1 2
+1 5VS 14 3 +3VS_PE
1 5VIN_1 3 3VOUT_1
12 5
1 5VIN_2 3 3VOUT_2 3
x D
17 10 NEWCARD_PRSNT# Q2701 USB_PN7
+3VSUS AUXIN CPPE# 18 USB_PN7
9 CPUSB# 2N7002
CPUSB# NCP# 18
13 17 26 28 37 40 41 49 A_RST# 6 18 REFCLK_EN 11
SYSRST# RCLKEN G
7
21
GND1
16 2 S D2702 D2703
GND2 NC RSB6 8S RSB6 8S
R5538D001 /X /X
/x
B B
+3VS
C2711 C2712 C2713 C2714 C2715 C2716 C2717
10UF/10V 0 01UF/16V 10UF/10V 10UF/10V 0 01UF 16V 10UF/10V 0 01UF/16V CON2701
1 14
LPC_AD0 1 SIDE2
2
2
3
LPC_AD1 3
4
4
5
LPC_AD2 5
6
6
7 7
LPC_AD3 8 8
9 9
LPC_FRAME# 10 10
11 11
17 LPC_CON_DEBUG 12 12 SIDE1 13
FPC_CON_12P
12G183301208
A
GND
Bottom Contact A
/DEBUG
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom New Card 20
Date: 14 2007 Sheet 27 of 69
5 4 3 2 1
5 4 3 2 1
R2820
+3VA_EC +3VPLL +3VS +3VACC 0Ohm +3VA_EC
1 2 +3VA_EC
+3VA
R2822 C2801 C2802 C2803
0Ohm 10UF 10V 0 1UF 16V 0 1UF/16V
1 2
U2800
17 27 37 LPC_AD0 15 163 SMCLK_BAT 65
LAD0 SMCLK0 GPB3
17 27 37 LPC_AD1 14
LAD1 SMDAT0 GPB4
164 SMDATA_BAT 65 to Battery
13 169 GND
17 27 37 LPC_AD2 LAD2 SMCLK1/GPC1 SMB1_CLK 21 48
17 27 37 LPC_AD3 10
LAD3 SMDAT1/GPC2
170 SMB1_DAT 21 48 to Thermal
18 +3VA_EC R2803 R2800
D 17 LPC_CLK_EC LPCCLK D
9 81 R2806 10KOhm 0Ohm 0Ohm
17 27 37 LPC_FRAME# LFRAME# ADC0/GPK0 BAT0_AD 29
EC_LPCRST# 30 82 NV_OVERT# 1 N/A 2 1 2 +3VACC 1 2
LPCRST#/WUI4 GPD2 ADC1/GPK1 OTEMP# 42
7 83 C2804
17 37 38 INT_SERIRQ SERIRQ ADC2/GPK2 AC_AD 29
22 84 1 T2802 TPC28T C2806
18 LPC_SMI# ECSM #/GPM0 ADC3/GPK3 KID0
31 93 10UF/10V
18 KB_SCI# ECSCI#/GPD3 ADC8/GPK4
5 94 KID1 0 1UF/16V GND EC_AGND
18 A20GATE_SB600 GA20 GPB5 ADC9/GPK5
18 KBRST#_SB600 6
EC RST# KBRST# GPB6 T2807 TPC28T
29 EC_RST# 19 99 1
T2803 WRST# DAC0/GPJ0 T2804 TPC28T GND GND
1 23
PWUREQ#/GPM1 DAC1/GPJ1
100 1
TPC28T 101 BRIGHT_PWM 22 R2801
DAC2/GPJ2
29 FRD# 150 102 BATSEL_2P# 63
FRD# DAC3/GPJ3 +3VPLL
29 FWR# 151 2 1
???
FWR# T2809 TPC28T
29 FCS# 173 32 1
FCS# PWM0/GPA0
29 FD0 138 33 FAN_PWM 21
FD0 PWM1/GPA1 T2805 TPC28T 0Ohm
29 FD1 139 36 1
FD1 PWM2/GPA2 T2806 TPC28T C2805
29 FD2 140 37 1
FD2 PWM3/GPA3 0 1UF 16V
29 FD3 141 38 CHG_LED_UP# 50
FD3 PWM4/GPA4
29 FD4 144 39 PWR_LED_UP# 50
FD4 PWM5/GPA5 T2811 TPC28T +3VS
29 FD5 145 40 1
FD5 PWM6/GPA6 GND
29 FD6 146 FD6 PWM7/GPA7 43 BACK_OFF# 22
29 FD7 147
FD7 C2800 +3VS
29 FA0 124 153 NUM_LED 50 AC_IN_OC# 65
FA0 RXD GPB0
29 FA1 125 154 CAP_LED 50
FA1 TXD GPB1 T2808 TPC28T 0 1UF 16V
29 FA2/ BADDR0 126 162 1
FA2/BADDR0 GPB2 C2807
29 FA3/ BADDR1 127 165 THRO_CPU 7
FA3/BADDR1 RING#/PWRFAIL# LPCRST#/GPB7 0 01UF 16V
29 FA4/ PPEN 128
FA4/PPEN
29 FA5/ SHBM 131 47 DJ_LED# 50
FA5/SHBM CLKOUT/GPC0 PWRLMT# GND
29 FA6 132 171 PWRLMT# 7 63
FA6 GPC3 GND KSO3
29 FA7 133 172 2 3 DJ_SCAN 50
FA7 TMR 0/WUI2/GPC4
29 FA8 143 175 OP_SD# 31
FA8 GPC5
29 FA9 142 176 BAT1_IN_OC# 65
FA9 TMR 1/WUI3/GPC6
29 FA10 135 1 EC_IDE_RST# 35
C FA10 CK32KOUT/GPC7 Q2801 2N7002 C
29 FA11 134
FA11 PM_SUSB# C2808
29 FA12 130 26 PM_SUSB# 18
FA12 RI1#/WUI0/GPD0 PM_SUSC# 0 01UF 16V
29 FA13 129 29 PM_SUSC# 18
FA13 RI2#/WUI1/GPD1
29 FA14 121 41 RF_OFF_SW# 52
FA14 GPD4
29 FA15 120 42
FA15 G NT/GPD5 GND
29 FA16 113 62 FAN0_TACH 21
FA16/GPG0 TACH0/GPD6
29 FA17 112 63 COLOREN# 50
FA17/GPG1 TACH1/GPD7 R2823 2 EC_GPE1#
29 FA18 104 1 10KOhm
FA18/GPG2 R2841 2 EC_GPF6#
29 FA19 103
FA19/GPG3 ADC4/GPE0
87 P4PHONE# 50 Email switch 1 10KOhm
88 EC_GPE1# R2842 2 1 10KOhm EC_GPJ4#
KSI0 ADC5/GPE1
29 KSI0 71 89 MARATHON# 50
KSI1 KSI0/STB# ADC6/GPE2
29 KSI1 72 90 DISTP_SW# 50
KSI2 KSI1/AFD# ADC7/GPE3
29 50 KSI2 73 2 PWRSW#_EC 50
KSI3 KSI2/INIT# PWRSW/GPE4 BAT2_IN_OC#
29 50 KSI3 74 44
KSI4 KSI3/SLIN# WUI5/GPE5 ME_ALERT#
29 50 KSI4 77 24
KSI5 KSI4 LPCPD#/WUI6 GPE6 R2832 1
29 50 KSI5 78 25 2 0Ohm PM_CLKRUN# 17 25 38
KSI6 KSI5 CLKRUN#/WUI7/GPE7 R2814 2 DVD/CD_ON#
29 KSI6 79 KSI6 1 10KOhm
KSI7 80 116 TPAD_CLK R2817 2 1 10KOhm TV_ON#_ NS
29 KSI7 KSO0 KSI7 PS2CLK2/GPF4 TPAD_DAT TPAD_CLK 29 BAT2_ N_OC#
29 KSO0 49 117 R2829 2 1 10KOhm
KSO0/PD0 PS2DAT2/GPF5 TPAD_DAT 29
29 KSO1 KSO1 50 118 EC_GPF6# R2831 2 1 10KOhm ME_ALERT#
KSO2 KSO1/PD1 PS2CLK3/GPF6 D2800
29 KSO2 51 119 DJSW# 50
KSO3 KSO2/PD2 PS2DAT3/GPF7
29 KSO3 52 2 1 PM_THERM# 19
KSO4 KSO3/PD3 +3VA_EC R2804 2 AC_IN_OC#
29 KSO4 53
KSO4/PD4 FA20/GPG4
3 LID_EC# 50 1 10KOhm
29 KSO5 KSO5 56 4 1 T2813 TPC28T R2805 2 1 10KOhm BAT1_ N_OC#
KSO6 KSO5/PD5 FA21/GPG5 1SS355
29 KSO6 57 27
KSO7 KSO6/PD6 LPC80HL/GPG6 AC_APR_UC# T2814 TPC28T R2807 2 10KOhm VSUS_GD_EC#
29 KSO7 58 28 1 1
KSO8 KSO7/PD7 LPC80LL/GPG7 R2809 2 10KOhm IMVPOK#
29 KSO8 59 Q2800 1
KSO9 KSO8/ACK# AC_APR_UC#
29 KSO9 60 48 R2813 1 2 0Ohm VSUS_ON 27 56 57 68
R2808 2 1 10KOhm
KSO10 KSO9/BUSY GPH0 3 R2811 2 10KOhm RF_OFF_SW#
29 KSO10 61 54 VSUS_GD_EC# 51 D 2N7002 1
KSO11 KSO10/PE GPH1 IMVPOK# R2810 2 10KOhm PWRLMT#
29 KSO11 64 55 MVPOK# 51 1
KSO12 KSO11/ERR# GPH2
29 KSO12 65 69 PM_PWRBTN# 18
KSO13 KSO12/SLCT GPH3 SUSC_EC# 11
29 KSO13 66 70 SUSC_EC# 66 AC_APR_UC 63
B KSO14 KSO13 GPH4 SUSB_EC0# 1 T2815 TPC28T G B
29 KSO14 67 75 S 2
KSO15 KSO14 GPH5 R2830 1 SMCLK_BAT
29 KSO15 68 76 CPU_VRON 51 55 2 4 7KOhm
KSO15 GPH6 R2834 1 SMDATA_BAT
GPH7
105 PM_RSMRST# 18 2 4 7KOhm
EC_XIN 158
EC_XOUT 160 CK32K EC_LPCRST_GATE
148
CK32KE GP 0 GND
149 PWRGD 13 18 33 67
GP 1
110 152 1 T2816 TPC28T Close to Switch
PS2CLK0/GPF0 GP 2
111 155 CHG_EN# 63
DVD/CD_ON# PS2DAT0/GPF1 GP 3 RN2801A P4PHONE# 1
114 156 PRECHG 63 1 10KOhm 2 2C2809 0 1UF 16V
TV_ON#_ NS PS2CLK1/GPF2 GP 4 R2833 COLOREN# 1
115
PS2DAT1/GPF3 GP 5
168 1 2 0Ohm BAT_LL# 18 3 10KOhm 4
RN2801B 2C2810 0 1UF 16V
174 /x 5 RN2801C MARATHON# 1 2C2811 0 1UF 16V
GP 6 BAT_LEARN 63 10KOhm 6
7 RN2801D DISTP_SW# 1 2C2812 0 1UF 16V
10KOhm 8
IT8511TE
+3VS +3VS R2815 2 1 10KOhm KID1
R2816 2 1 10KOhm KID0
R2818 2 1 10KOhm PM_THERM#
R2819 2 1 10KOhm TPAD_DAT GND
50 CIR_RX_EC EC_GPJ4# TPAD_CLK
R2821 2 1 10KOhm
GND EC_AGND 3 2 R2837 2 1 10KOhm A20GATE_SB600
CPU_THERMTRIP# 7 18 KBRST#_SB600
R2838 2 1 10KOhm
R2835 1 2 4 7KOhm SMB1_DAT
R2836 1 2 4 7KOhm SMB1_CLK
SUSB_EC1# 25 27 66 67 Q2802 LPC_SM #
R2839 2 1 10KOhm
2N7002 R2843 2 1 10KOhm NV_OVERT#
+3VA_EC
28 KSO7
KSO7
KSO0
CON2900
ISA ROM SST-PLCC32 4Mbits Flash ROM
PN:05G001014110
28 KSO0 26
KSI1 SIDE2 KSO7
28
28
KS 1
KS 7
KSI7
KSO9
1
2
1
2
3
KSO0
KSI1
(8Mbits) (FLASH SST SST39VF040-70-4C-NHE
4M-70 PLCC-32)
28 KSO9 3
KSI6 4 KSI7
28 KS 6 KSI5 4 KSO9
28 50 KS 5 5
KSO3 5 KSI6 U2900
28 KSO3 6
D KSI4 6 KSI5 D
28 50 KS 4 7
7 28 FA1 25
A0 DQ0
29 FD0 If need to use 8Mbits
28 ISA
KSI2 8 KSO3 24 31
28 50 KS 2
KSO1 8
9 KSI4
28 FA2/ BADDR0
23
A1 DQ1
33
FD1 ROM,could
8 choose
28 KSO1 9 28 FA3/ BADDR1 A2 DQ2 FD2 28
28 50 KS 3
KSI3
10
10 KSI2
28 FA4/ PPEN 22
A3 DQ3
35 FD3 SST39LF080.
28
KSI0 11 KSO1 21 38
28 KS 0
KSO13 11
12 KSI3
28 FA5/ SHBM
20
A4 DQ4
40
FD4 But it does not have PLCC32
28 KSO13 12 28 FA6 A5 DQ5 FD5 28
28 KSO5
KSO5
13
13 KSI0
28 FA7 19
A6 DQ6
42 FD6 package.
8
KSO2 14 KSO13 18 44
28 KSO2
KSO4 14
15 KSO5
28 FA8
8
A7 DQ7
30
FD7 ASUS
8 does not have part
28 KSO4 15 28 FA9 A8 DQ8
28 KSO8
KSO8
16
16 KSO2
28 FA10 7
A9 DQ9
32 number yet.
KSO6 17 KSO4 6 34
28 KSO6 17 28 FA11 A10 DQ10
KSO11 18 KSO8 5 36
28 KSO11 18 28 FA12 A11 DQ11
KSO10 19 KSO6 4 39
28 KSO10 19 28 FA13 A12 DQ12
KSO12 20 KSO11 3 41
28 KSO12 20 28 FA14 A13 DQ13
KSO14 21 KSO10 2 43
28 KSO14 21 28 FA15 A14 DQ14
KSO15 22 KSO12 1 45
28 KSO15 22 28 FA16 A15 DQ15/A 1 FA0 28
23 KSO14 48
23 28 FA17 A16
24 KSO15 17 26
24 28 FA18 A17 CE# FCS# 28
25 28 FA19 16 28 FRD# 28
SIDE1 A18 OE#
WE# 11 FWR# 28
9 12 EC_RST# 28
NC0 RESET#
10 15
FPC_CON_24P GND NC1 RY/BY#
13 47
+3VA_EC NC2 BYTE#
14
NC3
27
/A7K Vss1 R2915
37 46
Vcc Vss2 10KOhm
C2900 MX29LV800CTTC
1UF/10V
L2900 80Ohm/100Mhz
1 2 +V5S_TPAD 1 7
GND1
2
TPAD_DAT 3
28 TPAD_DAT
TPAD_CLK 4
28 TPAD_CLK
C2902 5
0 1UF/16V 6 GND2 8
U2901
GND
GND
B B
BAT
12.6V BADDR[1:0] EC Hardware Strap
+3VACC
No pull up:
R2901 R2902
10KOhm 10KOhm The register pair to access PNPCFG is 002Eh and
D2900 /x 002Fh
R2900 1N4148W Ext 10K up on BADDR0:
12 4KOhm /X FA2/ BADDR0 FA3/ BADDR1 The register pair to access PNPCFG is 004Eh and strap value sampled after
X R2903
1KOhm
004Fh VSTBY power up reset
1 /x 2 R2905 R2906 Ext 10K up on BADDR1:
BAT0_AD 28
10KOhm 10KOhm The register pair to access PNPCFG is determined
3V /x by EC domain registers SWCBALR and SWCBAHR
R2904 C2903
3 92KOhm D2901
X 1N4148W 0 1UF/16V
/X /x GND GND
GND
32 L NE1_JD R3012 2 1 10KOhm
SHORTPIN /X
GND
GND_AUDIO
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom ALC660 20
Date: 14 2007 Sheet 30 of 69
5 4 3 2 1
5 4 3 2 1
C3124 2 1 680PF/50V
R3113 1 2 10KOhm
(Headphone Mode) FH = 23.4KHz C3125 2 1 680PF/50V D3100
+3VSUS +12V
R3114 1 2 10KOhm 2 1
30 EAPD
R3117
1N4148W 2 2MOhm
R3115 1 2 0Ohm R3116
30 660_C_MUTE#
D3101 /x 10KOhm
1 5 /x r0402 1 R3118 2 MUTE_POP#
10KOhm
D3102 3
D
2 R3119 1 2 0Ohm 1
30 660_D_MUTE#
GND_JACK /x GND_JACK 3
2 3 11 C3126
28 OP_SD# D
3 4 LINE2_JD G 0 1UF 16V
30 AC_HP_R LINE2_JD 30
RB717F 2 S Q3100 c0402
G
S 2 DF5A6 8FU C3127
18 30 CODEC_RST#
CODEC_RST# 2 R3120 1 11 2N7002
1 Q3101 10PF/50V 100KOhm G
S
Q3102 2 2N7002
1
0402
2N7002
3
D
J3100
Fix POP of the internal speaker
CE3100 GND_JACK 6
when power-on GND
CE3101 R3121
1 2 1 2 75Ohm 120Ohm 100Mhz 1 2 L3101 1
1 2 R3122 1 2 75Ohm 120Ohm 100Mhz 1 2 L3102 4
B L3103 1 120Ohm/100Mhz B
100UF/6 3V 2 5
100UF/6 3V
JACK_IN# 7
3 C3128 C3129 11
D +5VS_AMP
Q3103 R3123 R3124 331K 331K C3130
10KOhm 10KOhm
R3.0---ITEM59 GND_AUDIO 100PF/50V
12
2N7002
MUTE_POP# 11 c0402 A GND 9
G VCC_SPDIF x B V C MS 10 D3103
2 S C V n JACK_IN# 2 1
10KOhm
R3125 GND_JACK GND_JACK GND_JACK 1SS355 r0402
30 AC_HP_L
GND_AUDIO GND_AUDIO 1 2 PHONE_JACK_8P
r0603_h24 GND_JACK CODEC_RST# 2 R3126 1 10Ohm
0Ohm C3131 P/N:12G140001089 100KOhm 2 R3130 1 SE BTL#
0 1UF/16V r0402
c0402 3
D
+3VS D3104 Q3104
OP_SD# 1 R3128 C3132
2N7002
R3127 GND_JACK 32 1 11
1 0Ohm 2 SPDIF_VIN R3131 1 2 0Ohm 2 1KOhm G 1UF/10V
17 30 SPDIF_OUT 30 660_D_MUTE#
r0603_h24 2 S
Q3105 C3133 RB717F
100PF/50V C3134
c0402
+5VS_AMP PMBS3906 R3132 1 2 0Ohm 2 2UF/10V
30 660_C_MUTE#
B /x
GND_JACK R3129
L NE2_JD R3135 D3105 GND_AUDIO
2 1 GND GND_AUDIO
R3134 Q3106 2 1
30 EAPD
R3133 100KOhm 10KOhm
r0402 r0402 VCC_SPDIF EMI Request
A 0Ohm 1N4148W A
/x
B 1 0Ohm 2
C3135 R3136 Fix POP of the internal speaker
0 1UF 16V PMBS3904
c0402 when power-off /x
/x +5VS_AMP GND GND_JACK
R3137
GND_AUD O JACK_ N# 2 1
100KOhm
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom AMP And Headphone 20
Date: 14 2007 Sheet 31 of 69
5 4 3 2 1
5 4 3 2 1
D D
30 MIC_VREFOUT_L
C3202
GND_JACK 10PF/50V
R3203
4 7KOhm J3200
30 MIC1_JD 5
4 7
3 R 8
L3201 6 9
30 M C_IN_AC_E 1 2 2 10
1 L
+5V_AUDIO 120Ohm/100Mhz AUDIO JACK
PHONE_JACK_6P
C3203 C3204
1UF/10V 10PF 50V
R3207
/x 4 7KOhm
R3208
2 /x 1
C3207 4 7KOhm
R3210 GND_JACK GND_JACK GND_JACK
0 1UF/16V 4 7KOhm
c0402 /x
/x 1 2 0Ohm
R3211
GND_AUDIO GND_AUDIO
C GND GND_JACK C
EMI Request
LINE1_VREF LINE1_VREFOUT
L NE1_VREFOUT 30 R3215 /x
1 2 LINEIN_R
L NE1_JD 30
R3213 R3214 0Ohm
C3209
0Ohm 0Ohm R3216 /x 1000PF/16V
/x LINE N_L c0402
1 2
B B
2 10KOhm 1 0Ohm
R3217 2 1 20KOhm GND_JACK
R3218 J3201
+5V_AUD O 1UF 10V LINE1_JD 5
+5V_AUDIO U3201 120Ohm/100Mhz 4 7
8 VCC + A+ 3 R3219 2 10KOhm 1 C3210 1 2 LINEIN_R_L L3204 1 2 L NEIN_R_C 3 R 8
LINE N_R 1 6 9
30 LINEIN_R A
AO 2 2 R3220 1 R3221 2 10KOhm 1 C3211 1 2 LINEIN_L_L L3205 1 2 L NEIN_L_C 2 10
20KOhm 1 L
B+ 5 1UF 10V 120Ohm/100Mhz AUDIO JACK
+
7 BO C3213 C3214 PHONE_JACK_6P
R3222 4 GND B 6 2 R3223 1 C3212 1 2 1UF/10V R3224 R3225 1000PF/16V 1000PF/16V
20KOhm c0402 c0402
47KOHM 47KOHM 47KOHM /x /x
GND_AUDIO LM358MX /x x
LINE1_VREF LINE N_L R3226 2 1 20KOhm
30 LINE N_L
GND_AUDIO GND_AUD O GND_AUDIO GND_JACK GND_JACK GND_JACK
2 10KOhm 1
R3227 C3215
22UF 6 3V C3217 R3228
47KOHM C3216
1UF/10V 22UF/6 3V C3218 R3229 R3230
0 1UF/16V 1 2 0Ohm
c0402 0Ohm 0Ohm R3231
/x
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom MIC And Line in 20
Date: 14 2007 Sheet 32 of 69
5 4 3 2 1
5 4 3 2 1
+2 5VS
D D
SHI_DAT RN3300A1
Option Bit[7] 8 2KOhm2
DSP_GPIO5 RN3300B3
8 2KOhm4
BOM: 06G110001011 RN3300D7
8 2KOhm8
DSP_DRx RN3300C5
8 2KOhm6
30 MIC2_VREFOUT Option Bit[5] CHI_TX RN3301A1
Option Bit[4] 8 2KOhm2
CHI_RX RN3301B3
Option Bit[3] 8 2KOhm4
R3300 CHI_BCLK RN3301D7
Option Bit[2] 8 2KOhm8
C3300 CHI_LRCK RN3301C5
2 2KOhm 8 2KOhm6
0 1UF 16V
+2 5VS +2 5VS_ADC +2 5VS Option Bit[0] DSP_DTx RN3302B3
8 2KOhm4
DSP_GPIO1 RN3302A1
8 2KOhm2
DSP_GPIO0 RN3302D7
8 2KOhm8
GND_AUDIO 1 2 +2 5VS_ADC DSP_TEST RN3302C5
8 2KOhm6
L3301 120Ohm/100Mhz C3302
C3301 VCC = 2 7V 5 5V
0 1UF 16V ICC(max) = 3 mA GND
C3303
R3301 R3302 0 1UF/16V
22 MIC_ NT_P 1 2 1 2 1 2 1 2
R3326
0Ohm 100Ohm 0Ohm GND_AUD O GND
C3305 0 1UF/16V
C3306 Side Tone Cancellation on/off
R3304 0 012UF/50V R3305 DSP_GPIO3 R3307 2 1 10KOhm
1 2 1 2 1 2 1 2 C3307 C3308
22 MIC_INT_N High/Low noise suppression level DSP_GPIO2
R3327 R3308 2 1 10KOhm
0Ohm 100Ohm 0Ohm
0 1UF/16V
R3306 0 1UF/16V 0 1UF/16V GND
2 2KOhm
C C
GND_AUDIO +2 5VS
+2 5VS
U3301
SHI_CLK R3311 2 1 10KOhm
GND_AUDIO Option Bit[1]:
C3311 Pull down for H/W R3312 1 2 100KOhm
37 24 DSP_GPIO4 0 1UF 16V
C3309 NC1 GPIO_4 debug from ext
R3313 R3310 38 23 DSP_GPIO3 x
NC2 GPIO_3 DSP_GPIO2 tool kit GND
30 L NE_IN_DSP 1 2 1 2 1 2 39
M C0_P GPIO_2
22
40 21 DSP_GPIO1
3 6KOhm R3314 0Ohm M C0_N GPIO_1 DSP_GPIO0 GND
41 20
C3310 0 1UF/16V NC3 GPIO_0
1KOhm C3312 42 19
R3315 NC4 VSS_D_G2
0 047UF/16V 43 18
LI_P VDD1 DSP_DTx +2 5VS
1 2 1 2 44
LI_N DTx
17
VD_R 45 16 DSP_DRx Option Bit[6]:
0Ohm BG_R VD_R DRx SHI_CLK DSP_GPIO4 R3316 1
46 BG_R CTS_SCL 15 Source from 2 100KOhm
0 1UF/16V SHI_DAT
47 14
GND_AUDIO 48
LO_P RTS_SDA
13 DSP_TEST 0: EEPROM R3317 1 2 100KOhm
LO_N TEST 1: Serial Host
C3313
R3319 R3320 Interface (SHI) x
1 2 NT_MIC_DSP 1 2 1 2 1 2 GND
30 MIC_ N_AC_I
R3318
0Ohm 100Ohm 0Ohm VP1010
C3314 0 1UF/16V
C3315
0 047UF/16V R3321
1 2 1 2
/X R3322 1MOhm
0Ohm 1 2
0 1UF/16V
GND_AUD O
+2 5VS_ADC
B DSP_SHI_EN 18 B
X330018 432Mhz
C3316 C3317 C3318 C3319 C3320 1 3
GND
1206
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom DSP 20
Date: 14 2007 Sheet 33 of 69
5 4 3 2 1
5 4 3 2 1
+3V
MDC 1
L3400
2
120Ohm/100Mhz
H3400 H3401
H3402
CON3400 +
CE3400 1 9 1 9 H3421
D C3400 2 8 2 8 1 9 1 /x D
100UF/6 3V
1 2 0 1UF/16V /X 3 7 3 7 2 8 CT256CB169D134
1 2
18 MDC_SDOUT 3 4 4 6 4 6 3 7
3 4 H3422
5 6 5 5 4 6
5 6 GND GND D4 D4 /x
18 MDC_SYNC 7 8 5 1
7 8 4
18 ACZ_SD N1 1 2 9 10 C276D91N C276D91N CT256CB169D134
R3400 22Ohm 9 10 GND GND GND GND
18 MDC_RST# 11 12 MDC_BCLK 18 C276D91N
11 12 GND GND H3423
/X /X 1 /x
BTOB_CON_12P C3401 X CT256CB169D134
1000PF/16V H3403 H3404 H3405 H3424
/x 1 /x
1 9 1 9 1 9 CT256CB169D134
GND P/N: GND GND
2
3
8
7
2
3
8
7
2
3
8
7
12G161200120 4 6 4 6 4 6
GND
4
5
4
5
4
5 CPU
C276D91N CRT276X295BD91N CRT276X295BD91N
GND GND GND GND GND GND
/X /X X
H3406 H3407 H3408
H3425
1 9 1 1 9 E40M20
2 8 2 5 2 8
3 7 3 4 3 7 H3426
4 6 4 6
5 5
4 4
C E40M20 C
CRT276X285BD91N CRT236X315D91N C276D91N H3427
GND GND GND GND GND GND
/x /x X
E40M20
H3409 H3410 H3411
1 9 1 9 1 9 GND
2 8 2 8 2 8
3
4
7
6
3
4
7
6
3
4
7
6
VGA
5 5 5
4 4 4
13GNCF10M010
C276D91N C276D91N C276D91N
GND GND GND GND GND GND
H3428
/X /X /X
L4E_1A
H3412 H3413 H3414
H3429
1 9 1 9 1 9 GND_JACK
/x
2 8 2 8 2 8
3 7 3 7 3 7 L4E_1A
4 6 4 6 4 6
5 5 5
D4 D4 4 GND
/x
GND
C276D91N
GND GND
C276D91N
GND GND
C276D91N
GND
MDC NUT
/X /X /X
B B
1 9 1 9 1 9 H3430
2 8 2 8 2 8 1
NP_NC1
3 7 3 7 3 7 2
NP
4 6 4 6 4 6 3
G 16
5 5 5 4 15
D4 4 4
5 14
C276D91N C276D91N C276D91N 6 13
GND GND GND GND GND GND 7 12
8 11
/X /X /X 9 GN D8 10
H3418 HOLE_2NPTH
1 9 GND /X GND
H3419 H3420
2
3
8
7
D
4 6 1 9 1 9
4 5 2 8 2 8
3 7 3 7
C276D91N 4 6 4 6
GND GND 5 5
D4 D4
/X C276D79N C276D91N
GND GND GND GND
/X /X
E
A G A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom MDC 20
Date: 14 2007 Sheet 34 of 69
5 4 3 2 1
5 4 3 2 1
D +5VS D
19 IDE_PDD[15 0]
CON3500 R3500
10KOhm
1 2 +5VS
30 CD_L_A CD_R_A 30
30 CD_GND_A 3 4
IDE_RST# 5 6 IDE_PDD8 IDE_PDASP#
IDE_PDASP# 50
IDE_PDD7 7 8 IDE_PDD9
IDE_PDD6 9 10 IDE_PDD10
IDE_PDD5 11 12 IDE_PDD11 +3VS
IDE_PDD4 13 14 IDE_PDD12 R3503 1 X 2 470Ohm ODD_CSEL
IDE_PDD3 15 16 IDE_PDD13
IDE_PDD2 17 18 IDE_PDD14
IDE_PDD1 19 20 IDE_PDD15
IDE_PDD0 21 22 R3502 R3504 1 2 470Ohm
IDE_PDDREQ 19
23 24 IDE_PD OR# 19
R3501 1 2 15KOhm IDE_PDIAG 2 1
25 26 /X
19 IDE_PDIOW#
27 28 10KOhm
19 IDE_PIORDY IDE_PDDACK# 19
29 30 GND
19 INT_IRQ14
31 32 IDE_PDIAG
19 IDE_PDA1
19 IDE_PDA0 33 34 IDE_PDA2 19 GND ODD_CSEL
35 36
19 IDE_PDCS#1 IDE_PDASP# 37 38
IDE_PDCS#3 19 Pull-Up: CDROM as Slave
39 40 Pull-Down: CDROM as Master
+5VS 41 42 +5VS
43 44
45 46
ODD_CSEL 47 48
C 49 50 C
+
C3503 CE3500 C3504
0 1UF/16V 47UF/6 3V
1UF/10V
+3VS
BtoB_CON_50P
+5VS +5VS R3505 1 2 4 7KOhm IDE_PIORDY
8 /x
8 +3VS
9
9 C3500 C3501
10
10 0 1UF/16V 10UF 10V
11
11 /x x
12
12
13
13
14
14
15
15
16 16 +5VS
17
17 TPC28T T3500
18 1 +
18 C3502 CE3501 C3505
19
19 0 1UF/16V
24 20 47UF/6 3V
NP_NC2 20 1UF/10V
21
21
26 22
P_GND2 22
SATA_CON_22P
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom HDD And ODD 20
Date: 14 2007 Sheet 35 of 69
5 4 3 2 1
5 4 3 2 1
+5V_USB +3V_BT
max. 60mA
USB_LP4
18 USB_PP4
10 12
1 T3600 TPC28T CON3601
8
GND4
GND2
GND6 90Ohm/100Mhz
N/A
L3604 Bluetooth Module 1
2
1
2
USB_LP0 7 CON3600 USB_PP5 3
F3600 L3605 USB_LN0 0P+ USB_LN4 USB_PN5 3
6 18 USB_PN4 4
USB01_PWR 0P BT_ON 4
1 2 1 2 5 5
VCC2 L3606 2 /x 5
26 CoEX_CLK 1 0Ohm r0603_h24 6
6
1 5A/6V 80Ohm/100Mhz 4 L3607 2 /x 1 0Ohm r0603_h24 7 9
USB_LP1 GND1 26 CoEX_DATA 7 SIDE1
+ 3 18 BT_DET# 8 10
CE3600 C3600 USB_LN1 1P+ D3608 D3609 8 SIDE2
2
1P EGA10603V05A1 EGA10603V05A1 WtoB_CON_8P
100U/6 3V
0 1UF/16V
1
VCC1 For Intel Wireless R3612
GND3 GND5
C
USB_CON_2X4P ESD Guard CoExistence System C
Close to /X /X 10KOhm
R3614 9 11
GND 1KOhm
USB Port
GND
R3620
GND +5V_USB GND
2 1 +3VS
USB_OC#01 18
GND 1 T3603 TPC28T
USB3600
2KOhm F3602 L3609
GND 5 SIDE G1 7
1 2 1 2 80Ohm/100Mhz USB4_PWR 1 VCC SIDE
USB_LN4 2 DA A0 USB_PP5
18 USB_PP5
1 5A 6V USB_LP4 3
+ R3616 4 GND
CE3601 C3603 1KOhm 6 SIDE G2 8
100U/6 3V SIDE G4
0 1UF/16V USB_CON_1X4P
+5V_USB USB_PN5
18 USB_PN5
GND R3618
1 T3601 TPC28T 2 1 USB_OC#4 18
GND D3610 D3611
EGA10603V05A1 EGA10603V05A1
2KOhm
F3601 L3611 ESD Guard
1 2 1 2 USB23_PWR GND X /X
Close to
80Ohm/100Mhz
USB Port
1 5A/6V
GND
+5V
1 T3602 TPC28T
Q3602
+3V
8 D S 1 GND GND
7 2
6 3 USB_LN3
USB23_PWR 52 BT_ON/OFF#
5 G 4 +12V
R3624
10KOhm
SI4800BDY C3606 CON3602 r0402
SATA_USB_15P
0 1UF/16V BT_ON
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
GND
GND Size Project Name Rev
Custom USB Connector and BT 20
Date: 14 2007 Sheet 36 of 69
5 4 3 2 1
5 4 3 2 1
+VREF_SIO
SIR_TX
D SIR_RX D
CIR_RX
C R_RX_SIO 50
GNDA_SIO
16 SIO_CLK 44
CLKIN SLCT
100 c0402 W=20mil 4 7UF 10V c0402
101 TFDU4100_TR3
PE R3702
48 102
FWE#/GP54 BUSY
47 103
FCS# GP53/SCIO ACK# GND GND GND GND
34 104
C3706 FRD#/GP52 SLIN# 2 7KOhm
33 105
FA17/GP51 N T#
10PF/50V 32 106
FA16/GP50 ERR# SIO_JP1
AFD# 107
/x +VREF_SIO SIO_JP2
31 108
FA15/GP37 STB# GND SIO_JP3
30
GND FA14/GP36 SIO_JP4
29 109
FA13/GP35 PD0
28 110
FA12/GP34 PD1 R3703 R3704 R3705 R3706
27 111
FA11/GP33 PD2 C3707
26 112
FA10/GP32 PD3
113
PD4 1UF 10V 2 7KOhm 2 7KOhm 2 7KOhm 2 7KOhm
114
PD5
115
PD6
116
PD7
GNDA_SIO GND
GND GND GND GND
B CLOSE TO ITE8705 B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom SIO and SIR 20
Date: 14 2007 Sheet 37 of 69
5 4 3 2 1
5 4 3 2 1
U3800A
4
C3813 C3814 GND1 C3815 C3816
13
0 1UF 16V 0 1UF/16V PCI_AD31 GND2 33PF/50V 33PF/50V
125 22 108
PCI_AD30 AD31 GND3 N/A C3817 TPAN0 TPA0 _1 39
126 28
PCI_AD29 AD30 GND4
127 54 2 1 96 109
PCI_AD28 AD29 GND5 FIL0 TPAP0 TPA0+_1 39
1 62
PCI_AD27 AD28 GND6 0 01UF/16V
2 63
PCI_AD26 AD27 GND7 R3801
3 68
PCI_AD25 AD26 GND8
5 118 1 2 101
PCI_AD24 AD25 GND9 10KOhm 1% REXT
6 122
C PCI_AD23 AD24 GND10 C
9
PCI_AD22 AD23 C3818
11
PCI_AD21 AD22
12 99 1 2 100
PCI_AD20 AD21 AGND1 VREF
14 102
R3802 PCI_AD19 AD20 AGND3 +3VS 0 01UF/16V
15 103
PCI_AD17 CB_IDSEL_J PCI_AD18 AD19 AGND2
1 2 17 107
PCI_AD17 AD18 AGND4
18 111
100Ohm PCI_AD16 AD17 AGND5
19
PCI_AD15 AD16 R3800
36
PCI_AD14 AD15 10KOhm
37 87 MDIO17_XDDAT7 39
PCI_AD13 AD14 MDIO17
38
PCI_AD12 AD13
39 92 MDIO16_XDDAT6 39
PCI_AD11 AD12 D3800 1SS355 MDIO16
40
PCI_AD10 AD11 +3VS
42 69 1 2 CB_HWSUSPEND 18 89 MDIO15_XDDAT5 39
PCI_AD9 AD10 HWSPND# MDIO15
43
PCI_AD8 AD9 +3VS
44 91 MDIO14_XDDAT4 39
PCI_AD7 AD8 MDIO14
46 AD7
PCI_AD6 47 58 R3803 2 1 10KOhm 90
PCI_AD5 AD6 MSEN MDIO13 SD/MS/XDDAT3 39
48
PCI_AD4 AD5 R3804 2
49
AD4 XDEN
55 1 10KOhm R3805 R3806
MDIO12
93 SD/MS/XDDAT2 39
PCI_AD3 50
PCI_AD2 AD3 10KOhm 10KOhm
51 81 SD/MS/XDDAT1 39
PCI_AD1 AD2 R3807 2 MDIO11
17 25 PCI_AD[31 0] 52
AD1 UD O5
57 1 100KOhm N/A N/A
PCI_AD0 53 82
AD0 MDIO10 SD/MS/XDDAT0 39
17 25 PCI_PAR 33
PCI_C/BE#3 PAR
7 65 1394_SCL 39
PCI_C/BE#2 C/BE3# UD O3
21 59 1394_SDA 39 75 MDIO05_XDWP# 39
PCI_C/BE#1 C/BE2# UD O4 MDIO05
35
PCI_C/BE#0 C/BE1#
45 56 88 SDCMD_MSBS_XDWE# 39
CB_IDSEL_J C/BE0# UD O2 MDIO08
17 25 PCI_C/BE#[3 0] 8
IDSEL
60 83 MDIO19_XDALE 39
UD O1 R3808 MDIO19
17 PCI_REQ#0 124
B REQ# B
17 PCI_GNT#0 123 72 1 2 INT_SERIRQ 17 28 37 85 MDIO18_XDCLE 39
+3VS GNT# UDIO0 SR RQ# MDIO18
17 25 PCI_FRAME# 23
FRAME# 0Ohm
17 25 PCI_IRDY# 24 78 MDIO02_XDCE# 39
IRDY# MDIO02
17 25 PCI_TRDY# 25
TRDY#
17 25 PCI_DEVSEL# 26
R3809 DEVSEL#
17 25 PCI_STOP# 29 115 PCI_ NTB# 17 77 SDWP_XDR/B# 39
100KOhm STOP# INTA# MDIO03
17 25 PCI_PERR# 30
PERR#
17 25 PCI_SERR# 31 116 PCI_ NTC# 17 80 SDCD# 39
C3819 SERR# INTB# MDIO00
2 1 71
GBRST#
R3810 1 2 0Ohm CB_PCIRSTNS# 119 79
17 22 25 35 PC RST# PCIRST# MDIO01 MSCD# 39
0 1UF/16V
17 PCI_CLK_CB 121
PCICLK R3812
MDIO09 84 SD/MSCLK_XDRE# 39
R3811
1 2 0Ohm 70 66 2 1
25 PCI_PME# PME# TEST
/x
R3814 2 0Ohm 117 10KOhm 76
17 25 28 PM_CLKRUN# CLKRUN# MDIO04 SD/MS/XDPWR 39
74
R3813 MDIO06
100KOhm 97 RSV
/x R5C833_TQFP128 73
MDIO07
R5C833_TQFP128
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Card Bus R5C832 20
Date: 14 2007 Sheet 38 of 69
5 4 3 2 1
5 4 3 2 1
+3VS
C R3907 C
+MC_VCC 10KOhm
P/N: R3909 100KOhm
R3908 150KOhm
1 2
12-340003800 1 2 G
CON3901
XD_VCC 3 C3904 +MC_VCC
D
2 0 1UF 16V
GND NP_NC2 Q3901 S 2301BDS_T1_E3
SD_DAT2 S9 X1 38 SD/MS/XDPWR 11
SD/MS/XDDAT3 DAT2 GND1 XD_CD# G 2N7002
S1 X0
SDCMD_MSBS_XDWE# S2
CD/DAT3 CD
X2 SDWP_XDR/B# 2 S Place as close to
CMD R/ B SD MSCLK_XDRE# C3905 C3906
S3
VSS1 RE
X3 SD/MSCLK_XDRE# 38 card reader socket
M10 X4 MDIO02_XDCE# 0 1UF/16V 0 1UF 16V as possible
VSS2 CE MDIO02_XDCE# 38
M9 X5 MDIO18_XDCLE
VCC1 CLE MDIO18_XDCLE 38
SD/MSCLK_XDRE# M8 X6 MDIO19_XDALE GND
SD/MS/XDDAT3 SCLK ALE SDCMD_MSBS_XDWE# MDIO19_XDALE 38
M7 X7 SDCMD_MSBS_XDWE# 38
MSCD# Reserved1 WE MDIO05_XDWP#
M6 X8 MDIO05_XDWP# 38
SD/MS/XDDAT2 NS WP
M5 X9
SD/MS/XDDAT0 Reserved2 GND2 SD MS/XDDAT0 GND
M4 X10 SD/MS/XDDAT0 38
SD/MS/XDDAT1 SD O D0 SD MS/XDDAT1
M3 X11 SD/MS/XDDAT1 38
SDCMD_MSBS_XDWE# VCC2 D1 SD MS/XDDAT2
M2 X12 SD/MS/XDDAT2 38
BS D2 SD MS/XDDAT3
M1
VSS3 D3
X13
MDIO14_XDDAT4
SD/MS/XDDAT3 38 ALPS Date Code 433(2004 year 33 week)
S4 X14 MDIO14_XDDAT4 38
SD/MSCLK_XDRE# S5
VDD D4
X15 MDIO15_XDDAT5 can solve MS Duo Adaptor short problem
CLK D5 MDIO15_XDDAT5 38
S6 X16 MDIO16_XDDAT6 ?
SD/MS/XDDAT0 VSS4 D6 MDIO17_XDDAT7 MDIO16_XDDAT6 38
S7 X17 Q3902 2N7002
SD_DAT1 DAT0 D7 MDIO17_XDDAT7 38 SD MS/XDDAT1 SD_DAT1
S8 X18 3 2
DAT1 VCC3
1
NP_NC1 Q3903 2N7002
B B
SD MS/XDDAT2 3 2 SD_DAT2
GND GND
SD_CARD_38P
SDCD# XD_VCC
38 SDCD# GND
SDWP_XDR B# Layout: SHIELD GND Q3904 2N7002
38 SDWP_XDR/B#
MSCD#
38 MSCD#
+MC_VCC 3 2
GND GND
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom 1394 And Card Reader 20
Date: 14 2007 Sheet 39 of 69
5 4 3 2 1
5 4 3 2 1
GND
GND
GND GND
CON4001
14
120Ohm/100Mhz P_GND2
11
AV_ N_C L4000 1 NP_NC2
2 10
10
9
AV_ N_Y L4001 1 2
120Ohm/100Mhz 8
7
9
8
7
ATV_DTV_FM Antenna
6
AV_ N_CVBS L4002 1 6
2 120Ohm/100Mhz 5
5
4
AV_ N_L L4003 1 4
2 120Ohm/100Mhz 3
3
2 CON4002
AV_ N_R L4004 1 2
2 120Ohm/100Mhz 1
1
12
NP_NC1
13 5 2
P_GND1 GND4 GND1
C4013 C4014 C4017 C4015 WTOB_CON_10P
4
GND3 GND2
3
14G152075000
C4016
47PF 50V 47PF 50V F_TERM NAL_1P
B GND GND B
BOM:12G171030104 GND
GND
USB_PP9
18 USB_PP9
CON4003
1 SIDE1 SIDE2 2
5 NP_NC1 NP_NC2 6
3 SIDE3 SIDE4 4
USB_PN9
18 USB_PN9
M NI_PCI_LATCH_4P
GND
GND D4000 D4001
EGA10603V05A1 EGA10603V05A1
A A
ESD Guard
Close to X /X
USB Port
GND
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Mini PCIE(TV) 20
Date: 14 2007 Sheet 40 of 69
5 4 3 2 1
5 4 3 2 1
D D
U4100A
PART 1 OF 7
GFX_TX_C_P0 1 2 GFX_TX_P0 AK33 AG31 GFX_RX_C_P0
GFX_TX_C_N0 C4100 0 1UF/16V GFX_TX_N0 PCIE_RX0P PCIE_TX0P GFX_RX_C_N0
1 2 AJ33 AG30
C4107 0 1UF/16V PCIE_RX0N PCIE_TX0N
C
E C
GFX_TX_C_P7 1 2 GFX_TX_P7 AC35 AA31 GFX_RX_C_P7
GFX_TX_C_N7 1 2 C4106 0 1UF/16V GFX_TX_N7 AC34
PCIE_RX7P R PCIE_TX7P
AA30 GFX_RX_C_N7
PCIE_RX7N PCIE_TX7N
C4105 0 1UF/16V F
GFX_TX_C_P8 1 2 GFX_TX_P8 AB33
A AA28 GFX_RX_C_P8
PCIE_RX8P PCIE_TX8P
GFX_TX_C_N8 1 2 C4117 0 1UF/16V GFX_TX_N8 AA33
PCIE_RX8N
C PCIE_TX8N
AA27 GFX_RX_C_N8
C4116 0 1UF/16V
E
GFX_TX_C_P9 1 2 GFX_TX_P9 AA35 W31 GFX_RX_C_P9
GFX_TX_C_N9 C4119 0 1UF/16V GFX_TX_N9 PCIE_RX9P PCIE_TX9P GFX_RX_C_N9
1 2 AA34
PCIE_RX9N PCIE_TX9N
W30
C4118 0 1UF/16V
+3VS_GPU
R4100
4 7KOhm
12 GFX_TX_C_P[0 15] GFX_RX_C_P[0 15] 12
A 12 GFX_TX_C_N[0 15] GFX_RX_C_N[0 15] 12 A
M76_RSR#
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom M76(1/5)PCIE I/F 20
Date: 14 2007 Sheet 41 of 69
5 4 3 2 1
5 4 3 2 1
AN9 DVI_A_CLK 24
TXCAM R4200 R4201
48 G_VID_0 AM12 AN10 DVI_A_CLK+ 24
VID_0 TXCAP
48 G_VID_1 AL12 1 2 1 2
VID_1
48 G_VID_2 AJ12 AR10 DVI_A_TX0 24
VID_2 INTEGRATED TX0M 180Ohm 180Ohm
48 G_VID_3 AH12 AP10 DVI_A_TX0+ 24
VID_3 TX0P
48 G_VID_4 AM10 TMDS
VID_4 V P / I2C
48 G_VID_5 AL10 AR11 DVI_A_TX1 24
D VID_5 TX1M R4202 R4203 D
48 G_VID_6 AJ10 AP11 DVI_A_TX1+ 24
VID_6 TX1P
48 G_VID_7 AH10 1 2 1 2
VID_7
AR12 DVI_A_TX2 24
TX2M 180Ohm 180Ohm
48 VHAD0 AM9 AP12 DVI_A_TX2+ 24
VHAD_0 TX2P
AL9
R4204 VHAD_1
AR14
TXCBM
AJ9 AP14
U4100F 1KOhm VPHCTL TXCBP
PART 7 OF 7 48 PSYNC AL7 AR15
VPCLK0 TX3M
48 DVALID AK7 AP15
VIPCLK TX3P
LVDDR AJ26 AG7
LVDDR_1 ControlVARY_BL BL_ENA 22
AH26 AM7 AR16
LVDDR_2 PSYNC TX4M
AJ6 FPVCC 22 AP16
DIGON TX4P
AJ7
DVALID
LVDDC AK27 AR17
LVDDC_1 TX5M
AL27 AK24 TXCLK_U+ 22 22 GLVDS_DDCDAT AK6 AP17
LVDDC_2 TXCLK_UP SDA TX5P
AL24 TXCLK_U 22 22 GLVDS_DDCCLK AM6
TXCLK_UN SCL
AM24 AN27 TXOUT_U0+ 22 AR13
LVSSR_1 TXOUT_U0P FOR M72M M76M NC_10
AN28 AN26 TXOUT_U0 22 AK14 AP13
LVSSR_2 TXOUT_U0N THE PINS WITH TEST POINTS NC_1 NC_9
AN21 LVSSR_3 TXOUT_U1P AP27 TXOUT_U1+ 22 ARE REQUIRED TO BE ACCESSIBLE
AN24 AR27 TXOUT_U1 22 AN8 AM14 TPVDD
LVSSR_4 TXOUT_U1N FOR DEBUG AND BOUNDRY SCAN DVPCNTL_MVP_0 TPVDD
AN25 AG24 TXOUT_U2+ 22 AP8 AL14
LVSSR_5 TXOUT_U2P PURPOSES USING TEST POINT DVPCNTL_MVP_1 TPVSS
AM22 AH24 TXOUT_U2 22 VIAS IF UNUSED OR COMPONENT AG1
LVSSR_6 TXOUT_U2N DVPCNTL_0
AP21 AK26 PADS AH3 AN19 TXVDDR
LVSSR_7 TXOUT_U3P DVPCNTL_1 TXVDDR_1
AP26 AL26 FOR M66M M71M AH2 AN20
LVSSR_8 TXOUT_U3N DVPCNTL_2 MULTI GFX TXVDDR_2
AM27 SEE DATA BOOK FOR EQUIVILANT DEBUG AH1 AP19
LVSSR_9 DVPCLK EXTERNAL TXVDDR_3
AR21 AR22 TXCLK_L+ 22 AND BOUNDRY SCAN SIGNALS AJ3 AR19
LVSSR_10 TXCLK_LP DVPDATA_0 TMDS TXVDDR_4
AR26 AP22 TXCLK_L 22 ENSURE DEBUG ACCESS STRAP AJ2
LVSSR_11 TXCLK_LN IS ALSO ACCESSIBLE DVPDATA_1
AM26 AN23 TXOUT_L0+ 22 AJ1 AN18
LVSSR_12 TXOUT_L0P SEE CONFIG STRAPPING PAGE DVPDATA_2 TXVSSR_1
AJ22 AN22 TXOUT_L0 22 AK2 AP18
LVSSR_13 TXOUT_L0N ACCESS TO ATI DEBUG PORT DVPDATA_3 TXVSSR_2
AJ24 AP23 TXOUT_L1+ 22 AK1 AR18
LVSSR_14 TXOUT_L1P IS MANDATORY ON INITIAL DVPDATA_4 TXVSSR_3
AR23 TXOUT_L1 22 AL3 AN16
C TXOUT_L1N PROTOTYPE DESIGNS DVPDATA_5 TXVSSR_4 C
AP24 TXOUT_L2+ 22 AL2 AN15
TXOUT_L2P DVPDATA_6 TXVSSR_5
AR24 TXOUT_L2 22 AL1 AN17
TXOUT_L2N DVPDATA_7 TXVSSR_6
LPVDD AL22 AP25 AM3 AN11
LPVDD TXOUT_L3P DVPDATA_8 TXVSSR_7
AK22 AR25 AM2 AN12
LPVSS TXOUT_L3N DVPDATA_9 TXVSSR_8
AN2 AN13
DVPDATA_10 TXVSSR_9
AP3 AN14
DVPDATA_11 TXVSSR_10
M76 M AR3
DVPDATA_12 OPTIONAL STRAP TO GROUND FOR RB GB BB
AN4 AH18
DVPDATA_13 NC_2 SEE DAC1 RGB SHEET
AR4 AG18
DVPDATA_14 NC_3
AP4 AH17
DVPDATA_15 NC_4
AN5 AG17
DVPDATA_16 NC_5
AR5 AP9
DVPDATA_17 NC_6
AP5 AR9
DVPDATA_18 NC_7
AP6 AG15
DVPDATA_19 NC_8 PLACE OR RESISTORS CLOSE TO ASIC
48 DVPDATA20 AR6
DVPDATA_20
48 DVPDATA21 AN7 AR31 G_RED 23
DVPDATA_21 R
48 DVPDATA22 AP7 DVPDATA_22 RB AP31
48 DVPDATA23 AR7
DVPDATA_23
AR30 G_GREEN 23
G
48 G_GP O0 AG2 AP30
GPIO_0 DAC1 GB
48 G_GP O1 AF2
GPIO_1
48 G_GP O2 AF1 AR29 G_BLUE 23
GPIO_2 GENERAL B
AE3 AP29
R4208 GPIO_3 PURPOSE BB
48 G_GP O4 AE2
GPIO_4 I/O
48 G_GP O5 AE1 AN29 G_HSYNC 23 48
10KOhm GPIO_5 HSYNC
48 G_GP O6 AD3 AN30 G_VSYNC 23 48
GPIO_6 VSYNC
AD2
GPIO_7_BLON
48 G_GP O8 AD1
GPIO_8_ROMSO RSET
AN31 2 R4209 1
AD5 DAC2 CAN BE TV SIGNALS (C Y COMP) OR SECONDARY
48 G_GP O9 GPIO_9_ROMSI CRT (R2 B2 G2
x AD4 AR32 AVDD 499OHM
GPIO_10_ROMSCK AVDD SIGNALS AS CONTROLLED BY AN INTERNAL MUX
48 G_GP O11 AC3
+1 8VS_GPU GPIO_11
48 G_GP O12 AC2 AP32
B GPIO_12 AVSSQ B
48 G_GP O13 AC1
GPIO_13
AB3 AR28 VDD1DI
R4210 GPIO_14_HPD2 VDD1DI
60 PWRCNTL_0 AB2 AP28
OSC_SPREAD GPIO_15_PWRCNTL_0 VSS1DI
AB1
499OHM GPIO_16_SSIN
28 OTEMP# AF5 AM19
GPIO_17_THERMAL_INT R2 IF Y C COMP OR R2 G2 B2 ARE
AF4 AL19
FOR M72M M76M R4212 /x 0Ohm GPIO_18_HPD3 R2B USED
28 52 56 67 FORCE_OFF# 2 1 AG4
VREFG VOLTAGE DIVIDER IS GPIO_19_CTFB R2B G2B B2B MUST BE
60 PWRCNTL_1 AG3 AM18
VREFG=VDDR4 5(1 8V)/3=0 6V R4211 GPIO_20_PWRCNTL_1 G2 CONNECTED
AD9 AL18
GPIO_21_BB_EN G2B TO GROUND OR TERMINATED AT
48 G_GP O22 AD8 CONNECTOR
249Ohm R4214 N/A 1 0Ohm GPIO_22_ROMCSB DAC2
16 G_CLKREQ# 2 AD7
GPIO_23_CLKREQB B2
AM17
AB4 AL17
T4227 TPC28T AB6 GPIO_24_JMODE B2B PLACE OR RESISTORS CLOSE TO ASIC
1 GPIO_25_TDI
1KOhm T4228 1 TPC28T AB7 AK19 G_C 23
T4229 TPC28T AB9 GPIO_26_TCK C OPTIONAL STRAP TO GROUND FOR
1 AK18 G_Y 23
R4213 T4230 TPC28T AA9 GPIO_27_TMS Y R2B G2B B2B
1 GPIO_28_TDO COMP
AK17 G_COMP 23
T4231 1 TPC28T AF8 SEE DAC2 RGB SHEET
T4232 TPC28T AF7 GENER CA
1 GENER CB V2SYNC
AL15 G_V2SYNC 48
2 1 2 1 AG5
GENER CC H2SYNC
AM15 G_H2SYNC 48
R4215 0Ohm R4216 0Ohm AD12 AM21 A2VDD
VREFG A2VDD
/x
R4220 0Ohm DPLL_PVDD AR20 AL21 A2VDDQ
GXI DPLL_PVDD A2VDDQ
2 1 AP20 DPLL_PVSS
A2VSSQ AK21
2 1 GXO PCIE_PVDD AM35 PCIE_PVDD
/x AM34 PCIE_PVSS VDD2DI AH22 VDD2DI
X4200 R4219 0Ohm AG22
1 2 VSS2DI
/x MPVDD A14 MPVDD
B15 PLL AJ21 1 R4221 2
C4201 27Mhz C4202 MPVSS CLOCKS R2SET 715Ohm
U4101 120Ohm 100Mhz
18PF 50V 18PF 50V AR33 XTALIN DDC1DATA AM29 GCRT_DDCDAT 23
A L4200 A
1 XIN XOUT 8 AP33 XTALOUT DDC1CLK AL29 GCRT_DDCCLK 23
2 VSS VDD 7 1 2 +3VS_GPU
3 SRS PD# 6 DPLL_VDDC AG19 DPLL_VDDC DDC2DATA AJ15 HDMI_SDA 24
OSC_SPREAD R4222 1 2 22Ohm 4 5 DDC AH15
ModOUT REF DDC2CLK HDMI_SCL 24
AG21 TS_FDO THERMAL
P1819B_08SRCN 6/4/2007 AJ5
DDC3DATA G_I2C_CLK 48
R4224 48 G_D AK4 DM NUS DDC3CLK AJ4 G_I2C_DAT 48
R4223 AM4
48 G_D+ DPLUS
M66 10G21269R814030 69 8OHM 1 2 GXI 2 1
AG6
DDC4DATA AH14
AG14
Title : A7K
24 DVI_DETECT HPD1 DDC4CLK
150Ohm Engineer: Endy Zhang
121OHM M76 M ASUSTECH CO LTD
Size Project Name Rev
Custom M76(2/5)DVI DAC DDC VID 20
Date: 14 2007 Sheet 42 of 69
5 4 3 2 1
5 4 3 2 1
U4100E
Part 6 of 7
P33 L33
PCIE_VSS_1 VSS_65
P34 P6
PCIE_VSS_2 VSS_66
P35 M9
PCIE_VSS_3 VSS_67
R27 M26
PCIE_VSS_4 VSS_68
R28 K28
PCIE_VSS_5 VSS_69
R29 M32
PCIE_VSS_6 VSS_70
R32 N14
D PCIE_VSS_7 VSS_71 D
R33 N17
PCIE_VSS_8 VSS_72
U29 N19
PCIE_VSS_9 VSS_73
U32 N22
PCIE_VSS_10 VSS_74
V29 N33
PCIE_VSS_11 VSS_75 +1 8VS_GPU U4100D
V32 N3
PCIE_VSS_12 VSS_76
T33 R5
PCIE_VSS_13 VSS_77
V34
PCIE_VSS_14 VSS_78
U8 PART 5 OF 7
V35 P13
PCIE_VSS_15 VSS_79
W29 P15 D1 AR34 PCIE_IO
PCIE_VSS_16 VSS_80 VDDR1_1 PCIE_VDDR_1
W32 P18 A8 AL33
PCIE_VSS_17 VSS_81 C4300 C4301 C4302 C4303 VDDR1_2 PCIE_VDDR_2
W33 P21 A12 AM33
PCIE_VSS_18 VSS_82 VDDR1_3 PCIE_VDDR_3
AA29 P23 10UF/10V 10UF/10V 10UF/10V 10UF/10V A16 AN33
PCIE_VSS_19 VSS_83 VDDR1_4 PCIE_VDDR_4
AA32 P26 A20 AN34
PCIE_VSS_20 VSS_84 VDDR1_5 PCIE_VDDR_5
AB29 P29 A24 AN35
PCIE_VSS_21 VSS_85 VDDR1_6 PCIE_VDDR_6
AB32 P30 A28 AP34
PCIE_VSS_22 VSS_86 VDDR1_7 PCIE_VDDR_7
Y33 R1 B1 AP35
PCIE_VSS_23 VSS_87 C4304 C4305 C4306 C4307 VDDR1_8 PCIE_VDDR_8
AB34 U5 H1
PCIE_VSS_24 VSS_88 VDDR1_9
AB35 P9 1UF/10V 1UF/10V 1UF 10V 1UF/10V H35 R26 PCIE_CORE
PCIE_VSS_25 VSS_89 VDDR1_10 PCIE_VDDC_1
AC33 R10 L18 U26
PCIE_VSS_26 VSS_90 VDDR1_11 PCIE_VDDC_2
AD29 PCIE_VSS_27 VSS_91 R14 L19 VDDR1_12 PCIE_VDDC_3 V25
AD32 R17 L21 V26
PCIE_VSS_28 VSS_92 VDDR1_13 PCIE_VDDC_4
AF29 R19 L22 W25
PCIE_VSS_29 VSS_93 C4308 C4309 C4310 C4311 VDDR1_14 PCIE_VDDC_5
AF32 R22 M10 W26
PCIE_VSS_30 VSS_94 VDDR1_15 PCIE_VDDC_6
AD33 V3 1UF/10V 1UF/10V 1UF 10V 1UF/10V M35 AA25
PCIE_VSS_31 VSS_95 VDDR1_16 PCIE_VDDC_7
AF34 AK9 P10 AD26
PCIE_VSS_32 VSS_96 VDDR1_17 PCIE_VDDC_8
AF35 U10 T1 AF26
PCIE_VSS_33 VSS_97 VDDR1_18 PCIE_VDDC_9 +VDD_CORE
AG27 U15 Y1 AA26
PCIE_VSS_34 VSS_98 VDDR1_19 PCIE_VDDC_10
AG29 U18 B35 AB25
PCIE_VSS_35 VSS_99 C4312 C4313 C4314 C4315 VDDR1_20 PCIE_VDDC_11
AG32 U21 M1 AB26
PCIE_VSS_36 VSS_100 VDDR1_21 PCIE_VDDC_12
AG33 U23 1UF/10V 1UF/10V 1UF 10V 1UF/10V D35
PCIE_VSS_37 VSS_101 VDDR1_22
AJ29 V7 K10
PCIE_VSS_38 VSS_102 VDDR1_23
AJ32 W8 K12 N13
C PCIE_VSS_39 VSS_103 VDDR1_24 VDDC_1 C
AH33 V10 K24 N15
PCIE_VSS_40 VSS_104 VDDR1_25 VDDC_2 C4316 C4317 C4318 C4319
AL34 V14 K26 N18
PCIE_VSS_41 VSS_105 VDDR1_26 VDDC_3
AL35 V17 L14 N21 10UF/10V 1UF 10V 1UF/10V 1UF/10V
PCIE_VSS_42 VSS_106 VDDR1_27 VDDC_4
AK32 V19 L15 N23
PCIE_VSS_43 VSS_107 VDDR1_28 VDDC_5
V22 L17 P14
VSS_108 VDDR1_29 VDDC_6
A2 V1 P17
VSS_1 VSS_109 VDDC_7
A34 AK12 VDD_CT AA11 P19
VSS_2 VSS_110 +3VS_GPU 3 3V_DELAY VDD_CT_1 VDDC_8 C4321 C4322 C4323 C4324 C4325
C3 V9 AB11 P22
VSS_3 VSS_111 VDD_CT_2 VDDC_9
C5 W10 AD10 V18 10UF/10V 1UF 10V 1UF/10V 1UF/10V 1UF/10V
VSS_4 VSS_112 VDD_CT_3 VDDC_10
A4 W15 AF10 V21
VSS_5 VSS_113 VDD_CT_4 VDDC_11
C18
A21
VSS_6 VSS_114
W18
W21 Q4300 R11
P VDDC_12
V23
W14
VSS_7 VSS_115 VDD_CT_5 VDDC_13
C23
VSS_8 VSS_116
W23 R25
VDD_CT_6 O VDDC_14
W17
C4326 C4327 C4328 C4329
C11 AA6 U11 W19
VSS_9 VSS_117 VDD_CT_7 VDDC_15
C13
VSS_10 VSS_118
AA10 U25
VDD_CT_8
W VDDC_16
W22 10UF/10V 1UF 10V 1UF/10V 1UF/10V
C14 AA14 AA15
A18
VSS_11
VSS_12
VSS_119
VSS_120 AA17 S D AE14 VDDR3_1
E VDDC_17
VDDC_18 AA18
A11 AA19 AE15 AA21
C26
VSS_13 VSS_121
AA22 C4331 C4332 C4333 C4334 AF12
VDDR3_2 R VDDC_19
AA23
VSS_14 VSS_122 R4300 VDDR3_3 VDDC_20 C4335 C4336 C4337 C4338 C4339
C33 AB8 10UF/10V 1UF/10V 1UF/10V 1UF 10V AE17 AB14
VSS_15 VSS_123 VDDR3_4 VDDC_21
F35 AB10 100KOhm AB17 10UF/10V 1UF 10V 1UF/10V 1UF/10V 1UF/10V
VSS_16 VSS_124 R4301 FOR M66M M71M M72M AND M76M VDDC_22
R7 AB13 AP2 AB19
VSS_17 VSS_125 SI2301BDS_T1_E3 VDDR4 OR VDDR5 CAN BE 3 3V OR 1 8V FOR EXT TMDS ON DV PORT VDDR4_1 VDDC_23
G10 AB15 0Ohm AR2 AB22
VSS_18 VSS_126 FOR M72M AND M76M VDDR4_2 VDDC_24
F15 AB18 AC13
VSS_19 VSS_127 +3VS_GPU VDDR4 AND VDDR5 MUST BE 1 8V IF MULTI GPU ON DV PORT VDDC_25
H17 AB21 AN1 AC15
VSS_20 VSS_128 VDDR5_1 VDDC_26 C4340 C4341 C4342 C4343 C4344
G21 AB23 AP1 AC18
VSS_21 VSS_129 VDDR5_2 VDDC_27
D29 AC14 AC21 10UF/10V 1UF 10V 1UF/10V 1UF/10V 1UF/10V
VSS_22 VSS_130 R4302 C4345 C4346 C4347 VDDC_28
A29 AC17 VDD_MEM_CLK0 A25 AC23
VSS_23 VSS_131 VDDRHA_1 VDDC_29
G1 AC19 10KOhm 10UF/10V 0 1UF/16V 1UF 10V VDD_MEM_CLK1 A32 AE18
VSS_24 VSS_132 VDDRHA_2 VDDC_30
F14 AC22 AE22
VSS_25 VSS_133 T4300 TPC28T 3 R4303 VDDC_31
J15 AF9 D B25 AE19
VSS_26 VSS_134 Q4301 0Ohm VSSRHA_1 VDDC_32
E19 AD6 1 B32 AE21
B VSS_27 VSS_135 VSSRHA_2 VDDC_33 B
E22 AB5 2N7002 R13
VSS_28 VSS_136 VDDC_34
E24 AD24 60 7 VGA_PWRGD 11 x C4348 C4349 VDD_MEM_CLK2 B2 R15
VSS_29 VSS_137 G VDDRHB_1 VDDC_35
D7 W5 1UF/10V 1UF/10V VDD_MEM_CLK3 L1 R18
G9
VSS_30 VSS_138
AF6 2 S VDDRHB_2 VDDC_36
R21
VSS_31 VSS_139 +1 8VS_GPU VDDC_37
F26 AF14 C2 R23
VSS_32 VSS_140 C4350 VSSRHB_1 VDDC_38
G29 AF21 L2 U14
VSS_33 VSS_141 VSSRHB_2 VDDC_39
D33 AF22 0 1UF/16V U17
VSS_34 VSS_142 VDDC_40
M5 AK10 W13 U19
VSS_35 VSS_143 BBN_1 VDDC_41
G4 AF17 AA13 U22
VSS_36 VSS_144 +VDD_CORE BBN_2 VDDC_42 120Ohm/100Mhz
E10 AF18 V15
VSS_37 VSS_145 VDDC_43 L4300
E12 AF19 U13
VSS_38 VSS_146 BBP_1
F17 AA3 V13 M12 1 2
VSS_39 VSS_147 OPTIONAL RC C4352 BBP_2 VDDCI_1
G18 AG12 M24
VSS_40 VSS_148 NETWORK TO FINE VDDCI_2 C4354 C4355 C4356
G22 VSS_41 VSS_149 AJ14 1UF/10V V11 VSS_174 VDDCI_3 P11
F30 AH21 TUNE POWER P25
VSS_42 VSS_150 SEQUENCING VDDCI_4 1UF/10V 1UF 10V 1UF/10V
J35 D4 +VDD_CORE W11
VSS_43 VSS_151 VDDC_44
J18 AF15
VSS_44 VSS_152
H19 AG10 M76 M
VSS_45 VSS_153
J21 AN6
VSS_46 VSS_154
F7 AK15
VSS_47 VSS_155
J12 VSS_48 VSS_156 AJ17
J24 VSS_49 VSS_157 AJ18
J26 VSS_50 VSS_158 AJ19
K30 VSS_51 VSS_159 AF24
J32 VSS_52 VSS_160 AN32
F33 VSS_53 VSS_161 AK3
K6 VSS_54 VSS_162 AN3
K9 VSS_55 VSS_163 AR8
K14 VSS_56 VSS_164 AM1
K15 VSS_57 VSS_165 AK30
K17 VSS_58
K18 VSS_59 MECH_1 A35
A A
K19 VSS_60 MECH_2 AR1
K21 VSS_61 MECH_3 AR35
K22 VSS_62
M28 VSS_63 RSVD_4 AF3
K3 VSS_64 RSVD_3 AG9
CORE GND
M76 M
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom M76(3/5)Power 20
Date: 14 2007 Sheet 43 of 69
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom <Doc> 20
Date: 14 2007 Sheet 44 of 69
5 4 3 2 1
5 4 3 2 1
CLKA0 CLKB0
46 CLKA0 CLKA0# 47 CLKB0 CLKB0#
46 CLKA0# 47 CLKB0#
CLKA1 CLKB1
46 CLKA1 47 CLKB1
CLKA1# CLKB1#
46 CLKA1# 47 CLKB1#
RASA0# RASB0#
D 46 RASA0# 47 RASB0# D
RASA1# RASB1#
46 RASA1# 47 RASB1#
CASA0# CASB0# U4100G
46 CASA0# 47 CASB0#
CASA1# U4100C CASB1#
46 CASA1# 47 CASB1#
Part 4 of 7
CSA0_0# Part 3 of 7 CSB0_0#
46 CSA0_0# 47 CSB0_0#
CSA1_0# CSB1_0# MDB0 H15 H2 MAB0
46 CSA1_0# 47 CSB1_0# DQB_0 MAB_0
MDA0 P27 C27 MAA0 MDB1 G14 H3 MAB1
MDA1 DQA_0 MAA_0 MAA1 MDB2 DQB_1 MAB_1 MAB2
P28 B28 E14 J3
MDA2 DQA_1 MAA_1 MAA2 MDB3 DQB_2 MAB_2 MAB3
P31 B27 D14 J5
MDA3 DQA_2 MAA_2 MAA3 MDB4 DQB_3 MAB_3 MAB4
P32 G26 H12 J4
MDA4 DQA_3 MAA_3 MAA4 MDB5 DQB_4 MAB_4 MAB5
M27 F27 G12 J6
CKEA0 MDA5 DQA_4 MAA_4 MAA5 CKEB0 MDB6 DQB_5 MAB_5 MAB6
46 CKEA0 K29 E27 47 CKEB0 F12 G5
CKEA1 MDA6 DQA_5 MAA_5 MAA6 CKEB1 MDB7 DQB_6 MAB_6 MAB7
46 CKEA1 K31 D27 47 CKEB1 D10 J9
MDA7 DQA_6 MAA_6 MAA7 MDB8 DQB_7 MAB_7 MAB8
K32 J27 B13 F3
WEA0# MDA8 DQA_7 MAA_7 MAA8 WEB0# MDB9 DQB_8 MAB_8 MAB9
46 WEA0# M33 E29 47 WEB0# C12 F4
WEA1# MDA9 DQA_8 MAA_8 MAA9 WEB1# MDB10 DQB_9 MAB_9 MAB10
46 WEA1# M34 C30 47 WEB1# B12 J1
MDA10 DQA_9 MAA_9 MAA10 MDB11 DQB_10 MAB_10 MAB11
L34 E26 B11 J2
A_BA2 MDA11 DQA_10 MAA_10 MAA11 B_BA2 MDB12 DQB_11 MAB_11
46 A_BA2 L35 A27 47 B_BA2 C9 J7
A_BA0 MDA12 DQA_11 MAA_11 B_BA0 MDB13 DQB_12 MAB_A12 B_BA2
46 A_BA0 J33 DQA_12 MAA_A12 G27 47 B_BA0 B9 DQB_13 MAB_BA2 F1
A_BA1 MDA13 J34 D26 A_BA2 B_BA1 MDB14 A9 G2 B_BA0
46 A_BA1 MDA14 DQA_13 MAA_BA2 A_BA0 47 B_BA1 MDB15 DQB_14 MAB_BA0 B_BA1
H33 C28 B8 G3
MDA15 DQA_14 MAA_BA0 A_BA1 MDB16 DQB_15 MAB_BA1
H34 B29 J10
WDQSA[0 7] MDA16 DQA_15 MAA_BA1 WDQSB[0 7] MDB17 DQB_16 DQMB#0
46 WDQSA[0 7] K27 47 WDQSB[0 7] H10 D12
MDA17 DQA_16 DQMA#0 MDB18 DQB_17 DQMBB_0 DQMB#1
J29 M29 F10 C10
MDA18 DQA_17 DQMAB_0 DQMA#1 MDB19 DQB_18 DQMBB_1 DQMB#2
J30 K33 D9 E7
RDQSA[0 7] MDA19 DQA_18 DQMAB_1 DQMA#2 RDQSB[0 7] MDB20 DQB_19 DQMBB_2 DQMB#3
46 RDQSA[0 7] J31 G30 47 RDQSB[0 7] G7 C6
MDA20 DQA_19 DQMAB_2 DQMA#3 MDB21 DQB_20 DQMBB_3 DQMB#4
F29 E33 G6 P3
MDA21 DQA_20 DQMAB_3 DQMA#4 MDB22 DQB_21 DQMBB_4 DQMB#5
F32 C22 F6 R4
DQMA[0 7] MDA22 DQA_21 DQMAB_4 DQMA#5 DQMB[0 7] MDB23 DQB_22 DQMBB_5 DQMB#6
46 DQMA#[0 7] D30 H21 47 DQMB#[0 7] D6 W3
MDA23 DQA_22 DQMAB_5 DQMA#6 MDB24 DQB_23 DQMBB_6 DQMB#7
D32 C17 C8 V8
MDA24 DQA_23 DQMAB_6 DQMA#7 MDB25 DQB_24 DQMBB_7
G33 G17 C7
C DMA[0 63] MDA25 DQA_24 DQMAB_7 DMB[0 63] MDB26 DQB_25 RDQSB0 C
46 MDA[0 63] G34 47 MDB[0 63] B7 J14
MDA26 DQA_25 RDQSA0 MDB27 DQB_26 QSB_0 RDQSB1
G35 M30 A7 B10
MDA27 DQA_26 QSA_0 RDQSA1 MDB28 DQB_27 QSB_1 RDQSB2
F34 K34 B5 F9
MAA[0 11] MDA28 DQA_27 QSA_1 RDQSA2 MAB[0 11] MDB29 DQB_28 QSB_2 RDQSB3
46 MAA[0 11] D34 G31 47 MAB[0 11] A5 B6
MDA29 DQA_28 QSA_2 RDQSA3 MDB30 DQB_29 QSB_3 RDQSB4
C34 E34 C4 P2
MDA30 DQA_29 QSA_3 RDQSA4 MDB31 DQB_30 QSB_4 RDQSB5
C35 B22 B4 P8
MDA31 DQA_30 QSA_4 RDQSA5 MDB32 DQB_31 QSB_5 RDQSB6
B34 F21 M3 W2
MDA32 DQA_31 QSA_5 RDQSA6 MEM_RST MDB33 DQB_32 QSB_6 RDQSB7
C24 B17 46 47 MEM_RST M2 V6
MDA33 DQA_32 QSA_6 RDQSA7 MDB34 DQB_33 QSB_7
B24 D17 N2
MDA34 DQA_33 QSA_7 MDB35 DQB_34 WDQSB0
B23 N1 H14
MDA35 DQA_34 WDQSA0 MDB36 DQB_35 QSB_0B WDQSB1
A23 M31 R3 A10
MDA36 DQA_35 QSA_0B WDQSA1 MDB37 DQB_36 QSB_1B WDQSB2
C21 K35 R2 E9
MDA37 DQA_36 QSA_1B WDQSA2 MDB38 DQB_37 QSB_2B WDQSB3
B21 G32 T3 A6
MDA38 DQA_37 QSA_2B WDQSA3 MDB39 DQB_38 QSB_3B WDQSB4
C20 E35 T2 P1
MDA39 DQA_38 QSA_3B WDQSA4 MDB40 DQB_39 QSB_4B WDQSB5
B20 A22 M8 P7
MDA40 DQA_39 QSA_4B WDQSA5 MDB41 DQB_40 QSB_5B WDQSB6
J22 E21 M7 W1
MDA41 DQA_40 QSA_5B WDQSA6 MDB42 DQB_41 QSB_6B WDQSB7
H22 DQA_41 QSA_6B A17 P5 DQB_42 QSB_7B V5
MDA42 F22 E17 WDQSA7 PLACE MVREF DIVIDERS MDB43 P4
MDA43 DQA_42 QSA_7B AND CAPS CLOSE TO ASIC MDB44 DQB_43
D21 R9 D2
MDA44 DQA_43 MDB45 DQB_44 ODTB0
J19 C31 R8 K5
MDA45 DQA_44 ODTA0 MDB46 DQB_45 ODTB1
G19 C25 R6
MDA46 DQA_45 ODTA1 MDB47 DQB_46 CLKB0
F19 U4 A3
+1 8VS_GPU MDA47 DQA_46 CLKA0 +1 8VS_GPU MDB48 DQB_47 CLKB0 CLKB1
D19 A33 U3 K1
MDA48 DQA_47 CLKA0 CLKA1 MDB49 DQB_48 CLKB1
C19 A26 U2
MDA49 DQA_48 CLKA1 MDB50 DQB_49 CLKB0#
B19 U1 B3
MDA50 DQA_49 CLKA0# MDB51 DQB_50 CLKB0B CLKB1#
A19 B33 V2 K2
MDA51 DQA_50 CLKA0B CLKA1# R4500 MDB52 DQB_51 CLKB1B
B18 B26 Y3
R4501 MDA52 DQA_51 CLKA1B MDB53 DQB_52 RASB0#
C16 40 2Ohm Y2 D3
MDA53 DQA_52 RASA0# MDB54 DQB_53 RASB0B RASB1#
40 2Ohm B16 A31 AA2 K7
PLACE MVREF DIVIDERS MDA54 DQA_53 RASA0B RASA1# MDB55 DQB_54 RASB1B
C15 D24 AA1
AND CAPS CLOSE TO ASIC MDA55 DQA_54 RASA1B MDB56 DQB_55 CASB0#
A15 U9 C1
MDA56 DQA_55 CASA0# MDB57 DQB_56 CASB0B CASB1#
H18 C32 U7 K4
B MDA57 DQA_56 CASA0B CASA1# MDB58 DQB_57 CASB1B B
F18 H26 U6
MDA58 DQA_57 CASA1B R4503 MDB59 DQB_58 CSB0_0#
E18 V4 E1
R4502 C4501 MDA59 DQA_58 CSA0_0# MDB60 DQB_59 CSB0B_0
D18 A30 100OHM W9 E2
0 1UF 16V MDA60 DQA_59 CSA0B_0 MDB61 DQB_60 CSB0B_1
100OHM J17 B30 W7
MDA61 DQA_60 CSA0B_1 MDB62 DQB_61 CSB1_0#
G15 W6 L3
MDA62 DQA_61 CSA1_0# MDB63 DQB_62 CSB1B_0
E15 G24 W4 M4
MDA63 DQA_62 CSA1B_0 DQB_63 CSB1B_1
D15 H24
DQA_63 CSA1B_1 CKEB0
B14 E3
CKEA0 MVREFDB CKEB0 CKEB1
N35 B31 A13 K8
MVREFDA CKEA0 CKEA1 +1 8VS_GPU R4504 MVREFSB CKEB1
N34 F24
+1 8VS_GPU MVREFSA CKEA1 WEB0#
1 2 AM30
TESTEN WEB0B
F2
C29 WEA0# AA8 M6 WEB1#
WEA0B WEA1# 1KOhm TEST_MCLK WEB1B
D22 AA7
WEA1B R4506 TEST_YCLK MEM_RST
AA5 MEMTEST DRAM_RST AA4
R4505 40 2Ohm AH19
PLLTEST
40 2Ohm
M76 M
M76 M
R4508
4 7KOhm
R4509 R4510 R4511 R4512
R4507 C4502 100OHM 4 7KOhm 4 7KOhm 240OHM
100OHM PLACE MVREF DIVIDERS
0 1UF 16V AND CAPS CLOSE TO ASIC
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom M76(5/5)Memory I/F 20
Date: 14 2007 Sheet 45 of 69
5 4 3 2 1
5 4 3 2 1
U4600 U4601
MDA8 T3 A1 MDA32 T3 A1
MDA11 DQ31/DQ23 VDDQ MDA35 DQ31/DQ23 VDDQ
T2 A12 T2 A12
MDA10 DQ30/DQ22 VDDQ#A12 MDA34 DQ30/DQ22 VDDQ#A12
R3 C1 R3 C1
MDA9 DQ29/DQ21 VDDQ#C1 MDA33 DQ29/DQ21 VDDQ#C1 +1.8VS_GPU
R2 C4 R2 C4
MDA12 DQ28/DQ20 VDDQ#C4 MDA39 DQ28/DQ20 VDDQ#C4
M3 C9 M3 C9
MDA13 DQ27/DQ19 VDDQ#C9 MDA37 DQ27/DQ19 VDDQ#C9
N2 C12 N2 C12
D MDA15 DQ26/DQ18 VDDQ#C12 MDA38 DQ26/DQ18 VDDQ#C12 D
L3 E1 L3 E1
MDA14 DQ25/DQ17 VDDQ#E1 MDA36 DQ25/DQ17 VDDQ#E1
M2 E4 M2 E4
MDA24 DQ24/DQ16 VDDQ#E4 MDA40 DQ24/DQ16 VDDQ#E4 A_BA2
T10 E9 T10 E9 45 A_BA2
MDA25 DQ23/DQ31 VDDQ#E9 +1.8VS_GPU MDA42 DQ23/DQ31 VDDQ#E9 A_BA1
T11 E12 T11 E12 45 A_BA1
MDA26 DQ22/DQ30 VDDQ#E12 MDA41 DQ22/DQ30 VDDQ#E12 A_BA0
R10 J4 R10 J4 45 A_BA0
MDA27 DQ21/DQ29 VDDQ#J4 MDA44 DQ21/DQ29 VDDQ#J4
R11 J9 R11 J9
MDA28 DQ20/DQ28 VDDQ#J9 MDA46 DQ20/DQ28 VDDQ#J9
M10 N1 M10 N1 45 MAA[0..11]
MDA31 DQ19/DQ27 VDDQ#N1 MDA43 DQ19/DQ27 VDDQ#N1
N11 N4 N11 N4
MDA29 DQ18/DQ26 VDDQ#N4 MDA47 DQ18/DQ26 VDDQ#N4
L10 N9 L10 N9 45 WDQSA[0..7]
MDA30 DQ17/DQ25 VDDQ#N9 MDA45 DQ17/DQ25 VDDQ#N9
M11 N12 M11 N12
MDA19 DQ16/DQ24 VDDQ#N12 MDA56 DQ16/DQ24 VDDQ#N12
G10 R1 G10 R1 45 RDQSA[0..7]
MDA23 DQ15/DQ7 VDDQ#R1 MDA59 DQ15/DQ7 VDDQ#R1
F11 R4 F11 R4
MDA18 DQ14/DQ6 VDDQ#R4 MDA57 DQ14/DQ6 VDDQ#R4
F10 R9 F10 R9 45 DQMA#[0..7]
MDA21 DQ13/DQ5 VDDQ#R9 MDA58 DQ13/DQ5 VDDQ#R9
E11 R12 E11 R12
MDA16 DQ12/DQ4 VDDQ#R12 MDA60 DQ12/DQ4 VDDQ#R12
C10 U1 C10 U1 45 MDA[0..63]
MDA22 DQ11/DQ3 VDDQ#V1 MDA61 DQ11/DQ3 VDDQ#V1
C11 U12 C11 U12
MDA20 DQ10/DQ2 VDDQ#V12 MDA62 DQ10/DQ2 VDDQ#V12
B10 B10
MDA17 DQ9/DQ1 MDA63 DQ9/DQ1 MEM_RST
B11 A2 B11 A2 45,47 MEM_RST
MDA3 DQ8/DQ0 VDD MDA49 DQ8/DQ0 VDD
G3 A11 G3 A11
MDA7 DQ7/DQ15 VDD#A11 MDA48 DQ7/DQ15 VDD#A11
F2 F1 F2 F1
MDA2 DQ6/DQ14 VDD#F1 MDA50 DQ6/DQ14 VDD#F1
F3 F12 F3 F12
MDA6 DQ5/DQ13 VDD#F12 MDA51 DQ5/DQ13 VDD#F12
E2 M1 E2 M1
MDA0 DQ4/DQ12 VDD#M1 MDA55 DQ4/DQ12 VDD#M1
C3 M12 C3 M12
MDA4 DQ3/DQ11 VDD#M12 MDA52 DQ3/DQ11 VDD#M12
C2 U2 C2 U2
MDA5 DQ2/DQ10 VDD#V2 MDA54 DQ2/DQ10 VDD#V2
B3 U11 B3 U11
MDA1 DQ1/DQ9 VDD#V11 MDA53 DQ1/DQ9 VDD#V11
B2 B2
DQ0/DQ8 DQ0/DQ8
B1 B1
VSSQ VSSQ
B4 B4
A_BA2 VSSQ#B4 A_BA2 VSSQ#B4
H10 B9 H10 B9
A_BA1 BA2/RAS# VSSQ#B9 A_BA1 BA2/RAS# VSSQ#B9 DDR3 MEMORY CONTROL SIGNAL PULLUP RESISTOR VALUES
G9 B12 G9 B12
A_BA0 BA1/BA0 VSSQ#B12 A_BA0 BA1/BA0 VSSQ#B12 MAY CHANGE BETWEEN M66M,M71M AND M72M,M76M.
G4 D1 G4 D1
BA0/BA1 VSSQ#D1 BA0/BA1 VSSQ#D1 SEE LAYOUT GUIDE FOR LATEST INFORMATION
D4 D4
C MAA11 VSSQ#D4 MAA11 VSSQ#D4 C
L4 D9 L4 D9
MAA10 A11/A7 VSSQ#D9 MAA10 A11/A7 VSSQ#D9
K2 A10/A8 VSSQ#D12 D12 K2 A10/A8 VSSQ#D12 D12
MAA9 M9 G2 MAA9 M9 G2 +1.8VS_GPU
MAA8 A9/A3 VSSQ#G2 MAA8 A9/A3 VSSQ#G2
K11 G11 K11 G11
MAA7 A8/AP/A10 VSSQ#G11 MAA7 A8/AP/A10 VSSQ#G11
L9 L2 L9 L2
MAA6 A7/A11 VSSQ#L2 MAA6 A7/A11 VSSQ#L2
K10 L11 K10 L11
MAA5 A6/A2 VSSQ#L11 MAA5 A6/A2 VSSQ#L11 R4600
H11 P1 H11 P1
MAA4 A5/A1 VSSQ#P1 MAA4 A5/A1 VSSQ#P1 CSA0_0#
K9 P4 K9 P4 45 CSA0_0# 1 2
PLACE VREF DIVIDER COMPONENTS MAA3 A4/A0 VSSQ#P4 MAA3 A4/A0 VSSQ#P4 R4601
M4 P9 M4 P9
MAA2 A3/A9 VSSQ#P9 MAA2 A3/A9 VSSQ#P9 CSA1_0#
AS CLOSE TO MEMORY AS POSSIBLE K3 P12 PLACE VREF DIVIDER COMPONENTS K3 P12 45 CSA1_0# 1 2 121OHM
MAA1 A2/A6 VSSQ#P12 AS CLOSE TO MEMORY AS POSSIBLE MAA1 A2/A6 VSSQ#P12
H2 T1 H2 T1
MAA0 A1/A5 VSSQ#T1 MAA0 A1/A5 VSSQ#T1 121OHM R4602
K4 T4 K4 T4
A0/A4 VSSQ#T4 A0/A4 VSSQ#T4 RASA0#
T9 T9 45 RASA0# 1 2
+1.8VS_GPU CSA0_0# VSSQ#T9 +1.8VS_GPU CSA1_0# VSSQ#T9 R4605
F9 T12 F9 T12
CS#/CAS# VSSQ#T12 CS#/CAS# VSSQ#T12 RASA1#
A3 A3 45 RASA1# 1 2 121OHM
WEA0# VSS WEA1# VSS
H9 A10 H9 A10
WE#/CKE VSS#A10 WE#/CKE VSS#A10 121OHM R4607
G1 G1
R4603 RASA0# VSS#G1 R4604 RASA1# VSS#G1 CASA0#
H3 G12 H3 G12 45 CASA0# 1 2
RAS#/BA2 VSS#G12 RAS#/BA2 VSS#G12 R4606
2.37KOHM L1 2.37KOHM L1
CASA0# VSS#L1 CASA1# VSS#L1 CASA1#
F4
CAS#/CS# VSS#L12
L12 F4
CAS#/CS# VSS#L12
L12 45 CASA1# 1 2 121OHM
U3 U3
CKEA0 VSS#V3 CKEA1 VSS#V3 L4600 121OHM R4611
H4 U10 H4 U10
C4601 R4608 CKE/WE VSS#V10 C4600 R4609 CKE/WE VSS#V10 CKEA0
45 CKEA0 1 2
5.49KOHM CLKA0# J10 120Ohm/100Mhz L4601 5.49KOHM CLKA1# J10 120Ohm/100Mhz R4610
0.1UF/16V CLKA0 CK# 0.1UF/16V CLKA1 CK# CKEA1
J11 K1 1 2 J11 K1 1 2 45 CKEA1 1 2 121OHM
CK VDDA CK VDDA
K12 1 2 K12 1 2
RDQSA1 VDDA#K12 RDQSA4 VDDA#K12 121OHM R4613
P3 P3
RDQSA3 RDQS3/RDQS2 C4602 120Ohm/100Mhz L4602 RDQSA5 RDQS3/RDQS2 C4604 120Ohm/100Mhz CLKA1
P10 P10 45 CLKA1 1 2
RDQSA2 RDQS2/RDQS3 C4603 RDQSA7 RDQS2/RDQS3 C4605 R4612
D10 D10
RDQSA0 RDQS1/RDQS0 0.1UF/16V RDQSA6 RDQS1/RDQS0 0.1UF/16V L4603 CLKA1#
D3 0.1UF/16V D3 0.1UF/16V 45 CLKA1# 1 2 60.4OHM
RDQS0/RDQS1 RDQS0/RDQS1
WDQSA1 P2 WDQSA4 P2 60.4OHM R4617
B +1.8VS_GPU WDQSA3 WDQS3/WDQS2 +1.8VS_GPU WDQSA5 WDQS3/WDQS2 CLKA0 B
P11 J12 P11 J12 45 CLKA0 1 2
WDQSA2 WDQS2/WDQS3 VSSA#J12 WDQSA7 WDQS2/WDQS3 VSSA#J12 R4616
D11 J1 D11 J1
WDQSA0 WDQS1/WDQS0 VSSA WDQSA6 WDQS1/WDQS0 VSSA CLKA0#
D2
WDQS0/WDQS1
D2
WDQS0/WDQS1 45 CLKA0# 1 2 60.4OHM
R4614 R4615
2.37KOHM DQMA#1 N3 J3 2.37KOHM DQMA#4 N3 J3 60.4OHM R4619
DQMA#3 DM3/DM2 RFU2 DQMA#5 DM3/DM2 RFU2 WEA0#
N10 N10 45 WEA0# 1 2
DQMA#2 DM2/DM3 DQMA#7 DM2/DM3 R4618
E10 J2 E10 J2
DQMA#0 DM1/DM0 RFU1 DQMA#6 DM1/DM0 RFU1 WEA1#
E3 E3 45 WEA1# 1 2 121OHM
DM0/DM1 DM0/DM1
U4 U4
R4620 MEM_RST SEN R4622 MEM_RST SEN 121OHM
U9 U9
C4606 R4621 RESET C4607 R4623 RESET
5.49KOHM 5.49KOHM
0.1UF/16V 1 2 A4 0.1UF/16V 1 2 A4
ZQ ZQ
243OHM 243OHM
H1 H1
VREF VREF
A9 A9
MF MF
H12 H12
VREF#H12 VREF#H12
HYB18H512321BF HYB18H512321BF
+1.8VS_GPU +1.8VS_GPU
A A
C4608 C4609 C4610 C4611 C4612 C4613 C4614 C4615 C4616 C4617 C4618 C4619 C4620 C4621 C4622 C4623 C4624 C4625 C4626 C4627 C4628 C4629 C4630 C4631
1UF/10V 1UF/10V 10UF/10V 10UF/10V 0.01UF/16V 0.01UF/16V 0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V 1UF/10V 1UF/10V 10UF/10V 10UF/10V 0.01UF/16V 0.01UF/16V 0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V0.1UF/16V
Title : A7K
ASUSTECH CO.,LTD. Engineer: Endy Zhang
Size Project Name Rev
Custom GDDR3 Memory(1/2) 2.0
Date: , 14, 2007 Sheet 46 of 69
5 4 3 2 1
5 4 3 2 1
U4700 U4701
MDB9 T3 A1 MDB33 T3 A1
MDB10 DQ31/DQ23 VDDQ MDB34 DQ31/DQ23 VDDQ
T2 A12 T2 A12
MDB11 DQ30/DQ22 VDDQ#A12 +1 8VS_GPU MDB32 DQ30/DQ22 VDDQ#A12 +1 8VS_GPU
R3 C1 R3 C1
MDB8 DQ29/DQ21 VDDQ#C1 MDB35 DQ29/DQ21 VDDQ#C1
R2 C4 R2 C4
D MDB15 DQ28/DQ20 VDDQ#C4 MDB38 DQ28/DQ20 VDDQ#C4 D
M3 C9 M3 C9
MDB14 DQ27/DQ19 VDDQ#C9 MDB36 DQ27/DQ19 VDDQ#C9
N2 C12 N2 C12
MDB13 DQ26/DQ18 VDDQ#C12 MDB39 DQ26/DQ18 VDDQ#C12
L3 E1 L3 E1
MDB12 DQ25/DQ17 VDDQ#E1 MDB37 DQ25/DQ17 VDDQ#E1
M2 E4 M2 E4
MDB24 DQ24/DQ16 VDDQ#E4 MDB40 DQ24/DQ16 VDDQ#E4
T10 E9 T10 E9
MDB26 DQ23/DQ31 VDDQ#E9 MDB42 DQ23/DQ31 VDDQ#E9
T11 E12 T11 E12
MDB25 DQ22/DQ30 VDDQ#E12 MDB41 DQ22/DQ30 VDDQ#E12
R10 J4 R10 J4
MDB27 DQ21/DQ29 VDDQ#J4 MDB43 DQ21/DQ29 VDDQ#J4
R11 J9 R11 J9
MDB30 DQ20/DQ28 VDDQ#J9 MDB46 DQ20/DQ28 VDDQ#J9 B_BA2
M10 N1 M10 N1 45 B_BA2
MDB28 DQ19/DQ27 VDDQ#N1 MDB47 DQ19/DQ27 VDDQ#N1 B_BA1
N11 N4 N11 N4 45 B_BA1
MDB31 DQ18/DQ26 VDDQ#N4 MDB45 DQ18/DQ26 VDDQ#N4 B_BA0
L10 N9 L10 N9 45 B_BA0
MDB29 DQ17/DQ25 VDDQ#N9 MDB44 DQ17/DQ25 VDDQ#N9
M11 N12 M11 N12
MDB3 DQ16/DQ24 VDDQ#N12 MDB58 DQ16/DQ24 VDDQ#N12
G10 R1 G10 R1 45 MAB[0 11]
MDB2 DQ15/DQ7 VDDQ#R1 MDB57 DQ15/DQ7 VDDQ#R1
F11 R4 F11 R4
MDB7 DQ14/DQ6 VDDQ#R4 MDB59 DQ14/DQ6 VDDQ#R4
F10 R9 F10 R9 45 WDQSB[0 7]
MDB6 DQ13/DQ5 VDDQ#R9 MDB56 DQ13/DQ5 VDDQ#R9
E11 R12 E11 R12
MDB4 DQ12/DQ4 VDDQ#R12 MDB60 DQ12/DQ4 VDDQ#R12
C10 U1 C10 U1 45 RDQSB[0 7]
MDB1 DQ11/DQ3 VDDQ#V1 MDB63 DQ11/DQ3 VDDQ#V1
C11 U12 C11 U12
MDB5 DQ10/DQ2 VDDQ#V12 MDB61 DQ10/DQ2 VDDQ#V12
B10 B10 45 DQMB#[0 7]
MDB0 DQ9/DQ1 MDB62 DQ9/DQ1
B11 DQ8/DQ0 VDD A2 B11 DQ8/DQ0 VDD A2
MDB18 G3 A11 MDB48 G3 A11 45 MDB[0 63]
MDB23 DQ7/DQ15 VDD#A11 MDB51 DQ7/DQ15 VDD#A11
F2 F1 F2 F1
MDB19 DQ6/DQ14 VDD#F1 MDB50 DQ6/DQ14 VDD#F1
F3 F12 F3 F12
MDB22 DQ5/DQ13 VDD#F12 MDB49 DQ5/DQ13 VDD#F12 MEM_RST
E2 M1 E2 M1 45 46 MEM_RST
MDB16 DQ4/DQ12 VDD#M1 MDB52 DQ4/DQ12 VDD#M1
C3 M12 C3 M12
MDB20 DQ3/DQ11 VDD#M12 MDB54 DQ3/DQ11 VDD#M12
C2 U2 C2 U2
MDB21 DQ2/DQ10 VDD#V2 MDB53 DQ2/DQ10 VDD#V2
B3 U11 B3 U11
MDB17 DQ1/DQ9 VDD#V11 MDB55 DQ1/DQ9 VDD#V11
B2 B2
DQ0/DQ8 DQ0/DQ8
B1 B1
VSSQ VSSQ
B4 B4
B_BA2 VSSQ#B4 B_BA2 VSSQ#B4
H10 B9 H10 B9
B_BA1 BA2/RAS# VSSQ#B9 B_BA1 BA2/RAS# VSSQ#B9
G9 B12 G9 B12
C B_BA0 BA1/BA0 VSSQ#B12 B_BA0 BA1/BA0 VSSQ#B12 DDR3 MEMORY CONTROL SIGNAL PULLUP RESISTOR VALUES C
G4 D1 G4 D1
BA0/BA1 VSSQ#D1 BA0/BA1 VSSQ#D1 MAY CHANGE BETWEEN M66M M71M AND M72M M76M
D4 D4
MAB11 VSSQ#D4 MAB11 VSSQ#D4 SEE LAYOUT GUIDE FOR LATEST INFORMATION
L4 D9 L4 D9
MAB10 A11/A7 VSSQ#D9 MAB10 A11/A7 VSSQ#D9
K2 D12 K2 D12
MAB9 A10/A8 VSSQ#D12 MAB9 A10/A8 VSSQ#D12 +1 8VS_GPU
M9 G2 M9 G2
MAB8 A9/A3 VSSQ#G2 MAB8 A9/A3 VSSQ#G2
K11 G11 K11 G11
MAB7 A8/AP A10 VSSQ#G11 MAB7 A8/AP A10 VSSQ#G11
L9 L2 L9 L2
MAB6 A7/A11 VSSQ#L2 MAB6 A7/A11 VSSQ#L2
K10 L11 K10 L11
MAB5 A6/A2 VSSQ#L11 MAB5 A6/A2 VSSQ#L11 R4700
H11 P1 H11 P1
MAB4 A5/A1 VSSQ#P1 MAB4 A5/A1 VSSQ#P1 CSB0_0#
K9 P4 K9 P4 45 CSB0_0# 1 2
PLACE VREF DIVIDER COMPONENTS MAB3 A4/A0 VSSQ#P4 PLACE VREF DIVIDER COMPONENTS MAB3 A4/A0 VSSQ#P4 R4701
M4 P9 M4 P9
AS CLOSE TO MEMORY AS POSSIBLE MAB2 A3/A9 VSSQ#P9 AS CLOSE TO MEMORY AS POSSIBLE MAB2 A3/A9 VSSQ#P9 CSB1_0# 1
K3 P12 K3 P12 45 CSB1_0# 2 121OHM
MAB1 A2/A6 VSSQ#P12 MAB1 A2/A6 VSSQ#P12
H2 T1 H2 T1
MAB0 A1/A5 VSSQ#T1 MAB0 A1/A5 VSSQ#T1 121OHM R4702
K4 T4 K4 T4
A0/A4 VSSQ#T4 A0/A4 VSSQ#T4 RASB0#
T9 T9 45 RASB0# 1 2
+1 8VS_GPU CSB0_0# VSSQ#T9 +1 8VS_GPU CSB1_0# VSSQ#T9 R4705
F9 T12 F9 T12
CS#/CAS# VSSQ#T12 CS#/CAS# VSSQ#T12 RASB1#
VSS A3 VSS A3 45 RASB1# 1 2 121OHM
WEB0# H9 A10 WEB1# H9 A10
WE# CKE VSS#A10 WE# CKE VSS#A10 121OHM R4707
G1 G1
R4703 RASB0# VSS#G1 R4704 RASB1# VSS#G1 CASB0#
H3 G12 H3 G12 45 CASB0# 1 2
RAS#/BA2 VSS#G12 RAS#/BA2 VSS#G12 R4706
2 37KOHM L1 2 37KOHM L1
CASB0# VSS#L1 CASB1# VSS#L1 CASB1#
F4
CAS#/CS# VSS#L12
L12 F4
CAS#/CS# VSS#L12
L12 45 CASB1# 1 2 121OHM
U3 U3
CKEB0 VSS#V3 CKEB1 VSS#V3 121OHM R4710
H4 U10 H4 U10
C4701 R4708 CKE/WE VSS#V10 C4700 R4709 CKE/WE VSS#V10 CKEB0
45 CKEB0 1 2
5 49KOHM CLKB0# J10 120Ohm/100Mhz L4701 5 49KOHM CLKB1# J10 120Ohm/100Mhz L4700 R4711
0 1UF 16V CLKB0 CK# 0 1UF 16V CLKB1 CK# CKEB1
J11 K1 1 2 J11 K1 1 2 45 CKEB1 1 2 121OHM
CK VDDA CK VDDA
K12 1 2 K12 1 2
RDQSB1 VDDA#K12 RDQSB4 VDDA#K12 121OHM R4713
P3 P3
RDQSB3 P10 RDQS3/RDQS2 C4702 120Ohm/100Mhz L4702 RDQSB5 RDQS3/RDQS2 C4704 120Ohm/100Mhz L4703 45 CLKB1
P10 CLKB1 1 2
RDQSB0 D10 RDQS2/RDQS3 C4703 RDQSB7 RDQS2/RDQS3 C4705 R4712
D10
RDQSB2 D3 RDQS1/RDQS0 0 1UF/16V RDQSB6 RDQS1/RDQS0 0 1UF/16V CLKB1#
RDQS0/RDQS1 0 1UF/16V D3
RDQS0/RDQS1 0 1UF/16V 45 CLKB1# 1 2 60 4OHM
B B
WDQSB1 P2 WDQSB4 P2 60 4OHM R4715
+1 8VS_GPU WDQSB3 P11 WDQS3/WDQS2 +1 8VS_GPU WDQSB5 WDQS3/WDQS2 CLKB0
J12 P11 J12 45 CLKB0 1 2
WDQSB0 D11 WDQS2/WDQS3 VSSA#J12 WDQSB7 WDQS2/WDQS3 VSSA#J12 R4714
J1 D11 J1
WDQSB2 D2 WDQS1/WDQS0 VSSA WDQSB6 WDQS1/WDQS0 VSSA CLKB0#
WDQS0/WDQS1
D2
WDQS0/WDQS1 45 CLKB0# 1 2 60 4OHM
R4716 R4717
2 37KOHM DQMB#1 N3 J3 2 37KOHM DQMB#4 N3 J3 60 4OHM R4718
DQMB#3 N10 DM3/DM2 RFU2 DQMB#5 DM3/DM2 RFU2 WEB0#
N10 45 WEB0# 1 2
DQMB#0 E10 DM2/DM3 DQMB#7 DM2/DM3 R4720
J2 E10 J2
DQMB#2 DM1/DM0 RFU1 DQMB#6 DM1/DM0 RFU1 WEB1#
E3
DM0/DM1
E3
DM0/DM1 45 WEB1# 1 2 121OHM
U4 U4
R4719 MEM_RST SEN R4722 MEM_RST SEN 121OHM
U9 U9
C4706 R4721 RESET C4707 R4723 RESET
5 49KOHM 5 49KOHM
0 1UF/16V 1 2 A4 0 1UF/16V 1 2 A4
ZQ ZQ
243OHM 243OHM
H1 H1
VREF VREF
A9 A9
MF MF
H12 H12
VREF#H12 VREF#H12
HYB18H512321BF HYB18H512321BF
+1 8VS_GPU +1 8VS_GPU
A A
C4710 C4711 C4722 C4723
C4708 C4709 C4712 C4713 C4714 C4715 C4716 C4717 C4718 C4719 C4720 C4721 C4724 C4725 C4726 C4727 C4728 C4729 C4730 C4731
1UF/10V 1UF 10V 4 7UF/6 3V 4 7UF/6 3V 0 01UF/16V 0 01UF/1 V 0 1UF/16V0 1UF/ 6V0 1UF 16V0 1UF 16V0 1UF 16V0 1UF 16V 1UF/10V 1UF 10V 4 7UF/6 3V 4 7UF/6 3V 0 01UF/16V 0 01UF/1 V 0 1UF/16V0 1UF/ 6V0 1UF/ 6V0 1UF/16V0 1UF 16V0 1UF 16V
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom GDDR3 Memory(2/2) 20
Date: 14 2007 Sheet 47 of 69
5 4 3 2 1
5 4 3 2 1
+3VS_GPU ALLOW STRAP FOR PLACE ALL DECOUPLING AS CLOSE TO ASIC AS POSSIBLE
+3VS_GPU THERMAL CONTROL POSSIBLE LVDDR TO 120Ohm/100Mhz (3 3V @ 250MA LVDDR)
FROM SYSTEM (SMBUS) +3VS_GPU +1 8V L4800 (1 8V @ 250MA LVDDR) L4801 (1 8V @ 400MA PCIE VDDR)
OR FROM ANY AVAILABLE FOR M72M M76M
3 3V_DELAY 1 2 LVDDR +1 8VS_GPU 1 2 /M76 PCIE_IO
ASIC DDC I2C
120Ohm/100Mhz C4801 C4802 C4803 400Ohm 100Mhz C4804 C4805 C4806
R4800 R4801 L4802 10UF/10 1UF 10V 0 1UF/16V 10UF/10V 1UF/10V 0 1UF/16V
C4800 C4807 4 7KOhm 4 7KOhm 1 2 /M66
+1 8VS_GPU
2 1 0 1UF 16V 120Ohm/100Mhz
L4804 (1 8V @ MA VDDRHA 1 INCLUDED IN VDDR1)
ADDRESS:9AH 120Ohm/100Mhz 1 2
2200PF/50V (1 8V @70MA LVDDC) +1 8VS_GPU VDD_MEM_CLK0
D A7K L4803 D
+1 8VS_GPU 1 2 /M76 LVDDC C4808 C4809 C4810
U4800 Q4800A 10UF/10V 1UF/10V 0 1UF/16V
1 8 1 6 C4811 C4812 C4813
VDD SCLK SMB1_CLK 21 28
2 7 UM6K1N 10UF/10 1UF 10V 0 1UF/16V 120Ohm/100Mhz
42 G_D+ D+ SDATA (1 8V @ MA VDDRHA 2 INCLUDED IN VDDR1)
3 6 L4806
42 G_D D ALERT#
4 5 120Ohm/100Mhz +1 8VS_GPU 1 2 VDD_MEM_CLK1
+3VS_GPU THERM# GND L4805 (1 8V @ 20MA LPVDD)
ADM1032ARMZ 2 Q4800B +1 8VS_GPU 1 2 LPVDD C4814 C4815 C4816
4 3 SMB1_DAT 21 28 10UF/10V 1UF/10V 0 1UF/16V
UM6K1N C4817 C4818 C4819
10UF/10V 1UF 10V 0 1UF/16V 120Ohm/100Mhz
3 2 A7K L4808 (1 8V @ MA VDDRHB 1 INCLUDED IN VDDR1)
21 OS#_OC_GPU
R4802 0Ohm /x 120Ohm/100Mhz +1 8VS_GPU 1 2 VDD_MEM_CLK2
1 2 L4807 (1 8V @ 40MA DPLL PVDD)
G_I2C_CLK 42
+1 8VS_GPU 1 2 DPLL_PVDD C4822 C4823 C4824
Q4801 R4803 0Ohm /x 10UF/10 1UF/10V 0 1UF/16V
2N7002 1 2 C4820 C4821 C4825 120Ohm/100Mhz
G_I2C_DAT 42 (1 8V @ MA VDDRHB 2 INCLUDED IN VDDR1)
120Ohm 100Mhz 10UF/10V 1UF 10V 0 1UF/16V L4809
L4810 +1 8VS_GPU 1 2 VDD_MEM_CLK3
+1 8VS_GPU 1 2 /M76
(1 8V @ 40MA PCIE PVDD) C4826 C4827 C4828
PCIE_PVDD 10UF/10V 1UF/10V 0 1UF/16V
C4829 C4830 C4831 120Ohm/100Mhz
C M72M AND M76M HAVE INTERNAL TEMP SENSORS AND AN EXTERNAL SENSOR CHIP IS NOT REQUIRED ( 95V 1 1V @ 345MA MPVDD) C
10UF/10 1UF 10V 0 1UF/16V L4811
120Ohm/100Mhz +VDD_CORE 1 2 MPVDD
ATI RESERVED CONFIGURATION STRAPS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE L4812
USED THEY MUST NOT CONFLICT DURING RESET 1 2 /M76 (2 5V @ 120MA A2VDD) C4833 C4832 C4834
3 3V_DELAY
+3VS_GPU A2VDD 10UF/10V 1UF/10V 0 1UF/16V
VID0 VID2 VID4 VID6 VID7 HSYNC VHAD0 GPIO2 GPIO3 GPIO8 DVALID
R4808 1 x 2 10KOhm C4835 C4836 C4837 (PCIE VDDC 1 2V 1 25V @ 1 55A
23 42 G_VSYNC 1 1V @ 1A )
10UF/10V 0 1UF/16V 1000PF/16V L4814
42 VHAD0 R4810 1 x 2 10KOhm +1 1V_1 2V_RGE 1 2 PCIE_CORE
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED THEY MUST NOT CONFLICT DURING RESET 120Ohm/100Mhz
R4809 1 x 2 10KOhm L4813 (1 8V @ 2MA A2VDDQ) 120Ohm 100Mhz C4838 C4839 C4840
42 PSYNC
GPIO 28 TDO GENERICC GPIO21 BB EN GPIO 23 CLKREQB (DRIVES LOW DURING RESET) V2SYNC H2SYNC 1 2 /M76 10UF/10V 1UF/10V 0 1UF/16V
+1 8VS_GPU A2VDDQ
42 G_GPIO0 R4811 1 2 10KOhm
C4841 C4842 C4843
R4812 1 2 10KOhm CONFIGURATION STRAPS RECOMMENDED SETTINGS 10UF/10 1UF 10V 0 1UF/16V
42 G_GPIO1 0= DO NOT INSTALL RESISTOR
R4813 1 x 2 10KOhm ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED 1 = INSTALL 10K RESISTOR 120Ohm/100Mhz C4844 C4845 C4846
42 G_V D_1 THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT ( 1 8V @ 100MA VDD1DI)
L4815 1UF 10V 1UF/10V 1UF/10V
R4815 1 x NA = NOT APPLICABLE
42 G_GP O13 2 10KOhm +1 8VS_GPU 1 2 VDD1DI
42 G_GP O12 R4814 1 x 2 10KOhm VDD2DI
42 G_GP O11 R4816 1 2 10KOhm C4847 C4848 C4849
R4817 1 x 2 10KOhm STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS 10UF/10 1000PF/ 6V
0 1UF/16V 120Ohm/100Mhz (DPLL VDDC 1 2V 1 25V @ 65MA
42 G_GP O9 1 1V @ 100 MA)
L4817
42 G_GP O4 R4818 1 x 2 10KOhm 120Ohm/100Mhz 1 2 DPLL_VDDC
B
BIF MSI DIS VID1 0 MESSAGE SIGNAL INTERRUPT ENABLED L4816 (1 8V @ 100MA AVDD) B
42 G_GP O22 R4819 1 x 2 10KOhm +1 8VS_GPU 1 2 AVDD C4850 C4851 C4852
BIF AUDIO EN VID3 X ENABLE HD AUDIO
10UF/10V 1UF/10V 0 1UF/16V
42 G_VID_5 R4820 1 x 2 10KOhm BIF 64BAR EN A VID5 0 64 BIT BARS DISABLED C4853 C4854 C4855
10UF/10V 1000PF/ 6V
0 1UF/16V
42 G_VID_3 R4821 1 2 10KOhm TX PWRS ENB GPIO0 X PCIE FULL TX OUTPUT SWING Q9113 T4801 1 TPC28T
120Ohm/100Mhz PMN45EN T4802 1 TPC28T
R4822 1 x 2 10KOhm TX DEEMPH EN GPIO1 1 PCIE TRANSMITTER DE EMPHASIS ENABLED L4818 (TXVDDR 1 8V @ 100MA SINGLE LINK
42 DVALID 200 MA DUAL LINK) +3VS +3VS_GPU
+1 8VS_GPU 1 2 TXVDDR +12VS
BIF DEBUG ACCESS GPIO4 0 DEBUG SIGNALS NOT MUXED OUT
42 G_VID_7 R4824 1 x 2 10KOhm C4856 C4857 C4858 C9118 (1.5
R4823 1 x 2 10KOhm PLL IBIAS RD 1 GPIO6 0 (M66/71)BIAS CURRENT FOR PCIE PHY PLL MSBIT (M72/76)RSVD 0 1UF/25V
42 G_VID_6 10UF/10V 1UF 10V 0 1UF/16V
42 G_VID_4 R4826 1 x 2 10KOhm R9117 MLCC/+/ 10%
R4825 1 x 10KOhm PLL IBIAS RD 0 GPIO5 0 (M66/71)BIAS CURRENT FOR PCIE PHY PLL LSBIT (M72 76)RSVD 120Ohm/100Mhz
42 G_VID_2 2 10KOhm
R4828 1 x 2 10KOhm L4819 (1 8V @ 20MA TPVDD)
42 G_VID_0 BIOS ROM EN GPIO 22 ROMCSB 1 ENABLE EXTERNAL BIOS ROM 1%
23 42 G_HSYNC R4827 1 2 10KOhm +1 8VS_GPU 1 2 TPVDD
42 G_GP O2 R4829 1 x 2 10KOhm ROMIDCFG(3 0) GPIO[13 11 9] SERIAL ROM TYPE OR MEMORY APERATURE SIZE SELECT
XXXX 3
42 G_GP O6 R4830 1 x 2 10KOhm C4859 C4860 C4861 D
42 G_GP O8 R4831 1 x 2 10KOhm VIP DEVICE STRAP ENA VSYNC X IGNORE VIP DEVICE STRAPS 10UF/10 1000PF/ 6V
0 1UF/16V Q9114
42 G_H2SYNC R4832 1 x 2 10KOhm C9119
R4834 1 x 2 10KOhm BIF VGA DIS PSYNC O VGA ENABLED 120Ohm/100Mhz 0 1UF/25V 11
42 G_V2SYNC GPUPWR_EN# 18 60 66
R4833 1 x 2 10KOhm L4820 (VDD CT 1 8V @ 110MA (VDD CT) MLCC/+/ 10% G 2N7002
42 G_GP O5 S
1 2 2
ECN 6/11/2007
MEM TYPE ANY UNUSED MEMORY TYPE MAKE AND SIZE INFO +1 8VS_GPU VDD_CT
GPIO OR DVP C4862 C4863 C4864
A THAT ARE NOT A
CONFIG STRAPS 10UF/10V 1000PF/ 6V
0 1UF/16V
FOR EXAMPLE
DVPDATA20 23 XXXX
IN THIS DESIGN
PLACE ALL DECOUPLING CAPS
CLOSE TO THE ASIC Title : A7K
R4835 1 /x 2 10KOhm AND RUN DEDICATED TRACES
42 DVPDATA20 FROM ASIC PINS ASUSTECH CO LTD Engineer: Endy Zhang
42 DVPDATA21 R4837 1 /x 2 10KOhm
R4836 1 /x TO JOIN THE GROUND PLANE
42 DVPDATA22 2 10KOhm WITH ONE VIA AT THE CAP
Size Project Name Rev
R4838 1 HYNIX 2 10KOhm
42 DVPDATA23 Custom M76 STARPS THERMAL PLL 20
Date: 14 2007 Sheet 48 of 69
5 4 3 2 1
5 4 3 2 1
DVDD3V 60mA
D D
R4900 1 2 0Ohm +3VS DVDD3V Place near pin 16,32,44
L4901
C4900 1 2 DVDD3V
R4901 1 2 0Ohm 10UF/10V
C4901 300Ohm 100Mhz C4902 C4903 C4904
0 1UF/16V 0 1UF/16V 0 1UF/16V 0 1UF 16V
GND
U4900
R4904 1 2 0Ohm JMB360_LGCZ0B
GND
52 4mA
37 24 ESATA_TXP
ZGPIO3 ASTXP ESATA_TXN ESATA_TXP 36 APVDD
38 23 ESATA_TXN 36
DG18_3 ASTXN
39 22 Place near the
R4905 1 XTEST ASG18 AVDD1 8V
50 ESATA_LED# 2 0Ohm 40
YHDLEDn ASV18
21 PIN18
DVDD1 8V 41 20 ESATA_RXN TA I/RM04FTN1202 Place near pin 4
DV18_3 ASRXN ESATA_RXN 36
42 19 ESATA_RXP L4900
DG18_2 ASRXP SREXT ESATA_RXP 36 APVDD
43 18 R4906 1 2 12KOHM 1 2
DVDD3V DG33_2 ASREXT +1 8VS
44 17
ESATA_SMBCLK DV33_2 ASG33 DVDD3V C4921 C4919 C4906
45 16 300Ohm/100Mhz
ESATA_SMBDAT XSMBCLK ASV33 ESATA XOUT GND C4905 10UF 10V 0 1UF/16V C4907
46 15
R4908 1 ZSMBDAT ASXOUT
2 0Ohm 47
XRSTn ASXIN
14 ESATA XIN 0 1UF/16V 1000PF/16V
13 17 26 27 28 37 40 41 A_RST# 48 13 100UF/6 3V
C DG18_1 NC1 R4909 1 C
2 10MOhm
C4909 GND GND GND
10UF/10V X4900
C4908 25Mhz GND
10UF/10V 1 2
DVDD3V DVDD3V GND C4910 ECERA GC2500003 C4911 C4912 101 1mA
22PF 25V 22PF 25V 10UF/10V
GND c0402 c0402 DVDD1 8V
Place near pin 1,33,41
R4910 R4911
4 7KOhm 4 7KOhm GND GND GND DVDD1 8V
GPP_TXN3 13
79 7mA
16 GPP3_CLK_N GPP_TXP3 13
16 GPP3_CLK_P AVDD1 8V Place near pin 9, 21
PREXT R4912 1 2 12KOHM AVDD1 8V
TA /RM04FTN1202
Place near the C4922 C4923
C4920 PIN6 0 1UF/16V 0 1UF 16V
10UF/10V GND
B B
GND GND
GND
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom E-SATA 20
Date: 14 2007 Sheet 49 of 69
5 4 3 2 1
5 4 3 2 1
+5VSUS +5VSUS
A7K TOP VIEW
PWR_LED#_R
PWR_SW R5001
LED5000
LED LED LED LED SW SW SW SW BLUE
POWER 10KOhm Q5000A
UM6K1N
BT SATA/IDE NumLock CapLock MARATHON P4PHONE CLOREN DISTP T5000 1 TPC28T 2
Q5000B
UM6K1N
R5000 5
D 28 PWR_LED_UP# D
SW LED SW SW SW SW LED LED LED LED 1KOhm
+5VS
+3VS +5VS
BT_LED#
C5000 CAP_LED#
R5002 R5003 0 1UF/16V NUM_LED#
10KOhm 1 2
10KOhm Q5001A D5000 RB717F 3
D
UM6K1N 1 3
49 ESATA_LED# D
2 3 Q5003
19 SATA_LED# 2 Q5002
28 CAP_LED 11
Q5001B U5000 11 G 2N7002
UM6K1N 1 A 5
28 NUM_LED G 2N7002 2 S
VCC 2 S
19 BT_LED_EN# 5
35 IDE_PDASP# 2 B
CON5000
+5V
FPC_20P
POWER SWITCH 1 2 +3VA
C5004
4 7UF 6 3V R5014 100KOhm
LID SWITCH 1 2 +3VA
R5015
GND /X GND 2 1 LID_SW#
A 28 LID_EC# A
R5016
1 2 CIR_RX 10KOhm C5005
37 CIR_RX_SIO
0 01UF/16V
0Ohm
R5017
1 2 GND
28 CIR_RX_EC
Title : A7K
N/A 0Ohm ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Function Key 20
Date: 14 2007 Sheet 50 of 69
5 4 3 2 1
5 4 3 2 1
D D
28 55 CPU_VRON
T5100 1 TPC28T
+3VSUS T5101 1 TPC28T
MVPOK# 28
R5104
R5102 100KOhm
VSUS_GD_EC# 28 3
100KOhm /x D
3 Q5101
D
2N7002
Q5100
55 67 CPU_VLD 11
11 G
56 67 SUS_PWRGD
G 2N7002 2 S
2 S
C5100 C5101
0 1UF/16V
0 22UF/6 3V GND
C C
R5103 0Ohm
GND 1 2 HTVDD_EN 66
GND GND
minimum 20ms
B B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Power Sequence 20
Date: 14 2007 Sheet 51 of 69
5 4 3 2 1
5 4 3 2 1
+3VA
SUSB_PWR SUSC_PWR
3 3 3 3 3 3
D D D D D D
C5201 Q5200 Q5201 Q5202 Q5203 Q5204 Q5205
C5200 11 11 11 11 11 11
G 2N7002 G 2N7002 G 2N7002 G 2N7002 G 2N7002 G 2N7002
Q5206A Q5206B 0 1UF/16V 2 S 2 S 2 S 2 S 2 S 2 S
UM6K1N 0 1UF 16V UM6K1N /x
SUSB#_PWR 2 /x SUSC#_PWR 5
56 57 58 59 60 66 68 SUSB#_PWR
GND GND GND GND GND GND
SUSC_PWR
D5200
FORCE_OFF# 2 1
+12VS +5VS +3VS +2 5VS +1 5VS
1SS355
D5201
FORCE_OFF# 2 1 3 3 3 3 3
D D D D D
Q5207 Q5208 Q5209 Q5210 Q5211
1SS355 11 11 11 11 11
C G 2N7002 G 2N7002 G 2N7002 G 2N7002 G 2N7002 C
2 S 2 S 2 S 2 S 2 S
150Ohm/100Mhz A D_DOCK_IN
WAFER_HD_4P L5201
4 DC JACK_IN 1 2 +3VS +12VS
3
2 150Ohm/100Mhz
1 C5202 D5202 C5203 C5204
T5208
0 1UF 16V 10UF/25V 0 1UF/16V
CON5200 c0402 FS1J4TP c1210_h87 c0402 R5213 R5214 1
10KOhm 100KOhm
L5202 r0402 r0402 TPC28T
1 2 TPC28T 1 T5206
B
DC_IN Conn. 18 WLAN_ON# 11
G
S S 2
G
11
BT_ON# 18 36 B
2N7002 2 2N7002
D5203
NA
DAN202K
GND GND
+3VA
+5VS R5218 2 1 100KOhm SW5201
r0402 x 4 P GND
FORCE_OFF# 28 42 56 67 1
1 2 RF_FORCE_OFF# 2
28 RF_OFF_SW#
R5216 D5204 1SS355 3
100KOhm 5 P GND
SWITCH_3P
SW5200
FORCE_OFF# 1 2
1 2
3 3 4 4 GND
C5205 5
5
0 1UF/16V
TACT_SW TCH_5P
GND GND
GND
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom Discharge 20
Date: 14 2007 Sheet 52 of 69
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom BLANK 20
Date: 14 2007 Sheet 53 of 69
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : A7K
ASUSTECH CO LTD Engineer: Endy Zhang
Size Project Name Rev
Custom BLANK 20
Date: 14 2007 Sheet 54 of 69
5 4 3 2 1
5 4 3 2 1
input
current
(4.3A) AC BAT SYS
+ +
Q8001 Q8002
SI4392DY SI4392DY
D D
12/13
11/17 (35A)
T8001 +VCORE
TPC28T DCR=0.0017om
+3VS
L8000 R8007
1 2 1 2
4G 4G D8001 1 82KOhm
51 67 CPU VLD
R8009 S S
1 2 C8005
7 CPU VID0
EC31QS04 2 1
7 CPU VID1
0Ohm
7 CPU VID2
0 22UF/25V C8006
7 CPU VID3
7 CPU VID4 1 2
7 CPU VID5
D8002 1 1000PF 50V
3 @ OA N
+5VS
2
U8000
C8007 OA N+
MAX8760ETL 4 7UF/16V RB717F R8025 2 1 0Ohm
R8024 2 1 0Ohm
R6139 close to
L6101
20 31 AC BAT SYS
OAIN+ D4 PGND
19 32
OAIN R8018 10KOHM @ D5 DLS
18 33
R8021 1MOhm SKIP# DHS R8022
C 2 1 1 2 17 OA N+ LXS 34 + + C
R8019 1KOhm R8026 470Ohm 1 2 16 35 1 2 C8011
7 CPU VDD FB OA N BSTS
2 1 @ 2 1 15 36 Q8005 Q8006 2 1
+VCORE R8020 1KOhm FB V+ 0Ohm
1 2 14 CCI CMP 37 SI4392DY SI4392DY
2 1 C8008 470PF/50V 13 38 0 22UF 25V
R8023 GNDS CMN C8009
7 CPU VDD FB# 12 CCV CSN 39
11/17 10Ohm 11 GND1 CSP 40 11/17 0 1UF/50V R8028
41 T8002
GND2
C8013 R8027 TPC28T 1 82KOhm 11/17
10Ohm C8014 12/13
100PF 50V 1000PF 50V L8001
C8016 1 2
4 7UF/16V
0 36UH
T8003 R8029 10Ohm
TPC28T 2 1
R8030 F 300kHz 11/17 D D + + + 11/1
1 2 D8000
28 51 CPU VRON
OAIN+
0Ohm R8032 R8043 EC31QS04
4G 4G
2 1 1 2 S S
68 CPUVDD EN PWR
0 1UF/50V 31 6KOhm R8033 0Ohm @
@ 2 1
C8019 C8021
5VS 100PF/50V R8034 200KOhm
169KOhm R8042
0Ohm
R8035
@ @
90 9KOhm
R8041
12/13 change for EMI issue
100KOhm
R8040
R8044
100KOhm 1 2 Q8009A
ER 03/27 11/30 ER VREF = 2V
UM6K1N Ton=GND F=400Khz OCP current is
2 CPU PSI#
B 53 6KOhm @
refer to the B
1% Q8000A inducter's DCR
T8004 UM6K1N
TPC28T 2
Q8000B Q8009B
UM6K1N 0 1UF 50V UM6K1N
5 @ C8023 5
7 CPU PSI#
R8045
470KOhm
@
12/14 change for PSI# issue,and CXTEST
A T8022 T8023 T8024 T8025 T8026 T8027 T8028 T8029 T8030 T8031 TPC28T A
TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T 1 CPUVDD EN PWR
TPT8020
T
T8021 1 CPU VLD
TPC28T
T8032 1 CPU VDD FB
TPC28T
T8033 1 CPU VDD FB#
Title : POWER_VCORE
input current
(5.73A) all AC_BAT_SYS input current
1 2 AC BAT_SYS (3.5A) +5VO
R8118
0Ohm +
C8126 r0805_h24
6800PF/50V
57 58 59 60 66 68 SUSB#_PWR
MLCC/+/ 10%
D R8134 D
+5VA 49 9KOhm Q8100
1% R8123 SI4800BDY 12/13
330Ohm
1%
R8126
1129 ER R8137 0Ohm +5VO
0Ohm 1 2 TPC28T
r0402 T8122
C8118 R8119 L8100
R8117 1500PF 50V 1 8KOhm 3 7UH JP8104
AC_BAT_SYS 0Ohm MLCC/+/ 10% 1%
(7.4A)
2 1 2 2 1 1 +5VSUS
@ r0402 1 2 1 2 C8112
R8131 0 1UF/50V rat=5 3A 1MM_OPEN_5MIL (0.02A)
10KOhm MLCC/+/ 10%
1% C8123 U8101 D8100
R8122 1 2 4700PF 50V 1 30 1 2 Q8101 FS1J4TP 12/08
0Ohm MLCC/+/ 10% INV1 VBST1 SI4800BDY
2 COMP1 OUT1_U 29 + +
r0402 1 2 3 28
SSTRT1 LL1
4 SKIP# OUT1_D 27
5 VO1_VDDQ OUTGND1 26
6 DDR# TRIP1 25 1 2
7 24 R8135 17 4KOhm 1% @
T8121 GND VIN
1 8 REF_X TRIP2 23 1 2
TPC28T 9 22 R8125 17 4KOhm 1% @ +5VAO +5VAO AC_BAT_SYS
ENBL ENBL1 VREG5
10 ENBL2 REG5_IN 21 +5VO
11 VO2 OUTGND2 20
12 19 R8129 +
51 67 SUS_PWRGD PGOOD OUT2_D
1 2 13 18 0Ohm input current
SSTRT2 LL2
2 1 1 2 14 COMP2 OUT2_U 17 2 1
C
C8122 15 INV2 VBST2 16 1 2 (2.23A) +3VO C
0 01UF/50V C8127 R8136 Q8103
R8132 MLCC/+/ 10% 3300PF 50V 2 7KOhm TPS51020 C8104 SI4800BDY
0Ohm MLCC/+/ 10% 1% 0 1UF/50V
r0402 F=450KHz MLCC/+/ 10%
12/13
@ C8121 +3VO
Vref=0 85V 12/27 4 7UF/16V TPC28T
1 2 MLCC/+80% 20% T8102
OCP to 9.3A(+5VO)
C8124
6800PF/50V
MLCC/+/ 10%
@
Rds(on)=0.023ohm
VSUS_ON
TPC28T TPC28T
T8118 T8106
JP8100
2 1% r0402
GND C8111
3 4 1UF 25V 2 Q8105A
EN NC or ADJ 27 28 57 68 VSUS_ON
MLCC/+80% 20% UM6K1N
<Var ant Name>
MIC5235YM5
R8104
ENBL
FB=1 24V 95 3KOhm
1%
Title : POWER_SYSTEM
ASUSTeK COMPUTER INC NB Engineer: Tanner Zhang
Size Project Name Rev
Cus om
A7K 11
Date: 14 2007 Sheet 56 of 69
5 4 3 2 1
5 4 3 2 1
MLCC/+/ 10%
12/15 R8216
67 1 2VO&NDDC_NB_PWRGD
0Ohm
R8213
35 7KOHM +VDDC_NB 1.207V 1.007V
1%
PWM 0%---100% 1 0
R8219
165KOhm
D8200
1SS355 L8202
2 1
1 2 SEL_VCC_NB 13
R8210 1 8UH
B 10KOhm C8214 B
27 28 56 68 VSUS_ON 2 1
0 1UF 25V
L8202,C8214 close to NB chipset
C8203
0 1UF/25V TPC28T TPC28T TPC28T TPC28T
MLCC/+/ 10% T8219 T8204 T8202 T8208
D8203
1SS355 +1 2VO
2 1 TPC28T TPC28T TPC28T TPC28T
T8212 T8207 T8205 T8211
C8204
0 1UF/25V <Var ant Name>
MLCC/+/ 10%
+5VO
D D
R8330
10Ohm input current
(3.114A)
R8328 R8320
0Ohm 0Ohm
52 56 57 59 60 66 68 SUSB#_PWR 1 2 2 @ 1 AC_BAT_SYS
+ +
D
D8301 @
1SS355 10/16 SR 4 +1.8VO
2 1 G S
1 2 12/13 ER JP8302
52 66 68 SUSC#_PWR
1 1 2 2
R8317 C8302 D8302
100KOhm 0 047UF/16V RB751V 40 TPC28T 3MM_OPEN_5MIL
1% MLCC/+/ 10% T8326 (17.5A)
1207 JP8301
@ R8324 R8321 1 2 1 2 1 1 2 +1.8V
0Ohm 0Ohm 1 2
R8323 R8312 C8301 L8300 3MM_OPEN_5MIL
0Ohm 0Ohm 0 1UF/50V R8327 1UH
R8319 R8326 2 @ 1 1 21 MLCC/+/ 10% D D 10Ohm rat=18A
C
0Ohm 53 6KOhm TON DL C
REF=2V 2 OVP UVP BST 20
+1 8VO 1 @ 2 2 1% 1 3 19 + +
REF U8300 LX D8303
4 ILIM DH 18 4 4
For foldback 5 MAX8632ETI 17 G S G S EC31QS04
POK1 VIN C8319
current limit 6 POK2 OUT 16
R8322 C8317 7 15 1000PF/50V
120KOhm 0 22UF/10V STBY# FB C8320 MLCC/+/ 10%
set the OCP at 20A
1% MLCC/+/ 10% 1UF/25V @ 12/14
MLCC/+80 20%
F=300KHz
67 DDR_PWRGD
R8329 12/27
10Ohm
2 1
D8300 FB=0.7V
1SS355 @ 1 2
SUSC#_PWR 2 1 C8318
0 1UF/25V R8318
MLCC/+/ 10% R8325 15 8KOhm
1 2 10KOhm 1% @
1% @ 2 1
R8305 C8315
22KOhm 0 033UF/16V 1207 C8316
1% MLCC/+/ 10% 4700PF/50V @
MLCC/+/ 10%
@
(80mil) (80mil)
B +0.9VO B
(2A)
JP8300
+0.9V 1 1 2 2
@ TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T
T8301 T8302 T8303 T8304 T8305 T8306 T8307 T8308 T8309 T8310 T8311 T8312
+0 9VO +0 9V +1 8VO
TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T
T8313 T8314 T8325 T8316 T8317 T8300 T8318 T8319 T8320 T8321 T8322 T8323
+1 8V
A A
<Variant Name>
D D
C
+2.5VS C
(0.033A)
Vref 1 215V
+3VS T8405 +2 5VO T8406
TPC28T +2 5VS TPC28T
U8401
1 JP8401
VIN
VOUT 5 1 1 2 2
2 R8405
GND
FB 4 1 2
3 1MM_OPEN_5MIL
SD# 107KOHM @
SI9183DT 9/13 SR
R8404
100KOhm C8405
C8406 4 7UF/6 3V
1UF/16V
B B
+2 5VREF
+5VO
TPC28T TPC28T
T8400 T8403 R8406
Q8400 24 3KOhm
SI2304BDS 1%
+1.5VS +1 8VO U8400
1 504V
3 2 1 8 TPC28T
VIN PGND
2 VFB AGND 7
3 6 T8407
TPC28T JP8400 VOUT0 VCCA
4 VOUT1 REFEN 5
T8401 2MM_OPEN_5MIL
+12V 1 2
+1.5VS 1 2 CM8562GISTR
R8403 R8402 1 2
100KOhm 47KOhm (1.3A)
+5VAO 1 r0402 2
+ R8407
TPC28T 36 5KOHM
T8402 1%
Q8401B
D8400 5 +1.5VO
1SS355 @ UM6K1N
2 1
C8401
1130 ER
0 1UF/25V
A A
2 1 2 Q8401A MLCC/+/ 10%
52 56 57 58 60 66 68 SUSB#_PWR UM6K1N
R8400
0Ohm C8402
0 1UF/25V
<Variant Name>
MLCC/+/ 10%
@
Title : POWER_I/O_+3VA & +2.5V
<OrgName> Engineer:
Size Project Name Rev
Custom A7K 11
Date: 14 2007 Sheet 59 of 69
5 4 3 2 1
5 4 3 2 1
+3VO
input current
+5VAO
+5VO
(2.284A)
D D
R8501 R8502 0Ohm
100KOhm 2 1 AC BAT SYS
0402
R8503
100KOhm
D8501 r0402
1SS355 3 R8505
Q8501A
D
C8519 0Ohm
9/25 SR +VDD_CORE_O
2 1
2 Q8508 0 047UF 16V
UM6K1N
11 MLCC/+/ 10% R8506 @ + + +VDD_CORE
R8507 Q8501B G 2N7002 @
0Ohm UM6K1N 2 S 0Ohm
2 1 5 D8502 4 4 (20.5A) JP8502
9 6 68 SUSB# PWR G G
1 2 1 1 2 2
Q8503 Q8502
C8504 RB751V 40 SI4392DY SI4392DY 3MM OPEN 5MIL
0 1UF/25V 18 48 66 GPUPWR EN# @
MLCC/+/ 10% C8500 JP8501
@ 4 7UF/6 3V 1 1 2 2
12/14 chager for ATI SLI TPC28t
T8501
L8500
3MM OPEN 5MIL
R8508
0305 ER JP8500 @
+5VAO +3VO 0Ohm 1 2 1 2
R8509 0 22UF/25V 1 2
2 1 1 21 0Ohm C8505 0 56UH 3MM OPEN 5MIL
R8511 TON DL @
2 20 1 2 2 1
100KOhm OVP/UVP BST
3 19
0402 REF LX
4 18 + +
IL M DH C8507
43 67 VGA PWRGD 5 17
R8512 POK1 VIN D8503
6 16 0 1UF/25V
100KOhm POK2 OUT FB
7 15 4 4
D8500 r0402 STBY# FB G S G S EC31QS04
1SS355
2 1 Q8506A U8500 9/25 SR
2 C8520 R8513 MAX8632ETI
UM6K1N 0 047UF/16V
C C
R8514 Q8506B 3 MLCC/+/ 10% 47 5KOHM
100KOhm UM6K1N C8509 Rds(on)=0.0042ohm
2 1% 1 5 Q8509
0 22UF 10V
GPUPW EN# 11 C8512
G 2N7002 @ 4700PF 50V
C8511 2 S 10/16 SR R8516 10Ohm
0 047UF/16V R8515 2 1 +1 2VSUS
MLCC/+/ 10%
VTTS=VREFIN/2=0.625V 1 2 +1 8VO
10KOhm 1 2
C8515
TON=REF 450KHz
1.12V 470PF/50V
+1.1V_1.2V_RGE_O
FB
For output adjustable
+1.1V_1.2V_RGE JP8504 (Vfb = 0.7V)
(1.32A) R8500
1 1 2 2
147KOhm
2MM OPEN 5M L C8517 C8518
@ 10UF/6 3V 10UF/6 3V
MLCC/+/ 10% MLCC/+/ 10%
B B
C8516
0 1UF/25V
0301 ER
1.117V 0.955V
PWRCNTL 0 0 1
R8520 R8525
TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T 232KOhm 232KOhm
T8502 T8503 T8504 T8505 T8506 T8507 T8508 T8500 T8509 T8510 T8511 T8512 PWRCNTL 1
R8523 @ R8524 0 0
100KOhm 100KOhm
10KOhm 10KOhm
A @ A
D D
C C
B B
A A
<Variant Name>
Title : N/A
<OrgName> Engineer:
Size Project Name Rev
B A7K 11
Date: , 14, 2007 Sheet 61 of 69
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : POWER_SHUTDOWN#
<OrgName> Engineer:
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 62 of 69
5 4 3 2 1
5 4 3 2 1
T8816
TPC28T JP8804 SHORT PIN
1 1 2 CSSP
T8814
POWER PATH & BAT_LEARN TPC28T JP8800 SHORT PIN
0914 1 1 2 CSSN
R8823
D8803 6 8KOhm CHG PDL
1SS355 R8822 1%
18KOhm
1%
CHG PDS
CSSP
CSSN
TPC28T
input current
T8818 (2.28A)
AC N Threshold 2 048Vmax A/D DOCK IN
> 17 44V active CHG PDS
AC BAT SYS
Adapter Iin(max) [0 075V/Rsense(ADin)]*[VCLS VREF]
Rsense(AD n) 0 01 ohm CHG PDL
VCLS 3 265V
> I n(max) 5 797A C8806
> Constant Power 19 * 5 797A 110W 1UF/25V
MLCC/+80% 20% +
CHG CCS @
1 588V
9/25 SR CHG GND
1 68V 0 188V 2 991V
3 115V
R8816 AD IINP
36 5KOhm C8815
1% @ R8820 0 047UF/50V
1 91KOhm
1% R8819 R8806 R8801
48 7KOhm 97 6KOhm 20KOhm
B 3 B
D 1% 1% 1%
1220 TPC28T
Q8808 T8820
28 BATSEL 2P# 11 +5VO
G 2N7002 +2 5VREF
2 S 90W >30K Ohm PWRLMT# 7 2
65W >137K Ohm
3 PKPRES#
D
@ R8826 1SS355
Q8805 C8807 107KOhm D8804 3 Q8812
D
28 PRECHG 11 1UF/10V @ U8801 2N7002
G 2N7002 MLCC/+80% 20% AD IINP 1 V+
2 S +
4 1 2 11
3 1 98V 3 G
V 2 S @
Q8803 LMV321IDBVR C8820
28 CHG EN# 11 0 1UF/25V 1 2
G 2N7002 R8825
R8804 2 S 143KOhm R8824
100KOhm @ 100KOhm
MAX8725 LDO 1 2
28 AC APR UC
MAX8725 LDO
MAX8725 LDO
R8808 PKPRES#
100KOhm
2 1 R8814
100KOhm
1% 3
D
mount: 4S
unmount: 3S Q8810
3
D 11
G 2N7002
Q8809 2 S
28 BAT LEARN 11
A G 2N7002 A
2 S
3 3
D D
R8821
Q8806 470KOhm Q8804
11 C8802
2N7002 65 TS1# 11
G G 2N7002 0 22UF/10V
S 2
2 S MLCC/+/ 10%
<Va iant Name>
Title : POWER_CHARGER
<OrgName> Engineer:
Size Project Name Rev
C A7K 11
Date 14 2007 Sheet 63 of 69
5 4 2 1
5 4 3 2 1
D D
C C
B B
A A
Title : NA
<OrgName> Engineer:
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 64 of 69
5 4 3 2 1
5 4 3 2 1
BAT1_IN_OC# 28
R9002
100KOhm TPC28T
R9001 r0402 Q9000B T9003
100KOhm UM6K1N R9004
r0402 5 243KOhm
28 AC_IN_OC#
1%
3
C
TS1# 63 B 1
Q9000A
UM6K1N
2 Q9001 E
PMBS3904 2 R9003 C9002
10 2KOhm 0 1UF/25V
Master Battery: TS1# 1% MLCC/+80% 20%
C9003
1000PF 50V
MLCC/+/ 10%
C C
BATCON
9/25 SR
+2.5VREF
A A
Title : POWER_DETECT
<OrgName> Engineer: Tanner Zhang
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 65 of 69
5 4 3 2 1
5 4 3 2 1
SUSB#_PWR POWER 6
5
1
C9117
0 1UF/25V
R9115
R9116
0Ohm 5%
TPC28T 2 1 1 2 +12VS
T9123 TPC28T
T9124 C9116
Q9100 100KOhm
TPC28T TPC28T 0 047UF/16V
1 6 T9125 T9126 MLCC/+/ 10% 1%
+1 8VO
2 D 5
S 4 3
3
G
+1 8VS (1A) D
C9109 Q9112
PMN45EN R9109 0 1UF/25V 11
1KOhm 1% MLCC/+/ 10% 2N7002 G
S 2
2 1 01/07 GPUPWR_EN# 8 48 60
C9110 12/14 chager for ATI SLI
0 033UF 16V 0914
MLCC/+/ 10%
0914
TPC28T TPC28T TPC28T
1207 T9128 T9129 T9127
Q9106
+3VS
TPC28T TPC28T
B T9130 T9131 Q9107
(5.516A) +1 2VO 8
7
D S 1
2
+1 2VS_HT
B
DRAIN 1 FDW2501NZ_NL DRAIN 2 C9112 6 3
0 1UF/25V C9100
+3VO 1
SOURCE 1
8
MLCC/+/ 10%
5 G 4
0 1UF/25V
(0.98A)
OURCE 3
2 7 SI4800BDY
3 6
SOURCE 2 OURCE 4 R9100 0Ohm 0914 1 2VSHT_EN_ON
4 5 2 1
GATE 1 GATE 2 R9110
C9111
0 1UF/25V 10KOhm
C9113
0 1UF/25V
MLCC/+/ 10% 12/11
TPC28T TPC28T +12VSUS +3VO T9132
T9133 T9134 TPC28T
Q9108 TPC28T TPC28T
DRAIN 1 DRAIN 2
+5VO 1 FDW2501NZ_NL 8 T9135 T9136
SOURCE 1 R9111 1 2VSHT_EN_ON
OURCE 3
2 7 +5VS 100KOhm
3
SOURCE 2
6
OURCE 4 R9112 0Ohm
(4.833A) Q9109A
4 5 2 1 C9114 UM6K1N
GATE 1 GATE 2 0 1UF 25V 2
MLCC/+/ 10% T9137
C9115 TPC28T
0 033UF/16V Q9109B
MLCC/+/ 10% 0914 UM6K1N
HTVDD_EN 5
51 HTVDD_EN
A
TPC28T R9113 TPC28T A
T9138 10KOhm T9140
9/25 SR 1%
+12VSUS (0.015A)
+12VS
TPC28T <Var ant Name>
T9139
Q9110
SUSB#_PWR UMC4N
R9114
Title : POWER_LOAD SWITCH
100KOhm <OrgName> Engineer:
1%
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 66 of 69
5 4 3 2 1
5 4 3 2 1
D D
+3VO +3VS
EC
SUSB_EC1#
PWRGD 13 18 28 33
25 27 28 66 SUSB_EC1#
FORCE_OFF# 28 42 52 56
R9202
0Ohm D9200 R9201
1 2 1SS355 560KOhm
C 58 DDR_PWRGD C
r0402
Q9200B
T9200 UM6K1N
2 1 TPC28T 5
51 56 SUS_PWRGD
D9201 Q9200A
1SS355 UM6K1N
57 1 2VO&NDDC_NB_PWRGD
1 2 2
R9203
0Ohm C9200
r0402 4 7UF/6 3V
2 1 MLCC/+/ 10%
43 60 VGA_PWRGD
D9202
@ 1SS355
R9207
r0402 0Ohm
51 55 CPU_VLD 1 2
1207
B B
A A
Title : POWER_PROTECT
<OrgName> Engineer:
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 67 of 69
5 4 3 2 1
5 4 3 2 1
AC_BAT_SYS
AC_BAT_SYS 22 55 56 57 58 60 63
D
+3VA +3VA 17 28 50 52 56
FOR POWER TEST D
+5VA +5VA 56
+5VO +5VO 56 57 58 59 60 63 65 66
+3VO +3VO 56 60 66 67
JP9300
+3VSUS +3VSUS 7 18 20 25 26 27 31 51 56
+3VA 1 1 2 2 CPUVDD_EN_PWR 55
+5VSUS +5VSUS 27 37 50 56
+3V SGL_JUMP
+3V 18 25 26 28 34 36 37 40 52 66
JP9301
+3VS +3VS 7 9 13 14 16 17 18 19 20 21 22 23 24 26 27 28 30 31 33 35 36 38 39 40 48 49 50 52 55 59 66 67
1 2 SUSB#_PWR
1 2 SUSB#_PWR 52 56 57 58 59 60 66
SGL_JUMP
+12VSUS
+12VSUS 56 66
JP9302
+12V
+12V 21 31 36 39 52 59 66
1 2 SUSC#_PWR
1 2 SUSC#_PWR 52 58 66
+12VS
+12VS 22 48 52 66
SGL_JUMP
JP9303
+5V
+5V 22 36 50 52 66
1 2 VSUS_ON
C 1 2 VSUS_ON 27 28 56 57 C
+5VS +5VS 20 21 23 24 29 30 31 35 37 50 52 55 66
SGL_JUMP
+2 5VO +2 5VO 59
+2 5VS +2 5VS 7 33 52 59
+1 8VO +1 8VO 58 59 60 66
+1 8V +1 8V 7 8 9 10 52 58
+1 8VS +1 8VS 13 14 17 20 49 66
+VDDC_NB_O +VDDC_NB_O 57
+VDDC_NB +VDDC_NB 14 57
+0 9V +0 9V 7 8 10 52 58
BAT BAT 29 63 65
+1 5VO +1 5VO 59
+1 5VS +1 5VS 26 27 40 52 59
+2 5VREF +2 5VREF 59 63 65
B +VCORE B
+VCORE 8 55
+VDD_CORE_O +VDD_CORE_O 60
+1 2VO +1 2VO 57 66
+1 2VSUS +1 2VSUS 20 57 60
+1 2V +1 2V 20 66
+1 2VS +1 2VS 13 14 17 19 20 66
+1 2VS_HT +1 2VS_HT 5 7 8 14 66
A A
Title : POWER_SIGNAL
<OrgName> Engineer:
Size Project Name Rev
Cus om A7K 11
Date: 14 2007 Sheet 68 of 69
5 4 3 2 1
5 4 3 2 1
UMC4N +12V
SUSC# PWR (SWITCH) (20mA)
AC_BAT_SYS +12VSUS
(100mA) UMC4N +12VS (15mA)
MIC5235 SUSB# PWR (SWITCH)
VSUS ON
D
+3VSUS (1.4A) D
+1.5VO
CM8562 +1.5VS (1.3A)
SUSC PWR PMN45EN +3V (1.51A)
SI9183DT +2.5VS
+3VO SUSB# PWR
FDW2501 +3VS (5.516A)
LM4040BIM
(Regulator) +2.5VREF (10mA)
TPS51020 +5VSUS (0.02A)
+5VO SUSC PWR
FDW2501
+5V (2.5A)
VSUS ON
SUSB# PWR
FDW2501 +5VS (4.833A)
FORCE OFF#
+5VAO
+5VA (20mA)
C C
+3VAO
SI9183DT +3VA ( 20mA)
3V 5V PWRGD HTVDD EN
SI4800 +1.2VS_HT (0.98A)
SUSB PWR
PMN45EN +1.2VS (1.56A)
VSUS ON SUSC PWR
PMN45EN +1.2V (0.08A)
+5VO +1.2VO
ISL6227 +1.2VSUS (0.08A)
SUSB# PWR +VDDC_NBO
+VDDC_NB (3.24A)
GPIO 1 2VO&NDDC NB PWRGD
+1.5VO
CM8562 +1.5VS (1.3A)
SUSB# PWR
FDS2501 +1.8VS (8.253A)
+1.8VO
SUSC# PWR +1.8V (6.6A)
MAX8632 +0.9VO
+5VO +0.9V (2.75A)
B B
DDR PWRGD
+VGA_VCORE_O
+VGA_VCORE (20.4A)
+1.1V_1.2V_RGE_O
+5VO MAX8632 +1.1V_1.2V_RGE (1.32A)
SUSB# PWR
VGA PWRGD
GPU VID
+5VS
MAX8760 +VCORE (44A)
CPUVDD EN
VR VID0 VR VID6, ,CPU PSI# CPU VLD
VCCSENSE,VSSSENSE,#
A A