Listing 1.3?

Example of Behavioral Description�VHDL and Verilog

VHDL Behavioral Description

entity half_add is

port (I1, I2 : in bit; O1, O2 : out bit);

end half_add;

architecture behave_ex of half_add is

--The architecture consists of a process construct

begin
process (I1, I2)
--The above statement is process statement

begin
O1 <= I1 xor I2 after 10 ns;
O2 <= I1 and I2 after 10 ns;
end process;
end behave_ex;

Verilog Behavioral Description

module half_add (I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2;
always @(I1, I2)
//The above abatement is always
//The module consists of always construct
begin
#10 O1 = I1 ^ I2;
#10 O2 = I1& I2;
end
endmodule