CO MODULE 4 NOTES - 21CS34

CHAP 2; BASIC PROCESSING UNIT

FUNDAMENTAL CONCEPTS

► To eKecute a progrwn. the processor fetches one instruction at a time and performs the operations
specified.
► The proces."°r keeps track of the address of the memory location containing the neKt instruction to be
fe1ched using the Program Counter.
► To eKecute W1 instruction, processor must perform following 3 steps:
I ) Felch content~ of memory-location poinled to by PC. Content of this location is 11n ins1ruc1ion

to he eKecuted. The instructions are loaded into IR, Symbolically. this operation is wriuen 11s:
JR f- [[PC]]

2) Increment PC by 4.

PC f-[PCJ + 4

3) Cany out the actions specified by instruction (in the JR).

► The fir.It 2 steps are repeated as many times as necessary to complete instruction and they are referred
to as Fetch Phase.

Step 3 is referred to as ExecuJion Phase.

► The operation specified by an instruction can he carried out by performing one or more of the following
actions:

I) Read the contents of a 1:,o:iven memory-location and load them into a register.

2) Read dalll from one or more registers.

3) Perform an arithmetic or logic operation and place the result into a register.

4) Store dalll from a register into u given memory-location

► An organisation in which the arithmetic and logic unit (ALU) and all the registers are in1erconnec1ed
viu single common bus is shown in the figure below.

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 CO MODULE 4 NOTES - 21CS34

Control signals
PC
Instruction
MAR deooderand
Memory bus
control logic
MOR

IR
Constant4
RO
Select •
•
•
ALU Rn-1
lines

S/nglc•Bus Organlral/on of the Dalapalh Inside a Pr001sscr

• ALU and all the registers are interconnected via a Single Common Bus

• Data & address lines of the external memory-bus is connected to the internal processor-bus via MDR
(Memory Datu Register) & MAR ( Memory Address Register) respectively.

• MOR has two input s and two ourputs. h means. the data may be loaded into MD Reither from memory-
bus (external) or from processor-bus.

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 CO MODULE 4 NOTES - 21CS34

• MAR's inpul is connected to in1ernal-bus and MAR's output is connec1ed to exlernal- bus (as address
bus is unidirectional).

• Instruction Decoder & Coolrol Unit is responsible for:

issuing the control-signals 10 all the units inside the proce.,;sor.
implementing lhe actions specified by lhe instruction (loaded in !he IR).

• Register RO lhrough R(n-1) are the Processor Registers. The programmer can access 1hese regis1ers
for general-purpose use.

• Only pmcessor c.an access 3 registers Y. Z & Tffllp for temporary storage during progrum-ei1ecu1ion.
The programmer canno1access these 3 registers.

• In ALU. I) "A" inpul gets !he operand from lhe output of the multiplexer (MUX).
2) ·'B" inpul gel~ lhe operand directly from the processor-bus.

• There are 2 options pmvided for "'A" inpul of the ALU.

• MOX is used lo select ooe of lhe 2 inputs.

• MUX selects either oulput of Y or constant-value 4 (which is used lo incremenl the PC).

• An instruction is executed by petforming one or more of the following operations:

I ) Transfer a word of data from one register to another or to the ALU.
2) Perform aridunetic o r a logic operation and store the result in a register.
3) Petch the conrents of a given memory-location and load them into a register.
4) Store a word of d:ua from a register into a given memory-location.

• Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.
So/11tio11: Provide multiple internal paths. Multiple paths allow several data-transfers to take place in
paraUel.

REGISTER TRANSFERS

• Instruction execution involves a sequence of steps in which data are transferred from one regis1er to another.

• For euch register. two control-signals ore used to place the contents of thot register on the bus or to load the
duta on the bus into the regis1er. The inpul and output of Register Ri are connected 10 the bus viu swilches
con1rolled by lhe signal!> Ri1n & Ri.., respectively.

• When Ri 1,.=l, data on bus is loaded in10 the register Ri. When Ri..=I. con1en1 of Ri is placed on bus and
when Ri.,,.=O, bus can be used for transferring data from other regis1ers.

• Por example,

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 CO MOOUL£ 4 l~OTES- 21CS34

MoveRl, R2
This transfers the contents of register RI 10 register R2.
This can be accomplished as foUows:
I) Enable the output o f re&,jsters RI by setting R 1.- 10 I . II places the contents of RI on processor-bus.

2) Enable the input of register R2 by setting R2.,,. to I . This loads data from processor-bus into register R4.

• All operations and data transfers within the processor take place within time-periods defined by the
processor-clock.

• The con1rol-signuls tha.1 govern a particular 1ransfor are a.~serted at the start of the clock cycle.

Input aid Ou1pu1 gating for the registers

Input & Output Gating for one Regbter Bit

• A 2-inpul multiplexer i.s used IO select the data applied to the input of an edge-triggered D flip-flop.
• Ri1n=I. mux select~ dalll on bus. This data will be loaded into flip-flop at rising-edge of clock. Ri1n=O. mux
feeds back the value c u!Telltly slOred in flip-flop.

• Q ou1pul of flip-Oop is connecled to bus via a tri-state gate. Ri..o=O. gate's ourpul is in the high-impedance
stale. Ri,..= l , the gale drives lhe bus to O or I . depending on the value of Q.

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 CO MODULE 4 NOTES - 21CS34

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• The ALU performs arithmetic operations o n the 2 operands applied to its A and B inputs.

• One of the operands is output of MUX and the other operand is obtained directly from processor-bus.

• The resull (produced by the ALU) is stored temporarily in register Z.

• The sequence of operations for Ami RI, Rl, RJ.

i.e .. fR31 ~fRll +[R21 is as follows:

I) R loul. Yin

2) R2out. Select Y. Add. Zin

3) Zou1. R3in

• lnstrucl ion execution proceeds a., follows :

Step /: Contents from register RI are loaded into register Y.

Step2: Contents from Y and from register R2 are applied to the A and B inputs of ALU; Addition is
performed & Result is st:ored in the Z register.

Step 3: The contents of Z register is stored in the R3 register.

• The signals are activated for the duration of the clock cycle corresponding 10 that step. All other signals are
inactive.

CONTROL-SIGNALS OF MDR

• The MDR register has 4 control-signals as shown in the figure.

I) MOR;. & MOR_ control the connection 10 the internal processor data bus &

2) MOR.DE & MDR..econtrol the connection lo the memory Data bus.

• MAR register bas 2 control -signals.

I) MAR.. contro ls 1he connection to the internal processor address bus &
2) MAR.,,. controls the connection to the memory address bus.

MO~ MOR..,
Memory Out• Bu,
lntcmul Prcx-.:ssor Bu.,

MOR

MOR"" MOR,,

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 CO MODULE 4 NOTES - 21CS34

FEI'CHING A WORD FROM MEMORY

• To fetch instruction/dalll from memory. processor transfers required address to MAR. At the same time.
processor issues Read signal on control-Hoes of memory-bus.
• When requested datll a:re received from memory. they are stored in MOR. From MOR, they are transferred
to other registers.
• The response time of each memory acce.,;s varies (ba.,;ed on cache miss. memory mapped 1/0). To
accommodate this. MFC is u~-d. (MFC - Memory Function Completed).
• MFC is n signal sent from nddres.,;ed device to the processor. MFC informs the processor thut the requested
ope.ration has been completed by addres.,;cd device.
• Consider the instruction Move (R I), R2. The sequence of steps is :
I) Rlout. MARin. Read: II desired address is laoded i111a MAR & Read co111111a11d is issued.
2) MDRinE, WMFC; II load MDR from memory-bus & Wait for M FC respome from memory.
3) MDRout. R2in; I/ load R2 from MDR. where WMFC=c:ontrol-sig11a/ 1/,at causes proces.ror's
c:011trol circuitry to wait for arrival of MFC sig11al.

,... ,- I -f :

Clo<l
I
).1AJI,. _J
AdohM

-...
MD._,
Dou

Mf1C

Ml--
_....____-+------------~,I_.,......- -
,L
llming Diagram for Read Opera lion

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 CO MODULE 4 NOTES - 21CS34

STORING A WORD IN MEMORY

• Consider the instruction Move R2. (RI). This requires the following sequence:

I) R lo ut. MARin: // desired address is loaded imo MAR.

2) R2out. MDRin. Write: // data robe 11·rimm are lm,dl!d imo MOR & Wrire rn111111c111d is issued.

3) MDRoutE. WMFC: II lt1ad daw imo "'""'"l)"•lt1,·atim1 poimed by RI fmm MOR.

EXECUTION OF A COMPLETE INSTRUCTION

• Consider the inst.ruction Add (R3). RI which adds the content.~ of a memory-location poin1ed by R3
to register RI.
• Executing this instruction requires the following actions:
I) Fetch the instruction.
2) Fetch the fir.it operand.
3) Perform the addition &

4) Load lhe result into RI.

.
Step Action

I PC,,., MAR.,. Read. Select4. Add. Z.

2 Z...,. PC;.. Y;.. WMFC

3 MDR.,,.. IR..

4 R3.,., MAR;.. Read

5 RI..,, Y;., WMFC

6 MDRo... Select Y. Add. Z,a

7 Z..,,. RI ,•. End
Control Sequenre to exeaite the Instruction Add(1l3}, RI

• Complete Instruction execution is as follows:

Step/: The instruction-fetch operation is initiated by loading content.~ of PC into MAR & sending a Read
request to memory. The Select !tignal is set 10 Select4. which causes the MUJt to select constant 4. This value
is added to operand at input B (PC's content). and the result is stored in Z.
Step2: Updated value in Z is moved 10 PC. This completes lhe PC increment operation and PC will now point
to next i.nstruction.

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 CO MODULE 4 NOTES - 21CS34

Step3: Fetched insbllction is moved into MDR and then to IR.

The step I through 3 constitutes the Fetch Phase.

At the beginning of step 4. the insbllction decoder interprets the contents of the IR. This enables
the control ci rcuiuy to activate the control-signals for steps 4 through 7.
The step 4 thro ugh 7 constitutes the Exec11tion Phase.
Step4: Contents of R3 are loaded into MAR & a memory read signal is issued.

Step5: Contents of RI nre transferred 10 Y to prepare for addition.

Step6: When Rend operation is completed. memory-operand is available in MOR. and the addition is
pe.rformed.
Step 7: Sum is stored in Z. then transferred to RI. The .Ei,dsignal causes a new instruction fetch cycle to begin
by returning 10 step I.

BRANCHING INSTRUCTIONS
• Control sequence for an i.nconditional branch instruction is as follows:

SlopAcllon

PC'c., , MAR.,, llem. Select4,Add, Z.,

2 Z.., PC,,, Y1o, WMFC
3 MDR.,. .IRe
4 Oflsel•field-ol•IFl.r, Add, z.,
S Z..., PC.. End

• Instruction execution proceeds as follows:

Step 1-3: The proces.~ing starts & the fetch phase ends in step3.
Step 4: The offset-value is extracted from IR by instruction-decoding circuit. Since the updated
value of PC is already available in rcgi~ter Y. the offset X is gated onto the bus,
and an addition operation is performed.
Step 5: the result. which is the branch-address. is loaded into the PC.
• The branch ins1ruc1ion loads lhe branch target address in PC so lhal PC' will fetch the nex1
instruction from the branch target address.
• The branch target address is usually obtaint."1 by adding the offset in the con1enl~ of PC.
• The offset X is usually the difference between the branch target-address and the address
immediutely following the branch instruction.
• In case of conditional branch. we have to check the statu.~ of the condition,ocles before loading a
new value in.to the PC.

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 CO MODULE 4 NOTES - 21CS34

For Example: Offset-field-of-JR..,.. Add. Z;.,

- If N=O. then End & processor returns to step I immediately after step 4.
IfN=I. step 5 is performed to load a new value into PC.

COMPLETE PROCESSOR
• This has sepw-ute processing-uniL~ to dent with integer data und floating-point data.

lnuiger Unit: To process integer data.

Floating Unit: To process floating - point data.

• Data-Cache is insened between these processing-units & main-memory. The integer and floating unit get
datu f:rom daw cache.

• Instruction-Unit fetches instructions from an instruction-cache or from main-memory when desired

instructions are not already in cache.

• Processor is connected to system-bus & hence to the rest of the computer by means of a Bus Interface.
• Using separate caches for instructions & data is common practice in many processors today.

• A processor may include several units of each type to increase the potential for concurrent operations.

• To e xecute instructions, the processor musl have some means of generdling the control-signals. There are
two approaches for thls purpose:
J ) Bardwired control and

2) Microprogrammed control.

--- Proc11aor

s.,..aembua

Blocl< diagram ol a complete p,ocesso<

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 CO MODULE 4 NOTES - 21CS34

HARDWIRED CONTROL

• Hardwired control is a method of control unit design.

• The control-signals are· generated by using logic circuits such as gates, nip-flops, decoders etc.

CU( Control Step

I Clock I
I counlef

...
- Extemal
••• Inputs

.• Decode</
IR
. encoder
Co<dlion
- .•• codes

•••

tr s

Comro/ Unit Organisalion

• Decoder/Encoder Block is a combinatiooal-cin::uit that generates required cootrol--0utpul~ depending on

state of all its inputs.
• lnstruclion Deroder: It decodes the instruction loaded in the IR.
If IR is an 8-bit register. then instruction decoder generates 28(256 lines); one for each instruction.
It consists of a separate output-lines INS I through IN Sm for each machine instruction.
According to code in the IR. one of the output-lines INS I through INSm is set to I, and all other
Iines are set to 0.
• Step-Deroder provides a separate signal line for each step in the control sequence.

• Encoder: It gel~ the input from instruct ion decoder. step decoder. external inputs. and condition codes. It
uses all these inpuL~ to generate individual control -signal~: Yin. PCout. Add. End and so on.
For example: Zin= Tl + (T6.ADD) + (T4.BR):
- This signal is asserted during time slot T l for all instructions.
- T6 for an Add instruction.
- T4 for unconditional branch i n.~truction

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 CO MODULE 4 NOTES- 21CS34

• End= TI.ADD + TS.BR + (T5.N + T4. NJ. BRN + . ..•.

The End signal starts a new instruction fetch cycle by resetting the control step counter to its starling
value.
• When RUN=I. counter is incremented by I at the end of every clock cycle. When RUN=O. counter
stops counting.
• This is needed w!henever the WMFC signal is issued to cause the processor to wait for the reply from
the memory.
• After execution o f each instruction. end signal is generated. End s ignal resets step counter.
• Sequence of operations curried out by this machine is determined by wiring of logic circuits, hence the
nume "hardwired".
• Advantage:
Cun operate ut high speed.

• Dmdvantages:
I) Since no. of instructions/control-lines is often in hundreds. the complexity of control unit i~ very high.
2) 11 is costly und difficul t to design.
3) The control unit is inflexible because i t is difficult to change the design.

-
c.:..,,,""'

...
ls.F,
I I
r, r, .. . r,

INS,
~
..
-
INS
lnllruclion
E,uds

Ccncffcti
codls
~

...
-,.,.--

Sepwat/on of Encoding and Decoding Functions

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 CO MODULE 4 NOTES - 21CS34

Zin=TI + T6.ADD + T4.BR

llrw,ct,

T, T,

End=TI.ADD + TS.BR +(T5 . N + T4 .N)BRN + ...

MICROPROGRAMMED CONTROL

• MicroprogrJ_mming is a method or con1rol unit design.

• Control-signals are genem ted by a program similar 10 machine language progrJ_ffiS,

• Control Word (CW) is u word wboi.e individual biu represent various control-signals (like Add, PCin).

• Each of lhe con1rol-s1cps in conirol sequence of an ins1ruc1ion defines a unique combina1ion of Is & Os in
cw.
• Individual conirol-wonis in micro-routine are referred 10 as microinsiruclion.~.

• A sequence of CWs corresponding 10 control-sequence of a machine insiruc1ion consti1u1es lhe micro-

routine.

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 CO MODULE 4 l~OTES- 21CS34

• The micro-routines for all instructions in the ins1ruction-se1 of a computer are stored in a special memory
cal led the Control Store (CS).

• Co n1rol-uni1 generates contro l-signals for any instruction by sequentially reading CWs of corresponding
micro-routine from CS.

• µPC is used 10 read C W s sequentially from CS. (µPC: Microprogram Counter).

• Every tin-.: new instruction is loaded into IR. output of Starting Address Genemtor is loaded into µPC.

• Then. µPC is automatically incremented by clock: causing successive microinstructions to be read from CS.
Hence. contro l-signal s are deli vered to various pruts of procesi,or in correct sequence.

Slatting
IR address
One function
generator
cannot be carried
~ ~ ~ - ~ out by this simple
organization.

Control
store CW

Basic Org.-,isation or Microprcqammed Control Unil

•
Ji J I ,l • I )J J a:J a:J )! -
'
.. ~ :I ► N

0 1 1 1 0 0 0 1 I I 0 0 0 0 0 0
2 I 0 0 0 0 0 I 0 0 0 I 0 0 0 I 0
3 0 0 0 0 I I 0 0 0 0 0 0 0 0 0 0
•s 0 0 I I 0 0 0 0 0 0
0 0 0 0 0 0 I 0 0 0
0 0 0 I 0 0
0 I 0 0 I 0
6 0 0 0 0 I 0 0 0 I I 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 I 0 0 I

An e11111T1ple for Micro Instructions

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 CO MODULE 4 NOTES - 21CS34

Advantages:

I. It simplifies the design of Control UniL Thus. it is inexpensive and error free implementation.
2. Control functions an: implemented in software rather than hardware.
3. The design p.rocess is systematic.
4. More ncxible. it can be adaptable i.e., cand correct the design errors quickly and cheaply.
5. Complex functio:ns such a.~ noating-poini arithmetic can be realized efficiently.

Disadvantages:

I. A microprogrammed control unit is somewhat slower than the hardwired control unit because Lime is
required to acce.<;:s the microinstruct ions from CM.
2. The flexibility is achieved at some extra hardware cost due 10 the control memory and iL~ access
ci rcuitry.

ORGANIZATION OF MJCROPROGRAMMED CONlllOL UNIT TO SUPPORT CONDmONAL

BRANCHING

• Drawback of previous Microprogram coatrol: IL cannot handle the situation whe n the control unit is
required to check the sla'lus of the condition codes or external inputs 10 choose between alternative courses of
action.

Solution: Use conditional branch microinstruction.

• In case of conditional branching, microinstructions specify which of the external inpuL~. condition codes
should be checked as a condition for branching 10 take place.

• Starting and Branch Addres.~ Generator Block loads a new address into µPC when a microinstruction
instruct~ it 10 do so.

• To allow implementa,tion of o conditionnl branch. inputs to this block consist of external inpuL~ and
condition-codes & contents of IR.

• µPC is incremented every time a new microinstruction is fetched from microprogram memory except in
following situations:

I) When a new instruction is loaded into IR. µPC is loaded with starting address of micro-routine for
th at instruction.

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 CO MODULI 4 NOTES- 21CS34

2) When a Branch microinstruction is encountered and hr.inch condition is satisfied, µPC is loaded
with brunch-address.

3) When an End microinstructio n is encountered. µPC is loaded with address of first CW in micro-
routine for i.nstruction fetch cycle.

Add 111llcn,ta•uct1on

0 PC,.. . MAR ., • Reld.Slled4,Add. Z.,

I Z,... , PCft , Yft . WMFC
2 MOR.., , IRft
3 8'anch10 Slal1ing--1allffllc,01ouline

25 IIN-4, U - t n n c h t o -

~
26 OltMl·fiold-ol·lf\.... Selec:IY. Add, Z.,
Z.... . PCft . End

Micro-routine for instruction Branch<O

J
Exlemal
i'1)UIS

Starting and
f=✓f>'anch address,,,.--< Concilion
IA codes
generator

Clock 1----1 µPC

Control
stote cw

Organisation of control unit to allow condltlonal branching In the microprogram

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