Digital System Design

Problem Based Learning

Submitted by:
M. Junaid Rehmat
Adeena Rahim
Alishba Islam
Aitzaz Azam
Submitted To:
Sir Hussain Ali
Dated.
June 3rd, 2022
Synchronous Counter with Parallel
Load:
In a synchronous counter we use JK flip flops to
increment and decrement counter from 0-15.
JK Flip Flop:
SR latch has a limitation in which if Set and Reset
are 1 the output becomes undefined. To fix this
limitation we use JK flipflop which provides us with
a unique functionality in which if Set and Reset are
1, the flipflop starts to Toggle at every positive or
negative edge clock pulse.
Binary Counter:
We use JK flipflops to make a 4-bit binary counter
and through the logic gates we make it such that it
runs from 0-15 counter.
Truth Table:

Parallel Load:
A parallel load circuit loads the desired inputs
directly to the outputs in a parallel fashion. I0 bit
replaces A0, I1 bit replaces A1, I2 bit replaces A2
and I3 bit replaces A3.

If we join parallel load with above binary counter

and add OR gates to combine functionality, we get
binary counter with parallel load. In order to stop
Count when load is initialized, we use an AND
gate.
Verilog Code + GTKWave: