Department of Electronics and Communication Engineering

PBR VISVODAYA INSTITUTE OF TECHNOLOGY & SCIENCE, KAVALI

CERTIFICATE

This is to certify that the project report titled “A Secure method for Image Signaturing
using SHA256, RSA, and Advanced Encryption Standard(AES)”, being submitted by
Names bearing Roll numbers
K. KUSUSMA 19731A0420
CH. SAI SREEJA 19731A0408
CH. MOUNIKA 19731A0411
K. SRI HARSHINI 19731A0423
Y. MUKESH CHOWDARY 19731A0444

in partial fulfillment of the requirements for the award of the degree of Bachelor of
Technology in Electronics and Communication Engineering, to the Jawaharlal
Nehru
Technological University Anantapur, Anantapuramu is a record of bonafide work carried
out by them under my guidance and supervision.

Internal Guide Head of the Department

Mr. G.
Mrs. R.Manga Rao, Associate Professor, Department of ECE PBR VITS,
Sravanthi,

KAVALI
Assistant Prof,

Department of ECE

PBR VITS,
External Viva KAVALI
Voce conducted on External Examiner

1
 DECLARATION

We hereby declare that the project entitled, “Title of the Project’ completed and

written by us, has not been previously submitted elsewhere for the award of any degree or

diploma.

Place:

Date:
K. KUSUMA 19731A0420

CH. SAI SREEJA 19731A0408

CH. MOUNIKA 19731A0411

K. SRI HARSHINI 19731A0423

Y. MUKESH CHOWDARY 19731A0444

3333333333

2
 ACKNOWLEDGEMENTS
We consider it as our duty to express our gratitude to all those who guided, inspired
and helped us in completion of this project work.

We acknowledge, with profound sense of gratitude, the guidance and support of our
guide Mr. G. Manga Rao, Designation, Department of Electronics and Communication
Engineering, PBR VITS, Kavali. His/Her timely suggestions and co-operation, both
professionally and personally, have greatly contributed in bringing out the project
successfully.

We express our heart-felt thanks to Mrs.R.Sravanthi, Associate Professor and Head

of the Department of Electronics and Communication Engineering, PBR VITS, Kavali, for
her kind encouragement and for providing us with all required facilities for the completion
of the project work.

We also express our gratitude to the principal Dr.B.Dattatraya Sarma, for providing
necessary infrastructure & an ambient atmosphere to complete our project work.

We are indeed indebted to all our teachers who have guided us throughout our
B.Tech course for the past four years and have imparted a sufficient knowledge and
inspiration to take us forward in our career.

Finally, we thank each and everyone who has helped us directly and indirectly in
completion of project work.

K. KUSUMA 19731A0420

CH. SAI SREEJA 19731A0408

CH. MOUNIKA 19731A0411

K. SRI HARSHINI 19731A0423

Y. MUKESH CHOWDARY 19731A0444

3
 Abstract

Hardware Security plays a major role in most of the applications which include net banking, e-
commerce, military, satellite, wireless communications, electronic gadgets, digital image
processing, etc. Cryptography is associated with the process of converting ordinary plain text
into unintelligible text and vice versa. There are three types of cryptographic techniques;
Symmetric key cryptography, Hash functions and Public key cryptography. The signature of the
image is done through 3 steps. The three steps include SHA256 (Secure Hash Algorithm 256),
RSA (Rivest-Shamir-Adleman), and AES (Advanced Encryption Standard). The signature of the
image is stored in a binary file which is sent to the person who needs to verify the image that is
already present near the viewer. The method has been tested y artificially applying attacks such
as blurring the image greyscale the image and changing one pixel in the image.
Keywords— Advanced Encryption Standard (AES), Rivest Shamir Adleman (RSA),
Cryptography, Digital Signature, SHA256

4
 CONTENTS

Chapter No Topic Name Page No

Main Page

Certificate 1

Declaration 2

3
Acknowledgements
4
Abstract
5
Contents
9
List of
12
figures List

of tables

1. 1. Introduction 13

14
1.1. Cryptography
1.1.1. Symmetric and Asymmetric
key 15
1.2. Cipher types
1.2.1. Block ciphers
16
1.2.2. Stream ciphers
1.3. S – BOX(substituition)
5
 16

2. 17
2. Literature Review

3. Existing method 18
3.
3.1. AES algorithm 20

3.2. Substitute Bytes 21

3.3. Shift rows 21

21
3.4. Mix column

3.5. Add round key 24

4. 4. Proposed System 36

4.1. SHA(Secure Hashing Algorithm)

37
4.2. RSA(Rivest Shamir Adleman)

4.3. Advanced Encryption Standard

38

5. 5.1. Advantages 39

5.2. Applications

6. 6. Vivado Xilinx and Verilog HDL 40

6.1. History of Verilog

6.2. Introduction

6.2.1. Design styles

6
 6.2.1.1. Bottom-up Design

6.2.1.2. Top-down Design

6.3. Features of Verilog HDL

6.4. VLSI design flow

6.4.1. System specification

6.4.2. Architectural Design

6.4.3. Behavioural or Functional design

6.4.4. Logic Design

6.4.5. Circuit Design

6.4.6. Physical Design

6.4.7. Layout Verification

6.4.8. Fabrication and Testing

6.5. Module

6.5.1. Instances

6.5.2. Ports

6.5.3. Identifiers

6.5.4. Keywords

6.5.5. Data types

6.5.6. Register Data types

6.6. Modeling concepts

6.6.1. Abstraction levels

6.6.1.1. Behavioural level

7
 6.6.1.2. Register – Transfer Level

6.6.1.3. Gate level

6.6.1.4. Switch level

6.7. Operators

6.7.1. Arithmetic Operators

6.7.2. Relational Operators

6.7.3. Bit – wise Operators

6.7.4. Logical Operators

6.7.5. Reduction Operators

6.7.6. Shift Operators

6.7.7. Concatenation Operators

6.7.8. Conditional Operators

6.8. Verilog HDL

6.9. Synthesis and Implementation of the design

7. Simulation Results
8. Conclusion
9. References

8
 LIST OF FIGURES

Figure No Figure Name Page No

1.
Figure 1.1.1.1: Symmetric Encryption 3

Figure 1.1.1.2: Asymmetric Encryption

4
Figure 1.3.1: Architecture of AES256

3. Fig 3.1.1: One round of AES256 13

Fig 3.1.2: Cycles required in each round

15

9
4. Fig. 4.1: One round in SHA256
19
Fig. 4.3.1: Combined structure of S-Box and Inverse S-box

Fig. 4.3.2: Combined structure of mix column and add

round key mix
20
Fig 4.3.3: Flow charts for both encryption and decryption

Figure 6.4: VLSI design flow

36
6.
Figure 6.8.1: Creating a project in
36
Vivado Xilinx Software
37
Figure 6.8.2: Set the project name and
37
location

Figure 6.8.3: Setting the category, family,

package, speed
10
11
Figure 6.8.4: Adding the files into our 38
project
38
Figure 6.9.1: Synthesis of the design

Figure 6.9.2: Report of timing

summary

Figure 6.9.3: Area report

Figure 7.1: Simulation of all modules

Figure 7.1.1: Add signals to wave

form

Figure 7.1.2: Converting Binary to

Hexadecimal

Figure 7.2: RTL schematic

Figure 7.2.1: Technology Schematic

Figure 7.3: Final output results

12
 LIST OF TABLES

Table No Table Name Page No

3. Table 3.1.2: Cycles required in each round

Table 3.1.3: Structure of conventional implementation
4

6. Table 6.7.2.1: Relational Operator

Table 6.7.3.1: Bit-wise Operator
Table 6.7.4.1: Logical Operator
Table 6.7.5.1: Reduction Operator
Table 6.7.6.1: Shift Operator
Table 6.7.8.1: Operator Precedence

7. Table 7.3.1: Evolution of Area and Delay

13
 CHAPTER-I

INTRODUCTION
As the Internet has grown in popularity, so has the number of people who use it. Security
issues have become more complicated as well. One of these safeguards is the concern is data
theft and forgeries. Data transport on the internet, unauthorized access to the internet can be
intercepted and altered. A person creating a one-of-a-kind sign is one approach to avoid this.
This guarantees that the information is genuine. Cryptography has been around for a long
time. Data encryption is a means of securing data. Because it can be used in a variety of
ways.
Digital signatures are a type of network security technology. A digital signature can be used
to identify whether or not a document is authentic. data from the sender is correct. then it is
required to verify. Digital signatures must serve the same purposes as traditional signatures.
traditional signatures, which can guarantee authentication, non-repudiation, and integrity In
their digital signatures. Two algorithms are combined in one implementation, namely public
key algorithms and hashing algorithms are two types of algorithms. The problem that is
addressed is that images being very sensitive and easily editable data available online can be
edited and convey wrong information sometimes could be very dangerous. So, the image will
be signed and even a onepixel change will be detected in the original image. Thus, saving
many people from viewing edited images and interpreting wrong and misleading images. The
filename is also misleading in some situations so the filename is included along with the
image data so that even changes in the filename can also be detected by one character in the
filename.
This method secures images digitally by signing the images and enhancing their security by
the current cryptographic techniques such as SHA256 Hash, Rivest Shamir Adleman(RSA),
Advanced Encryption Standard (Advanced Encryption Standard (AES)), etc. They all have
their unique algorithm design to perform encryption and decryption. Although some of them
including MD5 and Vigenere Cipher have to become quite old and easily decrypted.
Therefore, nowadays to secure the authenticity and to perform the secure transfer of sensitive
data Advanced Encryption Standard (AES) (Advanced Encryption Standard), SHA256 hash,
and RSA algorithms are being used.
These encryption algorithms are very hard to break, moreover, these algorithms are open-
source and are present for a long time. Due to this, the algorithms are prone to brute force.

14
This method uses three encryption layers and performs the sensitive data transfer and verifies
the image authenticity very securely.
1.1 CRYPTOGRAPHY
Cryptography is associated with the process of converting ordinary plain text into
unintelligible text and vice versa. Cryptography prior to the modern age was effectively
synonymous with encryption. Converting readable information to unintelligible text. Which
can only be ready by reversing the process. There are three types of cryptographic technique
namely - Symmetric key cryptography, Hash functions and Public key cryptography.
Symmetric key algorithms namely Advanced Encryption Standard (AES), Data Encryption
Standard use the same key for encryption and decryption. It is much faster, easy to implement
and requires less processing power.
Cryptography is the science of secret, or hidden writing.
It has two main Components:
 Encryption
Practice of hiding messages so that they cannot be read by anyone other than the
intended recipient
 Authentication & Integrity
Ensuring that users of data/resources are the persons they claim to be and that a
message has not been surreptitiously altered

1.1.1 Symmetric and Asymmetric key

Symmetric key: Symmetric-key algorithms are algorithms for crypography that use the same
cryptographic keys for both the encryption of plaintext and the decryption of ciphertext. It is
used to encrypt large amounts of data effieciently.Advanced Encryption Standard (AES) keys
are symmetric keys that can be three different key lengths (128,192, or 256 bits)

15
Fig:1.1.1.1 Symmetric Encryption
Asymmetric Key: Asymmetric keys are the public key infrastructure a cryptographic scheme
requiring two different keys, one to lock or encrypt the plaintext, and one to unlock or
decrypt the cyphertext.one key is published (public key) and the other is kept private (private
key).

Fig:1.1.1.2 Asymmetric Encryption

1.2 Cipher Types
Cipher: Cipher is a method for encrypting messages.

16
Encryption algorithms are standardized & published
The key which is an input to the algorithm is secret
– Key is a string of numbers or characters

– If same key is used for encryption & decryption the algorithm called symmetric

– If different keys are used for encryption & decryption the algorithm called asymmetric.

Uses a pair of keys for encryption

– Public key for encryption

– Private key for decryption

Messages encoded using public key can only be decoded by the private key
– Secret transmission of key for decryption is not required

– Every entity can generate a key pair and release its public key

Symmetric algorithms:
Algorithms in which the key for encryption and decryption are the same are Symmetric
Example: Caesar Cipher
Types:
1.2.1.Block Ciphers:
o Encrypt data one block at a time (typically 64 bits, or 128 bits)

o Used for a single message

17
1.2.2 Stream Ciphers:
o Encrypt data one bit or one byte at a time2530

o Used if data is a constant stream of information

1.3 S-BOX(Substitution):

In Cryptography, an S-Box(substitution-box is a basic component of symmetric key

algorithms which performs substitution. In general, an S-Box takes some number of input
bits, m, and transforms them into some number of output bits, n, where n is not necessarily
equal to m. An m*n S-box can be implemented as a lookup table with 2 mwords of n bits each.
In modern-day block ciphers, the role of substitution-boxes is to transform the plaintext data
nonlinearly to generate cipher-text data with sufficient confusion. It has been well-confirmed
that the robustness and security of such block ciphers heavily based on the cryptographic
strength of the underlying substitution-boxes. Reason being, they are the only components
that are held responsible to bring required nonlinearity and complexity into the security
system which can frustrate the attackers. Accordingly, a number of different concepts have
been explored to construct strong S-boxes. To move forward with the same aim, a novel
simple modular approach, the very first time, is investigated to construct nonlinear S-box in
this paper. The new modular approach consists of three operations such as new
transformation, modular inverses, and permutation. A number of highly nonlinear S-boxes
can be easily constructed with slight changes in the novel transformation parameters. An
example S-box is presented whose critical performance assessment against some
benchmarking criterions such as high nonlinearity, absence of fixed points, fulfillment of
SAC and BIC properties, low differential uniformity and linear approximation probability
and comparison with recent S-boxes demonstrate its upright cryptographic potentiality. In
addition, an image encryption algorithm is also proposed wherein the generated S-box is
applied to perform the pixels shuffling and substitution for strong statistical and differential
encryption performance.
Data and information communication has become very important ingredient of today’s
technological life and considered as significant assets of an individual or organization. If the
confidentiality of information is compromised, then the information can be used for harmful
purposes. Current innovations in information technology and their prolific applications in our
life have caused in a gigantic growth in the size of the data being transmitted online. The
private information being very sensitive assets require protection from attackers. Therefore,

18
prior to its transmission, data demand its protection and needs methods for its transformation
into a meaningless form for the invaders. Cryptographic algorithms are the mathematical
methods and techniques that assist in the protection of data. Stream ciphers transform the data
in a bit-by-bit or byte-by-byte manner. Whereas, the block ciphers transform data in chunks
which comprise large number of bits or bytes at a time. In modern symmetric encryption,
block ciphers are considered as one of the most effective tools for data protection. Data
Encryption Standard (DES), Blowfish, Advanced Encryption Standard (AES), RC5, etc. are
examples of contemporary block ciphers. Precise implementations of block ciphers are easy
and are more general in nature than the stream ciphers. One category of prevalent block
ciphers is known as the SP network-based block ciphers. These block ciphers use two major
operations of substitution and permutation for the transformation of data into a perplexing
form.

Fig.1.3.1 Architecture of AES 256

A substitution operation substitutes a byte/block with another byte/block using a substitution
table known as a substitution box or S-box. On the other hand, a permutation process shuffles
the input bits or bytes in some linear fashion. A substitution-box is a pivotal constituent of
modern-day block ciphers that helps in the generation of a muddled cipher text for the
specified plaintext. Through the incorporation of S-box, a nonlinear mapping among the input
and output data is established to create confusion. The more confusion an S-box can create in
the output data, the more secure a block cipher is. As a result, the provision of security by a
block cipher employing one or more S-boxes directly depends on how much stronger S-boxes
are. Block ciphers consist of many components in addition to one or more S-boxes. Contrary
to other components, an S-box is the alone nonlinear component of block ciphers that

19
supports the enhancement of data protection. Generally, a block cipher uses either a static S-
box or one or more dynamic S-boxes. A static S-box is fixed for every incoming data and
secret key which is used repeatedly in the block cipher. A block cipher based on a static S-
box employs that S-box in all its rounds. A static S-box allows an attacker to inspect its
characteristics, discover its fragilities, and eventually find the chance of getting plaintext
from the respective cipher-text. As an example, static S-boxes employed in Data Encryption
Standard (DES) were an easy target for the attackers. Consequently, to overcome the
weaknesses due to static S-boxes, many cryptographers have explored innovative techniques
to design dynamic S-boxes. Dynamic S-boxes are generated using cipher key and provide a
way to augment the cryptographic power of a block cipher. Construction and usage of the
key-dependent and dynamic S-boxes in a cipher enhance its cryptographic power. Blowfish
cipher employs such dynamic S-boxes in its working.

CHAPTER-II
LITERATURE REVIEW
M. Rajeswara Rao, Dr.R.K.Sharma, SVE Department, NIT Kurushetra “FPGA
Implementation of combined S box and Inv S box of AES” 2017 4th International
conference on signal processing and integrated networks (SPIN).
An implementation of a combinational memory-less S-Box and inv S-Box (combinely) for
ByteSub and InvByteSub transformations of AES on a same hardware. This is a part of the
combined architecture of AES in which both encryption and decryption can be performed
with an enable pin. Previously LUTs are used to implement the S-Box and Inv S-Box of AES
separately, which causes large amount of memory and area. In this paper, the proposed
architecture is implementing using composite field arithmetic in finite fields GF (28) which is
advantageous than LUT approach on the basis of hardware complexity. As both S-Box and
Inv S-Box are implementing on a same hardware, there is large reduction in gate count as
well as in area. The power consumption is also reduced because of the resource sharing of
multiplicative inverse module in both S-Box and Inv S-Box. The AES is suitable in wide
range of applications, such as banking, digital video recorders, web servers, ATMs and
cellular phones. Hardware implementation of AES offers more physical security and higher
speed too when compared to software implementation of AES. The main advantage of AES
over most of the cryptographic algorithms is that it doesn’t include Feistel structure.
Summary: By comparing with the LUT based in this hardware complexity is reduced.
Nalini C. Iyer ; Deepa ; P.V. Anandmohan ; D.V. Poornaiah “Mix/InvMixColumn

20
decomposition and resource sharing in AES”.
In this paper, compact architectures for AES Mix Column and its inverse is presented to
reduce the area cost in resulting AES implementation. In the hardware implementation of
AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn
transformation demands the utilization of logic resources and then effects the critical path
delay and resulting throughput. The proposed MixColumn/Inverse MixColumn design based
on byte and bit-level decomposition leads to two types of architecture which demonstrates
deeper resource sharing within byte and between bytes and rearrangement of output terms
with respect to FPGA architecture in bit level resply. The proposed architectures have been
investigated on a FPGA based implementation platform. Application of the proposed
architectures resulted in reduction of reconfigurable logic area by 40% as compared to
separate implementation of MixColumn and Inverse MixColumn reduction and also path
delay by 9% resply. Experimental results show that our proposed architecture can reduce the
area cost significantly and compared with other previous implementations reported so far.
There exist many presentations of hardware implementations (ASIC and FPGA) of Rijndael
AES algorithms in literature. Static implementations based on ASICs are inherently
impossible to update or upgrade in response to new security threats. On the other hand, Field-
programmable gate array (FPGA) technology has much greater potential for providing higher
security level in response to new threats because of its capability for dynamic reconfiguration
and also time to market as compared to ASIC implementation.
Summary: The proposed Mix/Inv mix architecture can reduce the area cost significantly.
Yulin Zhang ; Xinggang Wang; “Pipelined implementation of AES encryption based on
FPGA” 2010 IEEE International Conference on Information Theory and Information
Security.
This paper presents the outer-round only pipelined architecture for a FPGA implementation
of the AES-128 encryption processor. The proposed design uses the Block RAM storing the
S-box values and exploits two kinds of Block RAM. By combining the operations in a single
round, we can reduce the critical delay. As the network transmission speed upgrades to the
gigabits per second (Gbps), the software-based implementations of cryptographic algorithms
cannot meet its needs. The hardware-based implementations using some special optimization
techniques (such as pipeline and lookup tables, etc.), can greatly improve throughput and
reduce the key generation time. Besides, the processes of cryptographic algorithms and the
key generation packaged in chip, which cannot easily be read or changed by external attacker,
so hardware-based implementations can get the higher physical security .In recent years ,

21
many hardware based implementations had been proposed in literature[3- 5,7-15].Some
implementations use the field programmable gate arrays (FPGA) and the others use the
application specific integrated circuit(ASIC).ASIC lacks of flexibility and has high
development costs and long development cycle.
Summary: By combining the operations in a single round, we can reduce the critical delay.
C. Sivakumar ; A. Velmurugan ; “High Speed VLSI Design CCMP AES Cipher for
WLAN (IEEE 802.11i)” 2007 International Conference on Signal Processing,
Communications and Networking.
The Advanced Encryption Standard (AES) algorithm has become the default choice for
various security services in numerous applications. In this paper, we propose a high speed,
non-pipelined FPGA implementation of the AES-CCMP (Counter-mode/CBCMAC Protocol)
cipher for wireless LAN using Xilinx development tools and Virtex-It Pro FPGA circuits.
IEEE 802.11i defines the AES-based cipher system, which is operated on CCMP Mode. All
the modules in this core are described by using Verilog 2001 language. The developed AES
CCMP core is aimed at providing high speed with sufficient security. The
encryption/decryption data path operates at 194/148MHz resulting in a throughput of 2.257
Gbits/sec for the encryption and 1.722 Gbits/sec for decryption. Compared to software
implementation, migrating to hardware provides higher level of security and faster encryption
speed. A comparison is provided between our design and similar existing implementations.
Each input byte of the State matrix is independently replaced by another byte from a look-up
table called S-Box. The AES S-box is a 256-entry table composed of two transformations:
First each input byte is replaced with its multiplicative inverse in GF (2 8) with the element
{00} being mapped onto itself, followed by an affine transformation over GF (2 8). For
decryption, inverse S-box is obtained by applying inverse affine transformation followed by
multiplicative inversion in G(28).
Summary: In the current wireless LAN environment, WEP-the current algorithm for
security-is not safe against attacks. We consider AES CCMP algorithms for wireless LAN
security.
P. S. Abhijith ; Mallika Srivastava ; Aparna Mishra ; Manish Goswami ; B. R. Singh ;
“High performance hardware implementation of AES using minimal resources” 2013
International Conference on Intelligent Systems and Signal Processing (ISSP).
Increasing need of data protection in computer networks led to the development of several
cryptographic algorithms hence sending data securely over a transmission link is critically
important in many applications. Hardware implementation of cryptographic algorithms are

22
physically secure than software implementations since outside attackers cannot modify them.
In order to achieve higher performance in today’s heavily loaded communication networks,
hardware implementation is a wise choice in terms of better speed and reliability. This paper
presents the hardware implementation of Advanced Encryption Standard (AES) algorithm
using Xilinx– virtex5 Field Programmable Gate Array (FPGA). In order to achieve higher
speed and lesser area, Sub Byte operation, Inverse Sub Byte operation, Mix Column
operation and Inverse Mix Column operations are designed as Look Up Tables (LUTs) and
Read Only Memories (ROMs).
Encryption is usually done just before sending data. To utilize the channel resources
completely encryption algorithm must have a speed at least equivalent to data transmission
speed. Achieving high throughput for encryption algorithm for a communication channel of
high data rate is a challenging task.
Summary: With the designing of all the operations as LUTs and ROMs, the proposed
architecture achieves a throughput and thereby utilizing only slices in the targeted FPGA.
N. S. Sai Srinivas ; Md. Akramuddin; “FPGA based hardware implementation of AES
Rijndael algorithm for Encryption and Decryption” 2016 International Conference on
Electrical, Electronics, and Optimization Techniques (ICEEOT).
AES algorithm or Rijndael algorithm is a network security algorithm which is most
commonly used in all types of wired and wireless digital communication networks for secure
transmission of data between two end users, especially over a public network. This paper
presents the hardware implementation of AES Rijndael Encryption and Decryption
Algorithm by using Xilinx Virtex-7 FPGA. The hardware design approach is entirely based
on pre-calculated look-up tables (LUTs) which results in less complex architecture, thereby
providing high throughput and low latency. There are basically three different formats in
AES. They are AES-128, AES-192 and AES-256. The encryption and decryption blocks of
all the three formats are efficiently designed by using Verilog-HDL and are synthesized on
Virtex-7 XC7VX690T chip (Target Device) with the help of Xilinx ISE Design Suite-14.7
Tool. The synthesis tool was set to optimize speed, area and power. The power analysis is
made by using Xilinx XPower Analyzer. Pre-calculated LUTs are used for the
implementation of algorithmic functions, namely S-Box and Inverse S-Box transformations
and also for GF (28) i.e. Galois Field Multiplications involved in Mix-Columns and Inverse
Mix-Columns transformations. The proposed architecture is found to be having good
efficiency in terms of latency, throughput, speed/delay, area and power.
Summary: The LUT based design approach gives less complex architecture and saves the

23
processing time to a great extent by retrieving the necessary values from memory locations.
Ashwini M. Deshpande ; Mangesh S. Deshpande ; Devendra N. Kayatanavar; “FPGA
implementation of AES encryption and decryption” 2009 International Conference on
Control, Automation, Communication and Energy Conservation
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is
an approved cryptographic algorithm that can be used to protect electronic data. The AES can
be programmed in software or built with pure hardware. However Field Programmable Gate
Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES
algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware
Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and
optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e.
Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator,
ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using
an iterative design approach in order to minimize the hardware consumption. Xilinx
XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a
method to integrate the AES encrypter and the AES decrypter. This method can make it a
very low-complexity architecture, especially in saving the hardware resource in
implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most
designed modules can be used for both AES encryption and decryption. Besides, the
architecture can still deliver a high data rate in both encryption/decryption operations. The
proposed architecture is suited for hardware-critical applications, such as smart card, PDA,
and mobile phone, etc.
Finally, the normalized Hamming distance algorithm is used for matching retrieval. In order
to protect the speech security in the cloud, a speech encryption algorithm based on a 4D
hyper chaotic system is proposed. The experimental results show that the proposed method
has good discrimination, robustness, recall and precision compared with the existing
methods, and it has good retrieval efficiency and retrieval accuracy for longer speech.
Summary: This method can make it a very low-complexity architecture and low hardware
utilization.

24
 CHAPTER-III
EXISTING METHOD
In the existing method, we are implementing the AES 256-bits key for 128 bit data with the
same s-box. 256-bit AES encryption block is implemented in 14 rounds. Each round consists
of Add Round Key, Sub Bytes, Shift Rows, Mix column. Round 0 consists of only Add
round Key operation.
3.1.AES Algorithm:
In this alogorithm,Round 14 consists of Sub Bytes, Shift Rows and Add Round Key
operations, which need 3 clock cycles. Rounds 1 to 13 consists of all the four operations. We
do a distinct operation in each clock cycle. Hence once the hardware has been implemented
for Add Round Key, Sub Bytes, Shift Rows, Mix column, the same hardware can be used for
all the 14 rounds. None of the four operations shares the same clock cycle.
The sequence of round operation with specific sequence of 4 operations to complete the AES
encryption. AES algorithm is serial process, i.e. output of first round is the input to the
second round. Hence, we can use the same hardware for each round. The data structure of
128-bit matrix. Each column consists of 4 elements of 8 bits each, so in total we have 32 bits
per word. The number of S-box required and Mix Column required to implement
conventional AES algorithm.

25
 Fig:3.1.1 One round of AES 256

AES algorithm implementation is done using four operations namely Sub Bytes, Shift Rows,
Mix Columns and Add Round Key.The above figure shows the architecture of 256-bit AES
algorithm. In total there are 14 rounds of operation for encryption and 14 rounds for
decryption. The cipher text after encryption will be transmitted across the channel. The
receiver side will decrypt the message using same key which is used in encryption. In 256-bit
AES algorithm, the key size is 256 bits, but all the data size is 128 bits. Data include message
to be encrypted, cipher text and the decrypted message.
The internal data structure of 128-bit data. The 128-bit data is used as 4x4 matrix, where each
elements of the matrix is of 8 bits. Since all the four operations are performed on columns
basis, we convert the 128-bit data in 4x4 matrix with each element being 8 bits.
256-bit AES encryption block is implemented in 14 rounds. Each round consists of Add
Round Key, Sub Bytes, Shift Rows, Mix column. Round 0 consists of only Add round Key
operation as shown in Fig. 3. Round 14 consists of Sub Bytes, Shift Rows and Add Round
Key operations, which need 3 clock cycles as shown in Fig. 3. Rounds 1 to 13 consists of all
the four operations as shown in Fig. 13. We do a distinct operation in each clock cycle. Hence
once the hardware has been implemented for Add Round Key, Sub Bytes, Shift Rows, Mix
column, the same hardware can be used for all the 14 rounds. None of the four operations
shares the same clock cycle. Fig. 3 shows the sequence of round operation with specific
sequence of 4 operations to complete the AES encryption. AES algorithm is serial process,

26
i.e. output of first round is the input to the second round. Hence, we can use the same
hardware for each round.

Table:3.1.2 Cycles required in Each Round

Table:3.1.3 Structure of conventional implementation

3.1.1.Substitute Bytes: The first transformation, SubBytes, is used at the encryption site. It is
a non-linear byte substitution that operates independently on each byte of the state using a
substitution table (S-Box). All the 16 bytes of the state are substituted by the corresponding
values which are found from the lookup table. In decryption, InvSubBytes is used. Bytes of a
state are substituted from InvSubBytes table. Figure 2 shows the SubBytes operation.
3.1.2.Shift Rows: In the encryption, the state bytes are shifted left in each row. It is called
ShiftRows operation. The number of the shifts depends on the row number (0, 1, 2 or 3) of
the state matrix. Row 0 bytes are not shifted and row 1, 2, 3 are shifted to 1, 2, 3 bytes left
accordingly. Figure 3 shows the ShiftRows operation.

27
3.1.3.Mix Column: The MixColumns transformation operates at the column level. It
transforms each column of the state to a new column. The transformation is actually the
matrix multiplication of a state column by a constant square matrix. All the arithmetic
operations are conducted in the Galois Field (Finite Field). The bytes are treated as
polynomials rather than numbers.
3.1.4.Add Round Key: AddRoundKey proceeds one column at a time. It is similar to
MixColumns in this respect. AddRoundKey adds a round keyword to each column matrix.
Matrix addition operation is performed in the AddRoundKey stage. Figure 5 shows the
AddRoundKey operation.
In encryption, SubBytes, ShiftRows, MixColumns, and AddRoundKey are performed in all
rounds except the last round. MixColumns transformation operation is not performed in the
last round of encryption. The decryption process essentially follows the same structure as the
encryption, in addition to the nine rounds of Inverse ShiftRows, Inverse SubBytes, Inverse
AddRoundKey and Inverse MixColumns Transformation.
Rijndael S-Box Generation Method The Rijndael S-Box is a square matrix which is used in
the Rijndael cipher. The S-Box serves as a lookup table. It is generated by determining the
multiplicative inverse for a given number in GF(28 ) and then transforming the multiplicative
inverse using affine transformation.
1) Multiplicative Inverse Phase: In multiplicative inverse phase, the input byte is
inversed by substituting value from multiplicative inverse table.
2) Affine Transformation: Selection of the irreducible polynomial and the designated
byte are the two most important factors of affine transformation phase. In Rijndael
AES, x 8 + x 4 + x 3 + x + 1 is used as the irreducible polynomial and as the constant
column matrix 0x63 specially designated byte is chosen. Basically, the affine
transformation consists of two operations. Firstly, 8x8 square matrix’s multiplication
and secondly, 8x1 constant column matrix addition.

28
 CHAPTER-IV
PROPOSED METHOD
4.1.SHA (Secure Hashing Algorithm):
Hash function calculations are utilized during information transmission to produce the
message digest. Along these lines, it turns into a fundamental instrument for implanted
security in email, banking, and different applications. A has work takes a self-assertive length
message contribution to deliver a fixed-length yield. A hash method is a single direction
method; it is hard to reverse deliver the same hash. These properties become a significant
viewpoint to guarantee hash capacity can work approximately
SHA-256 is a cryptographic hash function that is most widely used in the field of
cryptocurrency and has undergone many changes to gain the security and Collision
Resistance it offers in the present day, Collision Resistance means the hashes will be
completely different and it is difficult to produce the same hash with two different samples of
data.
In SHA-256 the basic following operations are applied.
• Initial Preparation
• Initialization of Hash Values (h)
• Initializing the Round Constants
• Main Loop
• Compressing
• Modifying the Resulting Values
The size of the hash value produced by SHA-256 is given by 256 bits as mentioned in Table
1 this is done by taking a binary message and padding the image with a required number of
zeros if not divisible by 512 exactly and divided into blocks(b). This is the preparation in

29
initial preparation. The values mentioned in Table 2 are initial hash. These values remain the
same for any message.

Fig.4.1.one round in SHA256

Each round has a unique Kt. called around constant. Every round's output is used as an input
for the next round, and so on until just the last bits of the message are left, at which point the
result of the last round for the nth portion of the message block will give the result, i.e. the
hash for the entire message. The output has a length of 256 bits. Thus, the final hash of 256
bits of the hash will be produced.
4.2.RSA (Rivest Shamir Adleman):
As per research, utilizing advanced marks for advanced picture verification. Where the hash
of the first picture is being taken and scrambled with the RSA strategy. It has been effectively
performed on Lena's picture. The consequences of the tests show that RSA use has high
security and is ready to validate pictures.
Because of an examination paper entitled an adjusted RSA Calculation to upgraded
computerized security. By contrasting RSA what's more, adjusted RSA calculations at the
same time to handle information of various sizes, it was produced that the RSA key generated
modem calculation was quicker and could build security twice. Concerning RSA calculation
as far as speed of encryption and unscrambling quicker than Modified RSA calculation
RSA was the first is as yet the most broadly utilized calculation for public-key cryptography
furthermore, it is utilized for the huge number of uses from email encryption to get web-
based buying. It was the first cryptosystem to empower senders to "sign" each message they
send with the goal that the beneficiary has evidence.

4.3.Advanced Encryption standard:

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 4.3.1 Combined structure of S box and Inverse S box
In proposed 32-bit operation method, we are reusing S-box and Mix Column blocks. In
proposed design “Mix Column” and “Add Round Key” together we called Mix block.

Fig:4.3.2 Combined structure of Mix Column and Add Round Key – Mix
The use of reasons to obfuscate and decipher messages in a cryptographic framework is
known as cryptographic assessment. Secret Key Cryptography (SKC): Encryption and
unscrambling, or encryption and deciphering or decryption, are all done with the same key. In
a stream figure, the plaintext digits are blended one by one, and the distinction in reformist
digits consists during the encryption. Square code is a symmetric key code
The Add Round Key Operation
The Add-Round-Key function is the only part of the AES encryption process that works
directly with the round key. The input to the round and the round key is passed through an
exclusive or operator in this operation.
The Shift Row Operation
In this activity, each line of the state is consistently moved to one side, contingent upon the
line file.
• The primary column is moved 0 spots to the left.
• The subsequent line is moved 1 spot to the left.
• The third line is moved 2 spots to the left.
• The fourth line is moved 3 spots to the left.
SUB-BYTES Operation
The sub-byte operation is an unpredictable byte substitution, dealing with each byte of the

31
state freely. The substitution table (S-Box) is autonomous of any info and is outlined by the
mix of the two methods. • Take the multiplicative inverse in Rijndael's limited field.
• Apply a relative change
Since the S-box is independent of any, still up in the air structures are used. Each byte of the
state is then subbed by the value in the S-box whose record identifies with the value in the
state:
a(i, j) = S-Box[a(i, j)]
The opposite of Sub Bytes is something the same movement, using the changed the S-Box as
mentioned in Eq(10), Mathematically, an S-box is a vectorial Boolean function. S-Box uses
the characteristic 2 finite fields with 256 elements, which can also be called the Galois field
GF(2^8).

DECRYPTION ENCRYPTION

Fig:Flow Chart for both Encryption and Decryption

32
 CHAPTER 5
ADVANTAGES & APPLICATIONS
5.1 Advantages:
 Low complexity.

 High security.

5.2 Applications:
 Wireless security,

 Processor security,

 File encryption.

33
 CHAPTER 6
VIVADO XILINX AND VERILOG HDL
6.1.HISTORY OF VERILOG:
Verilog was started initially as a proprietary hardware modeling language by Gateway Design
Automation Inc. around 1984. It is rumored that the original language was designed by taking
features from the most popular HDL language of the time, called HiLo, as well as from
traditional computer languages such as C. At that time, Verilog was not standardized and the
language modified itself in almost all the revisions that came out within 1984 to 1990.
Verilog simulator was first used beginning in 1985 and was extended substantially through
1987. The implementation was the Verilog simulator sold by Gateway. The first major
extension was Verilog-XL, which added a few features and implemented the infamous "XL
algorithm" which was a very efficient method for doing gate-level simulation.

The time was late 1990. Cadence Design System, whose primary product at that time
included thin film process simulator, decided to acquire Gateway Automation System. Along
with other Gateway products, Cadence now became the owner of the Verilog language, and
continued to market Verilog as both a language and a simulator.
At the same time, Synopsys was marketing the top-down design methodology, using
Verilog. This was a powerful combination. In 1990, Cadence recognized that if Verilog
remained a closed language, the pressures of standardization would eventually cause the
industry to shift to VHDL. Consequently, Cadence organized the Open Verilog International
(OVI), and in 1991 gave it the documentation for the Verilog Hardware Description
Language. This was the event which "opened" the language.

34
6.2.INTRODUCTION :
 HDL is an abbreviation of Hardware Description Language. Any digital system can
be represented in a REGISTER TRANSFER LEVEL (RTL) and HDLs are used to
describe this RTL.
 Verilog is one such HDL and it is a general-purpose language –easy to learn and use.
Its syntax is similar to C.
 The idea is to specify how the data flows between registers and how the design
processes the data.
 To define RTL, hierarchical design concepts play a very significant role. Hierarchical
design methodology facilitates the digital design flow with several levels of
abstraction.
 Verilog HDL can utilize these levels of abstraction to produce a simplified and
efficient representation of the RTL description of any digital design.
 For example, an HDL might describe the layout of the wires, resistors and transistors
on an Integrated Circuit (IC) chip, i.e., the switch level or, it may describe the design
at a more micro level in terms of logical gates and flip flops in a digital system, i.e.,
the gate level. Verilog supports all of these levels.

6.2.1.DESIGN STYLES:
Any hardware description language like Verilog can be design in two ways one is bottom-up
design and other one is top-down design.
6.2.1.1 Bottom-Up Design:
The traditional method of electronic design is bottom-up (designing from transistors and
moving to a higher level of gates and, finally, the system). But with the increase in design
complexity traditional bottom-up designs have to give way to new structural, hierarchical
design methods.
6.2.1.2 Top-Down Design:
For HDL representation it is convenient and efficient to adapt this design-style. A real top-
down design allows early testing, fabrication technology independence, a structured system
design and offers many other advantages. But it is very difficult to follow a pure top-down
design. Due to this fact most designs are mix of both the methods, implementing some key
elements of both design styles.
6.3.Features of Verilog HDL:

35
  Verilog is case sensitive.
 Ability to mix different levels of abstract freely.
 One language for all aspects of design, testing, and verification.
 In Verilog, Keywords are defined in lower case.
 In Verilog, Most of the syntax is adopted from "C" language.
 Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch
level.
 There is no concept of package in Verilog.
 It also supports advanced simulation features like TEXTIO, PLI, and UDPs.

6.4.VLSI DESIGN FLOW:

The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of
steps, and eventually produces a packaged chip.

Fig:6.4.1 vlsi design flow

6.4.1 System Specification:
The first step of any design process is to lay down the specifications of the system. System
specification is a high level representation of the system. The factors to be considered in this
process include: performance, functionality, and physical dimensions like size of the chip.
The specification of a system is a compromise between market requirements, technology and
economical viability. The end results are specifications for the size, speed, power, and
functionality of the VLSI system.
6.4.2 Architectural Design

36
The basic architecture of the system is designed in this step. This includes, such decisions as
RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer),
number of ALUs, Floating Point units, number and structure of pipelines, and size of caches
among others. The outcome of architectural design is a Micro-Architectural Specification
(MAS).
6.4.3 Behavioral or Functional Design:
In this step, main functional units of the system are identified. This also identifies the
interconnect requirements between the units. The area, power, and other parameters of each
unit are estimated.
Modules. The key idea is to specify behavior, in terms of input, output and timing of each
unit, without specifying its internal structure.
The outcome of functional design is usually a timing diagram or other relationships between
units.
6.4.4 Logic Design:
In this step the control flow, word widths, register allocation, arithmetic operations, and logic
operations of the design that represent the functional design are derived and tested.
This description is called Register Transfer Level (RTL) description. RTL is expressed in a
Hardware Description Language (HDL), such as VHDL or Verilog. This description can be
used in simulation and verification

6.4.5 Circuit Design:

The purpose of circuit design is to develop a circuit representation based on the logic design.
The Boolean expressions are converted into a circuit representation by taking into
consideration the speed and power requirements of the original design. Circuit Simulation is
used to verify the correctness and timing of each component
The circuit design is usually expressed in a detailed circuit diagram. This diagram shows the
circuit elements (cells, macros, gates, transistors) and interconnection between these
elements. This representation is also called a netlist. And each stage verification of logic is
done.
6.4.6 Physical design:
In this step the circuit representation (or netlist) is converted into a geometric representation.
As stated earlier, this geometric representation of a circuit is called a layout. Layout is created

37
by converting each logic component (cells, macros, gates, transistors) into a geometric
representation (specific shapes in multiple layers), which perform the intended logic function
of the corresponding component. Connections between different components are also
expressed as geometric patterns typically lines in multiple layers.
6.4.7 Layout verification:
Physical design can be completely or partially automated and layout can be generated directly
from netlist by Layout Synthesis tools. Layout synthesis tools, while fast, do have an area and
performance penalty, which limit their use to some designs. These are verified.

6.4.8 Fabrication and Testing:

Silicon crystals are grown and sliced to produce wafers. The wafer is fabricated and diced
into individual chips in a fabrication facility. Each chip is then packaged and tested to ensure
that it meets all the design specifications and that it functions properly.
6.5 MODULE:
A module is the basic building block in Verilog. It can be an element or a collection of low
level design blocks. Typically, elements are grouped into modules to provide common
functionality used in places of the design through its port interfaces, but hides the internal
implementation.

Syntax:
module<module name> (<module_port_list>);
…..
<module internals> //contents of the module
….
Endmodule
6.5.1 Instances:
A module provides a template from where one can create objects. When a module is invoked
Verilog creates a unique object from the template, each having its own name, variables,
parameters and I/O interfaces. These are known as instances.
6.5.2 Ports:
 Ports allow communication between a module and its environment.
 All but the top-level modules in a hierarchy have ports.

38
  Ports can be associated by order or by name.

You declare ports to be input, output or inout. The port declaration syntax is:
Input [range_val:range_var] list_of_identifiers;
output[range_val:range_var] list_of_identifiers;
inout[range_val:range_var] list_of_identifiers;
6.5.3 Identifiers:
 Identifiers are user-defined words for variables, function names, module names, and
instance names. Identifiers can be composed of letters, digits, and the underscore
character.
 The first character of an identifier cannot be a number. Identifiers can be any length.
 Identifiers are case-sensitive, and all characters are significant.
An identifier that contains special characters, begins with numbers, or has the same name as a
keyword can be specified as an escaped identifier. An escaped identifier starts with the
backslash character(\) followed by a sequence of characters, followed by white space.
6.5.4 Keywords:
 Verilog uses keywords to interpret an input file.
 You cannot use these words as user variable names unless you use an escaped
identifier.
 Keywords are reserved identifiers, which are used to define language constructs.
 Some of the keywords are always, case, assign, begin, case, end and end case etc.
6.5.5 Data Types:
Verilog Language has two primary data types:
 Nets - represents structural connections between components.
 Registers - represent variables used to store data.
Every signal has a data type associated with it. Data types are:
 Explicitly declared with a declaration in the Verilog code.
 Implicitly declared with no declaration but used to connect structural building blocks
in the code. Implicit declarations are always net type "wire" and only one bit wide.

6.5.6 Register Data Types:

 Registers store the last value assigned to them until another assignment statement
changes their value.

39
  Registers represent data storage constructs.
 Register arrays are called memories.
 Register data types are used as variables in procedural blocks.
 A register data type is required if a signal is assigned a value within a procedural
block
 Procedural blocks begin with keyword initial and always.
The data types that are used in register are register, integer, time and real.

6.6 MODELING CONCEPTS:

6.6.1 Abstraction Levels:
 Behavioral level
 Register-Transfer Level
 Gate Level
 Switch level

6.6.1.1 Behavioral or algorithmic Level:

 This level describes a system by concurrent algorithms (Behavioral).
 Each algorithm itself is sequential meaning that it consists of a set of instructions that
are executed one after the other.
 The blocks used in this level are ‘initial’, ‘always’ ,‘functions’ and ‘tasks’ blocks
 The intricacies of the system are not elaborated at this stage and only the functional
description of the individual blocks is prescribed.
 In this way the whole logic synthesis gets highly simplified and at the same time more
efficient.

6.6.1.2 Register-Transfer Level:

 Designs using the Register-Transfer Level specify the characteristics of a circuit by
operations and the transfer of data between the registers.
 An explicit clock is used. RTL design contains exact timing possibility, operations are
scheduled to occur at certain times.
 Modern definition of a RTL code is "Any code that is synthesizable is called RTL
code".

6.6.1.3 Gate Level:

40
  Within the logic level the characteristics of a system are described by logical links and
their timing properties.
 All signals are discrete signals. They can only have definite logical values (`0', `1',
`X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc
gates).
 It must be indicated here that using the gate level modeling may not be a good idea in
logic design.
 Gate level code is generated by tools like synthesis tools in the form of netlists which
are used for gate level simulation and for backend.

6.7.9 Switch Level:

 This is the lowest level of abstraction. A module can be implemented in terms of

switches, storage nodes and interconnection between them. However, as has been
mentioned earlier, one can mix and match all the levels of abstraction in a design.
RTL is frequently used for Verilog description that is a combination of behavioral and
dataflow while being acceptable for synthesis.

6.7.OPERATORS:
Verilog provided many different operators types. Operators can be,
 Arithmetic Operators
 Relational Operators
 Bit-wise Operators
 Logical Operators
 Reduction Operators
 Shift Operators
 Concatenation Operator
 Conditional Operator

6.7.1 Arithmetic Operators

 These perform arithmetic operations. The + and - can be used as either unary (-z) or
binary (x-y) operators.

41
  Binary: +, -, *, /, % (the modulus operator)
 Unary: +, - (This is used to specify the sign)
 Integer division truncates any fractional part
 The result of a modulus operation takes the sign of the first operand
 If any operand bit value is the unknown value x, then the entire result value is x
 Register data types are used as unsigned values (Negative numbers are stored in two's
complement form).

6.7.2 Relational Operators

Relational operators compare two operands and return a single bit 1or 0. These operators
synthesize into comparators. Wire and reg variables are positive Thus (-3’b001) = = 3’b111
and (-3d001)>3d1 10, however for integers -1<>

Table:6.7.2.1 Relational Operator

 The result is a scalar value
 0 if the relation is false (a is bigger than b)
 1 if the relation is true ( a is smaller than b)
 x if any of the operands has unknown x bits (if a or b contains X)

Note: If any operand is x or z, then the result of that test is treated as false (0)

6.7.3 Bit-wise Operators

Bitwise operators perform a bit wise operation on two operands. This take each bit in one
operand and perform the operation with the corresponding bit in the other operand. If one
operand is shorter than the other, it will be extended on the left side with zeroes to match the
length of the longer operand

42
 Table:6.7.3.1 Bit-wise Operator
Computations include unknown bits, in the following way:
-> ~x = x
-> 0&x = 0
-> 1&x = x&x = x
-> 1|x = 1
-> 0|x = x|x = x
-> 0^x = 1^x = x^x = x
-> 0^~x = 1^~x = x^~x = x
When operands are of unequal bit length, the shorter operand is zero-filled in the most
significant bit positions.
6.7.4 Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for
single bit operands. They can work on expressions, integers or groups of bits, and treat all
values that are nonzero as “1”. Logical operators are typically used in conditional (if ... else)
statements since they work with expressions.

Table:6.7.4.1 Logical Operator

Expressions connected by && and || are evaluated from left to right
Evaluation stops as soon as the result is known
The result is a scalar value:
 0 if the relation is false
 1 if the relation is true
 x if any of the operands has x (unknown) bits

43
6.7.5 Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a single-bit value.
These are the unary (one argument) form of the bit-wise operators.

Table:6.7.5.1 Reduction Operator

 Reduction operators are unary.
 They perform a bit-wise operation on a single operand to produce a single bit result.
 Reduction unary NAND and NOR operators operate as AND and OR respectively,
but with their outputs negated.

6.7.6 Shift Operators

Shift operators shift the first operand by the number of bits specified by the second operand.
Vacated positions are filled with zeros for both left and right shifts (There is no sign
extension).

Table:6.7.6.1 Shift Operator

 The left operand is shifted by the number of bit positions given by the right operand.
 The vacated bit positions are filled with zeroes

6.7.7 Concatenation Operator

 The concatenation operator combines two or more operands to form a larger vector.
 Concatenations are expressed using the brace characters { and }, with commas
separating the expressions within.
 ->Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24
bits
 Unsized constant numbers are not allowed in concatenations

44
6.7.8 Operator Precedence

Table:6.7.8.1 Operator Precedence

6.8 Vivado Xilinx Verilog HDL Tutorial:
Introduction:
Xilinx Tools is a suite of software tools used for the design of digital circuits implemented
using Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic
Device (CPLD). The design procedure consists of (a) design entry, (b) synthesis and
implementation of the design, (c) functional simulation and (d) testing and verification.
Digital designs can be entered in various ways using the above CAD tools: using a schematic
entry tool, using a hardware description language (HDL) – Verilog or VHDL or a
combination of both. In this lab we will only use the design flow that involves the use of
Verilog HDL.
The CAD tools enable you to design combinational and sequential circuits starting with
Verilog HDL design specifications. The steps of this design procedure are listed below:
1. Create Verilog design input file(s) using template driven editor.
2. Compile and implement the Verilog design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a PLD
(FPGA or CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device
A Verilog input file in the Xilinx software environment consists of the following segments:
Header: module name, list of input and output ports.
Declarations: input and output ports, registers and wires.
Logic Descriptions: equations, state machines and logic functions.

45
End: endmodule
All your designs for this lab must be specified in the above Verilog input format. Note that
the state diagram segment does not exist for combinational logic designs.
Creating a New Project
Vivado Xilinx Tools can be started by clicking on the Project Navigator Icon on the
Windows desktop. This should open up the Project Navigator window on your screen. This
window below window shows the last accessed project.

Fig:6.8.1 Creating a project in Vivado Xilinx softaware

Opening a project
Select File->New Project to create a new project. This will bring up a new project window
(Figure 2) on the desktop. Fill up the necessary entries as follows:

46
 Fig: 6.8.2 Set the project Name and Location
Project Name: Write the name of your new project which is user defined.
Project Location: The directory where you want to store the new project in the specified
location in one of your drive. In above window they are stored in location c drive which is
not correct , the location of software and code should not be same location.

Clicking on NEXT should bring up the following window:

Fig:6.8.3 Setting the Category, Family, Package, Speed

47
For each of the properties given below, click on the ‘value’ area and select from the list of
values that appear.
 Device Family: Family of the FPGA/CPLD used. In this laboratory we will be using
the Spartan3E FPGA’s.
 Device: The number of the actual device. For this lab you may enter XC3S250E (this
can be found on the attached prototyping board)
 Package: The type of package with the number of pins. The Spartan FPGA used in
this lab is packaged in CP132 package.
 Speed Grade: The Speed grade is “-4”.
 Synthesis Tool: XST [VHDL/Verilog]
 Simulator: The tool used to simulate and verify the functionality of the design.
Modelsim simulator is integrated in the Xilinx ISE. Hence choose “Modelsim-XE
Verilog” as the simulator or even Xilinx ISE Simulator can be used.
Then click on NEXT to save the entries.
All project files such as schematics, netlists, Verilog files, VHDL files, etc., will be stored in
a subdirectory with the project name.
In order to open an existing project in Xilinx Tools, select File->Open Project to show the
list of projects on the machine. Choose the project you want and click OK.

Clicking on NEXT on the above window brings up the following window:

Fig:6.8.4 adding the files into your project

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6.9 Synthesis and Implementation of the Design:
The design has to be synthesized and implemented before it can be checked for correctness,
by running functional simulation or downloaded onto the prototyping board. With the top-
level Verilog file opened (can be done by double-clicking that file) in the HDL editor
window in the right half of the Project Navigator, and the view of the project being in the
Module view , the implement design option can be seen in the process view. Design entry
utilities and Generate Programming File options can also be seen in the process view.
To synthesize the design, double click on the Synthesize Design option in the Processes
window.
To implement the design, double click the Implement design option in the Processes
window. It will go through steps like Translate, Map and Place & Route. If any of these
steps could not be done or done with errors, it will place a X mark in front of that, otherwise a
tick mark will be placed after each of them to indicate the successful completion
After synthesis right click on synthesis and click view text report in order to generate the
report of our design.
Synthesis report completed will be like:

Fig:6.9.1 Synthesis of the Design

49
The below diagram shows how much time it takes by using vivado xilinx software

Fig:6.9.2 Report of Timing Summary

The below diagram shows that how much area it consumes by using vivado xilinx software

Fig:6.9.3 Report Area

50
 CHAPTER 7
SIMULATION RESULTS

Fig:7.1 simulation of all modules

51
 Fig:7.1.1 Add All Signals to Waveform

Fig: 7.1.2 converting binary to hexadecimal

RTL schematic:

52
Technology Schematic

53
7.3 Final Output Results:

54
Area:

Delay:

55
Evaluation table for Area, Delay:

Area (Slice Reg) Delay (ns)

Top 4793 2.68

Table:7.3.1 Evaluation for Area and Delay

CHAPTER 8
CONCLUSION

56
This method is very useful for protecting an image's authenticity by making use of efficient
encryption algorithms which means digitally signing the highly sensitive photographs or even
text images which when manipulated may lead to huge chaos like that happened in the
Lebanon war caused by miscommunication and misinterpretation of images these
miscommunications and misinterpretations can be prevented by using digital signatures with
three levels of protection to ensure that the images that are seen are authentic information that
is intended is conveyed in those images Hence this method can be used for the secure
transportation of their sensitive data files.

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