Department of Electronics and Communication Engineering

GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

(AUTONOMOUS)
Cheeryal (V), Keesara (M), Medchal Dist, Hyderabad– 501 301
(Affiliated to Jawaharlal Nehru Technological University, Hyderabad, accredited by NAAC and NBA, New Delhi)

BACHELOR OF TECHNOLOGY

In

Electronics and Communication Engineering

2019-2023

Major Project Abstract

Topic:
PLACE OF EXECUTION: GCET
8-bit CPU based on SAP-1 architecture
Guide Name: Mr. A. Shanker (Associate Prof)
BATCH NO: A14
1) 19R11A0438 – Sujit Rayaprolu
2) 19R11A0421 – Lodugu venkatasai Maheshwara reddy
3) 19R11A0420 – Venkatesh Kurva

Abstract
 In an introductory course of computer architecture, it is of high
value that students use a simple and special CPU designed for this
purpose and also a 7 segment display for better understanding of the
computer hardware operation. Here, we present a simple 8-bit processor
which we have specifically designed and built as the introduction part of
the computer architecture course to help students familiarize themselves
with the hardware and software of a real CPU. Effective use of our 8-bit
CPU along with the 7-segment display allows the students to deepen
their knowledge of logic circuits and the need for desired timing signals
in a CPU to perform specific tasks.

Objective

The main objective of this project is to design and develop an 8-bit CPU
with 2 general-purpose registers, an ALU with support for addition and
subtraction, and a 7-segment output display using SAP-1 architecture with
some additions from SAP-2.

Hardware: PCB, 1kΩ resistors, 10kΩ resistor, 100kΩ resistor, 470Ω resistor, 1MΩ
resistor, 1MΩ potentiometer, 0.01µF capacitor, 0.1µF capacitor, 1µF capacitor, 555
timer IC, 74LS00 (Quad NAND gate), 74LS02 (Quad NOR gate), 74LS04 (Hex
inverter), 74LS08 (Quad AND gate), 74LS32 (Quad OR gate), 74LS107 (Dual JK flip-
flop), 74LS86 (Quad XOR gate), 74LS138 (3-to-8 line decoder), 74LS139 (Dual 2-line
to the 4-line decoder), 74LS157 (Quad 2-to-1 line data selector), 74LS161 (4-bit
synchronous binary counter), 74LS173 (4-bit D-type register), 74189 (64-bit random
access memory), 74LS245 (Octal bus transceiver), 74LS273 (Octal D flip-flop),
74LS283 (4-bit binary full adder), 28C16 EEPROM, 8-position DIP switch, 4-position
DIP switch, LED of different colors, 7-segment display (common cathode), Momentary
6mm tact switch, Arduino nano, 74HC595 (shift registers)

Software: ArduinoIDE, Fusion360

Circuit Diagram:
Commercialisable: Yes/No: Yes

References:
1. https://en.wikipedia.org/wiki/Simple-As-Possible_computer
2. L. Null, J. Lobur, "The essentials of computer organization and
architecture", Sudbury, MA, Jones and Barlette Publishers, 2003
3. J. Phillips, "Simulation of simple CPU design and its use as an
instructional tool in a computer organization course", Journal of
Computing Sciences in Colleges, vol. 22, June 2007, pp.140-146
4. Mohammadamin Ajdari, Mahmoud Tabandeh, "An Educational
Hardware/Software Tool for the First Course in Computer
Architecture", Iranian Journal of Science and Technology,
Transactions of Electrical Engineering, 2016.

Date of Submission:

Signature of the
Signature of the
Guide with Date Project In-
Charge