Digital Electronics Lab Manual ABV-1IITM Gwalior

ABV- Indian Institute of Information Technology &

Management, Gwalior
Digital Electronics Lab

List of Experiments

Sr. No. Name of experiment

1. Study of basic components and IC's used in digital electronics lab.

junction diodes and

Implementation of basic logic gates using switches, p-n
2 bipolar junction transistor.

of universal gates and implementation of Boolean functions using

3 Study
NAND and NOR gatcs.

Implementation of 1-bit Full Adder/Subtractor using logic gates.

S.Implementation of 2-bit binary ripple adder using logic gates.

6. Implementation of 2x2 bit binary multiplier using logic gates.

binary and binary to gray code

Design and Implementation of gray to
converters.

Realization of Adder and Subtractor

circuits using Multiplexer.
8.
circuits and implementation of Flip-Flops
9 Study of sequential
asynchronous decade counter.
10. Design and implenentation of
ánd behavioral modeling) to realize all the gates
Write VHDL code (data flow
11. FPGA.
and implement these gates
on

ITM Gwalior
 Experiment No. # 1 The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits)
the experiments. Incorrect connection of power to the ICs could result in them
used during
Title: Study of basic components and ICs used in digital electronics lab. the people
exploding or becoming very hot with the possible serious injury occurring to
and all components
Objective: The objective of this lab exercise is to study of basic electronic components i.e. working on the experiment! Ensure that the power supply polarity
bread board, multi-meter, power supply and various digital ICs. and connections are correct before switching on power.

experiments will use TTL chips to build circuits.

Components and equipment: Bread Board, 74 series ICs, wires LEDS and power supply. Building the Circuit: Throughout these we

circuit should be Completed in the order described below:

The steps for wiring a
Introduction:
1. Turn the power (Trainer Kit) off before you build anything!
The Breadboard: 2. Make sure the power is off before you build anything!
The breadboard consists of two terminal atrips and two bus strips (often broken in the 3. Connect the +5V and ground (GND) leadsofthe power supply to the power and ground
Each of the two rows of contacts are a bus strips on your breadboard.
centre). Each bus strip has two rows
of contacts. in the same
node. That is, each contact along a row on a bus strip is connected together (inside the 4. Plug the chips you will be using into the breadboard. Point all the chips
direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a
breadboard). Bus strips are used supply connections, but are also used
primarilyfor power
for any node requiring a large number of connections. Each terminal strip has 60 rows and notch next to it on the chip package
ground bus strips the
S columns of contacts on each side of the centre gap.
Each
row S contacts is a node. You
of S. Connect +5V and GND pins of each chip to the power and on

will build your circuits on the terminal strips by inserting the leads of circuit components breadboard.
plece of hook-up wire between
into the contact receptacles and making connections with 22-26 gauge wire. There are wire 6. Select a connection on your schematic and place a is better to make the short
cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and OV corresponding pins of the chips on your breadboard. It
connections before the longer ones. Mark each connection on your schematic as you
power supply connections to separate bus strip5
later stage.
go, so as not to try to make the same connection again at a
7. Get one of your group members to check the connections, before you turn the power

S on.

8. If an error is made and is not spotted before you turn the power on. Turn the power off

immediately before you begin to rewire the circuit.

9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment
and return them to the demonstrator.

in and it in the same condition as it was

10. Tidy the area that you were working leave
before you started.
often gap hee
Common Causes of Problems:

1. Not connegtingthe groundand/or powenpinsfoeal chips

circuit.
2. Not turnin on the power süpplybeforecheckingthe operatlon of the
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates

6. Modifying the circuit with the power on.

Terminal Serl leads, components at the

experiments, you will be expected to obtain all instruments,
In all
after you have finished the
startof the experiment and return them to their proper place
Fig. 1: The breadboard. The lines indicate connected holes
technician if you locate faulty equipment. If
experiment. Please inform the demonstrator or

Somesh Kumar)
Department of Electronics and communication Engineering
(Dr.
Department of Electronics and communication Engineering (Dr. Somesh Kumar)
Digital Electronics Lab Manual ABV-IlITM Gwalior Digital Electronics Lab Manual ABV-IIUTM Gwalior
you damage a chip, inform a
demonstrator, don't put it back in the box of chips for ALVT- Low-voltage -2.5-3.3 V, 5 V tolerant inputs, high current s 64 mA, TPD <3 ns at
somebody else to use.
2.5 V.

Useful iC Pin details: AUC- Low-voltage -0.8-2.5 V, TPD<2.5 ns at 1.8 V.

Letters in front of IC numbers are usually specific to their manufacturers. SN is used by T, AUP- Low-voltage - 0.8-3.6 V (3.3 V typically), TPD 15.6/8.2/4.3 ns at 1.2/1.8/3.3V,
NS by National Semiconductor, MC by Motorola, and so forth.
partial power-down specified (IOFF), inputs protected.
Bipolar based ICs
AVC-Low-voltage-1.8-3.3 V, TPD < 3.2 ns at 1.8 V, bus hold, 1OFF.
74-Standard TTL.
74L Low-power. FC-Fast CMOS, performance similar to 74F.
LCX-CMOS with 3V supply and S V tolerant inputs.
74H-High-speed.
LV-Low-voltage CMOS-2.0-5.5 Vsupply and 5 V tolerant inputs.
74S High-speed Schottky. implemented with Schottky diode
clamps at the inputs to LVCLow voltage -1.65-3.3 and
prevent charge storage, this provides faster
operation than the 74 and 74H series at the
V
5V tolerant inputs, TPD < 5.5 ns at 3.3 V, TPD < 9 ns
cost of increased power at 2.5 V.
consumption and cost.
74LS Low-power Schottky. Implemented using LV-A-2.5-5 V, 5 V tolerant inputs, TPD< 10 ns at 3.3 V, bus hold, 1OFF, low noise.
the same technology as 74S but with
reduced power consumption and
switching speed. LVT-Low-voltage 3.3 V supply, 5 V tolerant inputs, high output current< 64 mA, TPD
74AS- Advanced <3.5 ns at 3.3 V, IOFF; low
Schottky, the next iteration of the 74S series with greater speed and
noise.
fan-out despite lower power
consumption. LVQ-Low-voltage-3:3V.
74ALS Advanced low-power Schottky.
-

Same LVX
technology as 74AS but with the
Low-voltage-3.3Vwith 5 Vtoterant inputs.
speed/power tradeoff of the 74LS.
VHCVery-high-speed CMoS-74S performance in CMOS
technologY and power.
74F- Fast.
CMOS based ICs
Many parts in the CMOS HC, AC, and FC families are also offered in "T" versions
C-CMOS 4-15 V operation. and FCT) which have
(HCT, ACT,
input thresholds that are compatible with both TL and 3.3 V CMOS
signals. The non-T parts have conventional CMOS input thresholds.
HC-High-speed CMOs, similar performance to 74LS.1
NOT Gate (7404)
HCT-High speed, compatible logic levels to bipolar parts.
AC-Advanced CMOSperformance generallybetween74S and 74F
ACT-Advanced CMOS, performance generally between 74S and 74F. Compatible logic
levels to bipolar parts. o r
ACQ Advanced CMOS with Quiet
outputs.
AHC Advanced high-speed
input.
CMOS, three times as

ALVC-Low-voltage-1.8-3.3 V, time Propagation Delay (TPD)<3 ns at 3.3 V.

fast as 74HC, tolerant of 5.5V on

L
 IC7408 (AND Gate)
IC7402 (NOR Gate)

IC 7402

AND
7403 Quad 2 Input

IC7403/7400 (NAND Gate) IC7486 (XOR Gate)

IC 7486

7403 Quad 2 Input NAND OC

L 7 GND

ww.o

IC7432 (OR Gate) simple circuits on

be able to implement
Result: At the end of this
lab exercise, one should

Vce14 13 121 11 109a bread-board.

Post lab design questions:

7432
on bread-board.
implement the Y=A+B
D 1. How can we

2. Explain about the multi-meter

Pearson Prentice Hall,
Computer Design",
Reference: M. Morris Mano, "Digital Logic and
IC7411 (3 Input AND Gate)
2008.
ITM Gwalior
vCC

PL
7411 Triple 3 Input AND

Engineering Dr. Somesh Kumar)

Electronics and communication
Department of
communication Engineering (Dr. Somesh Kumar)
and
Department of Electronics
 ABV-UTM Gwalior Digital Electronics Lab Manual ABV-IIITM Gwalior
Digital Electronics Lab Manual
Function Logic Symbol Truth Table
Experiment No. # 2

diodes and bipolar OR

Title: Implementation of basic logic gates using switches, p-n junction
A
junction transistor.

basic logic functions (AND,

Objective: The objective of this lab exercise is to implement the 0
and transistors (BJTS). Students
OR and NOT) using discrete switches, diodes (p-n junctions)
can be made to work as
functional Y=A+B
will be able to understand how switching circuits

building blocks for complex logic circuits.

diodes, BJTs, LEDS, power supply (C) NOT Gate: The truth table and output expression for a one input NOT gate are given
Components and equipment: SPDT switches, p-n junction
below:
and standard experimental setup.
three basic operations: AND, OR and Function Logic Symbol Truth Table
Introduction: Any digital iogic can be realized using
implement these functions are called
NOT (inversion). For this reason, circuits that can and
NOT
basic logic gates. These basic logic available in standard TTL and CMOS ICS
gates are
form the functional building blocks for complex combinational
carefuily examine the
and sequential circuits. If we

tables of these logic gates, we öbserve that they can be

truth
realized
A Y
toggle
be elementary switches (SPDT) or discrete Y=A
using basic switches. These switches can
current lab exercise, we
solid state devices (p-n junction diodes and transistors). In our
shall using switches to implement these logic functions.

Procedure: The truth table and output Boolean functions for the basic gates are given
1.
8ates using switches, diodes and BJTs explained Fig.
is in
below. Implementation of these AND gate using switchs OR gate uslng switchea
circuits on breadboard. For standard imputes
Using the given information, implement the
and verify the truth tables for these logic
(A & B), obtain the corresponding output (Y) sIA
3v

gates.
for two input AND gate are
(a) AND Gate: The truth table and output expression a

given below:

Function
LogicSymbol 1- 7S11TruthTable
AND

TTTTM GWalOT
Y=A.B

(b) OR Gate: The truth table and output expression for a two input OR gate are given
below:
 AND gate nsing diocdes
NOT gato using a switch

VDD« VV

3V Ra 1kn
**** R : 1kf

A (nput 01
A
Input D2
B
ED

NOT gate using a T

OR gate using diodes

VOD-3V
InputR 1k D1
1k
Input Re 1 02
BoW
LED
lnput Ra1k
LEQ
A PH

Fig. 1:Circuit diagrams for basic togic gates

Result: At the end of this lab exercise, one should be able to perform logic operations using
switches, diodes and transistors and verify their respective truth tables.

Post lab design questions:

1. Can we implement NOT gate using the diodes. If not give reasons.
ww
2. How would you implement AND and OR logic gates úsinig-8)Ts?
Reference: M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall,

2008.

IITM Gwalior

Department of Electronics and communication Engineering (Dr. Somesth Kumar) 11

 Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Elcctronics Lab Manual ABV-IIITM Gwalior

Experiment No. # 3
Title: Study of universal gates and implementation of Boolean functions using NAND and Procedure: The logic circuits for gates using NAND and NOR gates in tables 2 and3
NOR gates. respectively. Implement these circuits using the respective ICs (TTL IC 74LSOO for NAND and
TTL IC 74LSO2 for NOR). Using this information, implement the circuits and obtain the
Objective: The objective of this lab exercise is to verify whether NAND and NOR can be
corresponding outputs for different combinations of inputs. Also verify the truth tables for
Used to implement any Boolean function. Here we will implement the basic as well as
the circuits.
parity logic gates using the universal gates and verify their respective truth tables.

Components and equipment: TTL ICs 74LS00, 74LSO2, LEDS, power supply and standard Function Logic Symbol Circuit

experimental setup.
Introduction: The NAND and NOR gates
circuit

NOR
can be implemented with it.

gates rather than with other

are called the universal gates, because any logic
Digitalarcuits are frequently constructed with NAND or
gatesThisisbecause they are easier to fabricate with
electronic components and it is easy to imptement all the logic functions using these
NOT
- Y:= A
- y

gates.
Table 1 gives the symbols and truth tables for the NAND and NOR
gates.
SymboB Truth Table

AND

input Output
3
Y YA B

Y=A-B 1 1
-Y A Y
OR B
B-
A- Input Output
A

B IITM ar
A -

Y=A+B Y B
0 EXOR B
1
Y = A B =
Aß+
Table 1: Logic symbols and truth tables for NAND and NOR
gates
 EXOR
Y
EXNOR
Y =
AB = AB +AB
DDO Y= AB = AB + AAB
D

Table 2: Circuits for logic gates using NAND

Function Logic Symbol

EXNOR A
Circuit
YA -Y
B

Y =A® B AB+AB
NOT
A- - Y

YA
Table 3: Circuits for logic gates using NOR

Result: At the end of this lab exercise, one should be able to implement all the logic gates
A- using the NAND and NOR gates.
AND

B B-
Post lab design questions:

1. How can we implement the half/full adder and subtractor circuits using universal
Y = A B
gates?
2. Can, we implemient any Boolean exprèsslon iusing onlythe universal gates? If yes,
try to implement the few expressions.
Reference: M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall,

DD|
2008.
T M GWallo
OR

Y=A +B

Department of Electronics and communication Engincering (or. Somesh Kuimar) 14 Department of Electronics and communication Engineering (or.Somash Kumar) 15
 Digital Electronics Lab Manual ABV-IIITM Gwalior
Digital Electronics Lab Manual ABV-IUTM Gwalior
Experiment No. # 4 Inputs Outputs
Cin Cor
Title: implementation of 1-bit Full Adder/Subtractor using logic gates. O

Objective: The objective of this lab exercise is to perform addition and subtraction of
binary digits using combinational circuits. In this lab exercise we will design and implement 1 0
Adder and Subtractor circuits for 2/3-bit arithmetic operation.

Components and equipment: TTL ICs 74LS08, 74LS32, 74LS86, 74LS04, LEDs, power supply
and standard experimental setup
Introduction: The basic arithmetic operations performed by the computer are addition of
n-bit numbers. A combinational circuit that performs the addition of two bits is called a half
adder. The higher significant bit produced after the addition of any two digits is called a Half Subtractor: The truth table and the Boolean functions for the outputs
C.
carry. When the numbers contain mare sienificant digits, the carry obtained from the
addition of two bits is added to the ext higher order pair of significant bits. A
Difference (D) and Borrow (B) aregivenbelow:
combinational circuit that performs the addition of three bits (two significant bits and a
previous carry) is a full adder. Likewise, a combinational circuit that performs subtraction
Inputs Outputs
B D
of two bits is called as half-subtractor. While performing the subtraction operation, if the D AB+ = A ®B
minuend bit is smaller than the subtrahend bit 1 is borrowed from the next significant
B AB
position. A combinational circuit which performs the subtraction of two bits, taking into
account the borrow of the pervious stage, is called as full-subtractor
Procedure: The truth tables and Simplified Booleanfunctions for adder and subtractor
circuits are given below. Implementation of these circuits using logic gates is explained in D. Full Subtractor: The truth table and the Boolean functions for the outputs
Fig. 1. Using this information, implement the circuits. For given combination of inputs, Difference (D) and Borrow (BoUT) are given below:
obtain the corresponding outputs and verify the truth tables for the circuits.

A. Half Adder: The truth table and the Boolean functions for the outputs Sum (S) and Inputs Outputs
Carry (C) are given below: B Bin Bo D + B En +A B Bn +A B Bin
0 AB
=
Bin
Inputs Outputs S Bo AB Bn + En + Bin + AB Bin
S = AB + A =A 9 B = AB+ (A B)Bin
CAB
Vwalior
Full Adder: The truth table and the Boolean functions for
the outputs Sum (S) and
Carry (CouT) are given
below
S =AB Cin + BCn t+ ABCn +AB Cin A DB

ARC AR RG
 below:
SAB Cn +ABCn tABCn +ABCn =A9B
Cout AB Cin +A B CGn t ABCn +A BCin = AB

Full Adder
Half Adder

D
D
Cout

Cin

Full Subtractor
Half Subtractor

D
U

Figure 1: Logicdiagrams for adders and subtractor

addition and
one should be able to perform
Result: At the end of this lab exercise,
Adder and Subtractor circuits, respectively.
subtraction of any 2/3 1-bit numbers using

Post lab design questions:

Decoders? If yes,
Multiplexers and
1. Can we implement addition,operation using
how?
2 n-bit binary numbers?
2. Can we further extend this lab exercise to add/subtract
Design, Pearson Prentice Hall,
Reference: M Morris Mano Digital Logic and Computer
2008.

Somesh Kumar)
18
communication Eng1neering (Dr.
Department of Electronics and
 Digital Electronics Lab
Manual ABV-IIITM Gwalior
Digital Electronics Lab Manual ABV-IITM Gwalior
Experiment No. # 5
Title: Implementation of 2-bit binary ripple adder using logic eates. HALF-ADDER FULL-ADDER

Objective: The objective of this lab exercise is to

perform addition of two 2-bit numbers. In
this lab exercise, will be 1 -
we
designing a 2-bit ripple adder using the half and full adder
circuits, which are to be implemented using the basic logic gates.
Components and equipment: TTL ICs 74LS08, 74LS32, 74LS86, LEDs, power
supply and
standard experimental setup.

Introduction: A full adder adds two 1-bit binary numbers and an

input carry. When the two
n-bitbinary numbers are to be added, the number of full adders that are to be used are
equal to the number of bits (i.e. n) in each
adder
number.
The LSBs can be added a half using Figure 2: Logic diagram for 2-bit binary ripple adder
or a full adder with the carry
input connected to ground. The carry-out of each adder
is connected to carry-in of the next higher order adder. Such an adder is called as a ripple
adder. In the practical applications, the least
significant stage is also a ful adder. As, the Inputs Output
carry-out of each stage is connected to
carry-in of the next stage, the sum and carry-out B P
bits of any stage cannot be produced until the
carry-in of that stage This is due to occurs. Az A1 32 B1 Cout2 S
propagation delay in the logic circuitry. Thus, greater is the number of bits that a ripple 0 0
carry adder must add, greater is the time required for it to produce valid
addition.
Procedure: The block diagram for 2-bit binary ripple adder is shown in
figure 1, which is
implemented by connecting a half adder and full adder In cascade, half adder being the LSB
adder. The gate level logic diagram Is shown in flgure 2 and the truth table for various O

combinations of inputs A and B is shown in table 1. Using this information, implement the
circuit. For the two 2-bit inputs AA1, and B,B1 obtain the 3-bit final output Cou: S:S: 1
O 0
A B2 As 1

FA
|Cin? Coutl
HA 0

Cout?
Table 1: Truth table for 2-bit ripple adder
Figure 1: Block diagram for 2-bit binary ripple adder

Resut: At the end ofthis lab exercise, one shoud be able to perform addition of any wO

bit numbers using the 2-bit binary ripple adder

Post lab design questions:
1. Can we implement 2-bit subtraction operation using the same circuit? If yes, how?
2. Can we further extend this lab exercise to add 4-bit binary numbers?

Reference: M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall,

2008.
 Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Electronics Lab Manual ABV-IIITM Gwalior

Experiment No. # 6
Title: Implementation of 2x2 bit binary multiplier using logic gates.
B2
Objective: The objective of this lab exercise is to perform multiplication of two 2-bit
numbers. The 2-bit multiplier is to be designed using the AND gates and half adders.

Components and equipment: TTL ICs 74LSO8, 74LS86, LEDs, power supply and standard
experimental setup.
ntroduction: A binary multiplier is used for the multiplication of two binary numbers. The
multiplication of binary numbers is performed in the same way as in decimal numbers. The
HA1
multiplicand is multiplied by each bit of the mutiplier starting from the least significant bit. HA2

Each such mutiplication forms a partial product, successive partial products are shifted one
position to the left. The final product is obtained from the sum of the partial products.
Consider the multiplication of two 2-bit numbers A (multiplicand) and B (multiplier) as
shown in Figure 1. The multiplicand bits are Az and A, the multiplier bits are B2 and B1 and
the product is PaPaP2Pi. Initialy, Bi is multiplied with
As and
Az, generating the partial
product AB: and AzB1. Then Bz is multiplied with As and Az and generates partial product
A:B2 and AzB2 which are shifted by one bit to the left. Then sum of these partial products Figure 1:Block diagram for 2*2 bitbinary multiplier
produces the result of multiplication.

Az A1
B2 B1 P

HALADDER 1
Az B1 A1 B1
P2
Bz
2 Bz A Bz

Pa Par Pa

a Bure 1: 2-bitmultiplication
Procedure: The patial products are implemented with AND gates and the sum is

implemented using half-adders

combinations of 2-bit
shown in the Figure 2. The truth table for the various
as

A and B is
inputs in given table 1. Using this information, implement
the circuit and obtain the 4-bit
multiplication output PaPaPzP1. HALFADDER 2

Figure 2: Logic diagram for 2x2 bit binary multiplier

 Inputs Output
A B P

Az Ai B2 B1 Pa
P Pa P2 P1
0 0
0 0 1 0 0

0 1 0 0
0 1 0 0
0 0

1 1

0 1

1 0 0

0 1 0
0 1 0.
1 0
wwwww
0
0
01 1

Table 1: Truth table for 2-bitmultiplier

Result: At the end of this lab exercise, one should be able to

perform multiplication of any
two 2-bit numbers using the 2-bit binary
multiplier.
Post lab design questions:
1. UseK-map to obtain the expressions for each of the product bits and implement the
same using
basic logic gates T
2. Can we further extend this lab exercise for 3x2 bit binary
multiplication?
Reference: MMorris Mano, "Digital Logic.and Computer Design, Pearson Prentice Hall,
2008.

TMGwalior

Department of Electronics and communication Engineering (Dr. Somesh

Kumar) 24
 Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Electronics Lab Manual ABV-IIITM Gwalior

Experiment No. # 7
Title: Design and Implementation of gray to binary and binary to gray code converters. 1
Objective: The objective of this iab exercise is to design code converters to convert 4-bit
1
binary numbers to 4-bit gray code and vice-versa.

Components and equipment: TTL IC 74LS86, LEDS, power supply and standard
experimental setup.
Introduction: Code convertors are logic circuits whose inputs are bit patterns of one code
and output patterns are representations in a different code. The binary-to-gray code
convertor has binary inputs and it 1
outputs the corresponding
gray code words. The Gray
code is a cyclic code, in which successivecode words differ in one bit position. Hence, it is a

unit distancenumber
code. Another property
of graycode is that the code word corresponding to
(20- 1) for any differsfrom the code word for 0 by 1-bit position. It is
the decimal n

also a reflective code, as the n least significant bits of 2" through (2n1-1) are mirror images
of those for 0 through (2-1). The reason for the popularity of gray codes is the ease of
conversion to and from binary, due to the unit distance difference property.
Procedure: The logic diagram for 4-bit binary-to-gray convertor is shown in
figure 1. The
truth table for various combinations of binary input bits BaBaB2B1 and Table 1: Truth table for 4-bit Binary to Gray code convertor
correspondin8 gray
code bits G4G3G261 is shown in table 1. Using this
information, implement the circuit. The
same table is to be used to implement the 4-bit gray-to-binary convertor shown in figure 2.

G4 B4
B4 G4
B3
G3
G3
B3

B2
G2
G2
B2

G1
ior G1
B1

B1

Figure 2: Logic diagram for 4-bit Gray to Binary code convertor.

Figure 1: Logic diagram for 4-bit
binary to gray code convertor. Result: At the end of this lab exercise, one should be able to convert any 4-01t Dinary
Inputs number to its 4-bit gray code representation and vice-versa.

B4B B
Output
B G G3 G2 G1 Post lab desjgn questions
 put u n D e t o us 4-DIt
gray COde ntatic
represent
B4 Ba B2 B1 G4 G3 G2 G1 Post lab design questions:

1. Can we further extend this lab exercise to implement BCD to bit XS-3 code?
2. How can we design a parity bit generator using XOR gates?

Reference: A. Anand Kumar, "Fundamentals of Digital Circuits", Prentice Hall, 2008.

favaftaHTH sTHH
ITM Gwalior

Department of Electronics and communication Engineering (Dr. Somesh Kumar) 27

 Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Electronics Lab Manual ABV-IIITM Gwalior

Experiment No. # 8 Do

Title: Realization of Adder and Subtractor circuits using Multiplexer.

DI
Objective: The objective of this lab exercise is to perform addition and subtraction of
binary digits using the multiplexer. In this lab exercise we will design and implement Adder
and Subtractor circuits for 2/3-bit arithmetic operation.

Components and equipment: TTL ICs 74LS153, 74LS151, LEDs, power supply and standard
experimental setup.

Introduction: Multiplexer (MUX) is a logic circuit that accepts several data inputs and
allows only one of them to get to the outout in other words, the MUX selects 1-out-of-N
data inputs and transmits the selected data to the single output channel. The digital code
applied to the SELECT inputs decides gets routed to the output. The logic
which input
circuit for basic 4:1 MUX is shown in figure 1 - thas four data inputs namely, Do, Di, Dz, Da
and two select inputs So and S1. The input combination at the select input determines
The Figure 1: togic diagram.tor41MUX
which AND gate gets enabled, so that its data input passes through the OR gate.
function table (shown in table 1) can be used toderive the expression for the output Z as,

ZSSDo +SSoD +S,SoD +S19oDa
Select inputs
is shown in table 2.
Procedure: The truth tables for the adder and subtractor circuit
the function equal to 1.
Connect logic 1 to thedata inputs for which the truth table shows
Output
Connect 0 to rest of the inputs. For example, the input of the half adder is equal to 1,
sum

Z to D1 will get
for the input combination 01. So, when SSo 01, the data input connected half-adder
Do selected. Thus, 1 will be routed to the output. Hence
connect Dito 1.
Implement
two 8:1
Di
and h -subtractor using 4:1 MUX and full-adder and full-subtractor by connecting
D3 and observe the output at the output pin.
MUX ICs. Connect the inputs to the select lines
D4

Table 1: Function table for 4:1 MUX

Loglo.
Logie 1

generation. The MUX can be used in place

One of the applications of MUX is logic function
that it generate
implernents logical éxpression.ft can be so conpected
can
of logic gates to MUX

MUX is that, a single IC can perform a M

any Boolean expression. The advantage of using
function that might require numerous gate Cs.
HTM Gwalior Do

Di MUX
MUX

Logic
Logtc O

Half-subtractor
Half-adder
Rnllsuhtrartor
 Full-adder Full-subtractor
Inputs Outputs Inputs Outputs
OEIC
S Cout A B Bin Bo
Loie 3 Cin
0 0 0 0
D
1

8:1 D 0
MUX MUX

0
Do

1
L

Do Table 2: Truth tables for adder and subtractor circuits

D
D

MUX MUX
Result: We have implemented the adder and subtractor circults using the multiplexer.

Post lab design questions

1. How can we implement full adder and full subtractor using 4:1 MUX?
Logic 0 Logle 0 2. What is a DEMUX?Implement 1:4 DEMUXusingbasicgates.

Full-adder Reference: A. Anand Kumar, "Fundamentals of Digital Circuits", Prentice Hall, 2008.
Full-subtractor

Figure 2: Implementation of adder and subtractor circuits using MUX

Half-adder Half-subtractor

Inputs
B
Outputs nputs Outputs
D B IITM Gwalior
1

Departincnt of Electronics and communication Engineering (Dr. Somsh Kumar) 30 Department of Electronics and communication Engineering (or Soune 31
 Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Electronics Lab Manual ABV-IIITM Gwalior
Experiment No. # 9
clocked flip-flops. Thefigure shows positive edge triggered flip-flops, for which the
Title: Study of sequential circuits and implementation of transition takes place only
Flip-Flops. at the positive going edge
(0 to 1 or LOW to HIGH) of the clock
Objective: The objective of this lab exercise is to pulse. The working of edge triggered S-R flip-flop is similar to that of the latch,
implement the basic sequential circuit except the
element called flip-flop using the logic gates. In this lab Outputs change at the positive edge of the clock. The D flip-flop is constructed
exercise we will design and using an S-R
implement four types of flip-flops namely S-R, J-K, D and T flip-tlop, and the input given at D gets stored in flip-flop at the positive edge. The J-k flip-
flip-flops. flop is similar to the S-R flip-flop, except it has no invalid state. On the other hand when J=1
Components and equipment: TTL ICs 74LS00, 74LS02, 74LS11, 74LS04, LEDs, power supply and K=1, the flip-flop toggles (goes to the
opposite state) at the positive edge of the clock.
and standard
experimental setup. The T flip-flop can be constructed using the JK
flip-flop, by connecting both the inputs
together and labelling it as T. When T-0, it remains in its previous state, but when T=1, it
Introduction: The switching circuits
maybe combinational or sequential circuits. The toggles on every clock pulse.
sequential circuits are those whose
output depends on the present inputs as well on prior
input conditions. Thus, we can say
that the sequential circuits are made up of
combinational circuits and memory
elements. The most important memory element is flip- S-R flip-flop
flop, which is made up of logic gates. Logic gates have no J-K flip-flop
storage capacity by themselves,
but when connected in
arrangements, they can be used to store information. A ilip-flop
can have one or more
inputs and has two outputs, namely Q and Q.Qis the normal state
of the flip-flop and Q is its inverted state.

The simplest type of

flip-flop is called an S-R latch which has two inputs labelled S
and R and two outputs labelled Q and
Q, It can be constructed using two cross coupled
NOR gates as shown in
figure 1. Suppose the latch is initially SET i.e. Q=1 (Q =0) and if S=0
and R-0, the output of first NOR gate Gi is 1 and that of
G2 is 0, so the outputs do not
change. For S=0 and R=1, the output of G is 0, no matter what is the previous state of the
circuit and this in turn makes Q =1. Similarly for S=1 and R=0, Q=1 and Q=0. When S=1 and
D-
R=1, both Q and Q will be 0, thus this state is invalid.

D flip-flop T flip-flop

D-

7, lior
L
Figure 1: S-R latch

Figure 2: Logic diagrams for flip-flops

Fgure 2 shows the logic diagrams for various types of flip-flops using clock sIgnal.
he
e i c t times at which any output, in an synchronous circuits, can change states is called
S clock
signal andflip:tlops which are constructed using the clock signal are called
ectnonies ab Mapnal ARVITM Gralinr
Digital Electronics Lab Manual ABV-1IET MCwalfor

S-R flip-flop J-K flip-flop

Inputs Output Inputs Output

Clock Mode Clock Mode
S R a K
0 Qo No change Qo No change
00
1 Reset 1 Reset
Set 1 Set
Not
1 1 Qo Toggle
allowed

D flip-flop T flip-flop

Input Output Input Output

Clock Mode Clock Mode
D Q Q
T Reset Qo No change
1 Set Qo Toggle

Table 1 Truth tables for flip-tlops

wwww. A w wwwww

Procedure: The diagrams for various edge triggered flip-flops is shown in figure 2.
Implement the same using the logic gates and apply the positive going clock pulse directly
from the kit. For various combinations of inputs, verify the truth tables shown in table 1.

Result: Thus, we
have implemented, the circuits for various types of flip-flops using logiC
gates.

Post lab design questions:

1. What are PRESET AR inputs.How.can you mplement
K flip-flop that has
these inpts?
2. How can we further extend this lab exercise to implement Master-slave flip-flops?
Reference: M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall,
2008.

Department of Electronics and communication Engineering (Dr. Somesh Kumar)

34
 ABV-IIITM Gwalior
Digital Electronics Lab Manual Electronics Lab Manual
ABV-UTM Gwalior Digital
active
that R =
Q4Q2. The flip-flop has
K-map it can be seen
in figure 2. From the
Experiment No. # 10 shown

signal will be Q4Q2.

low clear terminal, so the reset
Title: Design and implementation of asynchronous decade counter.

Objective: The objective of this lab exercise is to design an asynchronous mod-10 counter
After Outputs
using J-K flip-flops.
pulses Qs
Components and equipment: TTL IC 74LS7473, 74LS0O, power supply and standard 0
experimental setup. 1
Introduction: A digital counter is a set of flip-flops whose states change according to the
pulses appied at the input. The flip-flops are so connected that their combined output is

thebinary equivalent of the total number of pulses that have been applied to ittillthat 1
time. A counter can also be used as a frequency divider that gives the waveforms whose
frequencies are specific fractions of clock frequency. Counters may be asynchronous or 1

synchronous. Asynchronous counters are also called as ripple counters in which the flip- 1

flops are not made to change the states at exactly the same time. The clock does not
directly control the time at which each stage changes state. Usually T flip-flops (1-K flip
flops in togele mode) are used to construct such counters. D flip-flops may also be used. 10

Table 1: Count table for decade counter

00

Q2
0

CLK-

Figure 1: Decade counter

decade counter(alsoknown BCDcounter)folows

A as

returns to 0 after the count of 9.Thecounterbeglnsat

a séauence of 10 states
0000 and goestill1001, The state
and
alior
the counter goes to 0000. t has
feedback provided,
after 1001 is1010, but because of the 1. The logic
Procedure: The diagrams for
the decade counter is shown in figure 1.
connected permanently to logic Implement the same
four whose J and K inputs are
flip-flops using -K flip-flops. Apply
the negative going clock pulse directly from the kit to the LSB
designated by Q, with a numeric subscript flip-
four outputs are
diagram is shown in Fig 1. The that the output flop. Use NAND gate for the reset
signal and apply the same to the clear
the BCD code. Note of all the inputs
of the corresponding bit in flip-flops.Verify the count table shown in table 1.
equal to the binary weight flip-flop, Q is appled to the clock
of second
of first Q1 is applied to the clock input
flip-flop for reset is
table is shown in
table 1. The K-map Result: Thus, have
and so on. The count we implemented the asynchronous decade counter using flip-flops.
input of third flip-flop

Department .of13leotono v
 Digital Electronics Lab Manual ABV-IIITM Gwalior

Post lab design questions:

1. Implement 4-bit asynchronous up counter using D flip-flops.

2. Implement 4-bit asynchronous down counter using J-K flip-flops.
Reference: M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall
2008.

ITM Gwalior

Department of Electronics and communication Engineering Dr. Somesh Kumar)

37
Digital Electronics Lab Manual ABV-IIITM Gwalior Digital Electronics
Lab Manual ABV-IIITM Gwalior

Experiment No. #11

Gates
Aim: Write VHDL code (data flow and behavioral modeling) to realize all the gates and Table No. 1: Truth Table for all Logic

implement these gates on FPGA. abC d

1 o 1
Apparatus: Xilinx ISE software, FPGA board, FRC"'s, junmper and power supply. |O 0 0 0 | 1 1
0 1 0 |1 |11 0 1 |0
Explanation:
1 0 0 1 001 0 10
0 0 |1
S.NO GATE SYMBOL NPUTS OUTPUT VHDL Code for all Logic Gates:
A B C

I. NAND IC library 1EEE;

7400
use IEEE.STD_LOGIC_1164.ALL;
entity gates is
NOR Port ( a,b : in std_logic;
7402
c,d,e,f.8.h,i : out std_ogic);
end gates;
architecture data flow of gates is
ANDI C
7408 begin
AB C= a and b;
de=a or b;
e = not a
f= a nand b;
4. OR
IC 1432 a n o r b;
CAB 8
h<=a xor b;
iK= a xnor b;
end data flow;
| NOT
7404
- CA UCF File Format:

6. EX-OR IC NET "a" LOC = "p74" ;

7486
NET "b" LOC = "p75"
C-AB+BA
NET LOC"pa": fyfta4a
NET "d" LOC = "p114";
_i4
NET "e" L0C = "p113";
Gates.
Fig.1: Realization of Logic
all
NET "f" LOC = "p115"

NET"g" LOC-p117TM Gwalior

IT lior NET "h" LOoC =#p118
NET "" LOC = "p121";
LOGIC
Result:
GATES
are simulated,
and NOT gates
All the VHDL codes for AND,
OR, NAND, NOR, EX-OR
correct.
implemented on FPGA & found

for all Gates. Post lab design questions:

Fig. 2: Logic Diagram

ABV-IIITM Gwalior

MUN codo for AND OR NAND NOR. FX-OR and NOT gates in Behavioral style
 Digital Electronics Lab Manual ABV 1ITMGwalior

1. Write a VHDL code for AND, OR, NAND, NOR, EX-OR and NOT gates in Behavioral style
of modeling.
22. Write a VHDL code for AND, OR, NAND, NOR, EX-OR and NOT
gates in Structural style of
modeling.
Reference:
1. M. Morris Mano, "Digital Logic and Computer Design", Pearson Prentice Hall, 2008.
2. Jayaram Bhasker, "A VHDL Primer", Prentice Hal, 3rdedition, 2009.

fagaft4 I-HH
A