June_2022 19EECC203

SRN

IV Semester B.E. Examination

(Electronics and Communication Engineering)
Linear Integrated Circuits(19EECC203)

Duration: 3 hours Max. Marks: 100

Note: i) Answer any TWO full questions from UNIT-I, any TWO full questions from UNIT-II and any ONE full
question from UNIT-III.

UNIT-I
1 a. Fig.Q1a shows the arrangement where M1 and M2 serve as current sources for the
currents 1 and 2. Design the circuit for the power budget of 3mW.

(06marks)
b. The internal circuitry of an op-amp can be simplified to a 1ma current source
charging 5pF capacitor during large signal operation. If an amplifier produces a
sinusoid with a peak amplitude of 0.5V, determine the maximum frequency of
operation that avoids slewing.
(06marks)
c. Assuming λ=0,
calculate the voltage gain
of the topology shown in fig.Q1c.

(08marks)
2 a. Determine the
small signal gain vout/i1
in the circuit shown in fig.Q2a.

(06marks)
Page 1
 b. Define CMRR and derive the same for the basic differential amplifier.
(06marks)
c. For the topology shown in fig.Q2c, all transistors are identical. Neglecting
channel length modulation, calculate the voltage at node N and Y.

(08marks)
3 a. Calculate the differential gain of the circuit shown in fig.Q3a.

(06marks)
b. With a neat circuit diagram derive the equation for the output
resistance of a Wilson current mirror.
(06marks)
c. Calculate the small signal voltage gain of the circuit shown in fig.Q3c.

(08marks)
UNIT-II
4 a. A non-inverting amplifier incorporates an op-amp having an open loop (06marks)
gain of 100 and bandwidth of 1MHz. If the circuit is designed for a
closed loop gain of 16, determine the resulting bandwidth and time
constant.

Page 2
 b. Determine the voltage Vo for the circuit shown in fig.Q4b (06marks)

c. The Z-parameters (08marks)

of the two port feed network shown in
fig.Q4c are Z11=Z22=11KΩ and Z12=Z21=1KΩ.
The op-amp is ideal, calculate the gain of the
amplifier.

5 a. Design a circuit which produces an output voltage vout proportional to (06marks)

the difference of two positive voltages v1 and v2 such that vout=0 when
both the voltages are equal and vout= 10V when v1-v2=1V

b. Identify the circuit shown in fig.Q5b and Derive the transfer function. (06marks)

c. For the circuit shown in fig.Q5c, let vin=8V and select values for R1, (08marks)
R2 and R3 to ensure an output voltage vout=4V

Page 3
6 a. For the circuit shown in (06marks)
fig.Q6a,
determine the deflection of
the ammeter
with a full scale deflection
of 1mA
when the switch is at
X2KΩ.
Consider the resistance of
the
offset voltage
compensating network to
be 10Ω.
b. Derive the equation for the output voltage of an instrumentation (06marks)
amplifier.

c. A signal Vi(t) 10Sin100πt+10Sin400πt+10Sin100000πt (08marks)

is supplied to a filter
circuit shown in fig.Q6c
made up of ideal op-amp.
Calculate the least attenuated component
in the output.

UNIT-III
7 a. With neat circuit diagram explain the working of RC phase shift (10marks)
oscillator and derive equation for the oscillating frequency.

b. Identify the circuit hown in fig.Q7b (10marks)

and explain the function of 100KΩ
resistor in series with two diodes
connected back to back
and determine the frequency of
oscillation.

8 a. With neat block diagram explain the working of SAR ADC. Justify (10marks)
your answer with an example.
b. With neat block diagram explain the working of R-2R DAC and design (10marks)
a 3 bit R-2R DAC with R1=2.5KΩ, Rf=5KΩ and VREF=5V. Assume that the
resistance of the switches are negligible. Determine the value of iTOT for each
digital input and corresponding output voltage vout.

Page 4