EXPT NO: 1 HALF ADDER AND FU ADDER DATE:09/03/2023 AIM: To write VHDL code for Half adder and Full adder. SOFTWARE REQUIRED: ModelSim SE 5.7g / Modelsim PE student edition THEORY: HALF ADDER: A half adder is a digital logic circuit that performs binary addition of two single-bit binary numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output is the least significant bit (LSB) of the result, while the CARRY output is the most significant bit (MSB) of the result. LOGICAL EXPRESSION: Sum = A XOR B = AB+AB" Carry = A AND B = AB CIRCUIT DIAGRAM: TRUTH TABLE: A Input Output B S A B Sum | Carry 0 0 0 0 0 1 lL 0 Cc 1 0 1 0 1 II 0 1FUL DDER: The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) anda carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit “above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. LOGICAL EXPRESSION: s=a XOR b XOR cin cout= (a AND b) OR (a AND cin) OR (b AND cin) CIRCUIT DIAGRAM: TRUTH TABLE: Inputs Outputs A A |B Cin [| Sum | Cout Bs Ss o foo 0 0 Cin 0 foli I 0 oO | 2 | r 0 o (mri 0 1 1 [ofo I 0 Cot [1 [oO [a 0 1 1/ifo 0 1 i f@ti 1 1CONCLUSION: The VHDL code for Half Adder and Full adder was written and implemented successfully.HALF ADD! VHDL code in Dataflow Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use iece.std_logic_unsigned.all; entity halfadder is port(a,b:in std_logic;s,c:out std_logic); end halfadder; architecture halfadder_are of halfadder is begin s<=a xorb; c<=a and b; end halfadder_are; OUTPUT: Testbench for Dataflow Modeling library i use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use iece.std_logie_unsigned.all; entity th_ha is end tb_ha; architecture tb_ha of th_ha is component haifadder port(a,bsin std_logic;s,c: out std_logic); end component; signal a,b: std_logic signal s,c: std_logic; begin add:halfadder port map(a, a<= not a after 10 ps; b<=not b after 5 ps; end tb_ha; lune eta ghee Sikes abo | Saar aanVHDL code in Structural Modeling library ieee; use ieve.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity stre_halfadder is port(a,b: in std_logic; s,c: out std_logic); end stre_halfadder; architecture structure of stre_halfadder is component xor_gate port(a,b:in std_ogic; op: out std_logic); end component; component and_gate port(a,b: in std_Jogie; op: out std_logic); end component; begin xorl: xor_gate port map(a,b.s); andl: and_gate port map(a,b,c): end structure; ouTPUT: Testbench for Structural Modeling library iece; use ieee.std_logic_1164.all; use ieee.std_logic_arithaall; use ieee std_logic_unsignedall; entity struc_th_halfadder is end struc_tb_halfadder; architecture th_halfaddert of struc_th_halfadder is component stre_halfadder port(a,b:in std_Togic's,c: out std_logic); end component; signal a,b: std_logic: signal s,c: std logic; 0%; begin add: stre_halfadder port map(a,b,s,¢); process begin ac='0';b<='0!; wait for 5 ps; ac='ol;be="1'; wait for 5 ps; ac='t';b<='0'; wait for 5 ps; ace!tisbe='t!, wait for 5 ps; end process; end th_halfadders;VHDL code in Behavioral Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bhy_halfadder is port(a,b:in std_logic; s,c:out std_logic); end bhv_halfadder; architecture behavioral of bhy_halfadder is begin process(a,b) begin s<=axorb; c<=aandb; end process; end behavioral; Testbench for Behavioral Mod: library iece; use ieee.std_logic_1164.all; use ieee.std_logic_arithaall; use ieee std_logic_unsignedall; entity bhv_tb_halfadder is, end bhv_th_halfadder; architecture tb_halfadder1 of bhy_tb_halfadder is, component bhv_halfadder port(a,b:in std_Togic;s,c: out std_logic); end component, signal a,b: std_logi signal s, c: std_logic; begin add: bhv_halfadder port map(a,b,s,c); process begin ac='0')b<='0'; wait for 5 ps; acs'ohbe=' wait for 5 ps, acs!tib<='0h; wait for 5 ps; aca't'ppe='t; wait for 5 ps; end process; end th_halfadders; LI 2 Lmlvoe (RR nai bas aa STAFULL ADDER: VHDL code in Dataflow Modeling library ieee; use ieee.std logic 1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fulladder is port(a,b,cin:in std_logic; s,cout: out std_logie); end fulladder; architecture dataflow of fulladder is begin s = axorb xor cin; cout <= ((a and b) or (b and cin) or (cin and a)); end dataflow; OUTPUT: (elven oe Testbench for Dataflow Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use iece.std_logie_unsigned.all; entity th_fa is end tb_fa; architecture tb_df of tb_fa is component fulladder port(a,b,cin: in std_logie;s,cout: out std_logic); end component; signal a,b,cin: std_logic signal s,cout: std_Jogic; begin Fada: fulladder port map(a,b,cin,s,cout); a<= not a after 20 ps; b<=not b after 10 ps; cin<= not cin after 5 ps; end tb_df,VHDL code in Structural Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity struc_fulladder is port(a,b,cin:in std_logic;s,cout:out, std_logic); end struc_fulladder; architecture structural of struc_fulladder is component halfadder port(a,b:in std_logic; s,cout:out std_logic); end component; signal s1,c1,c2:std_logic; begin hal: halfadder port map(a,b,s1,c1); ha2: halfadder port map(s1.,cin,s,c2); cout <= cl or ¢2; end structural; Testbench for Structural Modeling library iece; use ieee.std_logic_1164.all; use ieee.std_logic_arithaall; use ieee std_logic_unsigned all; entity tb_stre_fulladder is end tb_stre_falladder; architecture structural_th of tb_stre_fulladder is component fulladder port(a,b,cin:in std_logic;s,cout: out std_logic); end component; ignal a,b,cin: std_logic:="0'; signal s,cout: std_logic; begin add: fulladder port map(a,b,cin,s,cout);, process begin acz'0'sb<='0';cin: wait for 5 ps; ac='o'sbe='0';eine="14 wait for 5 ps; acs'o'sbe='t';cin<='0'; wait for 5 ps; acz'o'sb<='t';cin wait for 5 ps; acz'1'jb<='o';cin wait for 5 ps; ac='thbe="0';cine='1' wait for 5 ps; acz'1'jbe='t";cin<="0"; wait for 5 ps; ace't'jbe='tcine="1'; wait for 5 ps; end process; end structural_tb;VHDL code in Behavioral Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bhy_fulladder is port(a,b,cin:in std_logic;s,cout:out, std_logic); end bhy_fulladder; architecture behavioural of bhv_fulladder is begin process(a,b,cin) begin s<=a xor b xor cin; cout <= (a and bjor((a xor b)and ein); end process; end behavioural; Testbench for Behavioral Mod library iece; use ieee.std_logic_1164.all; use ieee.std_logic_arithaall; use ieee std_logic_unsigned all; entity tb_bhv_fulladder is end tb_bhv_fulladder; architecture tb_behavioural of tb_bhy_fulladder is component fulladder port(a,b,cin: in std_logic;s,cout:out std_logic); end component; ignal a,b,cin:std_ogic:='0'; signal s,cout: std_logic; begin fadd: fulladder port map(a,b,cin,s,cout); process begin acz'0'sb<='0';cin: wait for 5 ps; ac='o'sbe='0';eine="14 wait for 5 ps; acs'o'sbe='t';cin<='0'; wait for 5 ps; acz'o'sb<='t';cin wait for 5 ps; acz'1';b<='o';cin wait for 5 ps; ac='thbe="0';cine='1' wait for 5 ps; acz'1'jbe='t";cin<="0"; ‘wait for 5 ps; ace't'jbe='tcine="1'; wait for 5 ps; end process; end th_behavioural;