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    17 views8 pages

    FF

    Uploaded by

    Amogha kantak

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
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    EXPT NO: 1 HALF ADDER AND FU ADDER DATE:09/03/2023 AIM: To write VHDL code for Half adder and Full adder. SOFTWARE REQUIRED: ModelSim SE 5.7g / Modelsim PE student edition THEORY: HALF ADDER: A half adder is a digital logic circuit that performs binary addition of two single-bit binary numbers. It has two inputs, A and B, and two outputs, SUM and CARRY. The SUM output is the least significant bit (LSB) of the result, while the CARRY output is the most significant bit (MSB) of the result. LOGICAL EXPRESSION: Sum = A XOR B = AB+AB" Carry = A AND B = AB CIRCUIT DIAGRAM: TRUTH TABLE: A Input Output B S A B Sum | Carry 0 0 0 0 0 1 lL 0 Cc 1 0 1 0 1 II 0 1 FUL DDER: The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) anda carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit “above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. LOGICAL EXPRESSION: s=a XOR b XOR cin cout= (a AND b) OR (a AND cin) OR (b AND cin) CIRCUIT DIAGRAM: TRUTH TABLE: Inputs Outputs A A |B Cin [| Sum | Cout Bs Ss o foo 0 0 Cin 0 foli I 0 oO | 2 | r 0 o (mri 0 1 1 [ofo I 0 Cot [1 [oO [a 0 1 1/ifo 0 1 i f@ti 1 1 CONCLUSION: The VHDL codes for flipflops were written and implemented successfully. D FLIP FLOP: VHDL code in Behavioral Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dff_bhv is port(d,clk:in std_logie;q0,q:out std_logic); end dff_bhy; architecture behaviour of ‘dff_bhv is signal ql:std_logic: begin process(d,clk) begin if (clk ‘event and clk ='1') then if(d='0") then qi<=0'; elsif(d = '1') then qi<="I'; end if end if; end process; q0<=q1; <= not ql; end behaviour; OUTPUT: Testbench for Behavioral Modeling library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use iece.std_logic_unsigned.all; entity th_dff_bhy is end tb_dif' bhy; architecture tb_bhv of th_dff_bhy is component dif bhy port(d,clk:in std_logie;q0,q:out std_logic); end component; signal d,clk:std_logie signal q0,q:std_logic; begin dif : dff_bhv port map(d,clk,q0.9); clk <= not clk after 12.5 ns; d

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