SRM Institute of Science and Technology

College of Engineering and Technology

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MINI PROJECT REPORT

EVEN Semester, 2022-2023

Sub code & Sub Name : 18ECE206J & Advanced Digital System Design

Year & Semester : 2nd & 4th

Mini Project Title : FINITE STATE MACHINE

Course In charge : MRS.D.Vijayalakshmi

Registration number : RA2111004010001(SAPTHAGIRISH)

AND RA2111004010006(GANESHA SAI VARMA)
RA2111004010008(SURENDRA)
Name of the students :

Particulars Max. Marks Reg No. Reg No. Reg No.

Miniproject 15
Report 05
Total 20

REPORT VERIFICATION

Staff Name : MRS.D.Vijayalakshmi

Signature :

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 FINITE STATE MACHINE

OBJECTIVE:
Purpose of this project is to implement a finite state machine.

ABSTRACT:
FSM (Finite State Machines) is a simple state machine or a mathematical model of
computation.  Each FSM has a finite number of states, inputs, outputs, and rules to change from one state to
the other state. FSM is defined by a finite number of states and switches from one state to the other when
specific input is given to the state machine. FSM’s are widely used in vending machines, traffic lights,
security locks, and software algorithms.  In this article, you can learn about the basics of FSM and
implementing an FSM design in VHDL using ModelSim.

FSM DIAGRAM:

The green circles indicate the states of the FSM. So, the available states are A, B, C, D. The   near the
state circle A indicates that ‘A’ is the initial state. The double circled state, D indicates that D is the last state of
the FSM. We can see that arrows are running between the available states with 1’s and 0’s. These are the inputs
and outputs that determine where the next state should shift to and the corresponding outputs.

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Always remember that these arrows form the rule for transition.  The notations above the arrows left side of the
slash represent input, right side to slash represent the output. For example, if it is “1/0” 1 represents input, and 0
represents output.

FSM’s have a state transition table from which we can calculate the next state. The Transition Table is given
below.

Let us examine the State Transition Table and the State Diagram for a better understanding. If the present state
is A and the input is “1”, look for the arrows pointing outwards of state A which has input “1”. If so, the next
state is B and the output is 0. Now, the present state gets updated as “B”. Now lookup for the present state “B”,
says input is 0 the next state is “D”. So on, the state keeps changing.

Moreover, FSM has a clock and reset signal too. If the reset =1 or reset is active, it will go back to the initial
state which is “A” (i.e. starting state)

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Now, that we know the basics of FSM, let's implement the same design in VHDL using ModelSim.

Brace yourself let's learn how to implement the same design in VHDL using ModelSim .

SOFTWARE REQUIREMENTS:

Xilinx ISE 7.1i

ModelSim-Altera 6.4A

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fsm is

    Port ( reset : in  STD_LOGIC;

           input : in  STD_LOGIC;

           output : out  STD_LOGIC;

           clk : in  STD_LOGIC);

end fsm;

architecture Behavioral of fsm is

type state_available is (A,B,C,D);  --type of state machine.

signal present_state,next_state: state_available;

begin

process (clk,reset)

begin

 if (reset='1') then

  present_state <= A;  --default state on reset.

elsif (rising_edge(clk)) then

  present_state <= next_state;   --state change.

end if;

end process;

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process (present_state,input)

begin

  case present_state is

     when A =>        --when current state is "A"

     if(input ='0') then

      output <= '1';

      next_state <= C;

    else

      output <= '0';

      next_state <= B;

     end if;   

     when B =>        --when current state is "B"

    if(input ='0') then

      output <= '0';

      next_state <= D;

    else

      output <= '1';

      next_state <= B;

    end if;

    when C =>       --when current state is "C"

    if(input ='0') then

      output <= '1';

      next_state <= D;

    else

      output <= '1';

      next_state <= C;

    end if;

  when D =>         --when current state is "D"

    if(input ='0') then

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      output <= '1';

      next_state <= A;

    else

      output <= '0';

      next_state <= D;

    end if;

  end case;

end process;

end Behavioral;

OUTPUT:
(output screen shot with name and reg.no )

CONCLUSION:

Finite State Machine was designed and simulated using VHDL code

REFERENCES:
https://circuitdigest.com/microcontroller-projects/implementing-finite-state-machine-design-in-

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vhdl-using-modelsim