3D Analog Front End: Migrating From TMS37122 and TMS37127 To TMS37126D3

Application Report
SCBA032 – August 2012
3D Analog Front End: Migrating From TMS37122 and

TMS37127 to TMS37126D3
Siegfried Langner .............................................................................................................................
ABSTRACT
The TMS37122, TMS37127 and TMS37126 devices belong to the Passive Entry and Passive Start
(PEPS) product family used mainly for automotive applications. These devices are also usable in industrial
applications for similar functionality.
Since the TMS37122 and TMS37127 devices are becoming obsolete, this application report describes
how to migrate to the TMS37126D3 device as a replacement.
Contents
1 Introduction .................................................................................................................. 1
2 Comparison Overview ...................................................................................................... 2
List of Figures
1 Pin Assignment Comparison .............................................................................................. 2
2 TMS37122 and 127 Wakeup Without Wake Pattern ................................................................... 4
3 126 Wakeup Without Wake Pattern ...................................................................................... 4
4 Wakeup With 8-Bit Wake Pattern (1010 1010) LS-bit First ........................................................... 5
5 TMS37122 (5 Nibbles, 3 Rows) ........................................................................................... 5
6 TMS37127 (5 Nibbles, 4 Rows) ........................................................................................... 6
7 TMS37126 (5 Bytes, 3 Rows) ............................................................................................. 6
8 Schematic TMS37122 and TMS37127................................................................................... 7
9 Test Interface Pin Assignment TMS37122 and TMS37127 (4 V Level) ............................................ 7
10 Replacement Schematic for TMS37122 and TMS37127 .............................................................. 8
11 Test Interface Pin Assignment TMS37126 (5 V Level) ................................................................ 8
12 Function Definition Byte B ................................................................................................ 9
List of Tables
1 Comparison Table .......................................................................................................... 2
1 Introduction
The IC consists basically of a three dimensional analog frontend with internal Wake Pattern detection; two
16-bit wake patterns can be freely programmed and a sensitivity threshold assigned for each pattern.
In standby mode, all three channels are active and waiting for an RF field containing the specific
programmed wake pattern. During this phase, the current consumption of the analog frontend is extremely
low and the microcontroller can be put in low-power mode to extend battery life.
The reception of a correct wake pattern is indicated by the wake signal that wakes up the microcontroller
for further communications.
From a functional standpoint, the TMS37126D3 device is a superset of the TMS37122 and TMS37127
devices, but with additional features.
All trademarks are the property of their respective owners.
SCBA032 – August 2012 3D Analog Front End: Migrating From TMS37122 and TMS37127 to 1
Submit Documentation Feedback TMS37126D3
Copyright © 2012, Texas Instruments Incorporated
Comparison Overview www.ti.com
2 Comparison Overview
Table 1. Comparison Table

Parameter and Function Unit TMS37122 TMS37127 TMS37126D3 Compatibility
Embedded passive TRP
by Micro by Micro yes
functionality
Number of RF inputs
No. 3 3 3 √
(antennas)
Antenna inductance (PEPS) [mH] 2.66 to 10 2.66 to 10 2.66 to 10 √
Antenna inductance ( TRP) [mH] 2.66 2.66 4.6 and 7.2 no
Sensitivity [mVpp] 5 5 3.7 √√
Wake pattern No. A and B A and B A and B √
Wake pattern length [bit] 16 4, 8, 16 4, 8, 16 no
Adjustable sensitivity steps No. 16 16 32 √√
Watch dog selectable - yes yes √
Standby current [μA] 5 5 3.8 √√
RSSI (current sink) no no yes no
Programmer RI-ACC-PBOX-20 RI-ACC-PBOX-20 PTB2 no
Internal
Test interface EEPROM
[V] 16 16 Charge no
programming voltage
Pump
TSSOP 16 TSSOP 16 TSSOP 30
Package no
pitch0.65mm pitch0.65mm pitch0.5mm
SPI no no yes -
2.1 Pin Assignment

The gray pins are additional signals that are available on the TMS37126 device.
TSSOP 30 TSSOP 16
1 TDAT TCLK 30 1 GND VCL

2 TEN RF1 29 2 VCCO RF1
3 RF2 VCL 28 3 RF3 RF2
4 nc nc 27 4 TDAT TCLK
5 NPOR AMMOD 26 5 TEN MOD
6 RF3 GND 25 6 VBAT TX
7 VCC_CU RSSI 24 7 EOBA WDEEN
8 WDEEN WAKE 23 8 CLKA/M WAKE
9 VBAT BUSY 22
10 VBATI EOBA 21 TMS37122/127
11 nc CLKA/M 20
12 nc nc 19
13 nc SPI_SIMO 18
14 MOD SPI_SOMI 17
15 TX SPI_CLK 16
TMS37126
Figure 1. Pin Assignment Comparison
2 3D Analog Front End: Migrating From TMS37122 and TMS37127 to SCBA032 – August 2012
TMS37126D3 Submit Documentation Feedback
www.ti.com Comparison Overview
2.2 SPI Interface Signals

The TMS37126x devices have an SPI interface for accessing EEPROM memory as well as for using
different functionalities like hardware (HW) encryption or the block check character (BCC) generator.
If the SPI interface is not used, the clock input should be connected to GND in order to avoid spurious
clock pulses (for example, electrostatic discharge).
2.3 Programmer Box

The TMS122 and TMS37127 programmer box cannot be used for TMS37126x. Since the TMS37126 is
equipped with an internal charge pump to program the EEPROM cells, the test interface needs 5 V signal
levels. Probe test box (PTB or PTB2) is used for programming.
2.4 Watchdog
The TMS37127 and TMS37126x both have an integrated watchdog that can be enabled by the
configuration registers. The watchdog is not available in the TMS37122 device.
In case the device operates without Wake Pattern detection, the watchdog resets the device if no clock is
received by the RF inputs.
2.5 Wake Pattern

The TMS37126x can be configured for a 4-, 8-, or 16-bit Wake Pattern.
2.6 Wakeup Without Wake Pattern Detection

The front end can be configured to operate with or without Wake Pattern detection.
2.6.1 TMS37122 and TMS37127

If a continuous carrier is present for about 2 ms to 5 ms, the device will wake up and set the Wake output
to high (see Figure 2).
A The EOBA signal (blue trace) is the demodulated LF signal.

Figure 2. TMS37122 and 127 Wakeup Without Wake Pattern
2.6.2 TMS37126
In the TMS37126 device, the wake output is only set high if the continuous LF carrier is switched off and
on again (see Figure 3).
Figure 3. 126 Wakeup Without Wake Pattern
2.7 Wakeup With Wake Pattern Detection

If the Wake pattern detection is enabled, the behavior of the TMS37126 device is identical to the
TMS37122 and TMS37127 devices (see Figure 4).
Figure 4. Wakeup With 8-Bit Wake Pattern (1010 1010) LS-bit First
2.8 Configuration Memory

Since the TMS37122 and TMS37127 devices have different configurable features, the configuration
memory contains an additional row. One row consists of five Nibbles. The TMS37126 device has 5 bytes
per row.
2.8.1 TMS37122 (5 Nibbles, 3 Rows)

Figure 5 shows the memory configuration of the TMS37122 device.
NIBBLE
4 3 2 1 0
Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0
NO NO NO NO
CLKA WIDE3 WIDE2 WAKE PPM THRESHOLD VWAKE B/ 2/3 VWAKE B/ 1 VWAKE A/ 1
0
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C_TELEGR PASSIVE ENTRY WAKE PATTERN
1 ROW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C_WAIT PASSIVE START WAKE PATTERN
2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 3 Bit 0 Bit 15 Bit 0
Figure 5. TMS37122 (5 Nibbles, 3 Rows)
2.8.2 TMS37127 (5 Nibbles, 4 Rows)

Figure 6 shows the memory configuration of the TMS37127 device. The TMS37127 has one more row for
configuration than the additional features.
NIBBLE
4 3 2 1 0
Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0 Bit 3 Bit 0
NO NO NO NO
CLKA WIDE3 WIDE2 WAKE
PPM THRESHOLD VWAKE B/ 2/3 VWAKE B/ 1 VWAKE A/ 1 0
C_TELEGR PASSIVE ENTRY WAKE PATTERN 1 ROW
C_WAIT PASSIVE START WAKE PATTERN 2
VWAKE WDG
SINGLE ON
BIT_NO. VWAKE B/ 3 VWAKE B/ 2 VWAKE A/ 3 VWAKE A/ 2 3
Bit 3 Bit 0 Bit 15 Bit 0
Figure 6. TMS37127 (5 Nibbles, 4 Rows)
2.8.3 TMS37126 (5 Bytes, 3 Rows)

Figure 7 shows the memory configuration of the TMS37126 device. The configuration is byte wise
organized in comparison to the TMS37122 and TMS37127. Note that the TMS37122 and TMS37127
programmers cannot be used for the TMS37126 device (also see Section 2.3).
BYTE 4 BYTE 3 BYTE 2 BYTE 1 BYTE 0
AFE FUNCTION AFE FUNCTION

ROW 0 INTERNAL USE AFE CNTR DEF
DEFINITION B DEFINITION A
ROW 1 VWAKE A1 VWAKE A2 VWAKE A3 PE WAKE PATTERN PE WAKE PATTERN
ROW 2 VWAKE B1 VWAKE B2 VWAKE B3 PS WAKE PATTERN PS WAKE PATTERN
Figure 7. TMS37126 (5 Bytes, 3 Rows)
2.9 Principle Schematic TMS37122 and TMS37127

Figure 8 shows the principle schematic for the wake-up receiver. For details, see the device-specific
reference manual: Spec# 11-07-21-002.
VCC
L3 L2 L1
C2 C3 C4
IC2
1 16
GND VCL
2 VCC0 RF1 15
3 14
RF3 RF2
4 TDAT TCLK 13
TDAT TCLK
5 12
TEN TEN MOD
6 11
VBAT TX
7 10
EOBA EOBA WDEEN WDEEN
8 CLKA/M WAKE 9
WAKE
CBAT
TMS3712x CL
GND GND GND GND
Figure 8. Schematic TMS37122 and TMS37127
2.9.1 Programmer Box Signal Connections (TMS37122 and TMS37127)

For configuration and resonance tuning (tuning capacitor programming) of the TMS37122 and TMS37127,
the tool RI-ACC-PBOX-20 is used. The programmer supports all necessary signals with a 4 V level and
provides the 16 V EEPROM programming voltage at the TEN input.
Test Interface
CON1
VCL 1 2 TDAT
TCLK 3 4 TEN
WDEEN 5 6 VBAT
SPARE1 7 8 GND
(2x4pin)
Figure 9. Test Interface Pin Assignment TMS37122 and TMS37127 (4 V Level)
For programming the EEPROM cells at the end of the telegram, the TEN signal is switched to 16 V during
programming time.
2.10 Principle Replacement Schematic

Figure 10 shows the principle schematic for the wake-up receiver. For details, see the device-specific
reference manual: Spec# 11-09-21-046
3V
L2 L3 L1
C2 C3 C1
TMS37126
TDAT 1 30
TDAT TCLK TCLK
2 TEN RF1 29
TEN
3 28
RF2 VCL
4 NPOR 27
AM_MOD
5 26
RF3 GND
6 25
VCC_CU RSSI
7 24
WDEEN WDEEN WAKE WAKE
8 VBAT BUSY 23
9 22
VBati VBATI EOBA EOBA
10 21
NC1 CLKA/M
11 20
CL2 NC2 NC6
12 NC3 19
NC5
13 18
NC4 SPI_SIMO
14 17
MOD SPI_SOMI
15 TX 16
SPI_CLK
CBAT
RAID
CL
GND GND GND GND GND
Figure 10. Replacement Schematic for TMS37122 and TMS37127
2.10.1 Programmer Board Signal Connections (TMS37126)

For configuration and resonance tuning (tuning capacitor programming) of the TMS37126, the tool RI-
ACC-PTB2-00 is used. The programmer supports all necessary signals with a 5 V level. The EEPROM
programming voltage is provided internal to the IC.
Test Interface
CON1
VCL 1 2 TDAT
TCLK 3 4 TEN
WDEEN 5 6 VBAT
SPARE1 7 8 GND
(2x4pin)
Figure 11. Test Interface Pin Assignment TMS37126 (5 V Level)
2.10.2 Function Definition Byte B

Figure 12 shows the content of the Function Definition Byte B located in the Memory Block 2 Byte 1.
BIT 7 BIT 6 BIT 5 BIT 4 Bit 3 BIT 2 BIT 1 BIT 0
NOT USED VAR. tWRX ON NO_BACKUP NO_IMMOB BWM THRESHOLD
DEFAULT = 0 DEFAULT = 0 DEFAULT = 0 DEFAULT = 0 DEFAULT = 0111
NOT AVAILABLE IN TMS37122
Figure 12. Function Definition Byte B
2.11 3D Antenna
Connect the 3D antenna in such a way as to have the lowest mutual coupling between the three channels.
To accomplish that, contact the antenna supplier or test it by interchanging the winding sense. An
indication for high coupling is when the resonance of the already tuned channel is changed after tuning
one of the other channels.
2.12 ESD
For a higher ESD immunity additional ESD protection diodes must be added.
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3D Analog Front End: Migrating From TMS37122 and TMS37127 To TMS37126D3

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Application Report

SCBA032 – August 2012

3D Analog Front End: Migrating From TMS37122 and

Table 1. Comparison Table

2.1 Pin Assignment

1 TDAT TCLK 30 1 GND VCL

Figure 1. Pin Assignment Comparison

2.2 SPI Interface Signals

2.3 Programmer Box

2.5 Wake Pattern

2.6 Wakeup Without Wake Pattern Detection

2.6.1 TMS37122 and TMS37127

A The EOBA signal (blue trace) is the demodulated LF signal.

Figure 3. 126 Wakeup Without Wake Pattern

2.7 Wakeup With Wake Pattern Detection

2.8 Configuration Memory

2.8.1 TMS37122 (5 Nibbles, 3 Rows)

Bit 3 Bit 0 Bit 15 Bit 0

Figure 5. TMS37122 (5 Nibbles, 3 Rows)

2.8.2 TMS37127 (5 Nibbles, 4 Rows)

C_TELEGR PASSIVE ENTRY WAKE PATTERN 1 ROW

C_WAIT PASSIVE START WAKE PATTERN 2

Bit 3 Bit 0 Bit 15 Bit 0

Figure 6. TMS37127 (5 Nibbles, 4 Rows)

2.8.3 TMS37126 (5 Bytes, 3 Rows)

AFE FUNCTION AFE FUNCTION

ROW 1 VWAKE A1 VWAKE A2 VWAKE A3 PE WAKE PATTERN PE WAKE PATTERN

ROW 2 VWAKE B1 VWAKE B2 VWAKE B3 PS WAKE PATTERN PS WAKE PATTERN

Figure 7. TMS37126 (5 Bytes, 3 Rows)

2.9 Principle Schematic TMS37122 and TMS37127

GND GND GND GND

Figure 8. Schematic TMS37122 and TMS37127

2.9.1 Programmer Box Signal Connections (TMS37122 and TMS37127)

Figure 9. Test Interface Pin Assignment TMS37122 and TMS37127 (4 V Level)

2.10 Principle Replacement Schematic

GND GND GND GND GND

Figure 10. Replacement Schematic for TMS37122 and TMS37127

2.10.1 Programmer Board Signal Connections (TMS37126)

Figure 11. Test Interface Pin Assignment TMS37126 (5 V Level)

2.10.2 Function Definition Byte B

DEFAULT = 0 DEFAULT = 0 DEFAULT = 0 DEFAULT = 0 DEFAULT = 0111

NOT AVAILABLE IN TMS37122

Figure 12. Function Definition Byte B

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