U20EC090 EC: 304 DIC 2023

EXPERIMENT: 5

AIM: Implement TTL inverter using NPN BJT having Bf=18,

Rb=10k, Rc=9k.
a) Verify its functionality by performing transient analysis.
b) Plot VTC and calculate noise margin , transition width, total swing.
c) Find theoretical and practical fan out and compare them.
SOFTWARE: Ng spice
THEORY: TTL – Inverter:
With the rapid development of integrated circuits (IC’s), new problems were encountered
and new solutions were developed. One of the problems with DTL circuits was that it takes
as much room on the IC chip to construct a diode as it does to construct a transistor. But
what could be used to replace many diodes? Well, looking at the DTL NAND gate, we
might note that the opposed diodes look pretty much like the two junctions of a transistor.
In fact, if we were to have an inverter, it would have a single input diode, and we just might
be able to replace the two opposed diodes with an NPN transistor to do the same job.

The figure shows the resulting inverter. In addition, we can add multiple emitters to the
input transistor without greatly increasing the amount of space needed on the chip. This
allows us to construct a multiple-input gate in almost the same space as an inverter. One
problem shared by all logic gates with a single output transistor and a pull-up collector
resistor is switching speed. The transistor actively pulls the output down to logic 0, but the
resistor is not active in pulling the output up to logic 1. The use of a common emitter output
stage provides fast discharging of load capacitance but rather slow the charging process. On
the other hand, the use of an emitter follower output stage does the opposite.

Schematic Diagram :

Digital Integrated Circuit Rahul Jadav

 U20EC090 EC: 304 DIC 2023
CODE:
Transient Analysis for Functionality test :

Transistor Transistor Logic

*TTL Inverter
.model mod_90 npn(BF=18)

Vcc 1 gnd 5
*Vin ip gnd 5
Vin ip gnd PULSE(0 5 10us 1ns 1ns 10us 20us)
Rb 1 base1 10k
Rc 1 op 9k
Q1 base2 base1 ip mod_90
Q2 op base2 gnd mod_90

.tran 1us 40us

.control
run
plot V(op) V(ip)
set hcopydevtype=postscript
hardcopy ttl_func.ps V(op) V(ip)
.endc
.end

DC Analysis for VTC Curve :

TTL Inverter
.model mod_90 npn(BF=18)

Vcc 1 gnd 5
Vin ip gnd 5
Rb 1 base1 10k
Rc 1 op 9k
Q1 base2 base1 ip mod_90
Q2 op base2 gnd mod_90

.dc Vin 0 5 0.01

.control
run
plot V(op) V(ip)
set hcopydevtype=postscript
hardcopy ttl_vtc.ps V(op) V(ip)
.endc
.end

Digital Integrated Circuit Rahul Jadav

U20EC090 EC: 304 DIC 2023
DC Analysis for Practical Fan-out:
TTL Inverter
.model mod_90 npn (Bf=18)

Vcc 5 0 5
Vin 1 0 5
Rb 5 2 10k
Rc 5 4 9k
Q1 3 2 1 mod_90
Q2 4 3 0 mod_90

.subckt TTL_INV out in Vs gnd

rbs Vs b1 10k
rcs Vs out 9k
qs1 b2 b1 in mod_90
qs2 out b2 0 mod_90
.ends

x1 out1 4 5 0 TTL_INV
x2 out2 4 5 0 TTL_INV
x3 out3 4 5 0 TTL_INV
x4 out4 4 5 0 TTL_INV
.
.
Upto 38

x39 out39 4 5 0 TTL_INV

x40 out40 4 5 0 TTL_INV
* x41 out41 4 5 0 TTL_INV
* x42 out42 4 5 0 TTL_INV
* x43 out43 4 5 0 TTL_INV
* x44 out44 4 5 0 TTL_INV
* x45 out45 4 5 0 TTL_INV
* x46 out46 4 5 0 TTL_INV
* x47 out47 4 5 0 TTL_INV

.dc Vin 0 5 0.01

.control
run
plot V(4) V(1)
set hcopydevtype=postscript
hardcopy ttl_fanout.ps V(4) V(1)
.endc
.end

Digital Integrated Circuit Rahul Jadav

 U20EC090 EC: 304 DIC 2023
OUTPUT :
Transient Analysis for Functionality test :

DC Analysis for VTC Curve :

Digital Integrated Circuit Rahul Jadav

 U20EC090 EC: 304 DIC 2023
DC Analysis for Practical Fan-out:

CALCULATION :

Digital Integrated Circuit Rahul Jadav

U20EC090 EC: 304 DIC 2023

Digital Integrated Circuit Rahul Jadav

 U20EC090 EC: 304 DIC 2023
CONCLUSION : After Performing this experiment, we checked the functionality of TTL invertor, and found
All VTC parameters. We observed that TTL has high noise margin compare to RTL because
of less VOL.TTL has high Fan-out compare to RTL too.

SIGNATURE

Digital Integrated Circuit Rahul Jadav