EGEE-406 Design Applications with Microcontroller and FPGA

Final Project, Spring Semester 2023

Due at 23:59 on April 30, 2023

1. Follow the steps of "EGEE406 Project4 SOC part1.pdf" and "EGEE406 Project4 SOC
part2.pdf" to generate the Project of MicroBlaze with UART and memory components.
2. Add some IP components, which can be provided by Xilinx Vivado or created by yourself, to
the Project of MicroBlaze. with or without UART and memory components. That means if your
project needs UART or memory components, you can keep them. If your project does not
need UART or memory component, you can remove them.
3. Write a detailed project report and save it in pdf format. A project report template is shown in
the project documentation below.
4. Take a short video to explain the implementation results. Save the video in mp4 format.
5. Submit the document file (pdf file) and video file (mp4 file) to Canvas before the deadline.

Project Documentation:
1. Cover page including university name, department name, course name, project title, student
ID, student name, instructor name and date.
2. Introduction
discuss the Vivado block design and MicroBlaze CPU.
3. Project function
a) Project block diagram and entire circuit (Take a window shot of the block diagram window)
discuss the functionality of the entire block diagram
b) Each block, circuit, and component
discuss the functionality of each block, circuit, and component
4. VHDL code and C code
list entire VHDL code and C code with comments.
5. Verification
Attach some pictures with explanation. Upload a short video for verification.
6. Conclusion