Introduction

• Edge detection includes a variety of mathematical methods that aim at identifying edges and
curves in a digital image at which the image brightness changes sharply or, more formally,
has discontinuities.
• The same problem of finding discontinuities in one-dimensional signals is known as step

Edge Detection Algorithms detection and the problem of finding signal discontinuities over time is known as change
detection.
• Edge detection is a fundamental tool in image processing, machine vision and computer vision,
particularly in the areas of feature detection and feature extraction.
Dr Arunachalam V
Associate Professor, SENSE

Purpose & Significant of Edge Detection Viewpoint dependency on Edges’ Properties

• The result of applying an edge detector to an image may lead to a set of connected curves that
indicate as follows: • The edges extracted from a 2-D image of a 3-D scene can be classified as either viewpoint-
• The boundaries of objects, dependent or viewpoint-independent.
• The boundaries of surface markings as well as curves that correspond to discontinuities in surface
• A viewpoint-independent edge typically reflects inherent properties of the three-dimensional
orientation.
objects, such as surface markings and surface shape.
• Applying an edge detection algorithm to an image may significantly reduce the amount of data to
• A viewpoint-dependent edge may change as the viewpoint changes and typically reflects the
be processed and filter out information that may be regarded as less relevant while preserving the
scene’s geometry, such as objects overlapping with one another object.
important structural properties of an image.
• If the edge detection step succeeds, the subsequent task of interpreting the information contents in
the original image may be substantially simplified.
• However, it is not always possible to obtain such ideal edges from real time images of moderate
complexity.
Types of Edges Applications of Edge detection
• Edges are significant local changes of intensity in a digital image. • Edge Detection is a method of segmenting an image into regions of discontinuity.
• An edge can be defined as a set of connected pixels that forms a boundary between two disjoint • It is a widely used technique in digital image processing like
regions. • Pattern recognition
• There are three types of edges: • Image morphology
• Horizontal edges • Feature extraction
• Vertical edges
• Diagonal edges

Edge Detection Operators

Sobel Edge Detector
• Edge Detection Operators are of two types:
• Gradient-based operator which computes first-order derivations in a digital image. • It is a discrete differentiation gradient-based operator.

• Examples: Sobel operator, Prewitt operator, Robert operator • It computes the gradient approximation of the image intensity function for image edge detection.

• Gaussian-based operator which computes second-order derivations in a digital image. • It uses two 3 × 3 kernels/convolution masks, which are convolved with the input image to
calculate the vertical (𝑆𝑥 ) and horizontal (𝑆𝑦 ) derivative approximations.
• Examples: Canny edge detector, Laplacian of Gaussian
−1 0 +1 +1 +2 +1
• 𝑆𝑥 = −2 0 +2 𝑆𝑦 = 0 0 0
−1 0 +1 −1 −2 −1

• Magnitude of the gradient is , M = 𝑆𝑥2 + 𝑆𝑦2

Steps Involved in Sobel Operation A working example of Sobel filter
• Suppose we have the same 5*5 image.
• The Sobel algorithm can be summarized in four steps: i.j 1 2 3 4 5
1. Converting the image into grayscale • Use zero padding on the input image.
1 0 0 10 10 10
2. Convolving the gray image, calculate using 𝑆𝑥 • To maintain size at the output stage. 2 0 0 10 10 10
3. Convolving the gray image , calculate using 𝑆𝑦 0 0 0 −1 0 +1 3 0 0 10 10 10
• 𝑆1 = 𝐼1,1 ∗ 𝑠𝑥 = 0 𝟎 0 ∗ −2 0 +2 = 0
4. Calculating the gradient magnitude, M 4 0 0 10 10 10
0 0 0 −1 0 +1
0 0 0 −1 0 +1 5 0 0 10 10 10
• 𝑆1 = 𝐼0,1 ∗ 𝑠𝑥 = 𝐼0,1 ∗ 𝑠𝑥 = 0 𝟎 10 ∗ −2 0 +2 = 30
0 0 10 −1 0 +1 i.j 1 2 3 4 5
10 10 10 +1 +2 +1 1 0 30
• 𝑆3 = 𝐼3,4 ∗ 𝑆𝑦 = 10 𝟏𝟎 10 ∗ 0 0 0 =0 2
10 10 10 −1 −2 −1
3 0
0 10 10 +1 +2 +1
• 𝑆4 = 𝐼4,3 ∗ 𝑆𝑦 = 0 𝟏𝟎 10 ∗ 0 0 0 =0 4 0
0 10 10 −1 −2 −1 5

A working example of Sobel filter A working example of Sobel filter

• The gradient in x direction, (𝑆𝑥 ) using filter 𝑠𝑥 • 𝑆𝑥 i.j 1 2 3 4 5 𝑆𝑦 i.j 1 2 3 4 5
1 0 -10 -30 -40 -30
i.j 1 2 3 4 5 1 0 30 30 0 -30
2 0 0 0 0 0
1 0 30 30 0 -30 2 0 40 40 0 -40
3 0 0 0 0 0
2 0 40 40 0 -40 3 0 40 40 0 -40
4 0 0 0 0 0
3 0 40 40 0 -40 4 0 40 40 0 -40
5 0 10 30 40 30
4 0 40 40 0 -40 5 0 30 30 0 -30

5 0 30 30 0 -30

• The gradient in x direction, (𝑆𝑥 ) using filter 𝑠𝑥 • Calculate the gradient Magnitude = 𝑆𝑥 2 + 𝑆𝑦 2

i.j 1 2 3 4 5 i.j 1 2 3 4 5 The pixels, (1,2), (2,2), (3,2), (4,2) and (5,2) are
1 0 -10 -30 -40 -30 1 0 31.62 42.43 40 42.43 larger values than (1,1), (2,1), (3,1), (4,1) and
2 0 0 0 0 0 2 0 40 40 0 40 (5,1) therefore (1,2), (2,2), (3,2), (4,2) and (5,2)
3 0 0 0 0 0 3 0 40 40 0 40 are the edge pixels.
4 0 0 0 0 0 4 0 40 40 0 40

5 0 10 30 40 30 5 0 31.62 42.43 40 42.43

 𝑆𝑥 1 2 3 4 5
I 1 2 3 4 5
1 -4 -30 0 -30 4
Sobel Edge Detection
1 0 2 15 0 0
2 -12 -31 -115 -328 127 Advantages:
2 0 0 0 4 60
3 -34 -202 -463 -591 497 1. Simple and time-efficient computation
3 0 10 16 119 238
4 -136 -611 -748 -393 884 2. Very easy at searching for smooth edges
4 0 14 170 255 255
5 -210 -680 -555 -85 765
5 0 98 255 255 255 Limitations:

𝑆𝑦 1 2 3 4 5 1. Diagonal direction points are not preserved always

1 0 0 -4 -68 -124 2. Highly sensitive to noise
𝑀 1 2 3 4 5
2 -8 -17 -129 -478 -597 3. Not very accurate in edge detection
1 4 30 4 74 124
-14 4. Detect with thick and rough edges does not give appropriate results
2 14 35 172 579 610 3 -198 -605 -867 -641
3 36 282 761 1049 811
4 -88 -415 -702 -527 -168
4 162 738 1025 657 899
5 14 198 609 935 765
5 210 708 824 938 1081

References
• Canny Edge Detector (justin-liang.com)
• Sobel Edge Filter. We can think of an image, which is… | by Shailesh
Kumpawat | Analytics Vidhya | Medium
• Week 4: Image Filtering and Edge Detection (sbme-tutorials.github.io)
• Canny edge detector – Wikipedia Sobel edge detection - IP
• MATLAB - Image Edge Detection using Sobel Operator from Scratch -
GeeksforGeeks Dr Arunachalam V
Associate Professor, SENSE
Image Smoothening 𝑆𝑦 1 2 3 4 5
I 1 2 3 4 5 𝐺𝑥 1 2 3 4 5
• Kernel used for the smoothening is a 5 × 5 gaussian kernel. 1 21 64 128 178 144
1 0 2 15 0 0 1 2 4 5 4 2
2 30 90 174 231 181
2 0 0 0 4 60 2 4 9 12 9 4
1/159 3 20 56 99 121 88
3 0 10 16 119 238 3 5 12 15 12 5
4 -6 -23 -57 -89 -77
Original Image Image after smoothening 4 0 14 170 255 255 4 4 9 12 9 4
- - - -
5 0 98 255 255 255 5 2 4 5 4 2 5 -41
120 228 299 233

𝑀 1 2 3 4 5 𝑆𝑥 1 2 3 4 5
1 30 80 140 180 164 1 -20 -47 -57 -26 78
2 62 147 220 237 262 2 -54 -116 -135 -54 190
3 89 188 223 139 300 3 -87 -179 -199 -69 287
4 96 190 207 107 306 4 -96 -189 -199 -59 296
5 77 172 259 300 300 5 -65 -123 -124 -30 189

I 1 2 3 4 5 Sobel ED IP block – inputs /outputs

1 0 2 15 0 0
2 0 0 0 4 60
3 0 10 16 119 238
4 0 14 170 255 255
5 0 98 255 255 255

𝑀𝑆𝑜𝑏𝑒𝑙 1 2 3 4 5 𝑀𝑆𝑚𝑜𝑜 1 2 3 4 5
1 4 30 4 74 124 1 30 80 140 180 164
2 14 35 172 579 610 2 62 147 220 237 262
3 36 282 761 1049 811 3 89 188 223 139 300
4 162 738 1025 657 899 4 96 190 207 107 306
5 210 708 824 938 1081 5 77 172 259 300 300
• Camera interface module decodes the incoming video stream from the camera and
performs the colour space conversion (YCrCb to RGB). Finally, it converts 24-bit
RGB data into 8-bit grey data. • Therefore, 8-bit grey pixel data coming from the camera interface module cannot
be processed directly. It must be stored in FPGA memory before processing.
• DVI module uses edge information (output of edge detection module) and video
timing signals information (from camera interface) to display the edge detected • The gradient computation module uses eight neighborhoods pixels coming from
video stream on the display monitor. buffer memory for computing the approximate gradient value which is the sum of
absolute values of horizontal and vertical gradients.
• For the Sobel edge detector, there are three main modules: Sobel buffer memory,
gradient computation module, and edge map module. • Edge map module is a simple comparator which compares the gradient value
(GRD) with a user-defined threshold (TH).
• Sobel edge detector is a window-based operator which requires pixel
neighbourhood information for computing the edge map of a particular pixel.

The memory requirement of a 𝟔𝟒 × 𝟔𝟒 image Architectural aspects – pipelining, scheduling and

Complexity for (3x3) convolution operator
Sobel detector
I1,1
• Input grayscale image 64 × 64, Date width = 8 bit P1,1 M1
Adder
• Input memory size is 4096 Byte M2
Adder
• x & y filter (3 × 3) is also considered as an 8 bit M3
Adder
• memory size requires for filter input = 18 Byte Adder
M4 Complexity
• 𝑆𝑥 and 𝑆𝑦 horizontal and vertical direction 64 × 64, data width = 16 bit Number of multiplier: 9
M5 Number of adder:7
• memory size requires for intermediate output = 16 KB Adder
M6
Total 16 hardware units
• Gradient direction requires to store output = 8 KB. Adder
Likewise, canny edge also followed the same. M7
Adder
M8
I3,3
P3,3 M9

Parallel multiplication and serial adder

 Parallel multiplication and single adder Serial multiplication and adder References
I1,1
P1,1 M1 Cycle 3 Cycle 2 Cycle 1 • Canny Edge Detector (justin-liang.com)
I3,1 I2,1 I1,1
• Sobel Edge Filter. We can think of an image, which is… | by Shailesh
P3,1 P2,1 P1,1 M1
M2 Adder
I3,2 I2,2 I1,2
M3 P3,2 P2,2 P1,2
M2 Kumpawat | Analytics Vidhya | Medium
M4 Adder
I3,3
P3,3
I2,3
P2,3
I1,3
P1,3
M3 Adder • Week 4: Image Filtering and Edge Detection (sbme-tutorials.github.io)
M5
Complexity • Canny edge detector – Wikipedia
Number of multiplier: 3
M6 Number of adder:2 • MATLAB - Image Edge Detection using Sobel Operator from Scratch -
Total 5 hardware units GeeksforGeeks
M7 Here, inputs takes 3 cycles to
complete the process.
M8 Complexity
Number of multiplier: 9
I3,3 Number of adder:1
P3,3 M9
Total 10 hardware units but multiplied output
has to wait during addition

Canny Edge Detector

• It is a gaussian-based operator in detecting edges.
• This operator is not susceptible to noise. It extracts image features without
affecting or altering the feature.
• Canny edge detectors have an advanced algorithm. It is widely used as an optimal
Canny edge detection edge detection technique.
• It detects edges based on three criteria:
Dr Arunachalam V 1.Low error rate
2.Edge points must be accurately localized
Associate Professor, SENSE 3.There should be just one single-edge response
Canny Edge Detector Steps
Eg: Input Image after Sobel and Canny Edge Operation

Step 1: Image Smoothening Step 2: Finding Gradients

• The first stage in the canny edge detection algorithm is smoothing to remove noise that may cause • This is done using the Sobel operator in both the x and y direction and getting a gradient.
false edges.
• Kernel used in this step is a 5 × 5 gaussian kernel. Gradient Magnitude Image

Original Image Image after smoothening

Step 3: Finding Gradients Case 1:
• This step is also known as edge thinning because it preserves the sharpest gradients and discards
the others.
• The algorithm is implemented pixel-wise, given the gradient magnitude and direction.
• The gradient magnitude of the current pixel is compared with the magnitude of the neighboring
pixels that point in the same direction.

Case 2: Case 3:
Case 4: None Max Suppression Image

Step 4: Double thresholding

Double Thresholding Image
• After none-maxima suppression we need to suppress pixels with low gradient
values to have only strong edges.
• None-maxima suppression eliminates only local weak edges using two threshold
TL & TH.
Step 5: Edge tracking by hysteresis
• Used to decide whether to consider a weak edge in the final result or not. Advantages:
• Weak edges could be meaningful but they are just not as strong as strong edges, 1.It has good localization
• For each of the weak edges, compare the magnitude of the pixel being processed 2.It extract image features without altering the features
with its eight surrounding pixels.
3.Less Sensitive to noise
• If at least one of these pixels belongs to the strong edges group (255), the value of
the pixel being processed is preserved. Otherwise, it is discarded to zero value.
Limitations:
Complex computation and time consuming

Sobel vs. Canny Edge Detector References

• Canny Edge Detector (justin-liang.com)
• The main advantages of the Sobel operator are that it is simple and
more time-efficient. However, the edges are rough. • Sobel Edge Filter. We can think of an image, which is… | by Shailesh
Kumpawat | Analytics Vidhya | Medium
• Canny technique produces smoother edges due to the implementation
• Week 4: Image Filtering and Edge Detection (sbme-tutorials.github.io)
of Non-maxima suppression and thresholding.
• Canny edge detector – Wikipedia
• Canny algorithm is that it is more complex and less time-efficient than
• MATLAB - Image Edge Detection using Sobel Operator from Scratch -
Sobel. Knowing these differences is helpful in deciding which
GeeksforGeeks
technique is better for a particular application.
 Introduction
• Image enhancement refers to the process of highlighting certain information in an image and
weakening or removing any unnecessary information according to specific needs.
Image Enhancement • For example, eliminating noise, revealing blurred details, and adjusting levels to highlight features
of an image.
Algorithm • Contrast & brightness enhancement refers to the sharpening of image features to remove the
noisy feature such as edges and contrast boundaries.
• This algorithms aim to improve the perception of the image by human eye.
Dr Arunachalam V
Associate Professor, SENSE

Contrast improvement by Histogram Equalization Input Matrix

• In this Matrix, the Intensity of the pixels varies between 1 – 8.
3 2 4 5 • There is a need to perform histogram equalization on this Matrix and scale the
• Histogram equalization is an image processing technique that adjusts image intensities to intensity to 1-20.
improve contrast. 7 7 8 2
Pixel Intensity 1 2 3 4 5 6 7 8 9 10
• Histogram Equalization is one of the simplest and most used methods in low-level image No .of Pixels 1 3 3 2 2 1 3 1 0 0
enhancement using the histogram. 3 1 2 3

• The logic behind Histogram Equalization is that the image with the best visual appearance is the 5 4 6 7 • Total Number of pixels = 16
one whose histogram looks like the regular distribution. • Probability = No. of Pixels/ Total Number of pixels (16)
• Cumulative probability = Current Probability + (Previous Cum. Probability)
• A Cumulative Distribution Function(CDF) of a histogram is the fraction of pixels with a pixel
value that is less than or equal to the specified pixel value. Histogram Equalization
Original Pixel 1 2 3 4 5 6 7 8 9 10
8 5 11 13
• Histogram Equalization is particularly useful in cases where both backgrounds and foregrounds Intensity
are both bright or dark. Probability 0.0625 0.1875 0.1875 0.125 0.125 0.0625 0.1875 0.0625 0 0
18 18 20 5
Cum.Probability 0.0625 0.25 0.4375 0.5625 0.6875 0.75 0.9375 1 1 1

8 1 5 8 H.E = C.P * 20 1.25 5 8.75 11.25 13.75 15 18.75 20 20 20

Improved pixel by 1 5 8 11 13 15 18 20 20 20
13 11 15 18 Rounding HE
 Contrast Stretching
• In Contrast Stretching the contrast in an image is stretched from the range of intensity values it
contains to span a desired range of values.
• It is also called Normalization.
• Some Contrast Stretching techniques include:
• Minimum-Maximum,
• Percentage, and
• Piecewise Contrast Enhancement.

Min-Max Contrast Stretching Model architecture for image enhancement approach

• In Min-Max Contrast Stretching for an updated pixel value is given by:
𝑝𝑖𝑥𝑒𝑙−𝑚𝑖𝑛
• 𝑃𝑖𝑥𝑒𝑙𝑢𝑝𝑑𝑎𝑡𝑒𝑑 = × 255
𝑚𝑎𝑥−𝑚𝑖𝑛

Where min and max are the maximum and minimum pixel values in the image.

Contrast enhancement using RGB to HSV
algorithm
RGB Color Model
• The RGB colour model is an additive colour model in which red, green and blue light are added
together in various ways to reproduce a broad array of colours.
• The name of the model comes from the initials of the three additive primary colours, red, green,
and blue.
HSV / HSB Color Model
• HSV – (Hue, Saturation, Value), also known as HSB (Hue, Saturation, Brightness).
• It is often more natural to think about a colour in terms of hue and saturation than in terms of
additive or subtractive colour components.
• HSV is a transformation of an RGB colour space, and its components and colourimetry are relative
to the RGB colour space from which it was derived.
Steps to convert R, G, B pixel to H, S, V
1. Divide R, G, B by 255
R’=R/255
G’=G/255
B’=B/255
2. Compute cmax, cmin, difference
cmax = max(R’, B’ ,G’)
cmin = min(R’, B’ ,G’))
Difference (diff) = cmax - cmin
3. Hue calculation :
if cmax and cmin are equal, then H = 0
if cmax equal R’ then compute H = (60 * ((G’ – B’) / diff) + 360) % 360
if cmax equal G’ then compute H = (60 * ((B’ – R’) / diff) + 120) % 360
if cmax equal B’ then compute H = (60 * ((R’ – G’) / diff) + 240) % 360
4. Saturation computation :
if cmax = 0, then S = 0
if cmax ≠0, then S = (diff/cmax)*100
5. Value computation :
V = cmax*100
Example 1 Step 3: To find Hue (H), Inputs from step 2
Check the 4 condition
Step 1: Input R=31; G=52; B=29 H = (60 * ((B’ – R’) / diff) + 120) % 360
R’=R/255 = 31/255 = 0.1216 H= (60* (0.1137-0.1216))/0.0902)+120 = 114.78
H=mod (114.78, 360) = 114.78
G’=G/255 = 52/255 = 0.2039
B’=B/255 = 29/255 = 0.1137 Step 4: To find Saturation (S), Inputs from step 2
Check the 2 condition
Step 2: Input R’, B’, G’ from step 1 S=(diff/cmax)*100
S=(0.0902 /0.2039)*100 =44.23
cmax =max (R’, G’, B’)
cmax =max (0.1216, 0.2039, 0.1137) = 0.2039 Step 5: Too find value computation (V), Inputs from step 2
V=cmax*100
cmin =min (R’, G’, B’)
V= 0.2039 *100 =20.39
cmin =min(0.1216, 0.2039, 0.1137) = 0.1137
Diff =cmax-cmin = 0.0902 Finally, H; S; V= 114.78; 44.23; 20.39
Similarly, do this for all the pixels of the image

References
Example 2 • Embedded Motion Control 2012 Group 8 - Control Systems Technology Group
• Input : r, g, b = 45, 215, 0 (tue.nl)
Output : h, s, v = 107.44, 100.0, 84.3 • Program to Change RGB color model to HSV color model – GeeksforGeeks
• Types of Contrast Enhancement Algorithms and Implementation in Python
(opengenus.org)
Example 3
• (2) (PDF) Digital image enhancement by brightness and contrast manipulation
• Input : r, g, b = 31, 52, 29 using Verilog hardware description language (researchgate.net)
Output : h, s, v = 197, 31.11, 17.64

RGB to HSV conversion | color conversion (rapidtables.com)

 Introduction
• Traffic light are the signalling device used to manage traffic on multi-way road. These are
Traffic Light positioned to control the competing flow of the traffic at the road intersection to avoid
collisions.
Controller – • By displaying lights (red, yellow and green), they alternate the way of multi-road users.
FPGA-based • The implementation of traffic light controller can be through a Microcontroller, FPGA or
ASIC.
design • The microcontrollers use the C programming languages, the ASIC and FPGA use Verilog,
VHDL or system Verilog.
Dr Arunachalam V
• The algorithm for doing this is based on Finite State Machine (FSM) .
Associate Professor, SENSE

Traffic Light Controller (TLC) Design on FPGA A Structure of TLC Design on FPGA
• TLC design system is composed of a finite state machine (FSM), data storage (D_RAM), timer,
divider, and various synchronizers (latch, and synchronizer) as declared in the following: EN-W
L0-L1
• Finite State Machines (FSM) are the core of the traffic light controller system. It controls the loading of ADD-IN HEX-
F0-F1 D_RAM
CIN0-CIN4 Display
static data storage locations with timing parameters, reading RAM locations to display these parameters
and controls the actual traffic lights. GO

• D_RAM: This component is used to store the timing parameters. Depending on the signal en_w, select FSM
TS1-TS3 Traffic light (0-13)
to read the contents by L0-L1 switches, or write new timing parameters by C0-C4 switches and display
ADD_OUT
the contents on the HEX_LEDs.
• A divider is used to generate the clock (1 MHz) for an overall system from 50 MHz of the chip FPGA
LATCH
Spartan 3E. WR
• Sec_pulse is used to generate a one-second clock, which is used in the timing of the traffic lights.
• A timer is implemented as a counter Divider SEC_PULSE TIMER
• Latch: A pedestrian signal is latched so that when the user pushes the button once, the signal is queued
until the FSM needs it.
CLKS
• Sensors: There are three traffic sensors which are synchronized by simply passing it through a flip flop.
 State Diagram
4-Way Traffic Light Controller Based on FSM
• There are eight states in the state diagram which
• There are four roads: East, North, West, and are green and yellow states for each road.
South. • In the green state of a road, only that road will be
• The green light will go on circularly in the green, others will be red.
counter-clockwise direction. • The system will remain for 20 seconds in this
• The green light will remain on for 20 state.
seconds. • In the yellow state of a road, the corresponding
• In this period all other roads will be red. Then, road will be yellow, the next road to be green will
the yellow light will light up and the next road be red-yellow and others will be red.
to be green will be in a red-yellow state to • The system will remain for 4 seconds in this
caution the drivers. state. The states of the system will rotate as
• The system will be in this state for 4 seconds. shown in the figure.

Description of 8 states Emergency Condition

• The emergency condition is implemented by using a 4-bit variable named Emergency.

• If Emergency[3] is 1 then it means that the east road has an emergency conditions and the
system goes to east_green state whose binary value is 000.
• Similarly, emergency conditions for other roads are implemented.
 Jam Condition Flow Chart

• Similarly, the jam condition is implemented using a 4-bit variable Jam. It’s operation is like
that of the emergency condition.

2-Way Traffic Light Controller Based on FSM

State Description
Using Verilog

State State LA LB
(Binary)
S0 00 Green Red
S1 01 Yellow Red
S2 10 Red Yellow
S3 11 Red Green
 Verilog Code Moore FSM (Main Module)
Logic Circuit

References
• GitHub - raash1d/smart-traffic-light-controller: A Mealy Finite State Machine (FSM), developed in
Verilog, designed to control traffic lights at a crossroad having a major road (main road) and a
minor road (side road).
• PPT - Lecture 5. Verilog HDL #3 PowerPoint Presentation, free download - ID:2396169
(slideserve.com)
• Verilog code for Traffic light controller - FPGA4student.com
 Real Time Clock (RTC)
• RTC is an IC(integrated circuit) device and a computer clock that keep track of the current time.
• It assists to keep and maintain accurate time in devices.
• It is powered by an internal lithium battery.
• As a result of which even if the power of the system is turned off, the RTC clock keeps running.
Real Time Clock
Dr Arunachalam V
Associate Professor, SENSE

• RTC maintains its clock by counting the cycles of an oscillator — usually an external 32.768kHz
crystal oscillator circuit, an internal capacitor-based oscillator, or even an embedded quartz crystal. • A real-time clock (RTC) is an electronic device designed in the form of an integrated circuit to
measure the passage of real-time.
• Some can detect transitions and count the periodicity of an input that may be connected.
• Real-time clocks maintain accurate time measurements within an embedded system even when the
• Many RTCs can detect this change-over and go into an ultra-low power state where they power
main power is off.
down all circuitry except those essential for maintaining the clock in order to conserve battery life.
• It counts hours, minutes, seconds, months, days, and even years.
• RTCs can also include alarm functions — set times that when reached trigger the RTC to drive an
output that wakes the processor up. • These modules can be found in nearly every electronic device especially when the device requires
a form of accurate timekeeping.
• A real-time clock (RTC) is an electronic device designed in the form of an integrated circuit to
measure the passage of real-time.
• The need for accurate timekeeping is often used as a trigger for specific events.
• The reason independent power is necessarily comes down to the functional use of RTC modules in
laptops, computers, tablets, and other electronic devices.
 (or)
FPGA

RTC: Block Diagram

 RTL code (Sub module 1)
RTL Code (Top Module)

RTL code (Sub module 2) RTC Waveform

Example: Stop-Watch State Machine Difference between RTC and System Clock
• Processor relies on a small quartz crystal circuit called the system clock to control the timing of all
computer operations.
• While RTC is the form of an IC which is used to keep tracks of the current time.
• The term RTC refers to the devices used in servers, personal computers and embedded systems

System Clock For example

• System clock generates regular electronic pulses, or ticks, that set the operating pace of
components of the system unit.
• The processor relies on a small quartz crystal circuit called the system clock to control the timing
of all computer operations.
• The pace of the system clock, called the clock speed, is measured by the number of ticks per
second.
• Personal computer processors have clock speeds in the gigahertz range. Thus, one
gigahertz (GHz) equals one billion ticks of the system clock per second.
• A computer that operates at 3 GHz has 3 billion (giga) clock cycles in one second (hertz).
• The faster the clock speed, the more instructions the processor can execute per second.
• The speed of the system clock is just one factor that influences a computer’s performance.
• Other factors, such as the type of processor chip, amount of cache, memory access time,
bus width, and bus clock speed.
Definition RTC
• In the computing world, the term ‘clock’ is used for more than just tracking accurate time.
• Hardware clocks and clock cycles are often used to measure the speed of signals that happen
between specific components on the motherboard.
• The term real-time clock is used as a way of avoiding confusion with hardware clocks.
• Hardware clocks are used to measure signals that govern functionality or computing power in an
electronic device.
• Real-time clocks are used to measure the true passage of time in human-recognizable units such as
hours, seconds, minutes, days, and months.
• RTC, is also shared with other computing terms like real-time computing and real-time counter.
• This often leads to confusion early on for beginners, especially as real-time counters are sometimes
similarly used in software programming to real-time clocks.
• The best way to keep the terms easily separated and defined is to think of real-time clocks as
physical computer chip modules usually embedded in the microcontroller unit while the other
terms are used for software functions resulting from hardware performance
RTC Modules
• As an essential component for computers, RTCs are produced as modules to be installed onto
microcontroller units for electronic devices and computer motherboards.
• Most modern RTC modules have a rechargeable battery and can be soldered to the device it is
meant to be installed on.
• As a major computer component, you might expect to find them available for purchase.
• However, the reality is that most RTC module manufacturers produce the product for sale from
business to business rather than to the general consumer.
• It has only been recently that RTC modules have been manufactured to be used in Arduino or
raspberry pi projects in line with the growing open-source development community.
Benefits of an RTC Real-Time Clock Module Manufacturers
• NXP Semiconductors
• RTCs are more precise than software clocks.
• Dallas Semiconductors
• The use of an independent power source improves overall power consumption and frequency
stability. • STMicroelectronics
• By using an independent time-keeping module, it frees up resources on the main system for time- • Micro Crystal
critical tasks. • Petermann-Technik
• New Japan Radio
• Texas Instruments (TI)
• Microchip Technology
• Maxim Integrated

References
• Role of RTC(Real Time Clock) in Embedded Devices | by Iqram Ali | Medium
• What is a Real-Time Clock (RTC) and Why are They Important in Computing? - History-Computer
• How to Use a Real-time Clock Module with the Arduino - Circuit Basics
• GitHub - superzanti/Verilog_Clock: A real time clock written in Verilog for the Spartan-3AN FPGA
by Xilinx. This clock includes date and 24-hour time with an alarm clock. Interfacing & Programming
• DS1307.pdf (analog.com) Video Graphics Array (VGA) module
Dr Arunachalam,
Associate Professor, SENSE
 Introduction
VGA - Resolution
• The Video Graphics Array (VGA) connector is a standard connector used for computer video
output.
• VGA is slowly replaced by other displays such as DVI, HDMI, and DisplayPort.
• 15-pin connects to PCs, as well as many monitors, projectors and high-definition television sets.
• The HDMI specification is very detailed, so interfacing directly from an FPGA to an HDMI
• The Video Graphics Array (VGA) interface is common to most modern computer displays and is
display is more of a challenge than a VGA display.
based on a pixel map, color planes and horizontal and vertical sync signals.
• The resolution of the screen can vary from 480 × 320 up to much larger screens, but a
• A VGA monitor has three color signals (red, green and blue) that set one of these colors on or off
standard default size is 640 – 480 pixels.
on the screen.
• This is 480 lines of 640 pixels in each line, so the aspect ratio is 640/480 leading to the classic
• The intensity of each of those colors sets the final color seen on the display.
landscape layout of a conventional monitor screen.

Interface setup - FPGA and VGA

VGA Active vs. Inactive Area with 25 MHz Clock
• When the image is displayed on the
monitor, the pixels are actually
displayed from left to right, top to
bottom.
• Therefore, the top-left corner is the
first pixel displayed and the bottom-
right corner is the last pixel
displayed.
• The pixels are arranged so fast and
entire image looks to the human eye
The video pins are red, green, blue, horizontal sync, and vertical sync (analog, 0 for black & 0.7V for full like drawn at once.
intensity) & others are digital monitor ID pins.

A digital monitor keeps the timing of the sync signals w.r.t the resolution. Also, sets up some ADCs to
sample the voltages of the RGB lines.
 Industry Standard Timing
Timing parameters for the 640×480 resolution VGA Signal 640 x 480 @ 60 Hz

Control signals
Active Area, Horizontal Blanking, Vertical Blanking
• The two control signals Horizontal Sync (H_Sync) and Vertical Sync (V_Sync).
• H_Sync is high when frame area is horizontally active, and it activates the vertical
blanking area of the frame.
• V_Sync is high when frame area is vertically active, and it activates the horizontal
blanking area of the frame.
• Therefore, if H_Sync and V_Sync are both high, then the frame area is active on both
horizontally and vertically.
• VGA monitors were Cathode Ray Tubes (CRTs).
• Due to the way CRT displays work, it deals with the Front Porch and Back Porch.
• These allows the active area to be shifted around the VGA monitor.
 VGA Signal Timing VGA Signal Timing
• Video data at 60 Hz, means 60 frames per second.
• The refresh rate for the display is fixed at 60 Hz, which is the typical value used in monitors.
• Using an active area of 640 by 480, meaning 640 columns and 480 rows in the active area.
• In order to achieve this refresh rate on a 640×480 pixel screen, the pixel rate calculation is done as
follows: • There are a total of 794 columns and 525 rows in the total frame.
• Pixel Rate = Total Horizontal Pixels × Total Vertical Lines × Number of frames per second • This is a total of 794×525=416,850 pixels.
= 800 × 525 × 60 = 25 MHz • Board uses a 25 MHz clock. So if you draw one pixel per clock cycle, how much time does it take
to draw an entire frame?
416850/25000000 = 0.01667 seconds.

Block Diagram of a Video Controller VGA – Synchronization signals

• A video controller generates the synchronization signals and outputs data pixels serially through
the VGA port of the FPGA board.
• The synchronization signals generator circuit (vga_sync) generates the timing and control signals.
• The h_sync and v_sync signals control the horizontal and vertical scans.
• The pixel_x and pixel_y signals specify the current location of the pixel.
• The vga_sync circuit generates the video_on signal to indicate whether to enable or disable the
display.
• The Pixel generation circuit generates the three video signals which are collectively referred to as
the rgb signal.
 HDL implementation of VGA Controller
High-level block diagram of the VGA driver system
Step 1: The sync signal can be obtained by a special mod-800 counter and a decoding circuit. We
intentionally start the counting from the beginning of the display region so that the counter output can be
used as the horizontal (x-axis) coordinate. This output constitutes the pixel_x signal.
Step 2: The vsync signal can be obtained by a special mod-525 counter and a decoding circuit. This output
constitutes the pixel_y signal.
Step 3: video_on signal is used to indicate whether the current vertical coordinate is in the displayable
region. It is asserted when the line count is smaller than 480.
Step 4: 50MHz board clock is used as the system clock.
Step 5: The pixel clock is half of the system clock. A mod-2 counter is used to generate 25MHz pixel clock
signal.
Step 6: The pixel tick should be routed via port as output signal to pixel generation circuit to extract the
pixel content at the same rate.
Step 7: The values of the various regions of the horizontal scans and vertical scans are defined by the
constants.
Step 8: To avoid glitches, the output buffers are inserted for the hsync and vsync signals.

Verilog Modules for VGA interface References

• PLL: To get correct timings, a Phase-Locked Loop (PLL) clock generator is needed to convert the 50 • basic-vga-controller-design-example.pdf (intel.com)
MHz clock on the DE-10 Lite to 25 MHz. This IP component handles the instantiation of the PLL.
• Design Recipes for FPGAs - A Simple VGA Interface - EE Times
• VGA Controller: This module generates the necessary horizontal and vertical sync signals expected
• EEC180 Tutorial: Displaying to a VGA monitor using a combinational circuit (ucdavis.edu)
by the VGA receiver. In normal use, you should not need to use h_sync, v_sync, and disp_ena signals.
Pixels are drawn one at a time from left to right and then top to bottom (see figure). Pixel (0,0) is in • GitHub - RobertRWu/VGA-Verilog: A simple VGA interface for FPGA written in verilog.
the upper left corner. • VGA-Verilog/src at master · RobertRWu/VGA-Verilog · GitHub
To help with drawing, vga_controller exports the following two signals: • Real Time Image Processing - DE2i-150 at Purdue (google.com)
• row: The row (vertical coordinate) of the pixel being drawn.
• column: The column (horizontal coordinate) of the pixel being drawn.
• Combinational Circuit Block: This is the combinational logic block that determines RGB color
outputs given a certain row and column pixel and the position of the ten SW board switches.
 Introduction
• LCD (Liquid Crystal Display) is a type of flat panel display that uses liquid crystals in its primary
Interfacing & Programming- operation.
• LCDs were a big leap in the technology they replaced, including light-emitting diode (LED) and
Liquid Crystal Display (LCD) module gas-plasma displays.

Dr Arunachalam, • LCDs allow displays to be much thinner than cathode ray tube (CRT) technology. LCDs consume
much less power than LED and gas-display displays because they work on the principle of
Associate Professor, SENSE
blocking light rather than emitting it.
• Where an LED emits light, the liquid crystals in an LCD produce an image using a backlight.
• As LCDs have replaced older display technologies, LCDs have begun being replaced by new
display technologies such as OLEDs.

1 line × 16 characters module

Introduction
Character LCD
• A display is made up of millions of pixels. The quality of a display commonly refers to the number
of pixels. • Character LCDs are ideal for displaying text.
• For example, a 4K display is made up of 3840×2160 or 4096 × 2160 pixels. A pixel is made up of • They can also be configured to display small icons, but the icons must be only 7×5 pixels.
three subpixels; red, blue and green- commonly called RGB. • In character LCD, the little rectangles where the characters are displayed.
• When the subpixels in a pixel change colour combinations, different colours can be produced. • Each rectangle is a grid of pixels.
• With all the pixels on a display working together, the display can make millions of different
colours.
• A picture is created when the pixels are rapidly switched on and off.
 Graphical LCD 2 line × 16 characters- LCD module
• The graphical LCD has one big grid of pixels (in this case 128x64) - It can display text but its best
• An LCD screen is an electronic display module that uses liquid crystal to produce a visible image.
at displaying images.
• The 16×2 LCD display is a very basic module commonly used. The 16×2 translates a display of 16
• Graphical LCDs tend to be larger, more expensive, difficult to use and need many more pins
characters per line in 2 such lines.
because of the complexity added.
• In this LCD, each character is in an 8×5 matrix.

LCD- 2 line × 16 Pin Layout Features of LCD16x2

• Pin1 (Ground) & Pin2 (+5 Volt):
• This pin connects and supplies the LCD The features of this LCD mainly include the following.
• Pin3 (VE): • The operating voltage of this LCD is 4.7V-5.3V
• This pin selects the contrast of the LCD.
• It includes two rows where each row can produce 16-characters.
• Pin4 (Register Select):
• This pin is used to connect a data pin of an MCU & gets either 1 or 0. • It draws a 1mA current with no backlight.
• Here, data mode = 0 and command mode =1. • Every character can be built with an 8×5 pixels box
• Pin5 (Read & Write):
• The alphanumeric LCDs alphabets & numbers
• This pin is used to read/write data.

• Pin6 (Enable):
• Is display can work on two modes like 4-bit & 8-bit
• This enables the pin must be high to perform the Read/Write procedure. • These are obtainable in Blue & Green Backlight
• This pin is connected to the data pin of the microcontroller to be held high constantly.
• It displays a few custom generated characters
• Pin7 to 14 (Data Pins):
• The data pins are connected through the microcontroller for data transmission.
• The LCD module can also work on the 4-bit mode using only pins 0, 1, 2 & 3.

• Pin15 (LED Positive) & Pin16 (LED Negative):

• These connect to the backlight LED of the display.
 Example- To display ‘6’ in LCD
Interfacing an FPGA with 16×2 LCD
• FSM has two inputs (addr_reg and cnt_reg) and five outputs (s1, s2, RS, RW, and E).
• The FSM inputs allow us to monitor the status of the “Path 1” and “Path 2” blocks.
• The “s1” output controls “Path 1” and, consequently, the data applied to the DB7-DB0 pins.
• The “s2” output controls the “Path 2” block and can be used to generate the required time delays.
• The “RS”, “RW”, and “E” outputs generate the appropriate waveforms for the LCD control pins.
Interfacing an FPGA with 16×2 LCD
Displaying “HELLO WORLD!” with 16×2 LCD
• The “HELLO WORLD!” message has 12 characters, and we can use a 12 × 8-bit ROM to store the
message.
• However, let’s consider a 16 × 8-bit ROM for the message so that we can display messages as long
as 16 characters (the length of the first row of the LCD).
• In figure, it shows a 20 × 8-bit ROM if our message is at most 16 characters long.
• These additional four bytes will be used to store the data related to the LCD instructions that allow
us to configure the module.
• the building blocks for interfacing an FPGA with a common 16x2 LCD module requires ROM,
some DFFs, and multiplexers. Additionally, needs an FSM to control these building blocks.
 LCD module - Video display & Touch sensitive
• PIO – Parallel IO
• SPI – Serial Peripheral Interface
• MAX II – Voltage converter
FPGA 2.5 V to LCD 3.3 V
• Use the following link to explore more on interfacing Graphical LCD with Touch-sensitive display
with an FPGA:
• https://www.intel.com/content/www/us/en/content-details/653846/an-527-lcd-controller-
replacement.html
• Some of the major steps are:
• Add custom instructions to the NIOS II processor to accelerate the application
• Add hardware accelerator modules to accelerate the application
• Add custom hardware to the LCD controller to accelerate graphical operations
• Implement burst access in DMA modules to optimize memory bandwidth

References
• https://www.allaboutcircuits.com/technical-articles/how-to-interface-mojo-v3-fpga-board-16x2-
lcd-block-diagram-Verilog-code/
• https://www.fpga4fun.com/TextLCDmodule.html
• https://www.watelectronics.com/lcd-16x2/
• https://www.electronicsforu.com/technology-trends/learn-electronics/16x2-lcd-pinout-diagram
• https://www.mouser.in/applications/programmable-logic-display/
• https://www.elprocus.com/interface-lcd-liquid-crystal-display-using-arduino/
• https://www.elprocus.com/lcd-16x2-pin-configuration-and-its-working/
• https://www.intel.com/content/www/us/en/content-details/653846/an-527-lcd-controller-
replacement.html