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Fig 3.5.2
2.5D MEMORY ORGANIZATION: One way to tackle the exponential explosion of
growth in the decoder and word select wires is to organize memory cells into a two-
dimension grid of words instead of a one-dimensional arrangement. Then the MAR is broken
into two halves, which are fed separately into smaller decoders. One decoder addresses the
rows of the grid while the other decoder addresses the columns.
HOMEWORK (ASSESMENT)
Q1. The parallel mode of communication is not suitable for long devices because of ______
A. Timing skew
B. Memory access delay
C. Latency
D. None of the mentioned
Answer:A
Q2. User programmable terminals that combine VDT hardware with built-in microprocessor
is _____
A. KIPs
B. Pc
C. Mainframe
D. Intelligent terminals
Answer:D
Q3. The use of spooler programs or _______ Hardware allows PC operators to do the
processing work at the same time a printing operation is in progress.
A. Registers
B. Memory
C. Buffer
D.CPU
Answer:C
References
Reference Books:
Stallings, W., “Computer Organization and Architecture”, Eighth Edition, Pearson Education.
Text Books:
http://www.sgrrits.org/pdf/e-content/IT/Internal-organization-of-Memory-chips.pdf
https://www.ics.p.lodz.pl/~dpuchala/CompArch/Lecture_6.pdf
Video References
https://www.youtube.com/watch?v=LetdmZ3V-dk
https://www.youtube.com/watch?v=3x9OMMwU7dQ