MAIN ASSESSMENT

DATE: SESSION:

SUBJECT: DIGITAL ELECTRONICS I CODE: EDE115C

Duration: 180 Minutes Maximum marks: 100 Stationary: No answer books

1. Non-alphanumeric calculators allowed.
2. Show all calculations.
3. Answer all questions
ASSESSOR: Mr. P Veldtsman
ASSISTANT ASSESSOR: Me. N Koyana
MODERATOR: Mr. B vd Walt

INSTRUCTIONAL PROGRAMME: CODE:

BACHELOR OF ENGINEERING TECHNOLOGY IN ELECTRICAL ENGINEERING B_ETE

THIS PAPER CONSISTS OF 16 PAGES.

Question Assessor Moderator TOTAL

1 8
2 12
3 11
4 9
5 10
6 12
7 2
8 9
9 27
Total 100
Final Mark (%)

Signature
 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

To be completed by all candidates. (Please print legibly)

SURNAME AND FULL NAMES: ………………………………………………………….…………………………………………………

STUDENT NUMBER: ………………………..……… SEAT NUMBER: ……………………………………….

DATE OF ASSESSMENT: ………………………………………………………

SUBJECT AND PAPER (e.g. Economics III, Paper 1):
……………………………………………………………………………………………………………..

INSTRUCTIONAL PROGRAMME (E.G. BACHELOR OF ENGINEERING

TECHNOLOGY IN ELECTRICAL ENGINEERING):
………………………………………………………………………………………………………………
DECLARATION: I DECLARE THAT I HAVE READ THE INSTRUCTIONS, THAT I FULLY UNDERSTAND THEM, AND THAT
I UNDERTAKE TO ADHERE STRICTLY THERETO.

SIGNATURE OF CANDIDATE: …………………………………..…….

INSTRUCTIONS TO CANDIDATES

1. Complete all parts that do not appear in blocks. Your student number and full names and surname must also be written in the top
right-hand corner of each loose sheet of writing paper.

2. Write neatly and clearly, using both sides of the paper. Leave both margins entirely free for use by the assessor.

3. You will be allowed a 10-minute reading period prior to the published starting time of the assessment.
4. Every student shall complete and sign the attendance slip and receipt attached to the assessment script. Students will also be required
to present their student identification card.
5. Every student must read and comply with the instructions that appear on the inside of the cover of the answer script, as well as the
instructions on the question paper. As proof that they have read the instructions, students must sign in full on the front page of the
answer script.
6. No student will be permitted to enter the assessment venue more than 60 minutes after the published starting time. No student shall
leave the assessment venue before 60 minutes have elapsed from the published starting time.
7. No student shall commence writing answers until authorised to do so by the chief invigilator. All students shall cease writing when
instructed to do so by the invigilator at the end of the assessment.
8. After the assessment has commenced, you may only leave the assessment venue temporarily with the permission of the invigilator,
and then only under supervision.

9. Any student who wishes to leave the assessment room, temporarily, must hand to the supervisor all answer scripts, which must be
correctly endorsed to identify the student.

10. A student may not take into the assessment room any books, dictionaries, calculators, notes, other documents, or any written or
printed matter or devices except those authorised by the assessor and indicated on the cover page of the question paper.
11. During an assessment a student may not make contact and/or communicate with any other student.

12. No smoking is allowed.

13. No cellular phones or any other means of communication are allowed.

14. All answers are to be written in ink.
15. No student shall leave the assessment venue during the last 10 minutes of any assessment.
16. Any student who wishes to leave the venue must hand in all answer scripts to an invigilator.
17. If any invigilator has reasonable grounds to believe that a student has forbidden notes or any other items in his/her possession, the
learner may be confronted with the suspicion or be requested to leave the assessment venue in the company of two invigilators of the
same gender as the learner. One of the invigilators then has the right to search the person of the student for forbidden notes or items,
in the presence of the other invigilator and in a private room where only these three persons are present.

18. The Central University of Technology, Free State is not liable for the loss of personal possessions.
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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 1

(a) Complete the following: The stimulus that causes a current to flow is an …………… [1]

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(b) In the following circuit calculate the total current ( IT ) taken from the 12v supply. [3]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

(c) Find the two branch currents, I1 and I2 as shown. [2]

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(d) Find the equivalent resistance, for the following resistor combination circuit. [2]
A = 10Ω, B = 5Ω and C = 15Ω

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 2

Convert the following numbers as indicated:

(a) 100110,01112 to decimal [2]

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(b) 52,562510 to binary [2]

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(c) 53,312510 to hexadecimal [2]

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(d) 5B,E16 to decimal [2]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Calculate the following as indicated:

(e) 111102 – 11102 use 1’s complement [2]

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(f) 101102 – 110112 use 2’s complement [2]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 3

(a) Shown below is a circuit using switches and a lamp. What will the equivalent logic
expression (operation) be of this circuit? Draw the truth table for the output L.
Assume 0 = switch open, 1 = switch closed. [5]

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(b) Draw the logic symbol and truth table for a 2-input NAND gate. [3]

Logic symbol Truth table Boolean expression

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

(c) Draw the output waveform relative to the inputs if the following input waveforms are
applied to:

(i) a 2-input exclusive-OR gate

(ii) a 2-input NOR gate
(iii) a 2-input AND gate [3]

(i)

(ii)

(iii)

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 4

(a) Simplify the following using Boolean algebra: 𝐴̄𝐵̄ 𝐶 + 𝐴𝐵𝐶 + 𝐴𝐶 + 𝐴𝐶 [3]

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(b) Make use of a Karnaugh map to simply the following expression and write down the
simplified SOP expression: AB + A CD + A B CD + A BCD [3]

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(c) Make use of a Karnaugh map to simply the following expression and write down the
simplified POS expression: AB + A CD + A B CD + A BCD [3]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 5

(a) Identify the following flip-flop characteristics: [2]

CLK

(i)
(i) ..............................................................................................................................................

CLK

(ii)
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(b) Draw the waveforms for a negative edge triggered JK flip-flop. Assume the initial
value of Q is logic 0. [6]

CLK

PRE

CLR

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

(c) Draw the logic symbol of a negative edge triggered JK flip-flop. Identify the
synchronous and asynchronous inputs of the flip-flop. [3]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 6

(a) Make use of the 555 timer IC and design a circuit with an output frequency of 3.2kHz.
The circuit must have a duty cycle of 40% and a capacitor value of 150nF must be
used. Show all calculations. [7]

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(b) You are required to design a circuit to give out a high pulse of 20ms, when it receives
a falling edge. Make use of a 74LS122 to design the circuit. Show the logic diagram
as well as all calculations. Assume C=150nF. [5]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 7

(a) The following counters are connected to a 120kHz (30% duty cycle) square wave
oscillator (See sketch below). Answer the following questions:

120kHz Decimal f1 CTR Div f2

Oscillator counter 12

(i)What is the frequency for the signal labeled f2? [1]

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(ii)What is the frequency for the signal labeled f3? [1]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 8

(a) Complete the timing diagram for this circuit, assuming all Q outputs begin in the low
state: [4]

CLK

Q0

Q1

Q2

Q3

(b) Draw a logic diagram for a 5-bit serial-in / parallel-out shift register using negative
edge-triggered JK flip-flops. [5]
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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 9

(a) Design a synchronous counter using negative edge triggered JK flip-flops with the
following count sequence: 14, 5, 6, 9, 11, 4, 13 and repeat. You must show the state
diagram, next-state table, the transition table. All steps to design the counter must be
shown. No circuit diagram is required. [27]

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 DIGITAL ELECTRONICS 1: MAIN ASSESSMENT EDE115C
JUNE 2022

Question 9(d) Continued

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TOTAL 100
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