PULP PLATFORM

Open Source Hardware, the way it should be!

Research Challenges in Open Source HW

Luca Benini <luca.Benini@unibo.it, lbenini@iis.ee.ethz.ch>

http://pulp-platform.org @pulp_platform
Open Source Hardware

Hardware whose design is made publicly available so

that anyone can study, modify, distribute, make, and
sell the design or hardware based on that design
(source: Open Source Hardware (OSHW) Statement of Principles 1.0)

Very wide definition – includes PCBs and makers’ stuff

I will focus on Open Souce Computing Hardware (OSCHW) |

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OSCHW Needs an Open Source ISA
A modern, open, free ISA, extensible by construction
Endorsed by 1000+ Members & large SW ecosystem
An open ISA is a prerequisite!

Risc-V international moved to Zürich, CH

for international neutrality, 1/3 of members from EU
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 Technically, what is “open” in OSCHW Today?
 Only the first stage of the silicon production pipeline 
 RTL source code (permissive*, e.g. Apache is key for industrial adoption)
 Later stages contain closed IP of various actors  not open source by default

EDA Companies Cadence

PDK Foundries
license for
academic usage
forbids
HDL permissive
Simu- Logic
Netlist P&R GDSII FAB Chip open sourcing
lator Synth.
of designs
Sim. Std. made with
Models Cells CDNS tools
unless a
Other reciprocal*
IP license is used
Phy IP Providers
“See: https://cern-ohl.web.cern.ch/ (CERN-OHL-S, -W, -P) |
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 What about End-to-End Open HW (pdk, tools)?
Raven 130nm
mixed-signal
SoC

Open source process design kit for usage with

SkyWater Foundry 130nm tech.  40 submissions for
https://github.com/google/skywater-pdk the MPW-ONE
shuttle: 60%
submitted by first-
Open Source ASIC EDA flow time ASIC
OpenLANE is an automated RTL to GDSII flow based designers.
on several components including OpenROAD, Yosys,  MPW-TWO (June
Magic, Netgen, Fault and custom methodology scripts 18th tapeout)
for design exploration and optimization.  Most based on the
https://github.com/The-OpenROAD-Project/OpenLane Caravel harness

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 Not only cores – many IPs for a Platform
RISC-V Cores Peripherals Interconnect
RI5CY Ibex Snitch Ariane JTAG SPI Logarithmic interconnect
+ Ara
UART I2S APB – Peripheral Bus
32b 32b 32b 64b
DMA GPIO AXI4 – Interconnect
Platforms https://github.com/pulp‐platform/ M M M M
I M M M M M M M M
M M interconnect
M M MinterconnectM M
interconnect

O RV I interconnect
interconnect
I R5 R5 R5 RV

interconnect
interconnect

A RV RV RV R5 R5
cluster R5 RV
A O A RV RV RV
cluster
cluster O cluster
Single Core RV Multi-core R5 Multi-cluster
• PULPino • Open-PULP • Hero
• PULPissimo • PULP-PM • Manticore
IOT HPC
Accelerators HWCE Neurostream HWCrypt PULPO
(convolution) (ML) (crypto) (1st ord. opt)
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61-512.webp
61-512-1.webp

OSCHW to address key challenges

Energy

Security

Safety

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Research – XPULP ML extensions: RI5CY
PULP RI5CY – An Open MCU-class RISC-V Core for EE-AI
3-cycle ALU-OP, 4-cyle MEM-OPIPC loss: LD-use, Branch

ISA is extensible by construction

I, D mem IF tuned for low

latency & time borrowing

RISC‐V  V1
V1 Baseline RISC-V RV32IMC (not good for ML)
V2
V2 HW loops. Post modified Load/Store, MAC V3

V3 SIMD 2/4 + DotProduct + Shuffling.Bit manipulation, Lightweight fixed point

XPULP extensions: 25 kGE  40 kGE (1.6x) but 10x ML perf! |

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Product: GWT’s GAP8 IoT processor

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5

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Energy efficient OSCHW based Products?
FACT: prototype is prerequisite for product!

✘ prototype
(core,IO phy, tech,
MPW +$10M)
✘ product (+100M$)

✔✘ prototype (IO phy, MPW +2M$)

✘ product (+20M$)

✔ prototype, ✔ product (+5M$)

Edge/Mobile arXiv:2009.00993v1 [cs.DC] 2020

IoT Near-sensor HPC/Cloud |

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OSCHW to address key challenges

Energy

Security

Safety

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 Research – knowing how things “work” is vital
 From the “ZombieLoad” paper
From section 3.2, emphasis added for this presentation

“While we identified some necessary building blocks to observe the leakage (cf. Section 5), we
can only provide a hypothesis on why the interaction of the building blocks leads to the
observed leakage. As we could only observe data leakage on Intel CPUs, we assume that this
is indeed an implementation issue (such as Meltdown) and not an issue with the underlying
design (as with Spectre).”

 Closed implementations hide/abstract many secrets from users

 Being able to see inside and run experiments are vital for safety and security experts
M. Schwarz, M. Lipp, D. Moghimi, J. Van Bulck, J. Stecklina, T. Prescher, D. Gruss, “ZombieLoad: Cross-Privilege-Boundary Data Sampling”, arXiv:1905.05726

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Research  Product
 OpenTitan is the first
open source silicon
project building a
transparent, high-
quality reference
design for silicon root
of trust (RoT) chips.
 Founding Partners

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Research  Product
 OpenTitan is the first
open source silicon
project building a
transparent, high-
quality reference
design for silicon root
of trust (RoT) chips.
 Founding Partners

Leakage
resistant crypto
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OSCHW to address key challenges

Energy

Security

Safety

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PULP in Space: Protecting PULP from SEU
PULP

Fabric Controller CLUSTER

Scrubbing
RISC-V
DMA L1 Mem (TCDM)
core
ECC
Interconnect

Interconnect ECC
L2 Mem

RISC-V
RISC-V
RISC-V
RISC-V
RISC-V
RISC-V
HWPE Peripherals
core
core
core
core
core
core
C-TCLS
I/O
Configurable Triple core lockstep
icache

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Research  Product

OSHW for space and safety critical appls

Quantify failure rate due to soft errors

processor designs (similar approach for
automotive, servers, experimental
instrumentation, by adapting the error models)

 Detailed white-box analysis is possible

only for open-source (IP) cores
 OSCHW also helps with long-term
maintainability and helps avoiding
captivity

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Scaling up OSCHW industrial ambition
RISC-V Cores Peripherals Interconnect
RI5CY Ibex Snitch Ariane JTAG SPI Logarithmic interconnect
+ Ara
UART I2S APB – Peripheral Bus
32b 32b 32b 64b
DMA GPIO AXI4 – Interconnect
Platforms
M M M M
I M M M use-cases M M M M
Tens of activeMusers, M Mmany M interconnect
M MinterconnectM M
interconnect

O HW, I
RVSW specialization, verification,
interconnect
interconnect
documentation,
I R5
training R5 R5 RV

interconnect
interconnect

A RV RV RV R5 R5
cluster R5 RV
A Cannot be sustained
O
cluster
by one University, O or two…
A RV RV RV
cluster
cluster
Single Core RV Multi-core R5 Multi-cluster
• PULPino • Open-PULP • Hero
• PULPissimo • PULP-PM • MANTICORE
IOT HPC
Accelerators HWCE Neurostream HWCrypt PULPO
(convolution) (ML) (crypto) (1st ord. opt)
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Feel the momentum!
Ibex RISC-V core, flash interface,
communications ports, cryptography
accelerators, and more. Zero-Riscy Ibex

Vibrant repository

35+ Contributors
1300+ Contributions

470 GitHub Issues

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Academic open source  Industrial open source
Rick O’Connor (OpenHW CEO, former RISC-V foundation director)

 OpenHW Group is a not-for-profit, global organization (EU,NA,Asia) where HW and SW designers

collaborate in the development of open-source cores, related IP, tools and SW such as the Core-V family
 OpenHW Group provides an infrastructure for hosting high quality open-source HW developments in line
with industry best practices.

RI5CY, ARIANE

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OpenHW Group Ecosystem

Eval
Boards
GCC /
LLVM &
CV32 & OS
CV64 ports
Cloud Based SoC
Cores
Verification Protos
MPW
Layout
&
RTL Simulation Fab
Formal Methods
Stimulus

Verification is Key! |
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The role of public EU funding
 Facilitate prototyping of OSCHW (Europractice++)
 Tech. access and MPW cost (including substrate, packaging)
 Enablement (e.g. PLL) + IO/PHY (e.g. HBM) IPs cost
 Access to advanced EDA Tools + Expertise (e.g. advanced EDA cockpits)
 Design implementation support + Expertise (e.g. Backend, Packaging…)

 Nurture & Support the ecosystem

 EU Supported OpenHWGroup around RISC-V
 Develop commercial EU IP ecosystem with facilitated access for EU companies
 EU EDA tooling: research and companies
 Education-centric initiatives (+Training) Big risk: Fragmentation!!
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Luca Benini, Alessandro Capotondi, Alessandro Ottaviano, Alessio
Burrello, Alfio Di Mauro, Andrea Borghesi, Andrea Cossettini, Andreas
Kurth, Angelo Garofalo, Antonio Pullini, Arpan Prasad, Bjoern Forsberg,
Corrado Bonfanti, Cristian Cioflan, Daniele Palossi, Davide Rossi, Fabio
Montagna, Florian Glaser, Florian Zaruba, Francesco Conti, Georg
Rutishauser, Germain Haugou, Gianna Paulin, Giuseppe Tagliavini,
Hanna Müller, Luca Bertaccini, Luca Valente, Manuel Eggimann,
Manuele Rusci, Marco Guermandi, Matheus Cavalcante, Matteo Perotti,
Matteo Spallanzani, Michael Rogenmoser, Moritz Scherer, Moritz
Schneider, Nazareno Bruschi, Nils Wistoff, Pasquale Davide Schiavone,
Paul Scheffler, Philipp Mayer, Robert Balas, Samuel Riedel, Segio
Mazzola, Sergei Vostrikov, Simone Benatti, Stefan Mach, Thomas Benz,
Thorir Ingolfsson, Tim Fischer, Victor Javier Kartsch Morinigo, Vlad
Niculescu, Xiaying Wang, Yichao Zhang, Frank K. Gürkaynak,
all our past collaborators and many more that we forgot to mention

http://pulp-platform.org @pulp_platform