Design, testing and prototyping of a software
programmable 12C/SPI IP on AMBA bus
L. Bacciarelli, G. Lucia, S. Saponara, L. Fanucci
Dept. of Information Engineering,
University of Pisa
Via Caruso, 1-56122, Pisa - ITALY
Abstract- While power consumption and area occupation are
always critical constrains in System-on-Chip design, at the
same time high communication flexibility is required, due to
proliferation of communication protocols. In this work a novel
architecture for an 12C/SPI interface for APB AMBA bus is
presented, showing how it is possible to merge flexibility and
reduced area occupation. Large part of this work is centered
on the testing and FPGA prototyping of this IP. CMOS
synthesis results on 0.18 gm standard cell library are also
presented.
I. INTRODUCTION
In telecommunications, consumer and industrial
electronics, there are often many similarities between
seemingly unrelated designs. For example, nearly every
system includes:
* Some intelligent control, usually a microcontroller
core;
* General-purpose circuits like LCD drivers, remote
I/0 ports, RAM, EEPROM, or data converters;
* Application-oriented circuits for communication
interfaces and/or computation intensive task.
The general trend is to integrate all the components on a
unique System on Chip (SoC) that collects all available
blocks. In such scenario the reuse of intellectual property
(IP) macrocells is becoming the center of gravity for design
productivity and the key for being able to produce chips that
really work. All the integrated components must be
connected each other and every SoC must be linked each
other in an efficient way that allows a fast and error-free
communication. In industrial and automotive environment
the realization of networks of electronic control units (ECU)
is becoming even more crucial to handle the high quantity of
data requested by actual applications. The communication
among SoC is the key to grant high performances: the most
used solution for interconnecting SoC is a serial bus which
presents great advantage in terms of costs. Using few wires
to link different devices means few occupied area and
consequently minor costs for the producer. A large number
1-4244-0157-7/06/$20.00 p2006 IEEE
M. Forliti
SensorDynamics AG
Via Giuntini 25, 1-56123 Navacchio (Pisa), Italy
of serial protocols are actually used, so if a designer wants to
create a SoC that can communicate using various protocols
he must equip his system with a large number of interfaces,
despite the fact that when the SoC is on the field usually only
few of the supported protocols will be used. This means that
a large amount of area remains unused and on the system bus
are appended various useless structures. At the same time, if
there is not a pad sharing, a large number of pads remain
unused. Moreover a high number of pads lead to a pad-
limited structure that implies packaging problems and
increased product cost.
In this work an IP macrocell used as serial interface is
presented. The idea is to merge two different interfaces: a
Serial Peripheral Interface (SPI) and an Inter-Integrated
Circuit (12C) one [1] in a unique software programmable
structure. Taking pad reduction as a priority the pads are
shared between the two modules. The proposed IP cell was
originally developed for a single chip used in sensor signal
conditioning integrating a LEON2 [2] processor (32-bit
SPARCV8 architecture) and several interfaces appended to
LEON AMBA APB (Advanced Peripheral Bus) bus [3]. In
order to reuse the designed IP it is useful to note that a large
number of microcontrollers, like the wide spread ARM ones,
actually works with AMBA bus [4-6]: AMBA is becoming a
defacto standard for System-on-Chip buses.
II. 12C AND SPI STANDARD SPECIFICATION
12C is a patented protocol developed by Philips
Semiconductors. The 12C bus is a half-duplex, synchronous,
multi-master bus requiring only two signal wires: data
(SDA) and clock (SCL). It uses an addressable
communication protocol that allows the master to
communicate with individual slaves using a 7-bit or 10-bit
address. The 12C protocol allows three communication speed
ranges: standard (less than 100Kbps), fast (up to 400Kbps),
and high-speed (up to 3.4Mbps), each downward compatible.
12C bus distances are generally limited to on-board
communications, although it is possible to use 12C
successfully over distances of 15 meters. The true limit to
distances is the bit-rate and capacitance of the bus. As such,
for off-board communications, 12C is practically limited to
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less than 3 meters for moderate speeds. As shown in [7-9]
12C protocol is used in various IC with different purpose,
proof of its high flexibility.
SPI is a synchronous serial bus protocol developed by
Motorola and integrated in many of their microcontrollers
[10]. SPI bus consists of four signals: master out slave in
(MOSI), master in slave out (MISO), serial clock (SCK), and
active-low chip select (CS). As a multi-master/slave
protocol, communications between the master and selected
slave use the unidirectional MISO and MOSI lines, to
achieve data rates over 1Mbps in full duplex mode. A
disadvantage to SPI is the requirement to have separate CS
lines for each slave. As consequence for small, low-pin-
count microcontrollers, a multi-slave SPI interface might not
be a viable solution.
III. PROPOSED ARCHITECTURE
This 12C/SPI interface is a software programmable
device, working as 12C or SPI interface whose internal
registers are accessible through the AMBA APB bus. A
configuration bit allows the host CPU to switch from one
protocol to the other one. System clock division allows wide
range of bit rates for both communication protocols. The
design is fully synchronous and low power oriented. I/0
pads and internal registers are shared between 12C and SPI.
The block diagram of the device is shown in Fig. 1. It is
possible to see that the APB interface and the pin are shared
between the 12C and SPI modules. In this way the amount of
unused area is reduced to the minimum. SPI protocol uses
more pin than 12C (at least 4 instead of 2) so some pins are
SPI-dedicated while the others are shared between the two
modules. The IP is described in VHDL language and fully
integrate in the LEON environment; a high number of tests
are developed to grant functionality and compliance with the
standards requests.
IV. . VERIFICATION FLOW AND PROTOTYPING
The validation of the 12C/SPI interface has been
performed at different verification levels, starting from the
Figure 1. Block diagram of the 12C/SPI macrocell
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lowest one (single IP) and terminating with the highest one
(system); particularly the verification process was composed
by four steps in ascending hierarchy order: block-level, bus-
level, system level simulations and hardware emulation [11]
as shown in Fig. 2.
The block- and bus-level simulations aimed to verify the
IP functionality when it is considered as stand alone. The
checks were related to the reset condition (signals and
register values), to the register read/write accesses and to the
IP behaviour while performing its functionality. The IP-level
simulation requires a master agent (for register accesses), a
slave model (to be accessed by the DUT) and for bus
peripherals a bus functional model (BFM). At this level a
self-checking testbench using VHDL language has been
written.
The system-level simulation aimed to verify the correct
IP behaviour once it is plugged in a system. The main
difference compared to the previous phases is that in this
environment the host CPU was used to perform all
operations needed to verify the IP. This means that software
patterns in Assembly language were written to check its
functionality. The use of software to perform various checks
didn't prevent the self-checking characteristic to be
exploited: the expected results was written along the
Assembly code rather than in VHDL; finally the mechanism
to alert the user in case of failure was slightly different, using
some I/0 signals as flag to indicate the status of the test
(running, finished, successful or failed).
The host core used was the LEON-2 developed by the
European Space Agency (ESA) that is a 32-bit RISC
Figure 2. Verification flow
designed for embedded applications and targeting both the
ASIC and FPGA markets. A block diagram of the entire
system can be seen in Fig. 3.
SPARC defines general-purpose integer, floating-point,
and special state/status registers and 72 basic instruction
operations, all encoded in 32-bit wide instruction formats.
Particularly the integer units provides thirty-two general
purpose registers and grouped in overlapping register
windows. The alternate names of the registers and their
functions are summarized in Table I while the register
windows organisation is shown in Fig. 4.
The procedures of Transmission (TX) and Reception
(RX) that together with the Setup procedure were the main
calls of the interface drivers have been written using the
optimized leaf procedures technique described in the SPARC
V8 architecture manual [12]. A leaf procedure is one that
doesn't call (e.g. via CALL or JMPL) any other procedures.
Non-optimized leaf as well as ordinary procedures use a
SAVE instruction to allocate a stack frame and obtain a
register window for itself, and a corresponding RESTORE
instruction to deallocate it.
The time costs associated with this are:
* Possible generation of register-window overflow
/underflow traps at runtime. This only happens
occasionally, but when either underflow or overflow
does occur, it costs dozen of machine cycles to
process.
* The two cycles expanded by the SAVE and
RESTORE instructions themselves.
The space costs associated with this convention are:
* The space occupied on the stack by the procedure's
stack frame.
* The two words occupied by the SAVE and
RESTORE instructions
Of the above costs, the trap-processing cycles are
typically the most significant.
Figure 3. Block diagram of the LEON featuring 12C/SPI
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TABLE I. INTEGER REGISTER
Integer registers Alternate names Group names
%rO-%r7 %gO-%g7 Global registers
%r8-%rl 5 %oO-%o7 Output registers
%rl 6-%r23 %10-%17 Local register
%r24-%r31 %iO-%i7 Input registers
Figure 4. Register windows organisation
To improve the performance and to optimize the handle
of the peripheral, saving both time and space, the procedures
used for the 12C/SPI interface were made to operate without
their own register window or stack frame, using their caller's
instead. According with this policy have been used just
registers that its caller already assumes to be volatile across a
procedure call, namely, %o0...O%o5, %o7 and %gl.
The last step was the hardware emulation phase: the
system was being mapped onto a prototyping board and all
software patterns written for the system-level simulations
were compiled and loaded in the board memory. Each test
became a program running on the board and produced a
positive result in case the test for the interface was passed, or
negative result otherwise. This phase allowed useful timing
verification, since the IP was verified at system level in the
real hardware environment increasing the level of reliability.
The board used was a VIRTEX II (XC2V1000-4FG456C)
[13] based development board from Memec design [14]. The
P160 [15] expansion communications module which enables
further application specific prototyping and testing and
provides an 12C port and an SPI port has been also used.
First the LEON-2 core and the new IP added on the APB
BUS have been configured, then the synthesis with
Synplicity Synplify Pro [16] has been performed producing a
file in EDIF format. The synthesis results presented in Table
II are the total amount of lookup tables (LUT) used. In a
Xilinx Virtex-II FPGA circuit the LUT cells can implement
any logic function with up to four input variables. The
XC2V1000 has 10240 LUTs. Xilinx ISE [17] has been used
for place and route and programming phase of the board via
JTAG cable. The maximum working frequency is 33.275
MHz.
To probe the 12C BUS and the SPI BUS a digital
oscilloscope has been used then two commercial memories
 TABLE II. FPGA SYNTHESIS RESULTS TABLE IV. STATE-OF-ART SPI-I2C CONTROLLERS
Components Complexity: 4-input LUTs Module Area Max. Freq
50 MHz SPI/
12C\SPI Module 1049 LUTs SPI Controller 6600 gates 250 MHz
WISHBONE Bus
LEON2 7746 LUTs
LEON2 feat. I2C\SPI 8710 LUTs 12C Controller 4400 gates 3.4 MHz I2C
have been used to check in hardware the functionality of
both interfaces. Particularly a Serial SPI BUS EEPROM Synthesis results on 0.18 ptm CMOS technology are also
M95256 by ST [18] and a Microchip 24LC256 serial (12C) presented and favourably compared with the state-of-art. The
EEPROM [19] have been used. compliance to the 12C/SPI protocols and the interoperability
of the new interface have been fully verified.
V. SYNTHESIS RESULTS ON CMOS TECHNOLOGY
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