3D-3

Study on the Optimization of Off-State Breakdown Performance of p-GaN HEMTs

Fanming Zeng1,2,3,4, Qing Wang1,2,3,4, Shuxun Lin5, Liang Wang1,2,3,4, Guangnan Zhou1,2,3,4, Wei-Chih Cheng1,2,3,4, Minghao He1,2,3,4,Yang
Jiang1,2,3,4, Qi Ge1,2,3,4, Ming Li5, Hongyu Yu1,2,3, 4, a)
1
School of Microelectronics, Southern University of Science and Technology, 518055 Shenzhen, Guangdong, China
2
Shenzhen Institute of Wide-bandgap Semiconductors, Shenzhen 518100, China
3
The Key Laboratory of the Third Generation Semi-conductor, Southern University of Science and Technology, 518055 Shenzhen,
Guangdong, China
4
GaN Device Engineering Technology Research Center of Guangdong, Shenzhen 518055, China
5
Chengdu HiWafer Semiconductor Co., Ltd., 610299 Chengdu, Sichuan, China.
a) E-mail: yuhy@sustech.edu.cn

Abstract—Normally-off Gallium Nitride (GaN)
transistors with p-GaN gated technology for power
applications are studied for the optimization of off-state
breakdown performance. The gate-drain distance, gate
length, field plate length and its configuration have been
studied. Increase gate-drain distance will not only enhance
the breakdown performance but also increase the Ron, LGD
between 10 -20 μm is recommended. Extra gate length will
lead to the rising of the gate leakage current under high
voltage. The overhang length of the field plate is a critical
factor for breakdown performance, over placing the length
of overhang may result in an additional current leakage
path.
Keywords—p-GaN, HEMTs, Normally-off, Breakdown
I. INTRODUCTION
GaN-based III-nitride semiconductor materials offer
important advantages for HEMTs in the high voltage, high
temperature, and high switching frequency applications.
Polarization effects at the AlGaN/GaN heterointerface
induce high density of electrons. Thus, two-dimensional
electron gas (2DEG) channel is formed, enabling high
current densities and high cutoff frequencies for GaN-
based HEMTs [1]. Moreover, the large band gap and high
breakdown field strength of GaN-based III-nitrides allow a
high tolerance in the critical operations [2]. With the
important aspects of high current density and high
breakdown voltage, GaN-based HEMTs have great
potential for high power switching transistors. Normally-
off operation is essential for power-electronic applications
due to safety reasons, thus the structures such as gate
recess, fluorine incorporation, p-GaN gate etc., are
employed to achieve the enhancement-mode (E-mode)
transistors[3]. The HEMTs with p-GaN gated structure
exhibit a stable operation, are regarded as one of the
promising approaches to obtain normally-off HEMTs[4].
Intensive studies have been carried out to improve the
performance of E-mode GaN HEMTs, including threshold
voltage (Vth) [5], on-state resistance [6], current leakage
[7], off-state breakdown voltage [8], current collapse [9],
and other dynamic characteristics [10]. The off-state
breakdown voltage (BV) is one of the main limitations of
the power-switch performance. Improving BV while
keeping on-state resistance still low enough for high
efficiency operations is one of the most challenges in the
development of GaN-based HEMTs.
The high voltage capability of a GaN-based HEMT is
limited by many aspects, including leakage currents from
gate structure, buffer punch-through effect, channel region
breakdown, vertical breakdown through buffer and impact
ionization [7]. There are many solutions have been
proposed to improve breakdown voltage, such as: 1) the
application of field plates (FPs), 2) optimizing drain-gate
distance, 3) engineering of passivation film, 4) Fe- or
carbon- [11] doped GaN-buffer, 5) AlGaN back-barrier
[12], etc.
The FPs in a HEMT have the functions of redistribute
the electric field profile, and reduce the electric field peak
value. Thus, the BV performance and current collapse
effects can be improved. In addition, FPs structure would
not compromise the on-state resistance of the HEMTs.
There are many types of FPs, including source-connected
FPs, gate-connected FPs, multiple FPs [13] and multiple
gate FPs [12]. Many studies of BV performance are
focused on the device simulations [14], and the
performance of innovative structures [13]. The study on
the factors for optimizing off-state breakdown performance
of p-GaN HEMTs on practical devices is rarely reported.
In this paper, we have carried out studies on the
optimization of off-state breakdown performance of p-GaN
HEMTs. The gate-drain distance, gate length, field plate
length and its configuration have been studied on a 6-inch
GaN-on-Si wafer, important aspects on improving BV
performance have been discussed.
II. DEVICE STRUCTURE AND FABRICATION
The sample used in this study is a commercial 6-inch
GaN-on-Si wafer, provided by Enkris Semiconductor, Inc.
The epitaxy structure includes a 75 nm-thick p-GaN layer,
a 15 nm-thick Al0.2Ga0.8N barrier layer, a 0.8 nm-thick AlN
layer, a GaN channel layer and a 5 μm-thick buffer layer.
The p-GaN gate was etched by inductively coupled plasma
(ICP) process. The alloyed ohmic contacts were composed
by Ti/Al/Ni/Au [15]. A rectifying contact was formed by
Ti/Au for gate. Two SiNx layers deposited by PECVD
were used for the passivation. Devices were isolated by N+
ion implantation. Process details can be referred in Ref
[16]. The cross-sectional schematic of the device structure,
the fabricated 6-inch GaN-on-Si wafer, and the device
image are shown in Fig. 1. As shown in Fig.1 (a), the
length of gate-connected FP and the source-connected FP
are defined as G-FP and S-FP, respectively. The thickness
for Dielectric-1 was about 100 nm, and for Dielectric-2
was about 300 nm. For all devices, the distance between
source and gate were fixed at 3 μm. And 4 separate device
groups have been designed and fabricated for the study of
device BV performance.

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 • The variations of the distance between drain and
gate (LGD), including 3 μm, 5μm, 10μm, and 20
μm.
• The variations of the gate length (LG), including 2.5
μm, 3.5 μm, and 4 μm.
• The variations of the overhang length of gate-
connected FP (G-FP), including 2 μm, 4 μm, 6 μm,
and 8 μm.
• The comparation of gate-connected FPs, source-
connected FPs (S-FP), and the combination of
source/gate FPs (SG-FP).
(a)
(b) (c)
Fig. 1. The diagram of device structure (a), the fabricated 6-inch
GaN-on-Si wafer (b), and the device (c).
A control group was used for comparison, and the
parameters of the devices were fixed as LG=3.5 μm and
LGD=15 μm. Moreover, two kinds of gate width (LGW)
were employed: 20 μm for low current devices and 500
μm for medium current devices, respectively. All the on-
wafer measurements were performed using a Keysight
B1505A semiconductor parameter analyzer, together with
a Micromanipulator P200L probe station. For the BV tests,
the maximum force voltage and the current of the high-
voltage source monitor unit (HVSMU) are ±1500V and ±8
mA, with the measurement resolution of 200 μV and 10
fA, respectively. The current limit of BV test was set to be
2 mA.
Fig. 2. DC I-V characteristics of a p-GaN HEMTs from the
control group, (a) output curves measured with VGS stepped up
from 0-9 V, (b) transfer curves measured at VDS=1 V.
The off-state breakdown characteristics were evaluated
with the 3-terminal configuration. The VGS was set at 0V,
while the source terminal was grounded, and the substrate
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terminal was floating. The fabrication did not contain the
back-end-of-the line (BEOL) processes for simplification.
During the measurements, the devices were covered by
Fluorinert to avoid from arcing. Each type was measured
more than 10 devices on the wafer in order to perform
statistics analysis.
III. MEASUREMENT RESULTS AND ANALYSIS.
Fig.2 show the typical DC transfer and output
characteristics of a p-GaN HEMTs from control group, of
which the LG=3.5 μm, LGD=15 μm and LGW is 20 μm. It
can be seen that the maximum drain current reaches 350
mA/mm at VGS=9V, the Ron is about 14.2 Ω·mm, the
threshold voltage is larger than 2 V. The device exhibits
an on/off current ratio of higher than 1×107.
Fig. 3. Off-state breakdown characteristics for the variation of
LGD, including 3 μm, 5μm, 10μm, and 20 μm. (a) ID and (b)
standard deviation of ID. (c) Drain current and Ron as a function
of LGD.
The off-state breakdown characteristics for the
variations of LGD in the 1st group are shown in Fig.3. In this
group, the fixed structure for all devices are LG=3.5 μm
and LGW=20 μm. LGD was designed for 3 μm, 5μm,
10μm, and 20 μm. As shown in Fig.3 (a), LGD has a
significant impact on the device BV performance. For LGD
=3 μm, the devices could not survive even for VDS=300 V,
the leakage current can easily exceed the limitation. With
the LGD increased to 5 μm, the BV voltage extends 600 V,
but the average drain current also ramped quickly. Device
groups with LGD =10 μm and LGD =20 μm exhibit better
performance in the BV test. The off-state breakdown
voltage for both of these two types can achieve at 1000 V
with the leakage current still under the limitation. It is
clearly that the leakage current is remarkable restrained by
increasing the LGD distance. However, increasing LGD
distance would not always improve the breakdown voltage
[17]. Generally, in our case, the device groups with LGD
between 10 μm and 20 μm could achieve an appropriate
off-state current leakage under the stress below 1000 V.
 Moreover, with the increase in the distance between
drain and gate, Ron also increases at the same time. As
presented in Fig.3 (c), IDS reduces due to the increase of
LGD, and Ron increases linearly with LGD at the given range.
In the 2nd group, the gate length has been designed for 3
types, 2.5 μm, 3.5 μm, and 4 μm. LGD and LGW were set at
15 μm and 20 μm, respectively. As illustrated in Fig.4 (a),
the off-state drain leakage current curves for all the 3 types
are comparable under 1000 V. However, when we take a
close look at Fig.4 (b), the gate leakage current curve of
the device type with LG=4 μm rises faster than the other
two types when exceeding 800 V. The standard deviation
of the gate leakage current for the devices of LG=4 μm
keeps stable which indicates a reliable result. One possible
reason is that the relatively large gate area for this type of
devices contributes extra current leakage paths. Generally,
increasing gate length helps to prevent the punch-through
of the HEMT device. But based on our data, the devices
with LG=2.5 μm have already provided an excellent
current blocking in the channel, further increase the gate
length only leads to the deterioration of gate leakage and
creating high Ron, as shown in Fig.4 (c). It should be noted
that the threshold voltage increases as the extending of LGD
or LG, shown in Fig.3 (c) and Fig.4(c). Long LGD results in
a lower electric field between drain and source, and large
gate area enhances the carrier depletion.
Fig. 4. Off-state breakdown characteristics for the variation of
LG, including 2.5 μm, 3.5μm, and 4 μm. (a) ID, (b) IG, and (c)
drain current and Ron as a function of LG.
The devices in the 3rd group were designed to
evaluate the gate-connected FPs. Gate-connected field
plates were formed in the region between gate and drain.
The overhang length of gate-connected FP varies from 2
μm to 8 μm, with a step of 2 μm. Fig.5 displays the BV
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measurement results of this group. The drain leakage
current can be improved by the employment of the G-FP
for almost all types due to the redistribution of the electric
field profile. The high electric field strength at the gate
edge is alleviated. For the structure of G-FP=8 μm, the
off-state drain leakage current curve trends up quickly for
drain voltage higher than 800 V. This phenomenon may
be attributed to two main reasons. On one hand, by
extending the overhang of FPs, the distance between FPs
and drain is getting close to each other, the dielectric film
of passivation layer will sustain a higher voltage. If
thickness and the quality of the dielectric film are not well
managed, high current leakage would be expected. On the
other hand, the reduced distance between FPs and drain
pad could evidently increase the leakage current at the
surface or interface of the dielectric films. Thus, the FPs
engineering is an important aspect to achieve excellent
BV performance.
Fig. 5. Off-state breakdown characteristics for the variation of
G-FP, including 2 μm, 4 μm, 6 μm and 8 μm.
In the last group, as shown in Fig. 6, 3 different
combinations of FPs were studied. The device structure in
this group is different from all of the 3 groups above. The
LGD, LG, LGS, and LGW were designed to be 10 μm, 5 μm, 4
μm, and 500 μm, respectively. S-FP and G-FP were 3.5μm
and 1.5μm, respectively.
Fig. 6. Off-state breakdown characteristics for the gate-
connected FPs, the source-connected FPs, the combination of
Gate-connected and source-connected FPs, and the control group.
There are 3 types of FP configurations in this group,
gate-connected FPs, source-connected FPs, and the
combination of Gate-connected and source-connected FPs.
As can be seen from the statistics data, comparing with the
control group, all these 3 kinds of FPs have the function of
reducing current leakage under 900 V. But devices with S-
FPs and the SG-FPs have a superior performance in
leakage current control compared with the G-FPs. It should
be noted that there is a dielectric layer between S-FPs and
G-FPs, which may help to suppression the leakage path
between FPs and the channel. However, some simulations
with SiO2 passivation layer have a different result [18].
The dielectric materials may contribute to this result.
Further studies on BV performance with different
dielectric films of passivation layer is under preparation.
The device performance of p-GaN HEMTs studied in
this paper is plotted in the specific on-resistance versus
breakdown voltage benchmark and compared with some
enhancement-mode p-GaN HMETs in Fig.7. Devices with
Ron, sp of 2.8 to 3.4 mΩ·cm2 can sustain an off-state VDS of
1000 V. And devices with Ron, sp of 5.2 to 6.8 mΩ·cm2 can
sustain an off-state VDS of 650 V.
Fig. 7. The specific on-resistance versus breakdown voltage
benchmark.
IV. CONCLUSION
A systematic studies has been carried out to investigate
the important aspects related to BV performance of the p-
GaN HEMTs. The gate-drain distance, the gate length, the
field plate length and configuration have been discussed.
Increase gate-drain distance can not only enhance the BV
performance but also increase the Ron. LGD between 10 - 20
μm is recommended for the devices working under 1000
V. We find extra gate length could lead to the rising of the
gate leakage current. The overhang length of the FPs is a
critical factor for improving BV performance, but
overhang with over extension may result in an additional
current leakage path.
ACKNOWLEDGMENT
This work was supported by:
1. Research and Application of Key Technologies of GaN-based
Power Devices on Si Substrate (Grant No: 2019B010128001)
2. Study and optimization of electrostatic discharge mechanism
for GaN HEMT devices (Grant No:
JCYJ20180305180619573)
3. Research of AlGaN HEMT MEMS sensor for work in
extreme environment (Grant No: JCYJ20170412153356899)
4. Shenzhen Institute of the Third Generation Semiconductors,
Basic Research Institution of City of Shenzhen
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