Microproce ssO Aschitectue and openation of its componens

Data bus

Regis tens Enput

Memoay Output
Centaal Paocessing Unit
Device
Unit (CPU)
cU
ALU ClocK Address
Bus

L - - Contaol
Signol

Fig: qenehal a^chirectue of micxopsocessoA

unit peaforms mathematical

and ogic Unit CALU) -
Asithmetic This
Computations such a s addition,
ike
subtaaction, division and boolean funchons Clegical ope2ations
AND, OR etc ) The ALU also executes compaaisionS and lcgica
testing
thanSmits sianal to Hhe ALU , whrch intenprets
The CPU OA processo
the tnsthuctio0 and perform the calculation.
ane. used to hold o store binaly data
Kegisteis - Reaistes
Hhese reg istens Can be uwecl to store
tempoha .

geneal dafa, Dstauchon codes, intenmecliate Aesult ot any legica

0 mathermatical opesation.
1stauchon
Someegisfeis e alsO Used as pat of a
such as Accumulato (A ). most common neg iste^s of miCTO PYOCesser
ane Prgram Counte (Pc) , stock pojnte ( SP) , intauction egiste
buch
Contaol Unit -; Conthol unit consists of different components
as Instuchion decodel, cleck ei^cuit, conthol

togethe to Heceive and

lcgic cincuits. All hese Components wosk
thansmit bgnols rom diPferent Compon
ents of micropToce sse
Instauchion decoele inteprets he 1ostsuchèn
foA erample phe
gnd toke achon qccoding tothe idstauchon.
)The cloc sends slgnal thak snchronige and ensyae timely
execution of Ims tAuchon and phocesse
Buses- MicrOproce ssOs have q Sustem ot buses to move di terenr
type of clata
*) The data bus transfes data bettoeen he CPU and RAM
)The Contaol bus Sends Dece ssa 19formahirn to CoOAdi nate and
ContAel multiple taskss
X) The acddress bus holds Hhe address of RAM ROM OCations.
Cache MemoAy - Some advonce micropsoce ssOAS have memoh Cache,
which 94etains the iast data used by Hhe cPU
*) Memoy caches speed up Hhe computing proce ss , because the CPU
does net have to go to the slowe RAM to 1etieve data
Addve Ssing Modes
The opesation tield of an instsuction specifies he opesnrion to be
The
peafomed. Hhe way any opAahd 1S selected dusing Hhe p%ogtan
executien s dependent cn Hhe addressing mede ot the instauetim
Hhe fosmat of instauchon is 9iven beloud

Opcode opeiand

opeation codle oPesand can be 1 ,2 0 3

which spectnes whese the operahon
Specihes he tpc
hao to be pertormed
ef opeatiom
The pupose of usíng addressing mode is as follows
to the Use.
i)To give the programming Vensatality
numboe ef bits n addressing field ot instruehion
) To 1educe the

Type ot Addressing Medes-

In this mode. opc.and 1s specitied in Hhe
1) Tmmediate mode -
instauchèn itself
ADD which says Add to The Contents o+ Accumula
xp he.
i s he ope^and

2) Registe mode Ln his mode Hhe operand is stovad io he

Kegi'stes

OpcodeRegiste address

egis tens in cPU

3) Register. incineeh mode In his mode he instkuction speutnes
whose contet u He
the egiste give
address of ope>anol stored tó memov
*The
negish. centains Hhe address hathe Han ope^nnd itself
Opcocle Registe R Memo

opesAnd

Registers in CPU

4) Disecet addressing mede - In Hbis mode, effective addresS oT

opehancdis present n Hhe inshsuehicn itsel

Memo
opcocde Adress

6 pesand

4oCOH.
CXPADD B, 4ocoH udd Hhe contentof B with contentot
Here 4co0H 1S Hhe effechve address whesa opcud s Presen

mede In his mode, theinst?2uchion &o1\l

5) Tndisec addressing where the eHective
Hhe adcdress
Aive
address s stored 1o Hhe memoy

This mode slows doon he execuHon.

opcode Address

Pointes to
pesancd

peund
6) Displace mentt O Index addreseing mode - In his mode the

Content of indexed
registe 1s qdded to h e oddess past of the instauctiom, to

obtain the effecthve addresS of opcsan Pnegste

AddresS aiven in Instruchon + 9dexed Value
Efecive addvess

Index
Opcode Regste ER) Addvess A
BsL value

Aisplacement
opeAand

Pointeto
opesand +

Kegistes.s t CPU

Exp ADD R4 1oo CR1)

Tndex 1eg1stes
Base Value
EA loo + (R1)

T h e Displacermet ao be defthel by Indexed Hegises ,

Prcgvam Ceunlë On
aoy novmal Hegistes

The displacement is efeftned by psoqrem Ctuntes

EA A +(Pc)
Exp- ADD R4 1oo(Pc)
FA leo+ (Pc

7 t h e cdisplacement s by nosmal eg stens enl.

EA (RL) +(R2)

Exp ADD R4, ( R +R2)

He FA (Ri) +(Rz)
 Instauction Gycle
An insthuchion cycle 1s also Roown as etch- de code - execute ycle
this phoce ss is Hepeatecd Cotinueusly by CPU rom beot up( staztina
tun ON) to shuet doton of Compute..

tollewing asa the steps that occu. dusing Hhe instauchen cucle.
)Fetch he instAuchom s)The Iistucthion is fetched from the memo
*) +he address of the memory location oill
bc

iven by Hhe phogrom Couotes C PC).

xAttes fetching Iisthuehien T%em memont it s pla ceel 19

Hhe IR

InstsucHon Rege'stes)
Attesetching opesahm PC s automatically I6vemented L

thec Dstauchen placed in TR 13 decodeel

Deccde Hhe instuch) -:
by Hhe decocde

3 ) Read1he efective address- if Hhere a an address, the

Indihect
efechive qddresS is Head. fsom He

memo
4) Execution ot ostsue thon- The Contsol unit passes the Sgnaf
tothe funchonal uit of CPU to
czecute the operathien given by instruetien. the esult gen ehafkel
S Stohedl 1n the maln memony a s Sent to an outrut devjze

(Stast)

Loac Addaess to PC|

Locid Content ef pc
to IR

update PC to next
CiddresS

Fxecute Tnstuc Hm

NO Yes
Tnterruph 3avice Iotemt
 Data Trons fes
Schemes
We can connect Sevesal Ioputloutput and memont peuph als
micYo proce sso devire may difle in he speed ef cpeatien
Al hese
und data tyansfe.
Usually, when memany cennected to wih the micropsoES
Hhere s not a
maj0s difference t the processing sperel
But Hhe paoblem asi ses cohen exteal peaiphegls Ghe
Connected as iopu/tutput. A sloco ilo device won't be able to
tr2anstc dato at a satisfact7y nate. his might lead to seveje
data losses, o the cevice might get
cdamagecl. to avoid his
pToblem, a numbe of lata tiansfes schemes have bcen 1fLoduea

Data Transfel Schemes

PanalleL Data Tyansfes SeiaL Data Transfer

Synehrenous Transfe
Data
1) Paogrammedbata Transfe 1
2: Asynchvonous Dats Tran sfes
i)Snchrenous
1) Asynchncus
2) Intenupt D'siven Data Transfe
3) Device as. DMA Dats Transfes
) Busst o Block Tronafe. DMA
I1) Gycle steal on Single cuyke byTe tsanste DMA

hidden DMA
I) Transpaient o»

Pregsammed Ilo Data Transti

deviee to CPU/memosy
Data ane thanstersel sm an Ilo

9nc Vice - Vessa

u used cohen ámall ameyot dats

*) this type of thansfer
has to b2 t h a n s e e l
are used 1 Synchonous n 8jei
*IN gnd OUT 1stfuchc)S
thi's mode
READY Sgo uwc1 Asynch scncuS tanstoi.
mede
S also kooo) as handshaRilg
Intessupt Oniven olata Tronstes
oith pgsammed Tlo transte ts That CPU has to
The problem
watt long time fon the Ilo devi(e to be teadyto thans mis410
0 neceptien of dats.
CHIGH)
) I n the intenupt daiven mode, the ilo devjre yaisesa specia
Signal Called Intesnupt ,when he becomes Heady to transte
clata
OMA Tronsfes
amount
*)This type et taansfer is uaed Cohen theie s a buge
of datg have to be taansfessed
buses to eztesnal olerice. foi
The CPU 4elea ses the Contsol of
lata transfen
busesS
*)A pcsiphejal device cal|eek DMA Controlle taks ovesthe
the peiphes and the
and manage the trnsfes disectly betuoeen

Tmemo ransfer scheme

schemes
This t h e tastestgmmg all he
 Timing Diag
The timing diogan of microprecess0A. teprsants following tesms
No of clock Cycles used
) Dusation, delay and content of addrss bus
) Type ot* epesatien(head (rite| status sigat)
with he help ot timing diag vam , one cen udestpnd the
ocsRng
oteach nstAucthe and its executie
Impostaot tems helated to timing diagam
Instuchon cycle- 9t is defined as the no. of steps (clock
cycles) equisad by the cPU to Comple te
he entise prccess ( Fetching and exe
Ceution of nstuction)
2. Machine Cycle
9t is the time Sequised by the psecessO
to
complete he
opesatien of
I) accessing the memos
O
1) acceSsing the Ilo device
In machine cycle vaaieus opesahions ae pe>fosmed like

)opcocdle Coperation Code) fetch from memery

*) MemoTH 1ead On wute
)Ilo heae os write
3. T-State S- Each clock cyele 1s called as T- state.

T T6 T

Machine Cyele
Fetch Cycle CFc) Machine
k
Cy cle 2
Execution Ccle (Ec)

Instauction ycle

Instauchion ycle =
opeoce feteh cycle (Fe)+ Execuhon Gycle (Ec)
Machine Cycle 1 Machine Hcle2
 "6
process duing opcodc fetch
gene rates address, where Code is
)Dusing Ti state - PC.
stosed
D u n g T2 state - opcode i htad to be hocd by the psocessen

Dusing T3 state opcode is stosed t the insthuetion egiste

ill decode. the opcode and phevide
)Duaing T4 state Phocesso
hece ssOAH actions

(
 Intomupts
is he methed of Cieahing halt dwing
Intesmupt a
tem posay +he
acc e s s
pYogram exeuution gnd allowS peiphe^aL devices to
micropTOCess0
ifh
he miCre psdCessOA qes ponds to that inteaupt
an ISR (Intesnupt Seavice Routine) , whích 1s a short pwgTam?
t instauct h e microproces s O on how to hadle the intenupt

Totenupt
Hardwane IntesTupt Sehtwere Inteupt

Maskable Non mabkable

Inteup Tntesupt
Creafed
A hordwae intesiupt s nosmally
Handwane Toterupts-
oy the exte^nal device such a8 mouse,

Keyboa.d, pendaive ctc

touch bcreen, we
on a
ves. we click a mouse O top
Whene
Aend ao intesupt sgol to Hhe proce sSOA.
Sewice Queue
)Each input ond output device has a unique tnteupt
be that multiple devjces do not Cacate CoDlict.
seting cA phionity
cngbled /disabled be
intelupts Con
these
i) Maskable Tntenupts insTAuctions.
by using9 PTogTomming
Exp- INTR

hese inteuptS have bigh pnionity

) Non Maskable Inteuprs-
He proce ss0A
han mas kable intesmpts.
in ony cihLumtances
Con not ignone the non-mas kable intempr
Exp-timeouut Signal frem
times. ciauit.
powe docon Signals

Sotuant inteAupts a c u sed to handie ezro rs

SottuoaAc inteiupts - while a
gnd excepticns thar occu progsam

unin9
alloos h e pscgtam nGde the ChscA betere
these inteupts

continuing
interrupts ne also us ed To bHeak an intinite loop, obich
+hese
uld Cause progon be unsespon Cive
 Memovy
Add re ss Mne monics
2 o00
LXI SP,2 400 (H)
2003 LXI B, OoooCH)
2 006 PUSH B8
200 POP PSW
200 8 CALL DELAY ,DELAY storting at 2064lH)
OUT o1(H)
201 O HLT
2064 DELAY PUsH H
2065 PUEH 8
Save to 2066 LXI B,80FFCH)
STACK 20 69 L1 Ocx B8
206A MOV A, 8
206B ORA C

206C JNZ L1
206 F RET

*) When CALL IÖStsuctibn Executed he Poqam flou wil)

tronsfea from main progrom +o subrouhine DELAY). this
is accomplished by plaeing Hhe stasting address of sebvoutine
into poqtom counte.

)Before chonging he content of PC, Hhe addess of nezt

to CALL fnstsuction C200E) must be 3oved , So Hhat atter
execution of subvoutine
main pro9om Can execute
to sove Hhe Content of Pc ( 200E) 1ótesnal PUSH ope
ation pertormed by he
mic voprocessov. attes stoning Hhe
content
content of
of P
PC ne content is loaded 1nto
,
psogram couotey.
*) Nhen RET 's erecuted he content ot STACK 1a setrieved

qnd oodec into pOram Counten .

Advanced
subroutine Concepts Fr
From ti now we hove seen Hhat
Cwe call Subrouhine mutiple
+imes Other
P e ot
can a
here subsoutines ore also Used shich ove
discuS Sed
Nesin9- he
proaromming
Onothe
technique of
coil a
guboutine
colls Subroutine is
calied nesting ohen a bubroutine
onothe subroutine oll retusn addresS
address ore
ore stored
stored ió STACK.
2000
2001
2090
2050 CALL
2051 90 209A 20C2
2052 20 2098 CALL 20C3
2053 209 c2 20C4
2054 209D 20
2055 209E
RET RET
Man Paoham. subroutihe 1 Subhoutine 2
Multiple Ending SubrDutino ww
In his technique when a subroutine is
executed, Hhere úse 2 conditional
eturns CRZ and Rc) and one Un-
conditional Retusn CRET).
RZ 250CH
)if Hhe zero flag is set fe z=1 Hhen
SubroUtime caill retsn from 205o(H).
) i f he corty flg is set e c=1
Hhen subroutine ill returm
RC 2058 CH)
fron
2058CH
| RET 207otH)
Subroutno