Samiksha Gautam Permanent Address

M.tech(VLSI) H-304 sethi max royal

Email:gautam.samiksha4444@gmail.com sector 76 noida (UP)
Phone:+91 7669004821 Pin:201301

EDUCATIONAL QUALIFICATION:
• Qualified UGC N.E.T. examination, June 2019.

• M.tech (VLSI) from Indira Gandhi Delhi Technical University with first division with
72.82% in year 2018.
• B.tech (Electronics &Instrumentation) from M.J.P. Rohilkhand University with first
division with 72.12% in year 2016.
• Intermediate from Delhi public school CBSE board, with first division with 61% in year
2012.
• Higher school from Delhi Public School, CBSE board with first division with 80% in year
2010.

WORK EXPERIENCE
2 years teaching experience in government university.

RESEARCH EXPERIENCE
M. Tech Final Year Project

Title: Capacitor Less Low Dropout Regulators

Detail: I have successfully Designed the external capacitor less low dropout regulators
architecture. The purposed work shows that external capacitor is removed completely and the
transient response of the system is also enhanced with varying load current from 0mA to 100mA
providing a stable dc output voltage of 1.8V with dropout voltage of 0.2V and have settling time
of 0.1 s. The experimental results shows that it has a better transient response as compared to
already purposed work. Entire Project is done in LT spice XVII. This project is done as a part
of Research assistantship at Semiconductor Laboratory ISRO(Chandigarh).
 M.Tech Semester projects

Title: Low Power CMOS Encoder Using FinFET. Detail: A 4-input, 2-output priority encoder,
is implemented using FinFET technology. This work was implemented on various technology
nodes such as on 45nm, 32nm, and 7nm and accordingly the average power, leakage power and
leakage current is calculated and compared. Tool used synopsis.
B.Tech. final year Project

Title: Improved PEGASIS routing protocol for wireless sensor networks.

Detail: In this project, we describe PEGASIS Protocol which is based on greedy chain algorithm to
maximize the network lifetime. Fixed path sink mobility model is used. Tool used is Matlab.

COMPUTER SKILLS

Languages: C, Verilog, VHDL.

Software: Cadence Virtuoso, Lt Spice, Modelsim.

TRAININGS

Worked as an intern in Semiconductor laboratory ISRO Mohali (Chandigarh) for six

months.
Worked on project named FIFO using Verilog for six months as a trainee at Tevatron
(Noida).
Industrial Training from NTPC Limited (A Govt. of India Enterprises) on Power Plant
Control & Instrumentation systems.

PERSONAL DETAILS:
Name: Samiksha Gautam
D.O.B: 01-01-1995
Father’s Name: A.S. Gautam
Father’s Occupation: Manager (HR) NTPC
Mother’s Name: Pushpa Gautam

Declaration I do hereby declare that the above particulars furnished by me are true to the
best of my knowledge and belief.