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2. ADDWF
ADD W to f
Syntax: ADDWF f [,d] [,a]
Operation: (WREG) + (f) → dest
Status Affected: N, OV, C, DC, Z
Description: Add WREG to register ’f’. If ’d’ is 0, the result is stored in WREG. If ’d’ is 1,
the result is stored back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected. If
’a’ is 1, the Bank will be selected as per the BSR value.
Example: ADDWF REG, W
3.ADDWFC
ADD WREG and Carry bit to f
Syntax: ADDWFC f [ ,d [,a] ]
Operation: (WREG) + (f) + (C) → dest
Status Affected: N, OV, C, DC, Z
Description: Add WREG, the Carry Flag and data memory location ’f’. If ’d’ is 0, the result
is placed in WREG. If ’d’ is 1, the result is placed in data memory location 'f'. If ’a’ is 0, the
Access Bank will be selected. If ’a’ is 1, the Bank will be selected as per the BSR value.
Example: ADDWFC REG, W
4. ANDLW
AND literal with WREG
Syntax: ANDLW k
Operation: (WREG) .AND. k → WREG
Status Affected: N, Z
Description: The contents of WREG are AND’ed with the 8-bit literal 'k'. The result is
placed in WREG.
Example: ANDLW 0x5F
5. ANDWF
AND WREG with f
Syntax: ANDWF f [ ,d [,a] ]
Operation: (WREG) .AND. (f) → dest
Status Affected: N, Z
Description: The contents of WREG are AND’ed with register 'f'. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If ’a’ is 0, the
Access Bank will be selected. If ’a’ is 1, the bank will be selected as per the BSR value.
Example: ANDWF REG, W
6.BCF
Bit Clear f
Syntax: BCF f,b
Operation: 0 → f
Description: Bit 'b' in register 'f' is cleared.
Example : BCF FLAG_REG, 7
7. BN
Branch if Negative
Syntax: BN n
Example: BN 7
8.