International University

School of Electrical Engineering

Digital Logic Design Lab

EE054IU

Demultiplexers
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Date Performed: April 12th, 2023

Date Submitted: [insert date]
Lab Section: Lab 3
Course Instructor: M. Eng Trang Kien

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Table of Contents

List of Figures ........................................................................................….…..............................

2
List of Tables .................................................................................................…….......................
2
Nomenclature ...........................................................................................................…….…....... 2
Theoretical Background .............................................................................................……..........
3
Experimental Procedure.............................................................................................……...........
3
Experimental Results ........................................................................................................……...
4
Discussion of Results ...................................................................................................................
4
List of Figures
Figure 1.1a – …………………….……...……………………………………………………...
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Figure 1.1b – ………………………………………………………………..……………........ 5
Figure 1.2a – ………………………………………………………………………………….. 6
Figure 1.2b – ………………………………………………………………………………….. 7
Figure 2 – ……………………………………………………………………………………... 9
Figure 3.1a – ……………..........................................................................................................
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Figure 3.1b – ……………..........................................................................................................
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Figure 3.2a – ……………..........................................................................................................
12
Figure 3.2b – ……………..........................................................................................................
10

List of Tables
Table 1.a – ……………………………………..…………………….......................................... 4
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Table 1.b –
……………………………………..……………………........................................... 5
Table 2 – ……………………………………..……………………........................................... 8
Table 3 – ……………………………………..……………………........................................... 10

Discussion of Fundamentals

Experimental Procedure

1. Design demultiplexer using logic gates

a. Design 1-to-2 demultiplexer using logic gates:
A 1-to-2 demultiplexer has I is the input, S is the selector input, and Y1 and Y2 are two
outputs. When S = 0 then Y0 = I but when S = 1 then Y1 = I. The Figure 1 shows the
illustration of DEMUX 1-2.

Figure 1. The illustration of DEMUX 1-2.

Built the truth table:
Input Output
S I Y 0 Y1

0 0 0 X
0 1 1 X
1 0 X 0
1 1 X 1
Table 1.a

The expressions:
Y0 = S’I
Y1 = SI

Implement the circuit via simulation software and paste the result in here

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 Figure 1.1a

Implement the circuit on the board and paste the result in here

Figure1.1b

Make comment on the results

b. Design 1-to-4 DEMUX using logic gates.

Build the circuit. The inputs S0, S1, I, are driven by 6 switches. The outputs Y0, Y1,
Y2, Y3 are connected to LED.

Table
Input Output
S S I Y Y Y Y
1 0 0 1 2 3

0 0 0 0 X X X
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 0 0 1 1 X X X
0 1 0 X 0 X X
0 1 1 X 1 X X
1 0 0 X X 0 X
1 0 1 X X 1 X
1 1 0 X X X 0
1 1 1 X X X 1
Table1.b

The expressions:
Y0= S1'S0'I
Y1=S1'S0I
Y2=S1S0'I
Y3=S1S0I

Implement the circuit via simulation software and paste the result in here

Figure1.2a

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Implement the circuit on the board and paste the result in here

Figure.1.2b

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Make comment on the results

2. Investigate IC 1-to-8 DeMultiplexer (74HC238)

Construct the circuit as below:

- 8 outputs are connected by using LEDs.

- The inputs are controlled by switches.
- Observe the results and fulfill the truth table

INPUT OUTPUT
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Table 2

Implement the circuit via simulation software and paste the result in here

Figure 2

Briefly describe the operation of the IC

3. Design 1-bit Full Subtractor

a. Using logic gates
Construct the circuit as below:
Three inputs are A, B, Bin. Two outputs are D and Bout.
Build the truth table and the expressions
Input Output
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
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 1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Table 3
The simplified expressions:
D=A’B’Bin + A’BBin’+AB’Bin’+ABBin
Bout =A’B’Bin+A’BBin’+A’BBin+ABBin= A’Bin+A’B+BBImplement the circuit
via simulation software and paste the result in here

Figure 3.1a

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Implement the circuit on the board and paste the result in here

Figure 3.1b

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Make comment on the results

b. 1-to-8 DeMultiplexer (74HC238)

Implement the circuit via simulation software and paste the result in here

Figure 3.2a

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Implement the circuit on the board and paste the result in here

Figure 3.2b

Make comment on the results

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