DCIT

203
DIGITAL AND LOGIC SYSTEM DESIGN
Session 13 – Sequence/ Pattern Detector
Lecturer: Dwumfour Abdullai Aziz
Email: adwumfour@ug.edu.gh
Mobile: 0260541219

UNIVERSITY OF GHANA
College of Education
College of Education
School
School ofofContinuing
Continuingandand Distance
Distance Education
Education
2021/2022
2014/2015 – -2016/2017
2022/2023
 SESSION OVERVIEW

The session introduces student to the design

principles and procedures of Sequence / Pattern
detector. It focuses on the design of FSM for
sequence /pattern recognition using Moore/ Mealy
Models. State diagrams for Moore and Mealy Models
will be explored.

Dwumfour Abdullai Aziz Slide 2

 LEARNING OUTCOME
At the end of the session, the student should be able to:
q Understand the Moore and Mealy Models of computation
q Become familiar with the design of FSM for pattern
recognition
q Design a sequence detector using Moore and Mealy
Models
q Understand overlapping and non overlapping conditions
in the design of sequence detector.

Dwumfour Abdullai Aziz Slide 3

 SESSION OUTLINE

The key topics to be covered in the session include

q Classification of Finite State Machine with Output
q Moore Model of computation
q Mealy Model of computation
q Design of sequence detector using Mealy/ Moore
Models that recognizes a string of characters

Dwumfour Abdullai Aziz Slide 4

 PATTERN / SEQUENCE DETECTOR
❑ A sequence recognizer or detector is a sequential state
machine that looks for a special bit pattern occurring in
a binary string.
❑ A sequence detector takes an input string of bits and
generates an output 1 whenever the target sequence
has been detected.
❑ The recognizer circuit has only one input, X; one input
bit is supplied on every clock cycle.
❑ For every bit applied to the input X, the circuit
generates a bit at output Z.
Z = 1 when the most recent bits in the stream at input X
completes the pattern, otherwise the output Z=0
Dwumfour Abdullai Aziz Slide 5
PATTERN / SEQUENCE DETECTOR

Dwumfour Abdullai Aziz Slide 6

 PATTERN / SEQUENCE DETECTOR

Sequence detector is of two types:

q Overlapping
q Non-Overlapping

Dwumfour Abdullai Aziz Slide 7

 PATTERN / SEQUENCE DETECTOR

Overlapping
In an overlapping sequence detector, the last bit of
one sequence becomes the first bit of the next
sequence.

Non-Overlapping
In a non-overlapping sequence detector, the last bit
of one sequence does not become the first bit of the
next sequence.
Dwumfour Abdullai Aziz Slide 8
 PATTERN / SEQUENCE DETECTOR

❑ Design a sequence recognizer that recognizes the

string 101 in the bit sequence 0110101011001.

Using overlapping
Input :0110101011001
Output:0000101010000

Using non overlapping

Input :0110101011001
Output:0000100010000

Dwumfour Abdullai Aziz Slide 9

PATTERN / SEQUENCE DETECTOR
Mealy State Diagram with overlapping

Dwumfour Abdullai Aziz Slide 10

PATTERN / SEQUENCE DETECTOR
Mealy State Diagram with non overlapping

Dwumfour Abdullai Aziz Slide 11

PATTERN / SEQUENCE DETECTOR

State table

Dwumfour Abdullai Aziz Slide 12

PATTERN / SEQUENCE DETECTOR

State table

Dwumfour Abdullai Aziz Slide 13

PATTERN / SEQUENCE DETECTOR
Circuit excitation table

Dwumfour Abdullai Aziz Slide 14

 PATTERN / SEQUENCE DETECTOR

❑ Design a sequence recognizer that recognizes three

consecutive 1’s in a sequence of inputs.

Dwumfour Abdullai Aziz Slide 15

END OF SEMESTER

Dwumfour Abdullai Aziz Slide 16