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ENVIRONMENT
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DUT
Overview
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DUT
Description(1)
◼ The router has 16 input and 16 output ports
Each input and output port consists of 3 singles: data, frame, valid
These signals are represented in a bit-vector format (din[15:0],
dout[15:0], …)
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DUT
Description(2)
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DUT
Description (3)
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DUT
Input packet structure
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DUT
Output packet structure
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DUT
Reset signal
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SYSTEMVERILOG ENVIRONMENT
Phase of verification
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SYSTEMVERILOG ENVIRONMENT
Structure
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SYSTEMVERILOG ENVIRONMENT
Key feature
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SYSTEMVERILOG ENVIRONMENT
Program block
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SYSTEMVERILOG ENVIRONMENT
Interface: overview
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SYSTEMVERILOG ENVIRONMENT
Interface: example
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SYSTEMVERILOG ENVIRONMENT
Interface: clocking blocks
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SYSTEMVERILOG ENVIRONMENT
Interface: modport
◼ The signals that are not part of the modport do not get
connected and thus you have no access to them
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SYSTEMVERILOG ENVIRONMENT
Interface: modport
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SYSTEMVERILOG
Interface: modport
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SYSTEMVERILOG
Interface: completed
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SYSTEMVERILOG
Using interface in program
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SYSTEMVERILOG
Complete top level
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DRIVING & SAMPLING DUT SIGNAL
Overview
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DRIVING & SAMPLING DUT SIGNAL
Testbench timing
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DRIVING & SAMPLING DUT SIGNAL
Testbench timing
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DRIVING & SAMPLING DUT SIGNAL
Drive signal
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DRIVING & SAMPLING DUT SIGNAL
Example
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DRIVING & SAMPLING DUT SIGNAL
Sample signal
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DRIVING & SAMPLING DUT SIGNAL
Sample signal: example
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DRIVING & SAMPLING DUT SIGNAL
Signal synchronization
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COMPILE AND RUN
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LAB INTRODUCTION
◼ Lab1: build simulation environment
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