DCIT

203
DIGITAL AND LOGIC SYSTEM DESIGN
SESSION 8 – SEQUENTIAL LOGIC: FLIP FLOPS

Lecturer: Dwumfour Abdullai Aziz

Email: adwumfour@ug.edu.gh
Mobile: 0260541219

UNIVERSITY OF GHANA
College of Education
College of Education
School
School ofofContinuing
Continuingandand Distance
Distance Education
Education
2022/2023
2014/2015 – 2016/2017
 SEQUENTIAL LOGIC:
FLIP FLOPS

Dwumfour Abdullai Aziz Slide 2

 OVERVIEW

The session exposes students to the design process and

construction of sequential logic. Students will be
introduced to design principles of synchronous and
asynchronous sequential circuits. The session will
further highlight on the fundamental building blocks of
sequential logic, which are the Latches and Flip Flips.
Students will be required to simulate sequential logic
circuit using the simulator tools introduced in the course
(Logisim)

Dwumfour Abdullai Aziz Slide 3

 LEARNING OUTCOME
At the end of the session, the student will
q Evaluate logic circuit outputs, describe the operation of
logic gates, write truth tables for logic gates, logic gate.
q Understand the differences in synchronous and
asynchronous sequential logic circuits
q Understand the design principles of Flip Flops.
q Understand the difference between Flip Flops and
Latches
q Understand the various types of Flip Flops.
q Convert one Flip Flop into another Flip Flop
q Understand triggering methods
q Design and implement Sequential logic using Flip Flips.
Dwumfour Abdullai Aziz Slide 4
 SESSION OUTLINE

q Introduction to Synchronous Sequential Circuits

q Types of Flop Flops
ü S-R Flip Flop
ü D Flip Flop
ü J-K Flip Flop
ü T Flip Flop
ü Master/Slave S-R Flip Flop
ü Master/Slave J-K Flip Flop
q Flip Flop conversion
q Clock and Triggering methods
Dwumfour Abdullai Aziz Slide 5
 READING LIST

S. Salivahanan & S. Arivazhagan (2018), Digital Circuits and

Design.

Dwumfour Abdullai Aziz Slide 6

 INTRODUCTION TO
FLIP FLOPS

SYNCHRONOUS SEQUENTIAL CIRCUIT

Dwumfour Abdullai Aziz Slide 7

 LATCHES

❑ Latches and Flip Flops are the basic elements used to

store information in digital circuit.
❑ Both Latches and flip flops are circuit elements where the
output depends on the current inputs, previous input and
outputs.
❑ The peculiar feature about latches is that their outputs are
constantly affected by their inputs as long as the enable signal
is asserted, thus when the latches are enabled, their
content changes immediately when their inputs change.
❑ This behavior of the latch is referred to as asynchronous
❑ Latches are also level sensitive; thus only triggered when
enable is high or low
Dwumfour Abdullai Aziz Slide 8
 FLIP FLOP

❑ Flip-flops, on the other hand, have their content change only

either at the rising or falling edge of the enable signal.
❑ This enable signal is usually the controlling clock signal.
❑ We can obtain Flip flop from a gated latch by simply replacing
the enable control with a clock signal.
❑ The circuit only changes state when there is a rise or fall in
the edge of the clock signal.
❑ A Flip-Flop continuously checks its inputs and
correspondingly changes its output only at times determined
by clocking signal. It work’s on the basis of clock pulses. This
behavior is referred to as synchronous
❑ Flip flops are however edge sensitive; thus they are triggered
by the rising or falling edge of the clock
Dwumfour Abdullai Aziz Slide 9
 CLOCK
❑ In digital circuit a clock is a signal that oscillates between high
and low state in a specific time interval
❑ This oscillation is useful in controlling the activities of digital
circuits.
❑ The clock is used to control the state of synchronous
sequential circuit.
❑ It is a global time signal which determines when circuit
elements change state or retain state.
❑ A clock generator is used to generate a clock, which is an
oscillator that provides a square wave output.
❑ The output of the clock is used to trigger or activate circuit
elements. The components of clock is presented below
Dwumfour Abdullai Aziz Slide 10
 +v Edge
-v Edge

+v Level -v Level

CLOCK DUTY CYCLE

Duty cycle(DC) is the proportion of time during which the clock
is high. It is usually 50%
Mathematically:
DC=ratio of number of times clock is high/total time

Dwumfour Abdullai Aziz Slide 11

 CLOCK TRIGGERING

Triggering is the process of making the circuit active.

Different triggering mechanisms exist to make circuit active.
Clock can trigger circuits in two ways:
❑ Level triggering
❑ Edge triggering
Level Triggering: In level triggering the circuit will become
active when the gating or clock pulse is on a particular level
(high or low).
This level is decided by the designer.
We can have a negative level triggering in which the circuit is
active when the clock signal is low or a positive level triggering
in which the circuit is active when the clock signal is high.
Dwumfour Abdullai Aziz Slide 12
 CLOCK TRIGGERING

Edge triggering
❑ In edge triggering the circuit becomes active only at
the edge of the clock.
❑ Edge triggering may be negative or positive.
❑ If a circuit is positive edge triggered, the circuit will
take input at exactly the time in which the clock signal
goes from low to high(0 to 1)
❑ Similarly, negative edge triggering allows input to be
taken at exactly the time in which the clock signal goes
from high to low (1 to 0)
Dwumfour Abdullai Aziz Slide 13
 SYNCHRONOUS AND ASYNCHRONOUS CIRCUIT

❑ Sequential circuits can be synchronous or

asynchronous.
❑ Synchronous circuits change state only with the clock
signal whiles asynchronous circuit change state
whenever the input changes when enable is on.
❑ Latches are asynchronous whiles flip flops are
synchronous

Dwumfour Abdullai Aziz Slide 14

 TYPES OF FLIP-FLOPS

❖S-R Flip Flop

❖D Flip Flop
❖ J-K Flip-Flop
❖T Flip-Flop
❖Master/slave S-R Flip-Flop
❖Master/slave J-K Flip-Flop

Dwumfour Abdullai Aziz Slide 15

 TYPES OF FLIP-FLOPS CNT’D

S-R Flip Flop

This can be obtained from the gated S-R latch by
clocking the circuit with clock impulse

clk

BLOCK DIAGRAM OF SR FLIP FLOP

Dwumfour Abdullai Aziz Slide 16
NOR SR FLIP-FLOPS

BLOCK DIAGRAM OF SR FLIP FLOP

Dwumfour Abdullai Aziz Slide 17

NAND SR FLIP-FLOPS

BLOCK DIAGRAM OF SR FLIP FLOP

Dwumfour Abdullai Aziz Slide 18
SR FLIP-FLOPS TRUTH TABLE

Dwumfour Abdullai Aziz Slide 19

SR FLIP-FLOPS CHARACTERISTIC TABLE

Dwumfour Abdullai Aziz Slide 20

SR FLIP-FLOPS EXCITATION TABLE

Dwumfour Abdullai Aziz Slide 21

TIMING DIAGRAM FOR SR FLIP FLIP

Dwumfour Abdullai Aziz Slide 22

 D-FLIP FLOP

BLOCK DIAGRAM
Dwumfour Abdullai Aziz Slide 23
D-FLIP FLOP CNT’D

CIRCUIT DIAGRAM
Dwumfour Abdullai Aziz Slide 24
D-FLIP FLOP CNT’D

Dwumfour Abdullai Aziz Slide 25

 D-FLIP FLOP CNT’D

CHARACTERISTIC TABLE & CHARACTERISTIC

EQUATION
Dwumfour Abdullai Aziz Slide 26
D-FLIP FLOP CNT’D

EXCITATION TABLE
Dwumfour Abdullai Aziz Slide 27
TIMING DIAGRAM FOR D-FLIP FLOP

Dwumfour Abdullai Aziz Slide 28

 J K FLIP FLOP

BLOCK DIAGRAM
Dwumfour Abdullai Aziz Slide 29
NAND J K FLIP FLOP

CIRCUIT DIAGRAM
Dwumfour Abdullai Aziz Slide 30
 J K FLIP FLOP

JK FLIP FLOP TRUTH TABLE

Dwumfour Abdullai Aziz Slide 31

J K FLIP FLOP CHARACTERISTIC TABLE

Dwumfour Abdullai Aziz Slide 32

Dwumfour Abdullai Aziz Slide 33
TIMING DIAGRAM FOR J K FLIP FLOP

Dwumfour Abdullai Aziz Slide 34

Dwumfour Abdullai Aziz Slide 35
SUMMARY OF FLIP FLIPS

Dwumfour Abdullai Aziz Slide 36

T - FLIP FLOP

Dwumfour Abdullai Aziz Slide 37

T - FLIP FLOP

Dwumfour Abdullai Aziz Slide 38

T - FLIP FLOP: CHARACTERISTIC TABLE

Dwumfour Abdullai Aziz Slide 39

T - FLIP FLOP: TIMING DIAGRAM

Dwumfour Abdullai Aziz Slide 40

 MASTER-SLAVE FLIP-FLOPS
✧ Master- Slave flip flop are the cascaded combination of two
flip-flops among which the first is designated as master flip-flop
while the next is called slave flip-flop
✧ The master flip-flop is triggered by the external clock pulse
while the slave is activated at its inversion
✧ If the master is positive edge-triggered, then the slave is
negative-edge triggered and vice-versa.
✧ Hence a master-slave flip-flop completes its operation only after
the appearance of one full clock pulse for which they are also
known as pulse-triggered flip-flops.
✧ Master-Slave Flip Flop is an attempt to handle the Racing around
condition in the JK Flip Flop.
✧ The Master –Slave Flip Flop is used to create the toggle situation
Slide 41
Dwumfour Abdullai Aziz
MASTER-SLAVE FLIP-FLOPS

CIRCUIT DIAGRAM
Dwumfour Abdullai Aziz Slide 42
RECALL TRUTH TABLE FOR
POSITIVE EDGE FLIP FLOP

Dwumfour Abdullai Aziz Slide 43

MASTER-SLAVE FLIP-FLOPS

BLOCK DIAGRAM
Dwumfour Abdullai Aziz Slide 44
J K MASTER-SLAVE FLIP FLOP

Dwumfour Abdullai Aziz Slide 45

 J K MASTER-SLAVE FLIP FLOP TIMING DIAGRAM

Dwumfour Abdullai Aziz Slide 46

INTRODUCTION TO FLIP
FLOP CONVERSION

Dwumfour Abdullai Aziz Slide 47

 FLIP FLOP CONVERSION

Conversion of flip-flops causes one type of flip-flop to behave like

another type of flip-flop.
In order to make one flip-flop mimic the behavior of another certain
additional circuitry and/or connections become necessary.

✧ SR Flip – flop to JK Flip – flop

✧ SR Flip – flop to D Flip – flop
✧ SR Flip – flop to T Flip – flop
✧ JK Flip – flop to SR Flip – flop
✧ JK Flip – flop to D Flip – flop
✧ JK Flip – flop to T Flip – flop
✧ D Flip – flop to SR Flip – flop
✧ D Flip – flop to JK Flip – flop
Dwumfour Abdullai Aziz Slide 48
 STEPS TO FLIP FLOP CONVERSION

We shall consider the following steps:

1. Identify the available and required flip flops
2. Make characteristic table of the required flip flop
3. Make excitation table of the available flip flop
4. Derive Boolean expression for available flip flop
5. Draw circuit diagram

Dwumfour Abdullai Aziz Slide 49

SR FLIP FLOP TO JK FLIP FLOP CONVERSION

Available flip flop: SR

Required flip flop: JK
Characteristic table for JK flip flop
Excitation table for SR flip flop

Dwumfour Abdullai Aziz Slide 50

Dwumfour Abdullai Aziz Slide 51
SR TO JK FLIP FLOP

Dwumfour Abdullai Aziz Slide 52

 SR TO D FLIP FLOP

Available flip flop: SR

Desired flip flop: D
Characteristic table for D flip flop
Excitation table for SR flip flop

Dwumfour Abdullai Aziz Slide 53

Dwumfour Abdullai Aziz Slide 54
JK TO D FLIP FLOP

Dwumfour Abdullai Aziz Slide 55

JK TO D FLIP FLOP

Dwumfour Abdullai Aziz Slide 56

Dwumfour Abdullai Aziz Slide 57