Polytechnic University of the Philippines

College of Engineering
Department of Computer Engineering
NDC CAMPUS, Sta. Mesa, Manila

CMPE 420
ADVANCED LOGIC CIRCUITS

Experiment #1
FLIP-FLOPS

Submitted By:

ALMARIO, Melody P. ______________

APURADA, Jozean S. ______________
BACCAY, Elverie Joy L. ______________
NILOOBAN, Janine V. ______________

BSCMPE IV-4

Submitted To:
Engr. Norman David F. Delos Reyes
Instructor

November 30, 2010

I. OBJECTIVES

Through this experiment, students should be able to achieve the following:

(1) To be able to apply, explore and verify the knowledge learned from the previous lessons
about flip-flops particularly it first two types: the RS and D flip-flops, clocked and unclocked.

(2) To be able to construct flip-flop circuits through careful designing while promoting
organization of work and orderliness and the quickness in doing the given tasks.

(3) To be able to enhance the particular skills of each group member and to implement
collaboration in attaining the desired outcomes and outputs.

II. THEORETICAL FRAMEWORK

FLIP-FLOPS

Flip-flop circuit is the basic building block of the sequential logic circuit. Also called
“latches”, “bistable multivibrator”, or “binaries”; flip-flops can be wired from logic gates, such as
NAND and NOR gates, or can be bought in IC form. Flip-flops are interconnected to form
sequential logic circuits for data storage, timing, counting and sequencing. Unlike logic gates,
they have two complementary outputs labeled Q, which is the normal output, and Q’, which is the
complement of the output Q.

RS FLIP-FLOP

The simplest and most basic type of flip-flop is the RS flip-flop. Because of its typical
function of holding data temporarily, it is often called the RS Latch. Basic RS latch is an
asynchronous device; it does not operate within step with a clock or timing device. Figure 1-a
shows the logic symbol of an RS flip-flop. It has two inputs, labeled set (S) and reset (R). It can
be wired from logic gates (e.g. from two NAND gates or two NOR gates), as shown in figures 1-
b and 1-c.

The clocked RS flip-flop has an additional valuable synchronous feature to the RS latch. It
operates in step with a clock or timing device and operates synchronously. It has the set (S) and
reset (R) inputs and the added clock (CLK) input. It also has the customary normal output Q and
complementary output Q’. It can also be implemented from logic gates as shown in figure 1-d.
The CLK iput triggers the flip-flop when the CLK pulse goes HIGH.it is a level-tiggered device;
 anytime the clock impulse is HIGH, the information at R and S inputs will be transfered to the
outputs.
R
Q

CLK

Q’
S

Fig. 1-d

D FLIP-FLOP

Another type of flip-flop is the D flip-flop as shown in figure 2. It only has a single
data (D) input. Like RS flip-flop, it can be also clocked by adding a clock input (CLK). Often
called the delay flip-flop, whatever the input at the data (D) point is delayed from getting to the
normal output Q by one clock pulse. RS flip-flop can be converted to a D flip-flop by adding an
inverter. D flip-flops are widely used in data storage. Because of this use, it is sometimes called a
data flip-flop.
D
SET Q
D Q

CLR Q Q’

Fig. 2-a Fig 2-b

D
Q

CLK

Q’

Fig 2-c

III. MATERIALS

* presensitized pcb board *developer *ferric chloride

* Breadboard * Resistors * 74LS00 (4)
* 9V battery (2) * DIP switch * 74LS04 (1)
* Alligator clips * hand drill * 7-segment display (4)
* soldering lead * IC holders * Capacitors
* solid wire * soldering iron * wire wrap
IV. PROCEDURES

A. Preliminary
1. Study the basic functions of RS and D flip-flops. Analyze the schematic diagram of each type
and its implementation using logic gates.
2. Recall previous lessons regarding logic gates including its pin configurations.
3. Prepare all the materials needed for the experment.
4. Check all components in case of defectiviness.

B. Setup of pre-sensitized PCB

1. Construct the RS flip-flop and D flip-flops using the logic gates in the breadboard first to
ensure that it works. Figure shows the logic diagram of the clocked and unclocked flip-flops.
2. Test the finished circuits by connecting it in the 9V battery
3. Troubleshoot if necessary.
4. Fabricate your own Printed Circuit Board PCB by using a pre-sensitized PCB.
5. Create the circuit artwork on a transparent film. Draw the circuit on a paper and copy it on an
acetate film. Figure shows the PCB design.
6. Expose the board for 60-90 seconds. Put the artwork on top then press flat glass sheet as a top
layer to make good contact between the film and the circuit board. Keep a 10 to 15 watts
fluorescent table lamp on the glass with a distace of 5 cm plus 1 cm.
7. Developing is next. Put the powder on a liter of water into a tray. Immerse the board
completely. Rinse the board with running water.
8. Troubleshoot if unnecessary connections are seen.
9. Lastly is the etching of the board. Pour enough etching solution (ferric chloride) into a plastic
tray and immerse the board with artwork side up. Agitate the tray gently until unwanted copper
foil etched away, only the circuit pattern left. Rinse the board with plenty of water.

C. Actual Setup
1. Create a clock circuit in a PCB 201. This will be needed in making the fip-flops operate in step
with a clock. The schematic diagram of the astable 555 timer is shown in figure 3.
2. Test the finished circuits by connecting it in the 9V battery. Troubleshoot if needed.
3. Use two seven segment displays (common anode) for the output Figures 3 a-c shows the
schematic diagram of the experiment.
Use a DIP switch for the inputs. Each pin of the switch corresponds to each of the inputs
of each type of flip-flop. Another two DIP switches for the output: one switch for the normal
output Q and another for the complementary output Q’. Each pin of both two switches
corresponds to the type of flip-flop.
4. Connect the circuit into the clock circuit as shown in figure 3-d. This will able the flip-flops to
operate in step with the clock.
5. Test the circuit. Set the switches for desired type of flip-flop.

V. EXPERIMENTAL CIRCUIT AND SETUP

 R Q1

Unclocked RS Flip-flop

S Q’1

Q2

CLK Clocked RS Flip-flop

S Q’2

DIP Switch 1 D

Q3

Unclocked D Flip-flop

Q’3

Q4

CLK Clocked D Flip-flop

Q’4

Fig -3a: Schematic diagram of the experiment

Vcc Vcc
DIP Switch 2 DIP Switch 3
Q1 Q’1

Q2 Q’2

Q’3 CLK
Q3

Q4 Q’4

Fig 3-b Fig 3-c Fig 3-d

PICTORIAL DIAGRAM
 RS Flip-flop

Latch State Set

Reset Race
For D Flip-flop

VI. RESULTS/ OBSERVATIONS/ TABLES/ MEASUREMENTS

Upon performing the experiment, the following results and observations are being noted:

RS Flip-flop (Unclocked) RS Flip-flop (Clocked)

The truth table above defines the operations of the flip-flops. For
the RS flip-flop, the first line of the truth table 1 indicates a prohibited state which drives both
outputs to 1 or HIGH. This is called as the race condition and is not used in RS flip-flop because
it leads to unpredictable operation. The second line is the set condition, where a LOW or 0
activates the set (S) input and sets the normal output to HIGH or 1. The third line is the reset
state, activated by LOW or 0, that clears or resets the normal Q output to 0. The last line is the
hold or diabled condition wherein the outputs remain as they were before the hold existed. There
is no change in the previous states.
For the clocked RS flip-flop, anytime the clock pulse is HIGH, the information at the data
inputs (R and S) will be transferred to the outputs. It should be emphasized that the S and R
inputs are active during the entire time the clock pulse level is HIGH. The HIGH of the clock
pulse may be thought of as an enabling pulse as seen in table 2.

D Flip-flop (Unclocked) D Flip-flop (Clocked)

 For D flip-flop, in order to avoid the race condition, one input of the RS flip-flop is connected
to an inverter to avoid the race condition. Whatever the input is, it will be the same as the output.

VII. ANALYSIS/ DISCUSSIONS/ PROBLEMS ENCOUNTERED

ANALYSIS/ DISCUSSIONS

The timing diagram in fig 5-a and b shows how the input signals interact to produce the
output signl. R and S are normally HIGH to avoid the race condition. Only one of them goes
LOW at any time. As you can see, the output goes HIGH whenever R goes LOW; the output goes
LOW whenever S goes LOW.

Fig 5-a. UNCLOCKED RS LATCH

CLK

Fig 5-b. CLOCKED RS LATCH

For D flip-flop is figure 6. If the clock is LOW, the circuit is latched and the output Q cannot
be changed. While the clock is HIGH, however, Q equals D; when D goes HIGH, Q goes HIGH;
when D goes LOW, Q goes LOW. The latch is transparent; meaning that the output follows the
value of D while the clock is HIGH.
 CLK

Fig 6. CLOCKED D FLIP-FLOP

PROBLEMS ENCOUNTERED

1. Initially, the circuit doesn’t work due to some wrong connection.

2. The toggle function doesn’t work also, maybe due to problem in the clock circuit
3. We had some difficulty in the setup of the pre-sensitized PCB. Some connections got lost
while doing the developing part.

VIII. CONCLUSION AND RECOMMENDATION

Therefore, we conclude that in order to design and implement flip-flop circuit, an in-depth
knowledge is needed especially in the difference of unclocked and clocked flip-flop. In the
experiment, the functions of flip-flop were verified. RS flip-flop and D flip-flop can be
constructed using logic gates such as NAND and NOR gates or can be bought in IC form. The
clock is used for timing and synchronization.

We recommend that in this experiment, studying the basic functions of flip-flops will really
help. Before conducting the experiment, try to familiarize and review the functions of logic gates
and other components first before applying it to the circuit.

IX. BIBLIOGRAPHY/ REFERENCE

Schaum’s Outline of Theory and Problems of Digita l Principles; Tokheim, Roger L. Third
Edition. McGraw-Hill

Digital Computer Electronics, Third edition, Malvino, Albert & Brown, Jerald
X. GLOSSARY

555 timer
The 555 Timer IC is an integrated circuit (chip) implementing a variety of timer and
multivibrator applications.

Astable
Free running mode: the 555 can operate as an oscillator. Uses include LED and lamp
flashers, pulse generation, logic clocks, tone generation, security alarms, pulse position
modulation

Clock
An external (circuit) input signal that prevents sequential circuit (flip-flops) from
changing states at any time

Flip-flops
Building blocks of sequential logic circuits; Flip-flops can store 1 bit of information.

Logic gate
A logic gate performs a logical operation on one or more logic inputs and produces a
single logic output.

Memory Element
A device which can remember value indefinitely or change value on command from its
inputs

RACE
A condition whenever two inputs are HIGH the flip-flop goes on undetermined state.

Sequential Logic Circuit

It is a type of logic circuit wherein the output is not dependent on the input only but also
to the input history. It needs a special a special external input signal called the clock.