DCIT

203
DIGITAL AND LOGIC SYSTEM DESIGN
SESSION 7 – SEQUENTIAL LOGIC: LATCHES

Lecturer: Dwumfour Abdullai Aziz

Email: adwumfour@ug.edu.gh
Mobile: 0260541219

UNIVERSITY OF GHANA
College of Education
College of Education
School
School ofofContinuing
Continuingandand Distance
Distance Education
Education
2021/2022
2014/2015 – -2016/2017
2022/2023
 SEQUENTIAL LOGIC

Dwumfour Abdullai Aziz Slide 2

 OVERVIEW

The session exposes students to the design process and

construction of sequential logic. Students will be
introduced to design principles of synchronous and
asynchronous sequential circuits. The session will further
highlight on the fundamental building blocks of sequential
logic, which are the Latches and Flip Flips. Students will be
required to simulate sequential logic circuit using the
simulator tools introduced in the course (Logisim)

Dwumfour Abdullai Aziz Slide 3

 OUTCOME

At the end of the session, the student will

q Evaluate logic circuit outputs, describe the operation
of logic gates, write truth tables for logic gates, logic
gate simplification
q Understand the differences in synchronous and
asynchronous sequential logic circuits
q Understand the design principles of Latches
q Understand the difference between Gated and
transparent Latches.
q Design and implement Sequential logic using
Latches.
Dwumfour Abdullai Aziz Slide 4
 SESSION OUTLINE

q Introduction to Asynchronous Sequential Circuit

q Types of Latches
ü S-R Latches
ü D Latches
ü J-K Latches
ü T-Latches
q Gated Latches vs Transparent Latches
Dwumfour Abdullai Aziz Slide 5
 READING LIST

S. Salivahanan & S. Arivazhagan (2018), Digital Circuits and Design.

Dwumfour Abdullai Aziz Slide 6

 INTRODUCTION TO
ASYNCHRONOUS SEQUENTIAL CIRCUIT

LATCHES

Dwumfour Abdullai Aziz Slide 7

 SEQUENTIAL CIRCUIT

❑ Combinational circuits in digital systems produce an

output based on input variables only.
❑ They do not have memory. Hence the previous state of
input does not have any effect on the present state of the
circuit.
❑ Sequential circuit is a type of digital circuit which uses
current input, previous output to determine the next
output (state)
❑ To store information about the previous input and outputs,
we require a sort of memory .

Dwumfour Abdullai Aziz Slide 8

Dwumfour Abdullai Aziz Slide 9
 BISTABLE ELEMENT

BISTABLE ELEMENT
The simplest sequential circuit or storage element is a
bistable element, which is constructed with two inverters
connected sequentially in a loop as shown

Dwumfour Abdullai Aziz Slide 10

 LATCHES

❑ The bistable element is able to remember or store

one bit of information.
❑ However, because it does not have any inputs, we
cannot change the information bit that is stored in it.
❑ In order to change the information bit, we need to
add inputs to the circuit.
❑ The simplest way to add inputs is to replace the two
inverters with two logic gates.
❑ The logic gate could be a NAND gate or NOR gate and
the resulting circuit diagram is called Latch
Dwumfour Abdullai Aziz Slide 11
 S-R LATCHES (SET-RESET LATCH)

We shall focus on the following S-R latches

o S-R Latch using NOR gate
o S-R latch using NAND gate

Dwumfour Abdullai Aziz Slide 12

S-R LATCHES BLOCK DIAGRAM

R
Q

S Q’

Dwumfour Abdullai Aziz Slide 13

S-R LATCHES USING NOR GATE

Dwumfour Abdullai Aziz Slide 14

 Invalid

S-R LATCH WITH NOR GATE

The SR NOR latch is level sensitive active high
We shall make use of the above truth table to develop the characteristic
table as shown in the next slide
Dwumfour Abdullai Aziz Slide 15
The characteristic table is used to show the next state of the S-R
latch based on the current input and previous state of the latch

CHARACTERISTIC TABLE FOR S-R LATCH WITH NOR GATE

Dwumfour Abdullai Aziz Slide 16
 EXCITATION TABLE FOR S-R LATCH
WITH NOR GATE
✧ The excitation table is derived from the characteristic table
✧ It serves as the foundation for developing flip-flop convergence
and counters
✧ Given a current state and a desired next state, we want to find
out which inputs combinations will yield the next state given
the current state

Dwumfour Abdullai Aziz Slide 17

 S-R LATCHES USING NAND GATE

Note the position of the S and R compared to the S-R latch with NOR gate has been
swapped
SR NAND latch is level sensitive active low latch: this implies the latch is by default high so
to set the latch (set=0: low, Q=1) and to reset the latch(Reset=0: low, Q’=1)
Dwumfour Abdullai Aziz Slide 18
S-R LATCHES USING NAND GATE

S R Q Q’
0 0 Invalid
0 1 1 0
1 0 0 1
1 1 Memory

Dwumfour Abdullai Aziz Slide 19

CREATE THE CHARACTERISTIC TABLE
FOR S-R LATCH USING NAND GATE
S R QN QN+1 Q’N+1
0 0 0 INVALID
0 0 1 INVALID

0 1 0 1 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1Dwumfour Abdullai
1 Aziz Slide 20 0
 GATED SR LATCH

✧ The SR latch is sensitive to its inputs all the time.

✧ It is sometimes useful to be able to disable the inputs.
✧ The SR latch with enable (also known as a gated SR latch)
accomplishes this by adding an enable input, E, to the original
implementation of the latch that allows the latch to be enabled
or disabled.
✧ SR latch without enable input is referred to as transparent
latch.
✧ Gated SR latch is transparent only when it is enabled
✧ We shall modify the SR latch by adding enable input to obtain:
SR NOR latch with Enable
SR NAND latch with Enable
Dwumfour Abdullai Aziz Slide 21
GATED S-R NOR LATCH

Dwumfour Abdullai Aziz Slide 22

GATED SR NOR LATCH

Dwumfour Abdullai Aziz Slide 23

GATED SR NAND LATCH

Dwumfour Abdullai Aziz Slide 24

 GATED SR NAND LATCH CNT’D

TRUTH TABLE

Dwumfour Abdullai Aziz Slide 25

GATED SR NAND LATCH

CHARACTERISTIC TABLE

Dwumfour Abdullai Aziz Slide 26

 D LATCHES

✧ One of the main disadvantages of the basic S-R NOR Gate bistable
circuit is that the indeterminate input condition of SET = “1” and RESET
= “1” is forbidden.
✧ Similarly S-R NAND Gate has indeterminate input condition of SET=“0”
and RESET=“0” which is forbidden.
✧ In order to prevent this from happening an inverter can be connected
between the “SET” and the “RESET” inputs and replace them with just
one input (D).
✧ This is to ensure that the inputs to the SET and RESET do not have the
same value at the time.
✧ The resulting latch is regarded called D-latch or Data latch
✧ We give rise to another form of latch;
D-Latch using NOR GATE
D-Latch using NAND GATE Dwumfour Abdullai Aziz Slide 27
 D LATCHES USING NOR GATE

Dwumfour Abdullai Aziz Slide 28

TRUTH TABLE D LATCHES USING NOR GATE

D Q Q’
0 0 1
1 1 0

Dwumfour Abdullai Aziz Slide 29

 D LATCHES USING NAND GATE

Dwumfour Abdullai Aziz Slide 30

TRUTH TABLE D LATCHES USING NAND GATE

D Q Q’
0 0 1
1 1 0

Dwumfour Abdullai Aziz Slide 31

 D LATCH BLOCK DIAGRAM

Dwumfour Abdullai Aziz Slide 32

 GATED D LATCH USING NOR GATE

Dwumfour Abdullai Aziz S Slide 33

 GATED D LATCH USING NOR GATE CNT’D

Dwumfour Abdullai Aziz Slide 34

 GATED D LATCH USING NAND GATE

Dwumfour Abdullai Aziz Slide 35

GATED D LATCH USING NAND GATE CNT’D

Dwumfour Abdullai Aziz Slide 36

 J K LATCH
✧ J K latch is essentially a modified version of an S-R latch with no
“invalid” or “illegal” output state.
✧ We can say J K latch is a refinement of Gated RS latch.
✧ The two inputs of J K latch is J (set) and K (reset).
✧ JK latch is nothing but a Gated RS latch with the two outputs
acting as feedback to the input
✧ The JK latch helps to eliminate the ambiguous state of both (R=1
and S=1 OR R=0 and S=0)
✧ The “JK latch” has no invalid or forbidden input states of the SR
Latch even when S and R are both at logic “1” or “0”.
✧ JK latch could be constructed from :
✧ Gated NOR SR Latch JK NOR Latch
✧ Gated NAND SR Latch JK NAND Latch
Slide 37
TANSPARENT J K NOR LATCH

Dwumfour Abdullai Aziz Slide 38

 GATED J K NOR LATCH

EN

Dwumfour Abdullai Aziz Slide 39

J K NOR LATCH TRUTH TABLE

En J K QN
0 0 0 Latch
0 0 1 Latch
0 1 0 Latch
0 1 1 Latch
1 0 0 Latch
1 0 1 0
1 1 0 1
1 1 1 toggle
Dwumfour Abdullai Aziz Slide 40
J K NOR LATCH TRUTH TABLE SUMMARY

En J K QN
0 X X Latch
1 0 0 Latch
1 0 1 0
1 1 0 1
1 1 1 toggle

Dwumfour Abdullai Aziz Slide 41

J K NOR LATCH CHARACTERISTIC

QN J K QN+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1
Dwumfour Abdullai Aziz Slide 42 0
 GATED J K NAND LATCH

EN

Dwumfour Abdullai Aziz Slide 43

GATED J K NAND LATCH CNT’D

En J K QN
0 0 0 Latch
0 0 1 Latch
0 1 0 Latch
0 1 1 Latch
1 0 0 Latch
1 0 1 0
1 1 0 1
1 1 1 toggle
Dwumfour Abdullai Aziz Slide 44
J K NAND LATCH TRUTH TABLE SUMMARY

En J K QN
0 X X Latch
1 0 0 Latch
1 0 1 0
1 1 0 1
1 1 1 toggle

Dwumfour Abdullai Aziz Slide 45

J K NAND LATCH CHARACTERISTIC

QN J K QN+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1
Dwumfour Abdullai Aziz Slide 46 0
 GATED J K NAND LATCH
SUMMARY OF TRUTH TABLE

Dwumfour Abdullai Aziz Slide 47

 ASSIGNMENT
Describe the Gated “T latch” circuit diagram using
the JK latch and derive the characteristic table for
the T latch.

Dwumfour Abdullai Aziz Slide 48

Dwumfour Abdullai Aziz Slide 49