Lecture 1 Synchronous Sequential Logic Circuit Design

MODULE 1:
SYNCHRONOUS SEQUENTIAL
LOGIC CIRCUIT DESIGN
INTRODUCTION
WHAT IS A MICROPROCESSOR SYSTEM?
A microprocessor is just an
integrated circuit. On its own, without
a surrounding circuit and applied
voltages, it is quite useless.
A useful microprocessor-based
computer system must have a
memory, I/O devices, and a
Fig. 1. Intel 8086 Microprocessor
processing unit.
engradc©2011|engrkad©2013|engrcde©2017
INTRODUCTION
WHAT IS A MICROPROCESSOR SYSTEM?
Fig. 2. Example of a Simple Sequential Circuit
INTRODUCTION
ELECTRONIC CONSUMER PRODUCTS
Cellphones, personal computers, digital cameras, and

media players –
these are some examples of the many products that have the
ability to send, receive, store, retrieve, and process information
in binary format.
SEQUENTIAL LOGIC CIRCUITS
WHAT ARE SEQUENTIAL LOGIC CIRCUITS?
Virtually, all useful systems require storage of state

information. Hence leading to the development of sequential logic
circuits.
In this type of circuit, not only does the current input values
affect the output, but also upon the preceding values. Simply put, a
sequential logic circuit has memory elements.
SEQUENTIAL vs. COMBINATIONAL LOGIC CIRCUIT
The output of a Combinational Logic Circuit depends ONLY

and IMMEDIATELY on their inputs. Hence, it has no memory
element.
ADDERS MULTIPLEXERS DECODERS
SUBTRACTERS DEMULTIPLEXERS ENCODERS
On the other hand, Sequential Logic Circuits, act as storage

elements and have memory.
REGISTERS COUNTERS
SEQUENTIAL CIRCUIT BLOCK DIAGRAM
Fig. 3. Block Diagram of a Sequential Circuit
TYPES OF SEQUENTIAL CIRCUIT
1. Synchronous Sequential Circuit

This circuit employs signals that affect the storage elements at
only discrete instants of time. Synchronization is achieved by a
timing device called a clock generator.
2. Asynchronous Sequential Circuit

This circuit depends upon the input signals at any instant of
time and the order in which inputs change.
TYPES OF SEQUENTIAL CIRCUIT
1. Synchronous Sequential Circuit
The clock pulses or CLK determine

the computational activity that will
occur within the circuit and what
changes will take place affecting
the storage elements and outputs.
Fig. 4. Block Diagram of a Synchronous
Sequential Circuit
FORMS OF TRIGGERING OR CLOCKING
1. Level Clocking
This is a type of triggering wherein the output of the flip flop
responds during the high (or low) level of the clock signal.
CLK 1
1
D
0
Fig. 5. Example of a Timing Diagram
Determine Q For a Positive Level Clocked D Latch
1
2. Edge Triggering
This is a type of triggering wherein the flip flop produces
output only on the rising (or falling) edge of the clock signal.
CLK 1
1
D
0
Fig. 6. Example of a Timing Diagram
Determine Q For a Positive Edge Triggered D Flip Flop
1
1. Level Clocking
Fig 7a. Positive Level Clocking Fig 7b. Negative Level Clocking
2. Edge Triggering
Fig 7c. Positive Edge Triggering Fig 7d. Negative Edge Triggering
REVIEW ON FLIP FLOPS
Flip Flops are synchronous bistable devices. Its content

remains in one of the two possible states until triggered into
another.
1. SR FLIP FLOP 3. D FLIP FLOP
2. JK FLIP FLOP 4. T FLIP FLOP
It is said to be synchronous because its output changes state
only at a specified point (either leading or trailing edge) on the
triggering input called clock or clk.
1. SR Flip Flop Table 1. Characteristic Table of

SR Flip Flop
Q(t) S R Q(t+1)
0 0 0 0
0 0 1 0
Fig 8. Schematic Symbol of a 0 1 0 1
Positive Edge Triggered SR Flip Flop
0 1 1 ind
1 0 0 1
𝑸 𝒕 + 𝟏 = 𝑺 + 𝑸𝑹′ 1 0 1 0
Eqn. 1. Characteristic Equation 1 1 0 1
Of SR Flip Flop 1 1 1 ind
2. JK Flip Flop Table 2. Characteristic Table of

JK Flip Flop
Q(t) J K Q(t+1)
0 0 0 0
0 0 1 0
Fig 9. Schematic Symbol of a 0 1 0 1
Positive Edge Triggered JK Flip Flop
0 1 1 1
1 0 0 1
𝑸 𝒕 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸 1 0 1 0
Eqn. 2. Characteristic Equation 1 1 0 1
Of JK Flip Flop 1 1 1 0
3. D Flip Flop Table 3. Characteristic Table of

D Flip Flop
Q(t) D Q(t+1)
0 0 0
0 1 1
Fig 10. Schematic Symbol of a 1 0 0
Positive Edge Triggered D Flip Flop
1 1 1
𝑸 𝒕+𝟏 =𝑫
Eqn. 3. Characteristic Equation
Of D Flip Flop
4. T Flip Flop Table 4. Characteristic Table of

T Flip Flop
Q(t) T Q(t+1)
0 0 0
0 1 1
Fig 11. Schematic Symbol of a 1 0 1
Positive Edge Triggered T Flip Flop
1 1 0
𝑸 𝒕 + 𝟏 = 𝑻𝑸′ + 𝑻′ 𝑸
Eqn. 4. Characteristic Equation
Of T Flip Flop
What is an EXCITATION TABLE and why is it important in the

design process?
An excitation table lists the required inputs for a given change

of state.
This is important in the design process to determine the flip
flop input conditions that will cause the required transition.

design process?
Table 5. Excitation Table of SR Flip Flop Table 6. Excitation Table of JK Flip Flop
Q(t) Q(t+1) S R Q(t) Q(t+1) J K

0 0 0 x 0 0 0 x
0 1 1 0 0 1 1 x
1 0 0 1 1 0 x 1
1 1 x 0 1 1 x 0

design process?
Table 7. Excitation Table of D Flip Flop Table 8. Excitation Table of T Flip Flop
Q(t) Q(t+1) D Q(t) Q(t+1) T

0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
DESIGN MODELLING
The relationship that exists among the inputs, outputs,

present states, and next states can be specified by any of the
following:
1. STATE DIAGRAM
2. STATE TABLE
3. STATE EQUATION
DESIGN MODELLING
0/0 0/0
1. State Diagram
1/1
00 10
A state diagram is a graphical
representation wherein a state is
represented by a circle; and the 1/0 0/0
transition between states is

indicated by directed lines (or arcs) 01 11
0/0
connecting the circles.
1/0 1/0
Fig 12. Sample State Diagram
DESIGN MODELLING
Table 9. Equivalent State Table from the
Previous Diagram
2. State Table Present Input Next Output
State State
A state table is a
A(t) B(t) x A(t+1) B(t+1) y
tabulated representation 0 0 0 0 0 0
which consists of input, 0 0 1 0 1 0
present state, next state, 0 1 0 1 1 0
and output. 0 1 1 0 1 0
1 0 0 1 0 0
STATE STATE 1 0 1 0 0 1
1 1 0 1 0 0
DIAGRAM TABLE
1 1 1 1 1 0
DESIGN MODELLING
Table 9. Equivalent State Table from the

Previous Diagram
2. State Table Present Input Next Output
Table 10. Another Way to Write a State State
State Table (for State Reduction) A(t) B(t) x A(t+1) B(t+1) y
Present Next Output 0 0 0 0 0 0
State State
0 0 1 0 1 0
A(t) B(t) x=0 x=1 x=0 x=1
0 1 0 1 1 0
00 00 01 0 0
0 1 1 0 1 0
01 11 01 0 0
1 0 0 1 0 0
10 10 00 0 1
1 0 1 0 0 1
11 10 11 0 0
1 1 0 1 0 0
1 1 1 1 1 0
DESIGN MODELLING
3. State Equation
A state equation is an expression that specifies the conditions
of flip flop’s next state transition as function of the present state
and input variables. Other name for Characteristic Equation.
𝑸 𝒕 + 𝟏 = 𝑭{𝑸 𝒕 , 𝒙𝟏, 𝒙𝟐, … , 𝒙𝒏}
DESIGN APPROACH
0/1
Sample Problem No. 1

00
Based on the given state 1/0 0/0
diagram, design a sequential
circuit using JK Flip Flop.
1/1 01 11 1/0
0/0 0/1
10
Fig 13. State Diagram for
1/1
DESIGN APPROACH
STEP 1:
Identify the given. This can
be in a form of a word description
of the circuit behavior and may be
accompanied by a state diagram, a
timing diagram, or other pertinent
information.
DESIGN APPROACH
STEP 2: Table 11. Equivalent State Table of

Obtain the state table. Present Input Next Output
State State
A(t) B(t) x A(t+1) B(t+1) y
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 1
1 0 0 1 1 1
1 0 1 1 0 1
1 1 0 0 0 0
1 1 1 1 1 0
DESIGN APPROACH
STEP 3:
The number of states may Table 12. Another Way to Write a
State Table (for State Reduction)
be reduced by State Reduction Present Next Output
Method. State State
A(t) B(t) x=0 x=1 x=0 x=1
NOTE: 00 00 01 1 0
Two states are said to be equivalent 01 10 01 0 1
if, for each member of the set of inputs, 10 11 10 1 1
they give exactly the same output and 11 00 11 0 0
send the circuit either to the same state or
to an equivalent state.
DESIGN APPROACH
STEP 4:
Derive the circuit excitation and output tables based on the
type of flip flop to be used. To do this, determine how many flip
flops are to be used.
𝑵 = 𝟐𝒏 where:
n = number of bits or flip flops to be used
Eqn. 5. Relationship of the N = total number of states
number of bits and number of
states
DESIGN APPROACH
Table 13. Circuit Excitation and Output Table Using JK Flip Flop
PRESENT NEXT
INPUT FLIP FLOP INPUTS OUTPUT
STATE STATE
A(t) B(t) x A(t+1) B(t+1) JA KA JB KB y
0 0 0 0 0 0 x 0 x 1
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 1
1 0 0 1 1 x 0 1 x 1
1 0 1 1 0 x 0 0 x 1
1 1 0 0 0 x 1 x 1 0
1 1 1 1 1 x 0 x 0 0
DESIGN APPROACH
STEP 5:
Using k-map or any other simplification method, derive the
circuit output functions and the flip flop input functions or
equations. Do this for both the flip flop inputs and output/s.
DESIGN APPROACH
Bx Bx
A 00 01 11 10 A 00 01 11 10
0 1 0 1 x x
1 x x x x 1 1 x x Bx
A 00 01 11 10
𝑱𝑨 = 𝑩𝒙′ 𝑱𝑩 = 𝑨′ 𝒙 + 𝑨𝒙′ = 𝑨 ⊕ 𝒙 0 1 1
Bx Bx 1 1 1
A 00 01 11 10 A 00 01 11 10
0 x x x x 0 x x 1 𝒚 = 𝑨′𝑩𝒙 + 𝑩′ 𝒙′ + 𝑨𝑩′
1 1 1 x x 1 Output Equation
𝑲𝑨 = 𝑩𝒙′ 𝑲𝑩 = 𝒙′
JK Flip Flop Input Equations
DESIGN APPROACH
STEP 6: Draw the sequential logic circuit.
Fig 14. Equivalent Sequential Logic

Circuit Design of Sample
Problem No. 1
DESIGN APPROACH
Summary of Design Approach

STEP 1: Identify the given.
STEP 2: Obtain the state table.
STEP 3: Reduce number of states if possible.
STEP 4: Derive the circuit excitation and output tables
based on the type of flip flop to be used
STEP 5: Derive the circuit output functions and the flip
flop input functions.
STEP 6: Draw the circuit.
DESIGN APPROACH
0/1
Seatwork No. 1
00
Based on the given state 1/0 0/0
diagram, design a sequential
circuit using D Flip Flop.
1/1 01 11 1/0
0/0 0/1
10
Fig 13. State Diagram for
Seatwork No. 1
1/1
DESIGN APPROACH
Assignment No. 1
Design a sequential circuit with two T Flip Flops, A and B, and
two inputs, E and x. If E=0, the circuit remains in the same state
regardless of the value of x. When E=1 and x=1, the circuit goes
through the state transitions from 00 to 01 to 10 to 11 back to 00,
and repeats. When E=1 and x=0, the circuit goes through the state
transition from 00 to 11 to 10 to 01 back to 00, and repeats.
STATE REDUCTION AND ASSIGNMENT
State Reduction Algorithms are concerned with procedures

for reducing the number of states in state table, while keeping the
external input-output requirements unchanged.
NOTE:
Two states are said to be equivalent if, for each member of the set of inputs, they
give exactly the same output and send the circuit either to the same state or to an
equivalent state.

Based on the given state diagram:
a) Generate the input-output sequence
b) Reduce the number of states in the given table
c) Regenerate the output sequence using the
reduced table or state diagram
d) Draw the reduced state diagram
NOTE:
Consider the input sequence 01010110100 starting Fig 15. State Diagram for Sample
Problem No. 2
from a.
a) Generate the input-output sequence

NOTE:
Consider the input sequence 01010110100
starting from a.
State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
Fig 15. State Diagram for Sample

Problem No. 2
b) Reduce the number of states in the Table 14. Equivalent State Table of
given table
Present Next Output
State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
d=f e a f 0 1
f g f 0 1
e=g
g a f 0 1
b) Reduce the number of states in the Table 14. Equivalent State Table of
given table
Present Next Output
State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
d=f e a f 0 1
f g f 0 1
e=g
g a f 0 1
b) and d) Reduce the number of states Table 15. Reduced State Table of
in the given table and draw the reduced Sample Problem No. 2
diagram Present Next Output
State State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
EFFECT: From a total of 7 states (or consumption of 3 FFs), the number of
Fig 16. Reduced State Diagram for states is reduced to 5 states. However, 3 FFs are still needed.
c) Regenerate the output sequence using the

reduced table or state diagram
NOTE:
Consider the input sequence 01010110100
starting from a.
State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
State a a b c d e d d e d e a Fig 16. Reduced State Diagram for

Input 0 1 0 1 0 1 1 0 1 0 0 Sample Problem No. 2
output 0 0 0 0 0 1 1 0 1 0 0
REGISTERS AND COUNTERS
Registers are composed of group of flip flops, each one shares

a common clock and is capable of storing one bit of information or
modify stored binary word.
Counters, on the other hand, are registers that go through a
predetermined sequence of binary states. It counts the number of
clock pulses arriving at its input.
REGISTERS
4-bit Buffer Register

When RESET = 0, the 4-bit Register is forced to reset. When
RESET = 1, Q3Q2Q1Q0  X3X2X1X0 is stored through Parallel
Loading.
X3 X2 X1 X0
Q3 D3 Q2 D2 Q1 D1 Q0 D0
CLK CLK CLK CLK
R R R R
RESET
Fig 17. 4-bit Buffer Register engradc©2011|engrkad©2013|engrcde©2017

REGISTERS
4-bit Controlled Buffer Register

X3 X2 X1 X0
LOAD
When LOAD = 0, data will

be retained.
When LOAD = 1,
Q3 D3 Q2 D2 Q1 D1 Q0 D0
Q3Q2Q1Q0  X3X2X1X0 is
stored through Parallel
CLK CLK CLK CLK
Loading.
R R R R
RESET
Fig 18. 4-bit Controlled Buffer Register engradc©2011|engrkad©2013|engrcde©2017

REGISTERS
Shift Registers (Shift Left)

Storing of word in the shift register is done through Serial
Loading, wherein one bit is entered per clock pulse.
Q3 D3 Q2 D2 Q1 D1 Q0 D0 Xin
CLK CLK CLK CLK
R R R R
RESET
Fig 19. Shift Left Register

REGISTERS
Shift Registers (Shift Right)

Storing of word in the shift register is done through Serial
Loading, wherein one bit is entered per clock pulse.
Q3 D3 Q2 D2 Q1 D1 Q0 D0
Xin
CLK CLK CLK CLK
R R R R
RESET
Fig 20. Shift Right Register

REGISTERS
4-bit Controlled Shift Register
SHL
Xin
When SHL = 0, data will
be retained.
When SHL = 1, X3X2X1X0 is
stored through Serial
Q3 D3 Q2 D2 Q1 D1 Q0 D0
Loading.
CLK CLK CLK CLK
R R R R
RESET
Fig 21. 4-bit Controlled Shift Register engradc©2011|engrkad©2013|engrcde©2017

REGISTERS
4-bit Shift Register with Broadside Load

X3 X2 X1 X0
LOAD
SHL
Xin
Q3 D3 Q2 D2 Q1 D1 Q0 D0
CLK CLK CLK CLK
R R R R
RESET
Fig 22. 4-bit Shift Register with Broadside Load engradc©2011|engrkad©2013|engrcde©2017

COUNTERS
Design of Binary Counters

The design of binary counters
are typically done using either T or
JK Flip Flop.
Fig 23. State Diagram of a 3-bit

Binary Counter
COUNTERS
Table 16. State Table for a 3-bit Binary Counter
Flip Flop
Present State Next State
Inputs
Q2(t) Q1(t) Q0(t) Q2(t+1) Q1(t+1) Q0(t+1) T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
Fig 23. State Diagram of a 3-bit
Binary Counter 1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
COUNTERS
Q2 T2 Q1 T1 Q0 T0 HIGH
CLK CLK CLK
R R R
RESET
Fig 24. 3-bit Binary Counter Circuit
COUNTERS

Design a mod-6 synchronous counter using T Flip Flops.
COUNTERS
Assignment No. 2
Design a 3-bit counter with the following repeated sequence:
0, 1, 3, 5, 7. Use JK Flip Flops.
COUNTERS
4-bit Binary Ripple Counter

Count pulse is only applied at the FF holding the LSB. All T
flip flops are always in toggle but not at the same time. When
1111 is reached, the counter goes back to 0000.
HIGH
Q3 T3 Q2 T2 Q1 T1 Q0 T0
CLK CLK CLK CLK COUNT

PULSE
R R R R
RESET
Fig 25. 4-bit Binary Ripple Counter

COUNTERS
4-bit Binary Synchronous Counter Q0 is always in toggle

Q1 will toggle when Q0 is 1
Q2 will toggle when Q1Q0 is 1
Q3 will toggle when Q2Q1Q0 is 1
Q3 J3 Q2 J2 Q1 J1 Q0 J0 HIGH
CLK CLK CLK CLK
R K3 R K2 R K1 R K0
RESET
Fig 26. 4-bit Binary Synchronous Counter

COUNTERS
4-bit Ring Counter

This is a type of counter that resembles a shift register
which is initiated in such that only one of its flip-flops is at high
state while the rest are in low state.
Q3 D3 Q2 D2 Q1 D1 Q0 PR D0
CLK CLK CLK CLK
R R R
RESET
Fig 27. 4-bit Ring Counter

COUNTERS
Modulo-10 Counter (Decade Counter)
Fig 28. Decade Counter

Lecture 1 Synchronous Sequential Logic Circuit Design

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Lecture 1 Synchronous Sequential Logic Circuit Design

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MODULE 1:

WHAT IS A MICROPROCESSOR SYSTEM?

WHAT IS A MICROPROCESSOR SYSTEM?

Fig. 2. Example of a Simple Sequential Circuit

ELECTRONIC CONSUMER PRODUCTS

Cellphones, personal computers, digital cameras, and

WHAT ARE SEQUENTIAL LOGIC CIRCUITS?

Virtually, all useful systems require storage of state

SEQUENTIAL vs. COMBINATIONAL LOGIC CIRCUIT

The output of a Combinational Logic Circuit depends ONLY

On the other hand, Sequential Logic Circuits, act as storage

SEQUENTIAL CIRCUIT BLOCK DIAGRAM

Fig. 3. Block Diagram of a Sequential Circuit

TYPES OF SEQUENTIAL CIRCUIT

1. Synchronous Sequential Circuit

2. Asynchronous Sequential Circuit

TYPES OF SEQUENTIAL CIRCUIT

1. Synchronous Sequential Circuit

The clock pulses or CLK determine

FORMS OF TRIGGERING OR CLOCKING

FORMS OF TRIGGERING OR CLOCKING

FORMS OF TRIGGERING OR CLOCKING

REVIEW ON FLIP FLOPS

Flip Flops are synchronous bistable devices. Its content

REVIEW ON FLIP FLOPS

1. SR Flip Flop Table 1. Characteristic Table of

REVIEW ON FLIP FLOPS

2. JK Flip Flop Table 2. Characteristic Table of

REVIEW ON FLIP FLOPS

3. D Flip Flop Table 3. Characteristic Table of

REVIEW ON FLIP FLOPS

4. T Flip Flop Table 4. Characteristic Table of

REVIEW ON FLIP FLOPS

What is an EXCITATION TABLE and why is it important in the

An excitation table lists the required inputs for a given change

REVIEW ON FLIP FLOPS

What is an EXCITATION TABLE and why is it important in the

Q(t) Q(t+1) S R Q(t) Q(t+1) J K

REVIEW ON FLIP FLOPS

What is an EXCITATION TABLE and why is it important in the

Q(t) Q(t+1) D Q(t) Q(t+1) T

The relationship that exists among the inputs, outputs,

transition between states is

Table 9. Equivalent State Table from the

𝑸 𝒕 + 𝟏 = 𝑭{𝑸 𝒕 , 𝒙𝟏, 𝒙𝟐, … , 𝒙𝒏}

Sample Problem No. 1

STEP 2: Table 11. Equivalent State Table of

STEP 6: Draw the sequential logic circuit.

Fig 14. Equivalent Sequential Logic

Summary of Design Approach

STATE REDUCTION AND ASSIGNMENT

State Reduction Algorithms are concerned with procedures

STATE REDUCTION AND ASSIGNMENT

Sample Problem No. 2

STATE REDUCTION AND ASSIGNMENT

a) Generate the input-output sequence

Fig 15. State Diagram for Sample

STATE REDUCTION AND ASSIGNMENT

STATE REDUCTION AND ASSIGNMENT

STATE REDUCTION AND ASSIGNMENT

STATE REDUCTION AND ASSIGNMENT

c) Regenerate the output sequence using the

State a a b c d e d d e d e a Fig 16. Reduced State Diagram for