DE Notes

DIGITAL ELECTRONICS
SEQUENTIAL LOGIC
INTRODUCTION TO SEQUENTIAL LOGIC
Sequential Logic  Sequential circuit contains a set of inputs and outputs. The
outputs of sequential circuit depends not only on the combination
of present inputs but also on the previous outputs.
 Previous output is nothing but the present state.
 Therefore, sequential circuits contain combinational circuits

along with memory storage elements.
 Some sequential circuits may not contain combinational

circuits, but only memory elements.
Input Combinational Output

Circuit
Memory Elements
21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 2
COMBINATIONAL & SEQUENTIAL CIRCUITS
Sequential Logic  Combinational circuit:
A B X Y
A
X 0 0 0 0
B 0 1 0 1
1 0 0 1
Y 1 1 1 0
X  A B
Y  A B
 X= Carry
 Y =Sum

COMBINATIONAL & SEQUENTIAL CIRCUITS
Sequential Logic  Difference between combinational and sequential circuit.
Combinational Circuits Sequential Circuits

Outputs depend only on Outputs depend on both present
present inputs. inputs and present state.
Feedback path is not present. Feedback path is present.
Memory elements are not
Memory elements are required.
required.
Clock signal is not required. Clock signal is vital required.
Easy design mechanism Design mechanism is difficult
compared to combinational
circuit

LATCH
Sequential Logic  There are two types of memory elements based on the type of
triggering that is suitable to operate it.
 Latch
 Flip-flop
 Latches operate with enable signal, which is level

sensitive. Whereas, flip-flops are edge sensitive. We
will discuss about flip-flops in next chapter. Now, let us
discuss about SR Latch & D Latch one by one.
R
Q
Q
S
SR LATCH
Sequential Logic  SR Latch is also called as Set Reset Latch. This latch affects
the outputs as long as the level of input is not changed.
The circuit diagram of SR Latch is shown in the following
figure.
R
Q
Q
S

SR LATCH USING NOR GATE WORKING
Sequential Logic  Working of SR latch using NOR gate is as follows:
A B O (output)
A O 0 0 1
B 0 1 0
1 0 0
1 1 0
1
0
1
0
1 0 0 1
1 0
0 1
1 0 0 1
0 1 1 0
1 0
0 1
1 0 0
0 1 1
1 0 0 1
0 1 1 0
1 0 0
0 1 0 0 0 1 0

1 0 0 1
0 1 1 0
1 0 0 1
0 1 0 0
1 0 0 1
0 1 1 0
0 0 1 0
1 0 0 1

1 0 0 1
0 1 1 0
1 0 0 1
0 1 0 1
1 0 0 1
0 1 1 0
0 0 1 0
1 0 0 1
1 1

Characteristic Table
R Q R S Q’ Q
0 0 No Change
Memory State
0 1 1 0
Q’ 1 0 0 1
S
1 1 Undefined
Not used
 S =1 & R = 0, we have Q = 1 & Q’ = 0.
 S =0 & R = 0, we have Q = 1 & Q’ = 0. Memory State
 S =0 & R = 1, we have Q = 0 & Q’ = 1.


R R S Q’ Q
Q
0 0 No Change
Memory State
0 1 1 0
1 0 0 1
Q’
S 1 1 Undefined
Not used
 S =1 & R = 1, we have Q = 1 & Q’ = 1. Invalid State
Or we have Q = 0 & Q’ = 1.
 Since memory state failed to retains correct values, therefore

S =1 & R = 1 is termed as invalid state
SR LATCH USING NAND GATE WORKING
Sequential Logic  Working of SR latch using NAND gate is as follows:
A B O (output)
A O 0 0 1
B 0 1 1
1 0 1
1 1 0
1
0
1
0
1 0 0 1
1 0
0 1
1 0 0 1
0 1 1 0
1 0
0 1
1 0 1
0 1 1
1 0 0 1
0 1 1 0
1 0 0
0 1 1 1 1 1 0

1 0 1 1
0 1 1 0
1 0 0 1
0 1 1 0
1 0 0 1
0 1 1 0
1 1 1 0
1 0 0 1

1 1 1 0
0 0 0
1 0 1
0 1 0 0
1 0 0 1
0 1 1 0
1 1 1 0
1 0 0 1
0 0

R Q’
Q
S
Characteristic Table:
R S Q’ Q
1 1 No Change
0 1 1 0
1 0 0 1
0 0 Undefined

SR LATCH
Sequential Logic  Functional block of SR Latch using NOR.
S Q R S Q’ Q
0 0 No Change
0 1 1 0
R Q 1 0 0 1
1 1 Undefined
 Functional block of SR Latch using NAND.

R S Q’ Q
S Q 1 1 No Change
0 1 1 0
1 0 0 1
R Q 0 0 Undefined
FLIP-FLOP
Sequential Logic  Clocked enabled latch is known as Flip-Flop (FF).
S S
Q
Clock
Q
R R
Clock R S Q’ Q  When clock is low FF

0   Not used will be in “invalid
1 1 0 0 1 state”.
1 0 1 1 0
1 1 1 Memory
State
1 0 0 Not used

FLIP-FLOP (FF)
Sequential Logic  Clocked enabled latch is known as Flip-Flop (FF).
S S*
Q
Q
R R*
Clock R S Q’ Q  When clock is low FF
0   Memory will be in “invalid
State state”.
1 1 0 1 0
 Now NAND gate latch
1 0 1 0 1 have same character-
1 0 0 Memory istics table as NOR gate
State base latch
1 1 1 Not used

ENABLING SIGNAL (CLOCK)
Sequential Logic  Clock signal helps in synchronizing the digital circuits:
1
0 t
 Duration of on time for clock pulse must be greater than

propagation delay of gate.

D - FLIP-FLOP
Sequential Logic  D - Flip-Flop (FF).
D S Q
D
Q
CLK
Clock
R Q
Q
Clock D Q Q’
1 1 1 0  When clock is low FF will be
1 0 0 1 in “invalid state”.
0  Memory  Now NAND gate latch have
State
same characteristics table as
NOR gate base latch

J-K FLIP-FLOP
Sequential Logic  J-K Flip-Flop (FF).
S
A Q
Clock
Q
B R
Clock A B Qn+1 𝑸n+1

0   Qn 𝑸n
1 1 0 1 0
1 0 1 0 1
1 0 0 0 1 Memory State

J-K FLIP-FLOP
S
A Q
Clock
Q
B R

1 1 1 1 0
1 1 1 0 1
1 1 1 𝑸n Qn

J-K FLIP-FLOP
S
A Q
Clock
Q
B R

0   Qn 𝑸n
1 0 0 Qn 𝑸n
1 1 0 1 0
1 0 1 0 1
1 1 1 𝑸n Qn

RACING (TURN AROUND CONDITION)
Sequential Logic  This occurs when we have logic „1‟ to both gates.
S
A Q
Clock
Q
B R
1
0 t
Qn
t

MASTER SALVE FLIP FLOP
Sequential Logic  To avoid race, master slave configuration is used.
S S
A
Q
Q
B R R
Clock J K Qn+1 𝑸n+1

0   Qn 𝑸n
1 0 0 Qn 𝑸n Memory State
1 1 0 1 0
1 0 1 0 1
1 1 1 𝑸n Qn Toggle state

T FLIP FLOP
Sequential Logic  T Flip Flop is made of master salve configuration of J-K Flip
Flop.
S S
J
Q
Q
K R R
J-K Flip Flop

T
S S
J
Q
Clock
Q
K R R

T FLIP PLOT
Sequential Logic  Functional block representation:
T
S S
J
Q
Clock
Q
K R R
T Q
clk

TYPE OF TRIGGERING (CLOCK)
Sequential Logic  The master slave configuration helps to avoid race condition.
 However, its comes with cost of additional unit, and cause

increase in propagation delay.
 Therefore its effects the operational speed.
 In order to achieve same operational speed without adding

additional flip flop, we can use different type of clock.
1
0 t

BEHAVIOR OF DIFFERENT TRIGGERING
Sequential Logic  For this purpose first let us consider an arrangement of D -
Flip Flop in Master Salve configuration.
D QM D QS
clk clk
QM QS
clk

BEHAVIOR OF DIFFERENT TRIGGERING
Sequential Logic  Here we will observe the effect of different types of
triggering.
clk
D
1
0
QM
QS
QP
QN
TYPES OF FLIP FLOP
Sequential Logic  So far we have discussed 4 types of flip flops:
 S-R Flip Flop,
 D Flip Flop,
 J-K Flip Flop
 T Flip Flop
S Q D Q J Q T Q
clk clk clk clk
R Q Q K Q Q
 Functional Block Representation of Positive Level Triggered

Flip Flops.

TYPES OF FLIP FLOP
Sequential Logic  Functional Block Representation of Negative Level Triggered
Flip Flops:
S Q D Q J Q T Q
clk clk clk clk
R Q Q K Q Q
 Functional Block Representation of Edge Triggered Flip

Flops:
S Q D Q J Q T Q
clk clk clk clk
R Q Q K Q Q
S Q D Q J Q T Q
clk clk clk clk

R Q Q K Q Q
FLIP FLOP AS FREQUENCY DIVIDER
Sequential Logic  Now let us consider the following situation.
+5 V J1 Q1 +5 V J2 Q2
Clock clk Clock clk
K1 Q1 K2 Q2
clk
Q1
Q2

FLIP FLOP AS COUNTER
Sequential Logic  Now let us consider the following situation.
+5 V
J1 Q1 J2 Q2 J3 Q3 J4 Q4
Clock clk clk clk clk
K1 Q1 K2 Q2 K3 Q3 K4 Q4
+5 V
1
Clock
0 t
Q1 t
Q2 t
Q3 t
Q4 t

FLIP FLOP AS COUNTER
Sequential Logic clk Q4 Q3 Q2 Q1
+5 V
0 0 0 0 0 J1 Q1 J2 Q2 J3 Q3 J4 Q4
Clock clk clk clk clk

1 0 0 0 1
K1 Q1 K2 Q2 K3 Q3 K4 Q4
2 0 0 1 0
+5 V
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
clk Q4 Q3 Q2 Q1
6 0 1 1 0
16 0 0 0 0
7 1 1 1 1
17 0 0 0 1
8 1 0 0 0
18 0 0 1 0
9 1 0 0 1
19 0 0 1 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

FLIP FLOP AS ARBITER COUNTER
Sequential Logic  If we want to start count with some different number
than zero or we wish to terminate count before
terminating value 2P, ten we have to use two new
control inputs.
 These inputs are „Preset‟ and „Clear‟, both are active
low inputs.
PS CLR Q 𝑸n
0 1 1 0
J PS Q
1 0 0 1
clk 1 1 Normal
Mode
K CLR Q
0 0 Not
permitted

Sequential Logic  Lets design a up counter which counts form 0 to 5.
 Since its counts up to 5, thus we need 3 bits.
Qa Qb Qc
clk Qc Qb Qa
0 0 0 0 +5 V
1 0 0 1
Ja PSa Qa Jb PSb Qb Jc PSc Qc
2 0 1 0 Clock
clk clk clk
3 0 1 1
Ka CLR a Qa Kb CLRb Qb Kc CLRc Qc
4 1 0 0
5 1 0 1
Qb Qc
6 1 1 0 Qa
0 0 0
+5 V
Clock clk clk clk

Sequential Logic
 Lets design a up counter which counts form 2 to 6.
 Since its counts up to 6, thus we need 3 bits.
Qa Qb Qc
clk Qc Qb Qa
0 0 0 0 +5 V
1 0 0 1
2 0 1 0 Ja PSa Qa Jb PSb Qb Jc PSc Qc
Clock
3 0 1 1 clk clk clk
4 1 0 0 Ka CLR a Qa Kb CLRb Qb Kc CLRc Qc
5 1 0 1
6 1 1 0 Qa
Qb Qc
7 1 1 1
0 1 0
+5 V
Clock clk clk clk
Ka CLRa Qa Kb CLRb Qb Kc CLRc Qc

+5 V
DISADVANTAGES OF RIPPLE COUNTERS
Sequential Logic
 Propagation delay
 Ripple counter works perfect if we have:
 Max clock frequency fmax time period >> N·Tp,
 It mean each flip flop introduces a propagation delay
and this delay get added.
 Now if each FF as a propagation delay of Tp then if
there are N FF, so total propagation delay will be
N·Tp,
 If this total time is order of clock frequency time
period then counting fails.

SYNCHRONOUS COUNTERS
Sequential Logic
 To over come issue of propagation delay of ripple
counter, we can go for synchronous counters.
 Here same clock is applied simultaneously to all FFs.
 Now to able to make this counter to count we have
made changes in circuit. Q Q Q a b c
+5 V
clk Qc Qb Qa
0 0 0 0
clk clk clk
1 1 1 1
2 0 0 0
3 1 1 1
Clock

Sequential Logic
 Synchronous up counter:
clk Qc Qb Qa
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0 Qa Qb Qc
7 1 1 1
+5 V
clk clk clk
21-Jun-21 Clock Digital Electronics (Dr. Nikhil Agrawal) 43

Sequential Logic
 Synchronous up counter:
clk Qd Qc Qb Qa clk Qd Qc Qb Qa
0 0 0 0 0 15 1 1 1 1
1 0 0 0 1 16 0 0 0 0
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0 Qa Qb Qc Qd
9 1 0 0 1 +5 V
10 1 0 1 0
Ja PSa Qa Jb PSb Qb Jc PSc Qc Jd PSd Qd
11 1 0 1 1
clk clk clk clk
12 1 1 0 0 Ka CLRa Qa Kb CLRb Qb Kc CLRc Qc Kd CLRd Qd
13 1 1 0 1
Clock
14 1 1 1 0
FLIP FLOPS AS MEMORY ELEMENTS
Sequential Logic
 As we have discussed that Flip Flop primary task is to
store.
 For this purpose we use D Flip Flop.
 The basic purpose of register is to store group of bits.
A B C D
Da Qa Db Qb Dc Qc Dd Qd
clk clk clk clk
Qa Qb Qc Qd
Qa Qb Qc Qd

FLIP FLOPS AS MEMORY ELEMENTS
Sequential Logic
 For having more control and proper functioning of
register, there are some more controls points.
 Load: Enable to load content on Flip Flops. If this
control is disable irrespective of clock, FF remains
in memory state.
 Clear (clr): It is used to wipeout the content of FF.
 Load: Da Db Dc Dd
Asynchronous load clear
Synchronous load Load
clock
Qa Qb Qc Qd
 Clear:
Asynchronous clear
Synchronous clear

TYPES OF REGISTER
Sequential Logic
 Serial-in to Serial out (SISO): the data is shifted
serially “IN” and “OUT” of the register, one bit at a
time in either a left or right direction under clock
control.
Serial
Data Da Qa Db Qb Dc Qc Dd Qd
clk clk clk clk
clr clr clr clr

clear
clock
Serial
Data out
clk Qa Qb Qc Qd
0 1 0 0 0
1 IN1 1 0 0
2 IN2 IN1 1 0
3 - IN2 IN1 1
4 - - IN2 IN1

TYPES OF REGISTER
Sequential Logic
 Serial in to parallel out (SIPO): the data is shifted
serially “IN” and “OUT” of the register, one bit at a
time in either a left or right direction under clock
control.
A B C D
Serial
Data Da Qa Db Qb Dc Qc Dd Qd
clk clk clk clk
clr clr clr clr

clear
clock

TYPES OF REGISTER
Sequential Logic
 Parallel in parallel out (PIPO): the parallel data is
loaded simultaneously into the register, and transferred
together to their respective outputs by the same clock
pulse. C D
A B
clk clk clk clk
clr clr clr clr

clear
clock
Qa Qb Qc Qd

TYPES OF REGISTER
Sequential Logic
 Shift left register:
Serial
Data
clk clk clk clk
clr clr clr clr

clear
clock

RING COUNTER
Sequential Logic
 A ring counter is a type of counter composed of Flip-
Flops connected into a shift register, with the output of
the last flip-flop fed to the input of the first, making a
“Circular" or “Ring" structure.
clk clk clk clk
Qa Qb Qc Qd
clock
clk Qa Qb Qc  There are N number of states,

0 1 0 0
where N is the number of Flip
Flops. Clock period = N  Sys
1st 0 1 0
2nd 0 0 1
3rd 1 0 0
Clock.
4th 0 1 0

TWISTED RING COUNTER
Sequential Logic
 A twisted ring counter is a type of counter composed of
a shift register, with the complimented output of the last
flip-flop fed to the input of the first, making a "circular"
or "ring" structure.
clk clk clk
Clock

RING COUNTER USING J-K FLIP FLOP
Sequential Logic
 Let us consider a shift register consist of J-K Flip Flop having
Q = 0 and Q’ = 1.
clk Qa Qb Qc  There are 2  N number of states,
0 0 0 0 where N is the number of Flip Flops.
1st 1 0 0 Clock period = 2  N  Sys Clock.
2nd 1 1 0
3rd 1 1 1  There is phase difference of one
4th 0 1 1 original clock period between
5th 0 0 1 successive clock.
6th 0 0 0
 This is known as Multi-phase clock.
1
Clock
0 t
Qa t
Qb t
Qc t
RING COUNTER USING J-K FLIP FLOP
Sequential Logic
 This is also known by:
 Johnson counter,
 Recirculating shift register,
 Twisted Ring counter.

Sequential Logic  Let us consider that Clock
1
0 t
only one on pulse is
A
required for one clock t
period. B t
C t
D t
E t
F t
clk Qa Qb Qc 𝑸𝒂 𝑸𝒃 𝑸𝒄 Logic
1 0 0 0 1 1 1 𝑄𝑎 ∙ 𝑄𝑐
2 1 0 0 0 1 1 𝑄𝑎 ∙ 𝑄𝑏
3 1 1 0 0 0 1 𝑄𝑏 ∙ 𝑄𝑐
4 1 1 1 0 0 0 𝑄𝑎 ∙ 𝑄𝑐
5 0 1 1 1 0 0 𝑄𝑎 ∙ 𝑄𝑏
6 0 0 1 1 1 0 𝑄𝑏 ∙ 𝑄𝑐
0 0 0 1 1 1
Sequential Logic
 Now lets examine graphically:
1
Clock
0 t
Qa t
Qb t
Qc t
Qa
t
Qb
t
Qc
t Logic
A 𝑄𝑎 ∙ 𝑄𝑐
t
𝑄𝑎 ∙ 𝑄𝑏
B t
𝑄𝑏 ∙ 𝑄𝑐
C t
𝑄𝑎 ∙ 𝑄𝑐
D t 𝑄𝑎 ∙ 𝑄𝑏
E 𝑄𝑏 ∙ 𝑄𝑐
t
21-Jun-21 F Digital Electronics (Dr. Nikhil Agrawal) t 56

Sequential Logic
 Now the circuit:
clk clk clk
Clock
Logic
B 𝑄𝑎 ∙ 𝑄𝑏
𝑄𝑎 ∙ 𝑄𝑏

PSEUDO RANDOM SEQUENCE GENERATOR
Sequential Logic
 Now consider one of the application of serial in parallel
out shift (SIPO) register. clk A B C D
0 1 0 0 0
Db Dc Dd
Da 1st 0 1 0 0
Serial
Input Load 2nd 0 0 1 0
clear 3rd 1 0 0 1
clock
Qa Qb Qc Qd
4th 1 1 0 0
5 0 1 1 0
6 1 0 1 1
7 0 1 0 1
8 1 0 1 0
9 1 1 0 1
A B C D
10 1 1 1 0
11 1 1 1 1
12 0 1 1 1
13 0 0 1 1
14 0 0 0 1
21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal)
15 1 0 0 58 0
STATE MACHINE
Sequential Logic
 A digital machine, which have different states or level
in which it may switch is known as State machine.
 Combinational circuits have only one state.
 Sequential circuits come under State machine.
x z
clk
S0
S3 S1
x=1
21-Jun-21
S 2
Digital Electronics (Dr. Nikhil Agrawal) 59
STATE MACHINE
Sequential Logic
 If machine has external output also associated with
states.
S. No. State
x z
1 S0 00
2 S1 01 clk
3 S2 10
4 S3 11 A B
S0
QA DA
z=1
S3
S1
QB DB
z=1
z=0
S2
21-Jun-21 z = 1 (Dr. Nikhil Agrawal)
Digital Electronics 60
STATE MACHINE
Sequential Logic
 Now clock is the actual event that triggers the
transaction.
 Therefore, the digital system will now be:
Input Output
S. No. State
x y
1 S0 00 Present state Next state
information A A information
2 S1 01 B B
3 S2 10 DB
QB
4 S3 11 clk
QA DA
clk
S0
z=1
S3
S1
z=1
z=0
S2
21-Jun-21 z Digital
=1 Electronics (Dr. Nikhil Agrawal) 61
COUNTER AS STATE MACHINE
Sequential Logic
 Counter is an example of state machine, whose state
diagram will be:
000
111 S0 001
S7 S1
S6 S2 010
S5 S3 011
S4
101 3 Bit A
100
Counter B
clk
C

STATE MACHINE
Sequential Logic
 Now clock is the actual event that triggers the
transaction.
 Therefore, the digital system will now be:
Input Output
S. No. State
x y
1 S0 00 Present state Next state
2 S1 01 B B
3 S2 10
QB DB
4 S3 11 clk
QA DA
S0 clk
z=1
S3
S1
Generalized Model of a State Machine
z=1
z=0
S2
z=1
21-Jun-21 State (Dr.
Digital Electronics diagram
Nikhil Agrawal) 63
STATE MACHINE EXAMPLE
Sequential Logic
 Let us consider an example of traffic light controller.
Main Main
Road Road
Secondary Secondary
Road Road
GR YR
 Main Road Green (MR-G) Secondary Road Red (SR-

R). State is (GR).
 Main Road Yellow (MR-Y) Secondary Road Red (SR-
R). State is (YR).
Sequential Logic
 Stage 2
Main Main
Road Road
Secondary Secondary
Road Road
YR RG
 Main Road Yellow (MR-Y) Secondary Road Red (SR-

R). State is (YR).
 Main Road Red (MR-R) Secondary Road Green (SR-
G). State is (RG).
Sequential Logic
 Stage 3
Main Main
Road Road
Secondary Secondary
Road Road
RG RY
 Main Road Red (MR-R) Secondary Road Green (SR-

G). State is (RG).
 Main Road Red (MR-Y) Secondary Road Yellow (SR-
Y). State is (RY).
Sequential Logic
 Stage 4
Main Main
Road Road
Secondary Secondary
Road Road
RY GR
 Main Road Red (MR-R) Secondary Road Yellow (SR-

Y). State is (RY).
 Main Road Green(MR-G) Secondary Road Red (SR-Y).
State is (GR).
Sequential Logic
 Now we can make the state graph as:
S0
GR
S1
S3
YR  Now there must be
RY
S2
some input on basis of
RG which transition of
states must occur. Lets
T1 = 0 us consider some input,
S0 which sets to „1‟, when
T4 = 1 GR desired time reaches.
S1
S3
YR T2 = 0
T4 = 0 RY
S2
RG
T3 = 0
Sequential Logic
 Now from state graph we can have our state machine:
T1 = 0
S0
T4 = 1 GR
S1
S3
YR T2 = 0
T4 = 0 RY Combination
Outputs
Inputs logic
S2
T1 GR
RG
T2 YR
T3 RG Next
T3 = 0 State
T4 RY
A+ DA QA
Present clk
State A QA
B B+ DB QB
clk
QB
QC
QC clk
Clock
ARBITRARY COUNTER
Sequential Logic
 Now lets consider an example of arbitrary counter
1, 4, 3, 5, 2, 6 A B C
0 0 1
1 0 0
001 0 1 1
S0 1 0 1
0 1 0
110 S5 S1 100
1 1 0
010
S4 S2 011
S3
21-Jun-21 101 (Dr. Nikhil Agrawal)
ARBITRARY COUNTER
Sequential Logic
 Now state machine will be:
001
Excitation Table
S0
Qn Qn+1 D
110 S5 S1 100
0 0 0
0 1 1
010
S4 S2 011
S3 Combination
logic
Next
State
101 A+ Da QA
clk
QA
Present
State B+ DB QB
A clk
B QB
C C+ DC Qc
clk
QC
QC
QC clk

Clock 71
DESIGN OF ARBITRARY COUNTER
Sequential Logic
 Now designing of state machine starts with formulation
of state table:
1, 4, 3, 5, 2, 6
State Table
001
Present State Next State
S0
A B C A+ B+ C+ 110 S5 S1 100
0 0 0   
0 0 1 1 0 0
010
S4 S2 011
0 1 0 1 1 0
S3
0 1 1 1 0 1
101
1 0 0 0 1 1
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1   
Sequential Logic
 Now we have to design logic for A+, B+, and C+ which
are inputs to D Flip Flops using K Map.
BC
State Table 00 01 11 10
Present State Next State 0  1 1 1
A
A B C A+ B+ C+ 1 0 0  0
0 0 0   
0 0 1 1 0 0
K Map for A+ A  A
0 1 0 1 1 0
0 1 1 1 0 1 BC
1 0 0 0 1 1 00 01 11 10
1 0 1 0 1 0 0  0 0 1
A
1 1 0 0 0 1 1 1 1  0
1 1 1   
K Map for B+ B  A  B  A  C
Sequential Logic
 Now we have to design logic for A+, B+, and C+ which
are inputs to D Flip Flops using K Map.
BC
State Table 00 01 11 10
Present State Next State 0  0 1 0
A
A B C A+ B+ C+ 1 1 0  1
0 0 0    K Map for C+
0 0 1 1 0 0 C  AC  B C
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 0 1 1
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1   
Sequential Logic
 We will proceed to design:
A  A B  A  B  A  C C  AC  B C
Da QA
clk
Combinational
Combination
logic
Next
State
Circuit QA
A+ Da QA
clk
QA
Present
State A
B+ DB QB B+ DB QB
B
clk
QB A clk
C C+ DC Qc
clk
QC B QB
QC
C+
QC clk
Clock
C DC Qc
A clk
QC
Clock
QC clk
DESIGN OF ARBITRARY COUNTER USING J-K FF
Sequential Logic
 We will proceed to design:
Combination
logic
Next
State
Ja QA
A+ clk
KA QA
Present
JB QB
State A B+ clk
B KB QB
C JC Qc
C+
clk
KC QC
QC
QC clk
21-Jun-21 Digital Electronics

Clock (Dr. Nikhil Agrawal) 76
J-K FF
Sequential Logic
 State table will be modified now:
Transition Table
A B C JA KA JB KB JC KC A+ B+ C+
0 0 0         
0 0 1 1 0 0
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 0 1 1
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1         

J-K FF EXCITATION TABLE
Sequential Logic
 For switching into next state form current state, we use
excitation table:
J K Qn Qn+1 J K Qn+1
0 0 0 0 0 0 Qn
0 0 1 1 0 1 0
0 1 0 0 1 0 1
0 1 1 0 1 1 𝑸n
1 0 0 1
1 0 1 1 Excitation Table
1 1 0 1 Qn Qn+1 J K
1 1 1 0 0 0 0 
0 1 1 
1 0  1
21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 1 1  0 78
Sequential Logic
 State table will be modified now:

A B C A+ B+ C+ JA KA JB KB JC KC
0 0 0         
0 0 1 1 0 0 1
0 1 0 1 1 0 1
0 1 1 1 0 1 1
1 0 0 0 1 1 
1 0 1 0 1 0 
1 1 0 0 0 1 
1 1 1         

Sequential Logic
 Final transition table:

A B C A+ B+ C+ JA KA JB KB JC KC
0 0 0         
0 0 1 1 0 0 1  0   1
0 1 0 1 1 0 1   0 0 
0 1 1 1 0 1 1   1  0
1 0 0 0 1 1  1 1  1 
1 0 1 0 1 0  1 1   1
1 1 0 0 0 1  1  1 1 
1 1 1         

Sequential Logic
 Now steering logic BC
00 01 11 10
A B C JA KA 0  1 1 1
A
0 0 0   1    
0 0 1 1  K Map for JA
0 1 0 1  JA 1
0 1 1 1 
1 0 0  1 BC
1 0 1  1 00 01 11 10
1 1 0  1 0    
A
1 1 1   1 1 1  1
K Map for KA
KA 1
Sequential Logic
00 01 11 10
A B C JB KB 0  0  
A
0 0 0   1 1 1  
0 0 1 0  K Map for JB
0 1 0  0 JB  A
0 1 1  1
1 0 0 1  BC
1 0 1 1  00 01 11 10
1 1 0  1 0   1 0
A
1 1 1   1    1
K Map for KB
KB  A  C
Sequential Logic
00 01 11 10
A B C JC KC 0    0
A
0 0 0   1 1   1
0 0 1  1 K Map for Jc
0 1 0 0  JC  A
0 1 1  0
1 0 0 1  BC
1 0 1  1 00 01 11 10
1 1 0 1  0  1 0 
A
1 1 1   1  1  
K Map for Kc
KB  B
Sequential Logic
 State Machine
1 Next
State
Ja QA
A
clk
KA QA A
Present
State JB QB
B
A clk
KB QB
C B
JC Qc
C
A clk
KC QC C
B
QC
QC clk
Clock
DESIGN EXAMPLE
Sequential Logic
 Let make the inclusion of input in the previous design
example
State Table
A B x (i/p) A+ B+
0 0 0 0 0
S0
0 0 1 0 1
0 1 0 1 0
0 1 1 0 1
S3 S1
1 0 0 0 0
1 0 1 1 1
S2 1 1 0 0 1
1 1 1 0 0

DESIGN EXAMPLE CONT…
Sequential Logic
 Now steering logic for state machine using D FF
Bx
State Table
Next State 00 01 11 10
Present State
A+ B+ 0 0 0 0 1
A B x (i/p) A
0 0 1 0 1 0 0
0 0 0
0 0 1 0 1 K Map for DA
0 1 0 1 0 DA  A  B  x  A  B  x
0 1 1 0 1 Bx
1 0 0 0 0
00 01 11 10
1 0 1 1 1
0 0 1 1 0
1 1 0 0 1 A
1 0 1 0 1
1 1 1 0 0
K Map for DB

DB  A  B  B  x  A  86B  x
STATE MODEL
Sequential Logic
 State machine model
Da QA
x
clk
Combinational +
B QA
Circuit
A
B DB QB
clk
clk
QB
C
Clock

DESIGN EXAMPLE
Sequential Logic
 Design a state machine for given state graph
S1
x=1
S3 S2
S2
x=1

STATE MODEL WITH OUTPUT
Sequential Logic
 State machine with outputs State Machines with
Output
 Mealy State
Machine
have output Mealy State Machine Moore State Machine
associated Combination
with input logic
and state. Z1 Outputs

Inputs T1
 Moore State T4 ZM
Machine A+ DA QA
have output clk QA

associated A DB QB
with and state B B+ clk

QB
only.
Clock
MEALY STATE MODEL WITH OUTPUT
Sequential Logic
 State machine with outputs. Combination
logic
Inputs x z Outputs
A+ DA QA
Present clk QA
State A DB QB
B B+ clk
QB
x=0
z=0 Clock
S0
S2 x=1
x=0 S1
z=0
z=1
21-Jun-21 S2 (Dr. Nikhil Agrawal)
Sequential Logic Bx
 State machine with outputs.
00 01 11 10
State Table 0 0 0 0 1
A
Present State Next State 1 0 0  
A B x (i/p) A+ B+ z (o/p) K Map for DA
0 0 0 0 0 0 DA  B  x
0 0 1 0 1 0 Bx
0 1 0 1 0 1
0 1 0 00 01 11 10
0 1 1
0 0 0 A 0 0 1 1 0
1 0 0
0 0 1 1 0 0  
1 0 1
1 1 0   0 K Map for DB
1 1 1   0 DB  A  x  B  x

Sequential Logic Bx
 State machine with outputs.
00 01 11 10
State Table 0 0 0 0 1
A
Present State Next State 1 0 1 0 0
A B x (i/p) A+ B+ z (o/p) K Map for z
0 0 0
0 0 0 z  A  B  x  A B  x
0 0 1 0 1 0
0 1 0 1 0 1
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 0 0 1
1 1 0   0
1 1 1   0

PATTERN DETECTOR BY MEALY MACHINE
Sequential Logic
 Design a state machine with outputs.
 Task is that machine must produce logic „1‟ on
successful identification of pattern „010‟.
 Overlapping of pattern is allowed.
Input Output
x z
Present state Next state
B B
QB DB
clk
QA DA
clk

Sequential Logic
 Now first task is to draw the state graph.
 x=0110010100…
 y = 0 0 0 0 0 0 1 0 1 0…
x/ z
1/ 0  S0 = Reset
x/ z
S0
x/ z
0/ 0  S1 = „0‟
1/ 0
S1 x/ z  S2 = „01‟
x/ z
0/ 0
0/ 1
S2 x/ z
1/ 0

MEALY MACHINE STATE TABLE
Sequential Logic
 State machine with outputs.  S0 = 00
State Table  S1 = 01
Present State Next State  S2 = 10
A B x (i/p) A+ B+ z (o/p)
Bx
0 0 1 0 0 0
0 0 0 0 1 0 00 01 11 10
0 1 0 0 1 0 0 0 0 1 0
A
0 1 1 1 0 0 1 0 0  
1 0 0 0 1 1 K Map for DA
1 0 1 0 0 0 DA  B  x
1 1 0   0
1 1 1   0

Sequential Logic
Bx
0 0 1 0 0 0
0 0 0 0 1 0 00 01 11 10
0 1 0 0 1 0 0 0 1 0 1
A
0 1 1 1 0 0 1 1 0  
1 0 0 0 1 1 K Map for DB
1 0 1 0 0 0 DB  B  x  A  x  A  B  x
1 1 0   0
1 1 1   0

Sequential Logic
Bx
0 0 1 0 0 0
0 0 0 0 1 0 00 01 11 10
0 1 0 0 1 0 0 0 0 0 0
A
0 1 1 1 0 0 1 1 0  
1 0 0 0 1 1 K Map for z
1 0 1 0 0 0 z  A x
1 1 0   0
1 1 1   0

Sequential Logic  State Machine Model

Sequential Logic
 Design a state machine with outputs.
 Task is that machine must produce logic „1‟ for one
clock period on successful identification of pattern
„010‟ and 1001.
 Overlapping of pattern is allowed.

Sequential Logic
 Now first task is to draw the state graph.
 x=011000100100101100…
 y=00000001011010100…
x/ z  S0 = Reset
x/ z 0/ 0
1/ 0  S1 = „0‟
S0
x/ z
1/ 0 x/ z  S2 = „1‟
S2 S1 0/ 0
x/ z  S3 = „01‟
0/ 0
x/ z  S4 = „10‟
x/ z S3 1/ 0
0/ 1 x/ z
S4  S5 = „100‟
1/ 0 x/ z
1/ 1 x/ z
21-Jun-21
x/ z S5
Digital Electronics (Dr. Nikhil Agrawal)
0/ 0 100
0/ 0
Thank You
Email: nagrawal@iiit.ac.in

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DIGITAL ELECTRONICS

 Previous output is nothing but the present state.

 Therefore, sequential circuits contain combinational circuits

 Some sequential circuits may not contain combinational

Input Combinational Output

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 3

Combinational Circuits Sequential Circuits

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 4

 Latches operate with enable signal, which is level

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 6

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 8

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 9

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 10

 S =0 & R = 1, we have Q = 0 & Q’ = 1.

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 11

 S =0 & R = 0, we have Q = 1 & Q’ = 0. Memory State

 Since memory state failed to retains correct values, therefore

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 14

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 15

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 16

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 17

 Functional block of SR Latch using NAND.

Clock R S Q’ Q  When clock is low FF

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 19

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 20

 Duration of on time for clock pulse must be greater than

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 21

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 22

Clock A B Qn+1 𝑸n+1

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 23

Clock A B Qn+1 𝑸n+1

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 24

Clock A B Qn+1 𝑸n+1

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 25

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 26

Clock J K Qn+1 𝑸n+1

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 27

J-K Flip Flop

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 28

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 29

 However, its comes with cost of additional unit, and cause

 Therefore its effects the operational speed.

 In order to achieve same operational speed without adding

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 30

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 31

 S-R Flip Flop,

 J-K Flip Flop

clk clk clk clk

 Functional Block Representation of Positive Level Triggered

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 33

clk clk clk clk

 Functional Block Representation of Edge Triggered Flip

clk clk clk clk

clk clk clk clk

Clock clk Clock clk

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 35

Clock clk clk clk clk

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 36

Clock clk clk clk clk

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 37

21-Jun-21 Digital Electronics (Dr. Nikhil Agrawal) 38

Ja PSa Qa Jb PSb Qb Jc PSc Qc