Lokmanya Tilak Jankalyan Shikshan

Sanstha’s
PRIYADARSHINI J. L.
COLLEGE OF ENGINEERING,
NAGPUR
846, New Nandanvan Layout, Nagpur
– 440 009

DEPARTMENT OF ARTIFICIAL INTELLIGENCE

Question Bank

Programme : Artificial Semester : VI

Intelligence

Course Code : BECSE404T Course Title : Digital System Design Using

Verilog

Course Teacher : Prof. P. S. Date of Display : 17-03-2023

Chawla

UNIT-II

Q1.Explain about array of Instances in Verilog with example.

Q2.Write a Verilog code for Half Adder.
Q3.Write a Verilog code for 4:1 MUX.
Q4.Explain Conditional Operator and Operator Precedence in Verilog.
Q5.Define and explain Tri-state gates.
Q6.Explain Strength and Contention Resolution.
Q7.What is Continuous Assignment Structure.
Q8.Write a Verilog Code for SR-Latch and also write Stimulus code.
Q9. What are Rise, Fall and Turn-Off Delays.
Q10. What would be the output of the following if A=4’b0111 B=4’b1001
i) &B ii)A<<<2 iii){A,B} iv){2{B}} v)A^B vi)A|B vii)A*B
viii)A<=B
Q11. Design AOI based 4 : 1 MUX and write verilog code and its stimulus code.
Q12. Explain the following Data Types with an example i) Nets ii)Register
iii)Vectors iv)Parameters
Q13. What are the four values and eight strengths support in Verilog.List out with
neat table.
Q14.Declare the following variables in Verilog
i) decimal number 123 as a sized 8 bit number in binary.
ii) a 16 bit hexadecimal number with all x’s
iii) a 4 bit negative 2 in decimal.Write 2’s compliment for this number.
iv) an unsized hexadecimal number 1234
Q15. Write a Verilog data flow description for 4-bit full adder with carry look ahead.