Lokmanya Tilak Jankalyan Shikshan

Sanstha’s
PRIYADARSHINI J. L.
COLLEGE OF ENGINEERING,
NAGPUR
846, New Nandanvan Layout, Nagpur
– 440 009

DEPARTMENT OF ARTIFICIAL INTELLIGENCE

Question Bank

Programme : Artificial Semester : VI

Intelligence

Course Code : BECSE404T Course Title : Digital System Design Using

Verilog

Course Teacher : Prof. P. S. Date of Display : 17-03-2023

Chawla

UNIT-I

Q1.Write difference between Task and Function.

Q2.Mention Data Types used in Verilog.
Q3.Explain the Lexical Conventions with example.
i) White Spaces ii)Strength iii)Operators
Q4.Write notes on Concurrency and Functional Verification.
Q5.Explain Port Declaration using Verilog code.
Q6.Write short notes on Programming Language Interface.
Q7.Explain System Tasks in detail.
Q8.Define and Explain Keywords,Identifiers and Parameters.
Q9.Explain the typical Design Flow for designing VLSI IC circuits using block
diagram.
Q10.What are the advantages of HDL? Explain Trends in HDL.
Q11.Explain Top-Down and Bottom-Up design Methodology with an example.
Q12.Explain different levels of abstraction used for programming in Verilog.
Q13. Explain module and module instances with an example.
Q14.Explain in detail the Levels of design description.
Q15. Explain Simulation and Synthesis in Verilog HDL.
Q16. Explain with exampleabout:1)Display Task ii)Strobe Task iii)Monitor Task
Q17.Write the difference between Task and Function.
Q18.What is the difference between scalar and vector in module.
Q19.Define Strength and list out types of strength.
Q20.Write short notes on Compiler Directives.
Q21.Define and Explain Keyword ,Parameter.