Lokmanya Tilak Jankalyan Shikshan

Sanstha’s
PRIYADARSHINI J. L.
COLLEGE OF ENGINEERING,
NAGPUR
846, New Nandanvan Layout, Nagpur
– 440 009

DEPARTMENT OF ARTIFICIAL INTELLIGENCE

Question Bank

Programme : Artificial Semester : VI

Intelligence

Course Code : BECSE404T Course Title : Digital System Design Using

Verilog

Course Teacher : Prof. P. S. Date of Display : 06-04-2023

Chawla

UNIT-III

Q1. Describe behavior of JK Flip Flop using an Always statement.

Q2. Write a Verilog program for a positive edge triggered D Flip Flop with
Asynchronous clear (q=0) and preset (q=1) using assing and de-assign statements.
Q3. Discuss LOOP and Forever statement with an example.
Q4. Design a 4x1 MUX and develop a Verilog code using case statement.
Q5. Diferentiate between blocking and non-blocking statement.
Q6. Discuss types of delays in the continuous assignment statement.
Q7. Design a 2x1 MUX using bufif0 and bufif1 gates.Write Verilog code using gate
level modelling for the given delay specifications

Min Max Typ

Rise 1 3 5
Fall 3 5 4
Turn-off 5 7 6

Q8. Discuss the gate delays along with its types of delay specifications
Q9. Using Forever statement design a clock with time period=10 and duty
cycle=40%,initial value of clock is 0.
Q10. Write a Verilog program for 8:1 MUX using Case statement and test bench.
Q11. Write a Verilog Description of D-Flip Flop using assign and de-assign
procedural continuous assignments.
Q12.Write a Verilog code for clock generation with a period of 20 units using forever
loop.
Q13. Write a Verilog module for 8-bit comparator with test bench.
Q14. Describe procedural continuous assignment statements -assign,de-assign,force
and release.
Q15. Write a Verilog module for positive edge triggered flip flop with test bench.
Q16. Explain how Always statement are used in Verilog.
Q17. Write difference between intersegment delay and intrasegment delay using
example.
Q18. Explain Case statement in detail with example.
Q19. Explain if then else statement and its variations with example.
Q20. Explain Wait construct with example.