2023 Digital Control Homework #2

Part I: Essay Problems

1. Consider the discrete dynamics G in Figure 1, which is a composite of three operators at the
sampling period T : the first-order holder (FOH), a continuous dynamics Ĝ , and the sampler.

u First-order û Continuous ŷ Sampling y

Holder @ T Dynamics Ĝ @ T

Discrete Dynamics G
Figure 1

(a) Let u be a unit pulse defined by

u (0)  1 and u (k )  0 , k  1,2,
Prove that the Z -transform of a unit pulse is one, that is,
Z u (k )  1 .
(b) Prove the principle of convolution:

y (n)   u (k ) g (n  k ) , n  1,2,
k 0

where g is the impulse response of the dynamics G , which is defined by the output of G
subject to the unit-pulse. Therein u is any bounded input, and y is the output resulting
therefrom.
(c) With the convolution summation in (b), derive the principle of Block Diagram, i.e.
Y ( z )  G ( z )U ( z ) .
Thus, the transfer-function of G is defined by the Z -transform of its impulse response.
Reason this definition.
(d) The above functional analysis implies a complete basis of linearly interpolated functions?
What is it? Prove your answer.

2. Following Prob. #1, let the transfer function of the continuous dynamics in Figure 1 be
1
Gˆ ( s )  .
s
(a) Calculate the impulse response g of the discrete dynamics G , based on which calculate
the transfer function of G .
(b) Infer the ordinary difference equation (ODE) that governs the discrete dynamics G from
its transfer function derived in (a).
(c) Based on the ODE in (b), show that G is just the Tustin equivalent of Ĝ . That is, check
whether or not temporal integration is approximated by trapezoidal area.
 (d) Derive the controllability-canonical state-space realization of G based on the ODE
inferred from (b),
(e) Write down the digital implementation of G with discrete state-space (IIR-SS).

3. Consider the digital implementation of a single-degree vibrator Ĝ :

s
Gˆ ( s )  ,
s 2
2

as a frequency generator. Let the input to Ĝ be a unit step, and  is the to-be-generated
(angular) frequency, which is able to be changed in real-time fashion. Let G be the Tustin
equivalent of Ĝ at sampling period T .
(a) (5%) What is the transfer function of G ?
(b) (5%) Express all state-space realizations of G .
(c) (5%) Digitally implement G with IIR-SS.
(d) (5%) Digitally implement G with IIR-AC, that is, directly digitalize the analog computer of
controllability-canonical form.
(e) (5%) Digitally implement G with IIR-AO, that is, directly digitalize the analog computer of
observability-canonical form.

4. The fundamental principle of Digital Control says that ‘Incorparation delay of half a sampling
period into continuous plant results in excellectent prediction of sampling effects’.
(a) Explain this argument by assessing stairs fumctions in time domain and frequncy domian.
(b) Take the intergrator, Gˆ ( s )  1 / s , to verify this argement. Compare the frequncy response of
its ZOH equivalent with that of its Tustin equivalent at sampling period T  0.2 .

5. Consider a van der Pol oscillator Ĝ serial-connected by a first-order low-pass filter:

y  10( y 2  1) y   2 y  0 ,
Z (s) 2
 ,
Y ( s ) 1   1 s
to be a frequency generator. Apply ZOH equivalence to digitally implement such a nonlinear
dynamics.

Part II: Optional problems (pick up one from options)

1. In the design of actuators, sensors or other components, we choose microcontrollers rather than
general-purpose processors to implement transfer functions for dynamic regulation, mainly
because microcontrollers (A) are usually comprised of A/D and PWM peripherals (B) are usually
implemented into an open-source operating system (C) cost much less than generous-purpose
computers (D) can perform computer simulation (E) spend much less time on communicating
with the environment through peripherals.
2. A general-purpose microprocessor is usually (A) of RISC (Reduced Instruction Set Computer)
architecture (B) comprised of a diversity of peripherals (C) less expensive than a microcontroller
(D) more energy-saving than an embedded controller (E) supported by an operating system being
the bridge between application instructions and computing units.
3. Implementation of ordinary differential equations into microcontrollers (A) is of similar process
to computer-simulation programming (B) is an important technique for control synthesizers (C)
is replacing DSP techniques (D) is easy for Matlab users (E) can obtain phase compensation or
magnitude filtering.
4. Programmers get peripherals to work by setting the contents of (A) file registers (B) BIOS (C)
flash memory (D) EEPROM (E) special function registers.
5. Which is an advantage of implementing transfer functions into a microcontroller over an analog
computer? (A) The latter is merely capable of minimum-phase functions (B) The former needs
no signal conditioners (C) The former is adaptable to communication with digital devices (D)
The former is more energy-saving (E) The latter does not need power supply.
6. Compared with analog computers, dsPIC chips (A) do computation faster (B) are capable of
filtering white noises out of measurement (C) are belonging to model-based design (D) are
usually supported by Windows (E) need less signal conditioners.
7. PWM signals are usually sent to the (A) driving circuits of switching power converters (B) signal
conditioners (C) voltage regulators (D) power-amplification devices (E) motors.
8. For dsPIC embedded design, C30 coding is more popular than Assembly 30; however the latter
(A) has more flexible addressing modes (B) is more portable (C) involves tidy programming (D)
is more friendly to users (E) create smaller hex files.
9. Feedback control programmed into the microcontrollers mounted on the controller board can not
(A) improve energy-efficiency of the steady-state responses (C) make the operation more
reliable (C) change transient responses (D) filter color noises (E) communicate with other
modules in designing a new mechanical component.
10. Microchip dsPIC4012 is with the CAN bus peripheral mainly for the industry of (A) machine
tools (B) green energy (C) electric machinery (D) cars (E) motors.
11. The UART peripheral in a dsPIC can connect to PC through (A) USB ports (B) PCIs (C) RS232
ports (D) parallel ports (E) Internet cards.
12. The CPU of dsPIC 4011 is not comprised of (A) Program Counter (B) DSP Engine (C) Divide
Unit (D) Instructor Decoder (E) ALU.
13. The DSP engine in a dsPIC is specially designed for (A) Boolean operation (B) addition and
multiplication of floating numbers (C) setting up barrel shifting (D) controlling data flow (E)
being adaptable to Harvard architecture.
14. In general, the DSP engine takes (A) two (B) three (C) four (D) six (E) eight clock periods to
execute one instruction.
15. The current content of the program counter will be pushed down into the top stack register when
(A) the CPU is busy (B) work registers overflow (C) clock signals are contaminated (D)
interruption subroutines are to be executed (E) regular subroutines finish executing.
16. An instruction word is of (A) 8 (B) 12 (C) 16 (D) 20 (E) 24 bits in dsPIC 4011.
17. The program counter in dsPIC 4011 is of 24 bits, that is, there are (A) 64K (B) 2M (C) 4M (D)
16M (E) 64M addresses in code memory space.
18. The code data bus is of 16 bits in dsPIC 4011, that is, an instruction occupies (A) 1 (B) 2 (C) 4
(D) 8 (E) 16 addresses.
19. The data address bus is of 16 bits in dsPIC 4011, that is, there are (A) 4K (B) 8K (C) 16K (D)
32K (E) 64K addresses in data memory space.
20. Which of the followings about dsPIC 4011 is not correct? (A) Some of data memory addresses
is not physically implemented (B) The bus to fetch the contents of file registers is of 16 bits (C)
The content in each data address is of 16 bits (D) In fact, Modified Harvard architecture is
applied by all dsPIC chips (E) There are more than 3 levels of stacks.
21. Why is Harvard architecture not applied by generous-purpose processors? (A) Wiring layout is
 expensive (B) Execution will become slower (C) Reduced Instruction Set Computer is applied
(D) Too many registers are needed (E) Operating system adapts merely to von Neumann
architecture.
22. Static RAM has an advantage over dynamic RAM, that is, it (A) costs less in manufacturing (B)
does not need to be refreshed from time to time (C) needs one capacitor to store one bit of data
(D) is still suitable for generous-purpose computers (E) keeps the data in memory space as the
power supply is off.
23. With the DSP engine, dsPIC chips are the best choice to design (A) Programmable Logic
Controller (B) high-resolution analog signal acquisition (C) an operation with analog inputs and
analog outputs (D) online Fourier transform (E) high-order filters.
24. Special function registers in Microchip datasheets are not used to (A) store data (B) reveal
status (C) control peripherals (D) set up operation parameters (E) perform indirect addressing
modes.
25. As the power of dsPIC is reset, the program counter is reset to point to the starting address of (A)
the code ROM (B) Interruption Vector Table (C) Alternate Vector Table (D) Data EEPROM (E)
Device Configuration Registers.
26. Any peripheral calls the chip’s CPU for special task through (A) trigging ports (B) resetting the
clock (C) power reset (D) watchdog timer’s detection (E) interrupting the program on going.
27. Compared with Microcontroller Units (MCU), the dsPIC digital controllers (A) handle floating
numbers more powerfully (B) are more energy-saving (C) are more inexpensive (D) own a
bigger market (E) have more reduced set of instructions.
28. ICD2 is not used to (A) load codes into ROM (B) perform in-circuit debugging (C) detect
syntax errors (D) watch contents of registers (E) check the machine codes.
29. The Harvard architecture shortens the execution time because (A) it allows for pipelining (B) it
makes an instruction executed with less than four clock periods (C) it utilizes many kinds of
special function registers (D) the code and file registers share the same data bus (E) the code
data bus has dual channels.
30. Most of capacitors in the auxiliary circuit of a dsPIC are for (A) voltage regulation (B) current
amplification (C) power switching (D) prevention for surging currents from damaging codes or
data (E) filtering noises.
31. The C30 instruction “while (1)” means (A) execution forever (B) jumping to the next line (C)
execution in case of truth (D) execution in case of false (E) staying here until “0” is happened.
32. The CLK signals that enables flip-flops in peripherals are transferred though the (A) code
address bus (B) code data bus (C) RAM address bus (D) RAM data bus (E) CAN bus.
33. Which of the following statements about dsPICs’ peripherals is not correct? (A) Every
peripheral is on when the chip is reset (B) Special function resisters are the bridge between CPU
and peripherals (C) PWM modules are programmed for switching power converters to drive the
actuators (D) Most of peripherals can be programmed to work under interruption mode (E)
Watchdog is not a peripheral.
34. Compared with Assembly 30, C30 sources codes (A) are not friendly (B) are less portable (C)
runs more faster (D) are more powerful in memory management (E) do not clear the
interruption flags as the related peripherals are to re-enabled.
35. Which of the following statements about the dsPICs’ ports is not correct? (A) Each pin can
accommodate only one channel of a port, even though it is multiplex functional (B) With Port
Configuration, the Port B can be set to input analog signal (C) Buffers of ports are made of
flip-flops (D) Improper resistance connected to an input port in the auxiliary circuit of the chip
could damage the port due to impulsive currents (E) With Tri-state registers, ports can be
disabled.
36. Which of the following statements about the Interruption of dsPIC30F4011 is not correct? (A)
There are 30 kinds of interruption (B) Each interruption is enabled by an interruption flag bit,
even though the enable bit is not set (C) There are 30 interruption-enable bits (D) The next
contents of program counter are pushed into stack memory when interruption routines are to be
performed (E) There are 7 levels of interruption priority.
37. Which of the following statements about the ADC module is not correct? (A) There is one ADC
converter (B) There are four sample-holders (C) There are nine input channels (D) The
maximum sampling rate can be 500k for merely one sample-holder involved to work (E) The
ADC clock period is the same as the instruction period.
38. The symbol of Tad appearing at the ADC chapter in the dsPIC30F4011/4012 datasheet means
(A) the period of the internal clock (B) the period of the instruction (C) the time required for
data acquisition (D) the time required for data conversion (E) the period of the ADC clock.
39. Inside any of the 16 ADC buffers, the value is at most about (A) 1K (B) 4K (C) 16K (D) 32K (E)
64K.
40. To set the PWM, we need to (1) enable the PWM; (2) set the PWM frequency; and (3) change
the PWM duty, which are better programmed in the sequence of (A) (1)-(2)-(3) (B) (1)-(3)-(2)
(C) (3)-(2)-(1) (D) (2)-(3)-(1) (E) (2)-(1)-(3).
41. Microchip developed PWM modules originally for serving the industry of (A) power converters
(B) generous-purpose processors (C) linear technology (D) automobiles (E) machines tools.
42. Most of Microchip’s DAC chips are supported by (A) CAN bus (B) UART (C) SPI (D) USB (E)
ICD2 communication.
43. Microchip’s datasheet suggests that users adopt (A) CAN bus (B) UART (C) SPI (D) USB (E)
ICD2 for mutual communication of two dsPICs.
44. For communication between dsPIC and PC Windows, it is better to adopt (A) CAN bus (B)
UART (C) SPI (D) USB (E) ICD2 to minimize the need of auxiliary hardware.
45. Which of the following statements about the UART communication is not correct? (A) It is a
serial communication (B) Programmers can write values into Transmit or Receive registers and
read the contents of them (C) Transmit Interrupt flag is raised when the Transmit buffer is empty
(D) Receive Interrupt flag is raised when the Receive buffer is full (E) Programmers are able to
read the contents of Transmit Shift Register (TSR).
46. Once we know how to (A) setup BIOS (B) program Windows APIs (C) apply TCP/IP (D) insert
PCI cards (E) install RTX system, PC can control or transfer data to devices connected thereto
without additional software or hardware.
47. As the oscillator’s frequency is 5M Hz and the internal clock is configured to be XT with
PLL_MULTIPLITY being 16, then about (A) 12.5ns (B) 34ns (C) 50ns (D) 200ns (E) 500ns is
needed to execute an instruction.
48. Following Prob. #47, setting the register PEPER of the PWM module by (A)1000 (B) 1500 (C)
2000 (D) 2500 (E) 3000 will obtain PWM signal output at the frequency of 20k Hz.
49. Following Prob. #47, and the Pre-scale value of Timer1 counter is set to one. Then, to involve
Timer1 in functioning 0.0001sec delay, the register PR1 should be set by (A) 1000 (B) 1500 (C)
2000 (D) 2500 (E) 3000.
50. Follows Prob. #47. As the register SPBRG is set to be 50, the baud rate of serial transmission
with UART will be about (A) 50k (B) 20k (C) 10k (D) 2k (E) 9600.