726
3, MARCH 2005
Complete High-Frequency Thermal Noise Modeling
of Short-Channel MOSFETs and Design of
5.2-GHz Low Noise Amplifier
Kwangseok Han, Member, IEEE, Joonho Gil, Member, IEEE, Seong-Sik Song, Student Member, IEEE,
Jeonghu Han, Student Member, IEEE, Hyungcheol Shin, Senior Member, IEEE, Choong-Ki Kim, Fellow, IEEE, and
Kwyro Lee, Senior Member, IEEE
Abstract—Taking a velocity saturation effect and a carrier
heating effect in the gradual channel region, complete thermal
noise modeling of short-channel MOSFETs including the induced
gate noise and its correlation coefficients is presented and verified
extensively with experimentally measured data. All of the four
noise models have excellently predicted experimental data with
maximal error less than 10% for the deep-submicron MOSFETs.
Using these models and a simultaneous matching technique for
both optimal noise and power, a low noise CMOS amplifier opti-
mized for 5.2-GHz operation has been designed and fabricated.
Experiments using an external tuner show that both 50 and
min are very close to 1.1 dB, which is an excellent figure of
merit among reported LNAs.
Index Terms—Four noise parameters, induced gate noise, low
noise amplifier, noise correlation coefficients, RF CMOS, thermal
noise.
I. INTRODUCTION
C ONTINUOUS advances in CMOS process technology
have reduced the minimum gate length of MOS devices,
improving the microwave performances accordingly [1], [2].
CMOS technology is a viable option for wireless application,
because it provides such advantages as low cost, high-level
integration, and easy access over other technologies. Low noise
design is one of the key issues in most of the RF receiver
circuits. Unfortunately, however, existing MOSFET compact
models used in modern circuit simulators are not suitable
for predicting high-frequency thermal noise behaviors. This
inevitably leads to long development time. Therefore, accurate
Manuscript received May 11, 2004; revised August 13, 2004. This work was
supported by the MICROS Center through the Korea Science and Engineering
Foundation.
K. Han was with the Department of Electrical Engineering and Computer
Science, Korea Advanced Institute of Science and Technology, Daejeon
305-701, Korea, and is now with RF/Analog PT, System LSI Division,
Samsung Electronics Company, Ltd., Gyeonggi 449-711, Korea (e-mail:
kwangseok.han@samsung.com).
J. Gil was with the Department of Electrical Engineering and Computer Sci-
ence, Korea Advanced Institute of Science and Technology, Daejeon 305-701,
Korea, and is now with RadioPulse Inc., Seoul 138-711, Korea.
H. Shin was with the Department of Electrical Engineering and Computer
Science, Korea Advanced Institute of Science and Technology, Daejeon 305-
701, Korea, and is now with the School of Electrical Engineering, Seoul Na-
tional University, Seoul 151-742, Korea.
S.-S. Song, J. Han, C.-K. Kim, and K. Lee are with the Department of Elec-
trical Engineering and Computer Science, Korea Advanced Institute of Science
and Technology, Daejeon 305-701, Korea.
Digital Object Identifier 10.1109/JSSC.2005.843637
0018-9200/$20.00 © 2005 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.
modeling of high-frequency noise is indispensable to develop
low noise amplifiers (LNAs) with short development time.
There has been a lot of controversy on the excess thermal
noise in short-channel MOSFETs. Recently, after extensive and
accurate measurement of intrinsic MOSFET noise, however,
we have found that large enhancement was not observed in the
devices of 0.18- m technology. The excess factor for 0.18- m
n-channel MOSFET does not exceed two at strong inversion
and the excess factor has converged among various groups
[3]–[6]. For the drain thermal noise current, we showed that
the simple well-known formula, previously derived
for long channels, remained valid even for short channels [6].
To describe the high-frequency noise behavior completely,
however, three additional noise parameters of the induced gate
noise and complex correlation coefficients between the gate
and drain noise are necessary, all which originate from the
coupling of channel fluctuation through the oxide capacitance.
The induced gate noise has also been very controversial. For
example, recent experiments in [7] and [8] for a 0.25- m
gate length MOSFET reported a large enhancement factor as
large as 30 for the induced gate noise, which was attributed to
the hot carrier in the velocity saturation region. On the other
hand, much less enhancement was reported in [9], which was
explained by a channel segmentation-based model without
considering the hot carrier effect.
In this paper, we have shown that the enhancement of induced
gate noise in short-channel MOSFETs is also moderate, which
indicates that the contribution of hot carrier is negligible. Ana-
lytical equations for the four noise models will be derived and
presented differently from the segmentation-based model. This
paper presents complete high-frequency thermal noise models
of short-channel MOSFETs, which includes the drain current
noise, the induced gate noise, and their correlation coefficients.
In Section II, after repeating our previously proposed drain cur-
rent thermal noise modeling, the induced gate noise and the cor-
relation coefficient are derived, based on the same assumptions.
In Section III, these models are verified with extensively mea-
sured data. Finally, a 0.18- m 5.2-GHz CMOS LNA is opti-
mally designed using these models and analyzed extensively in
Section IV.
II. HIGH-FREQUENCY NOISE MODEL
The basic frame of high-frequency noise modeling of the
field-effect transistor (FET) was first described by Van der
HAN et al.: COMPLETE HF THERMAL NOISE MODELING OF SHORT-CHANNEL MOSFETs AND DESIGN OF 5.2–GHZ LNA
Ziel in a series of classic papers [10]. Van der Ziel showed
the intrinsic noise effects could be represented by two noise
generators, the drain noise current and the induced gate one.
These noise currents are partially correlated with each other
because they are generated from the same physical origin, i.e.,
thermal fluctuation of carriers in the channel. But Van der Ziel’s
model cannot be applied to short-channel MOSFETs because
the model did not account for the velocity saturation effect.
Velocity saturation within the channel not only modifies the
small-signal parameters, but also the noise currents as well.
Recently, we have presented a drain current thermal noise
model valid for deep-submicron MOSFETs, which takes the ve-
locity saturation. Applying an impedance field method to this
nonlinear channel [6], we obtained
(1)
Here, is the noise current at the drain terminal due to
that is a local noise source located between and , the
direction of is along the channel, is the source-referenced
channel potential at , is the length of gradual channel re-
gion, is the drain-source voltage, and is the critical field
at which the carrier velocity becomes saturated. Integrating (1)
over the channel leads to a following simple drain noise current
formula:
(2)
for all biases and gate lengths [6]. Here, is the Boltzmann’s
constant, is the ambient temperature, is the measurement
bandwidth, is the gate field dependent mobility, and is
the total inversion charge. It is very interesting that the remark-
ably simple formula of (2) derived for short-channel MOSFETs
is the same as that for long-channel devices as shown in [11].
Due to the local noise source ( ), the noise current ( ) example,
flows from source to drain terminal and the established potential
along the channel becomes perturbed. The induced gate noise
can be calculated by integrating the perturbed potential. The
details of the derivation of the perturbed potential, the induced
gate noise, and the correlation can be found in the Appendix. In
the saturation regime, the induced gate noise and its correlation
for short-channel devices can be approximately calculated as
(3a)
(3b)
(4)
(5)
Here, is the gate oxide capacitance per unit area, is the
device width, is the drain conductance at . is
, which indicates how strong the velocity saturation
727
effect is. is the gate overdrive voltage ( – ). Note
that in the case of (or long channel limit) (3)–(5) reduce
to the long channel model, which coincide with those derived
earlier [10], as they should. The -related terms in (3)–(5) indi-
cate how much the noise in the short-channel devices increases
or decreases compared to the long-channel theory.
III. EXPERIMENTAL RESULTS OF HIGH-FREQUENCY
NOISE MODELING
To verify the proposed high-frequency noise model for short-
channel MOSFETs, the devices fabricated with 0.18- m tech-
nology were characterized. All the devices under test (DUTs)
were laid out with multifinger structure. Each finger width and
the number of fingers were fixed to 5 m and 16, respectively.
Noise parameters ( , , and ) and scattering param-
eters were measured by ATN noise and Agilent -parameter
measurement setup in the frequency range from 3 to 10 GHz.
All required various electrical parameters that includes ,
, , and so on, were extracted from – and – mea-
surements [5], [6]. Parasitic components in the MOSFET, which
include a source/drain resistance ( ), a gate electrode resis-
tance ( ), a substrate resistance ( ), and source/drain
junction capacitance ( ), were extracted from measured
-parameters [12]. Especially, after the effect of source/drain
resistance was de-embedded, the input referred total gate resis-
tance ( ), which consists of the distributed electrode resis-
tance ( ) and the distributed channel resistance ( ) seen
from the gate, was extracted by using
(6)
as a function of gate bias when . After that,
was determined as a constant part of versus gate bias. For
of 2.5 was extracted for the device with gate
length of 0.18- m. is a dominant contributor to the ad-
ditional noise current, especially to the gate terminal noise [9].
With extracted parasitic components, noise correlation matrices
were constructed to determine intrinsic noise sources [13].
A. Drain Current Noise and Induced Gate Noise Modeling
The drain thermal noise is often expressed as
(7)
is an enhancement factor and is 2/3 for the long-channel MOS-
FETs when devices are biased at the saturation regime. Fig. 1
shows the measured and modeled as a function of for
the devices with various gate lengths. For the devices with in-
termediate gate lengths (0.35 and 0.5 m), was close to 2/3.
However, in the case of 0.18 m, moderate increase of was
observed, which was explained in [6].
To show the bias dependencies of the induced gate noise, rig-
orous measurements of the noise were carried out. Fig. 2 shows
the measured as a function of gate bias and drain bias
for various gate lengths. The symbol represents the measured
and the line represents the modeled value by using (3). To
728 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

devices with 0.5- m and 0.18- m gate lengths, the moderate in-
crease was observed compared to the long-channel model. The
increase becomes more pronounced as the gate bias increases
as shown in Fig. 2(a). as large as 6 is observed in the case of
the device with 0.18- m gate length at . Since the
effective local channel resistance increases due to the velocity
saturation effect, increases in short-channel devices and
the proposed model given by (3) explains excellently such in-
crease of the measured induced gate noise as shown in Fig. 2.
The dotted line in Fig. 2(a) represents the modeled value for the
device with m by Van der Ziel’s equation, which
tried to account for the velocity saturation effect [10], [14]. Al-
though the same heating condition was used, the model underes-
timated measured noise, which clearly shows that the previous
model is not correct for short-channel devices. The basic dif-
Fig. 1. versus gate voltage at saturation regime.
ference between the proposed model and the previous model is
explained in the Appendix.
At low gate voltages, the measured noises of devices with
gate length of 1.5 m and 0.8 m were much smaller than the
predicted value. We believe that this is due to the small cutoff
frequencies ( ) of the devices, which is much less than 1 GHz
when the gate voltage is small. Therefore, the non-quasi-static
(NQS) effect plays an important role at the noise measurement
frequency of 4 GHz, which makes (3) invalid. The channel resis-
tance seen from gate will be smaller as the NQS effect becomes
large. Correspondingly, the induced gate noise will be smaller
than the value predicted as shown in Fig. 2(a). Additionally, the
measured drain current noise became larger than the predicted
value at the low gate bias regions and for the long-channel de-
vices, because the channel conductance becomes larger due to
the NQS effect [9].
The drain bias dependency of the induced gate noise is shown
in Fig. 2(b). After , induced gate noise for all gate
lengths remains constant, which indicates that the contribution
of hot carriers in the velocity saturation region to the gate noise
is negligible.
Fig. 3 shows the measured and the modeled correlation coef-
ficient as a function of gate bias for the devices with gate lengths
of 0.8 m and 0.5 m. The measured correlation coefficient
was almost imaginary. Although the coefficient remains at the
long-channel limit of at low gate biases, it slightly de-
creases as the gate bias increases. The correlation coefficient of
device with 0.18- m gate length is not plotted here, because it
is hard to measure accurately. It shows large fluctuation due to
the fluctuation of induced gate noise.

B. Four Noise Parameters

Until now, there has only been a noise parameter model for
Fig. 2. Measured i h ias a function of (a) gate biases and (b) drain biases.
h i
i at f = 4 GHz was plotted for the devices with L > 0:18 m intrinsic device [15]. However, as the parasitic components
h i
and i at f = 6 GHz was plotted for the device with L = 0:18 m. such as the gate electrode and source resistance become crucial
h i
i moderately increased at high gate voltage and remained almost constant for the device performance in the short-channel devices, it is
beyond V  V .
important to have a noise parameter model for the extrinsic
devices. For example, in the device with m,
show how much is enhanced in the short-channel devices and generate additionally about 60% gate ter-
compared to the long channel theory, the long channel noise minal noise current compared to . For the extrinsic
model [10] was also added in Fig. 2(a) with the dashed lines. device represented with a simple small-signal equivalent circuit
The measured noise agrees well with the value predicted with (Fig. 4), when high-order frequency terms are neglected, the
the long channel model for high gate voltages. However, for the noise parameters are calculated as given in (8)–(11) shown at
HAN et al.: COMPLETE HF THERMAL NOISE MODELING OF SHORT-CHANNEL MOSFETs AND DESIGN OF 5.2–GHZ LNA 729

the dotted line represents the modeled when only

is taken into account. In the case of devices with 0.5 m gate
length, there is a large difference between the measured and
the modeled using only . However, the difference
becomes small in the device of 0.18- m gate length. This is
due to the contribution of parasitic and to the
noise current at the gate terminal in (9). The role of and
on the is shown in Fig. 5(c). and should be
necessarily considered to model correctly as shown in
Fig. 5(c). But, as the gate length scales, the difference between
the measured and the modeled with only becomes
small as shown in (10) and Fig. 5(c). Fig. 5(d) shows clearly
the scalability of with gate length, which presents the
attractive noise performance of scaled-down CMOS devices
at high frequency. Finally, it is worth noticing that
Fig. 3. Correlation coefficient slightly decreases at the high gate biases. becomes less sensitive to as the gate length scales down.

IV. NOISE MODEL VERIFICATION IN CMOS LNA

A. Design of 5.2-GHz LNA
To show the feasible noise characteristics of RF CMOS,
we have designed an LNA at 5.2 GHz. To describe the
high-frequency small-signal characteristics of the MOSFET
accurately, the gate–source, the gate–drain, the source–bulk,
and the drain–bulk capacitances were added to BSIM3v3 core
as shown in Fig. 6(a). Additionally, the gate resistance, the
source/drain resistances, and the substrate resistance were
Fig. 4. Equivalent small-signal circuit for the extrinsic device. added [1], [12]. The drain thermal noise current, which is orig-
inally included in the BSIM model, was intentionally removed.
the bottom of the page, where is the equivalent resistance, Then, the new noise current source given by (2) was connected
( ) is the optimum noise conductance, between the drain and the source terminals. Also, the induced
is the minimum noise figure, is the angular frequency, gate noise, which was not modeled in the BSIM3v3 at all,
, and . Since was incorporated into Agilent ADS simulator [16] as shown
is mostly dominated by the term in (8), most of the in Fig. 6(a). Note that the gate resistance consists of and
LNA circuits were designed only considering . However, as explained in the Section III. Since the induced gate
and should be included for accurate modeling of noise noise covers the noise generated due to , was set
parameters at high frequency. Especially, and should to be noiseless and instead the induced gate noise source was
be considered for accurate determination of and , connected between the intrinsic gate and source terminal. The
respectively. Fig. 5(a) shows the measured and the modeled correlation, , was also implemented into the ADS circuit
as a function of gate bias for various gate lengths. As the gate simulator. All used passive elements including inductors and
length scales down, becomes small at low gate voltage, MIM capacitors were modeled using the small-signal equiva-
which indicates that the noise figure is less sensitive to the mis- lent circuits in [17] and [18], respectively. In addition, to reduce
match between a source admittance and . But at high gate the substrate loss and to prevent the coupling of thermal noise
biases, of devices with gate length of 0.18 m is larger than generated from substrate resistance, the substrate was shielded
that of devices with longer gate length. This is due to the fact by using the grounded metal in the MIM and the patterned
that the transconductance ( ) starts to saturate. In Fig. 5(b), ground poly in the inductor.

(8)

(9)

(10)
(11)
730 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 5. Noise parameters including (a) R , (b) G , (c) B , and (d) NF are excellently modeled as a function of gate biases (solid line). The dotted line
represents the modeled value by using only hi i. Although hi i is the most dominant factor, hi i and C should be considered to obtain accurate noise
parameters.

Fig. 6(b) shows the complete schematic of the CMOS cas-

code LNA with inductive source degeneration. When designing
LNAs with a common-source single-gate FET ( nH), it
is well known that simultaneous matching for both optimal noise
and optimal input power is very difficult. For such simultaneous
matching purpose, an inductive source degeneration inductor
( ) is widely used [15], [19]–[22]. All circuit components ex-
cept an input matching inductor ( ) were integrated in a test
chip. The input impedance of the LNA shown in Fig. 6(b) is cal-
culated as

(12)

Here, , and is the operating frequency.

There are two different approaches to obtain a minimum noise
factor. The first is to change the geometry of the device. When
is matched to and is not used, the
noise factor is approximately given by [20]

(13)

There are terms in (13) proportional and inversely proportional Fig. 6. (a) Macro-model of MOSFET for high-frequency small-signal and
to device width ( ). Therefore, there exists an optimum width noise. (b) Complete LNA schematic employing inductive source degeneration.
HAN et al.: COMPLETE HF THERMAL NOISE MODELING OF SHORT-CHANNEL MOSFETs AND DESIGN OF 5.2–GHZ LNA 731

( ) where becomes minimal. When the device width is

larger than , the contribution of the drain thermal noise of
is dominant and the induced gate noise becomes dominant
in the case of [20] as shown in (13). By choosing
the device with , the minimum noise factor can be ob-
tained. For the device with , is very close to
. However, this approach results in large . For
example, was 730 m in 0.18- m CMOS technology [19],
which may consume large current. Therefore, this approach is
not useful in the case of low power application. The other ap-
proach is to transform of with the fixed device
width to 50 by introducing an additional capacitance as
shown in Fig. 6. Note that the noiseless and are con-
nected with in parallel and in series, respectively. Therefore,
of is transformed to

(14) Fig. 7. Die photo of the LNA.

The asterisk ( ) means conjugate. Using and ,

and of the LNA can be si-
multaneously matched to 50 . Although (14) is helpful to
understand the role of and in the noise matching, (14)
is only valid when the second stage including is noiseless.
Unfortunately, an analytical transformation expression of
is very complicated when generates additional noise. So,
final values of of 0.5 nH and of 50 fF were determined
through the circuit simulator to match both and
to 50 .
Fig. 8. Measured and modeled S -parameters before the input matching from
B. Experimental Results of LNA 4.9 to 6.0 GHz. The gate bias V is 0.8 V and the supply voltage V is
1.8 V.
Fig. 7 shows a die photo of fabricated LNA. The die size
except probing pads is 0.35 0.64 . With external gate
bias via dc-probing pad, small-signal performance of the LNA Fig. 9(c). Excellent noise figure close to 1.1 dB was obtained
on-wafer was characterized with a two-port -parameter mea- at 5.2 GHz. The measured noise performances of the LNA are
surement setup and noise parameters were characterized by very close to the values simulated by using our noise model.
using an external tuner. Input port matching was accomplished However, conventional BSIM3v3 predicts the underestimated
using ADS. Output impedance was matched to 50 through value as shown in Fig. 9(b) and (c), which indicates the model
on-chip , , and . Fig. 8 shows the measured and the is not accurate for predicting high-frequency thermal noise
modeled -parameters from 4.9 to 6.0 GHz after de-embedding behaviors.
probing pads at and . Output Fig. 10 shows effects of induced gate noise and correlation on
impedance was well matched to 50 at the center frequency. LNA design. Various LNAs were designed with different gate
On-chip output matching was sufficient to realize a return lengths. The solid line represents the optimized NF when
loss of 13 dB at 5.2 GHz. Due to the proper and , is only considered and the dashed line means the optimized NF
lies in the 50- circle, and thus the input impedance can be when and were additionally considered. For each opti-
easily matched to by adding an inductor of 5.2 nH in mization procedure, and was determined to match
series to the input port. After the input matching, the measured and to 50 . The optimization method to take only
and modeled and are illustrated in Fig. 9(a). At the always leads to larger NF than the optimization to consider fully
operating frequency of 5.2 GHz, both and are very noise sources, which is caused by the fact that and
close to , which indicates that simultaneous optimal make different and so the optimized values of and
matching for noise and power is achieved. Fig. 9(b) and (c) were different. Therefore, NF difference between the solid line
show the matched and the noise figure versus frequency. and the dashed line in Fig. 10 addresses how much the matching
When the input port is matched, the noise resistance is greatly is important in the LNA design with different gate lengths. For
reduced and minimal at the design frequency, which indicates LNA that consists only of , there is about 1 dB NF difference
that a little mismatch between and is not critical to at gate length of 0.5 m whether and are considered or
achieve the low noise performance. The fact is also verified not. However, the difference becomes small as the gate length
by a small difference between and as shown in scales down. This is due to the following two reasons: First, the
732 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 9. After the input matching with L = 5:2 nH, (a) S and S are very close to R = 50
(b) and the equivalent noise resistance is greatly reduced.
NF of excellent 1.1 dB is very close to N F (c). Dashed line represents simulated value using BSIM3v3.

parasitic gate electrode and source resistance play a so signifi-

cant role to determine as shown in (9) that is less sen-
sitive to and as the gate length scales down. Second,
becomes very small when LNAs are matched as shown in
Fig. 9(b), which indicates that a little mismatch between
and is not critical. Generally, matching components and
are different whether and are considered or not.
For example, in the case of gate length of 0.18 m, and
was 0.15 nH and 25 fF, respectively when was only con-
sidered. But when and are fully considered, and
was 0.25 nH and 55 fF, respectively. Although the values
of matching components become different, the small makes
NF insensitive to the mismatch. LNAs with and have
showed the larger NF and were much less sensitive to the mis-
match than LNAs with only as shown in Fig. 10 because the Fig. 10. Simulated N F of LNAs designed with different gate lengths. The
second stage adds the noise at high frequency. effects of hi i and C on the matching become less critical as the gate length
Fig. 11 shows the noise figure as a function of the gate bias of scales down.
the input transistor ( ). The proposed noise model predicts the
bias dependency of the noise characteristics accurately. Analyt- , 0.3 dB NF increased although the power gain was almost
ical results in [22] have shown that the substrate parasitics of the the same. Consequently, for different bias and design, the pro-
integrated capacitor ( ) degrade the noise performance signif- posed noise model accurately predicts the noise performance of
icantly. Thus, to show the effect of lossy silicon substrate and the LNA.
to show the validity of the noise model in the different design, Table I summarizes the measured performance of the LNA.
we have fabricated the LNA using with/without the metal Linearity parameters of P1dB ( GHz) and IIP3 (
ground-shield. As shown in Fig. 11, in the case of unshielded and GHz) were measured without the input matching
HAN et al.: COMPLETE HF THERMAL NOISE MODELING OF SHORT-CHANNEL MOSFETs AND DESIGN OF 5.2–GHZ LNA 733

carefully shielded to prevent noise coupling. Based on the pro-

posed model, excellent noise figure close to 1.1 dB at 5.2 GHz
was obtained.

APPENDIX
We start from the following – expression considering ve-
locity saturation effect:

(15)

where ,
is the electronic charge, is the areal carrier number density,
Fig. 11. NF comparison as a function of the gate bias. When the unshielded and is the coefficient accounting for the bulk charge effect.
C capacitor was used, 0.3 dB NF increased.
The local thermal noise current source is generally given by
the diffusion noise source [10]
TABLE I
MEASURED PERFORMANCE OF 5.2-GHZ LNA (16)

where is the diffusion coefficient. And we assume the dif-

fusion coefficient is constant along the channel, which implies
a carrier heating condition in the gradual channel region [6],
[23]–[25]

(17)

where is the diffusion constant at low field.

circuit. A 7.5 dB gain enhancement is achieved by adopting the
input matching circuit. Therefore, the P1dB and IIP3 are ex-
pected to be 19.9 dBm and 11.5 dBm , respectively, for the
matched input.
Let us first write and
, where and are the established average potential
and the current caused by DC biases, respectively, and
and are the fluctuating potential and the noise current to
flow through the channel due to the local noise source ( ),
respectively. Since is independent of the position for fre-
quencies lower than cutoff frequency, after inserting the dis-
turbed potential and the current to (15), expanding in
and neglecting the second-order term in , we obtain

V. CONCLUSION (18)

In this work, a complete physics-based analytical model for

Here, .
the drain thermal noise, the induced gate noise, and their corre-
Note that (18) is a very important starting equation to for-
lation, which takes into account a velocity saturation effect and
mulate gate-related noises. However, in the previous works
a carrier heating effect, was proposed and verified by measured
[10], [14], was formulated differently with (1) and
noise data for short-channel MOSFETs. Experimental results
term in the right side of (18) was omitted, which
have shown that the contribution of hot carriers in the velocity
results from inappropriate linearization steps from (15) to (18).
saturation region to both the drain and gate terminal noises is
Therefore, the previous models predict less induced gate noise
negligible and the velocity saturation effect has more influence
than the measured one.
on the induced gate noise rather than the drain thermal noise.
Bearing in mind , can be
With the complete four noise models, measured noise parame-
found by integrating (18). Then, is found by
ters were excellently modeled for all gate lengths and biases.
A cascode 5.2-GHz LNA was designed and analyzed using
the proposed model. The method of simultaneous optimal noise (19)
and power matching was discussed and the effects of ,
, and on the optimum noise matching were shown. As After some algebra
the gate length scales down, the roles of and became
less critical for optimal noise matching. It has been shown that
the parasitic components such as the MIM capacitor should be (20)
734
where
This gives the contribution of the noisy element located between
and to the gate terminal current noise. Integrating
it over the entire gradual channel region leads finally to
(21)
Using (1) and (20), the correlation between and
current can be derived as
(22)
Equations (21) and (22) are too complicated to be useful for
circuit design. If we approximate
and evaluate them as a function of biases, (21) and (22) can
analytically be given by (3) and (4), respectively, in the satu-
ration regime. Here, is . The validity of the used
approximation was checked by
comparing (3) [or (4)], which was calculated by numerical inte-
gration, and (21) [or (22)]. The difference was less than 5% for
all gate biases and gate lengths. The correlation coefficient was
calculated by using (2)–(4) and then fitted as a function of .
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Kwangseok Han (S’99–M’05) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering and
computer science from the Korea Advanced Institute
of Science and Technology (KAIST), Daejeon,
Korea, in 1998, 2000, and 2004, respectively.
Since 2004, he has been with Samsung Elec-
tronics, Kyunggi, Korea, as a RF circuit designer. His
research activities include nonvolatile nano-crystal
memory, RF CMOS modeling, high-frequency
thermal noise modeling, and RF circuits design.
Dr. Han received a Best Student Award for the Out-
standing Paper in the Silicon Technology at the 1999 IEEE International Con-
ference on VLSI and CAD and an Outstanding Paper Prize from the Applied
Materials, Inc., Korea Branch, Paper Contest in 2001. He also received a Korea
Foundation for Advanced Studies scholarship.
HAN et al.: COMPLETE HF THERMAL NOISE MODELING OF SHORT-CHANNEL MOSFETs AND DESIGN OF 5.2–GHZ LNA
Joonho Gil (S’98–M’04) received the B.S. and M.S.
degrees in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1997 and 1999, re-
spectively, and the Ph.D. degree in electrical and
computer science from KAIST in 2003.
He is currently with RadioPulse Inc, where he has
developed CMOS RF-ICs for wireless applications.
His research interests include CMOS RF/microwave
integrated circuits for wireless communication and
on-chip passive device modeling.
Dr. Gil received a Splendor Prize in the Samsung Humantech Paper Contest
in 1999.
Seong-Sik Song (S’02) was born in Seoul, Korea,
in 1979. He received the B.S. and M.S. degrees in
electrical engineering and computer science from the
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2001 and 2003, respec-
tively. He is currently working toward the Ph.D. de-
gree in electrical engineering and computer science
at KAIST.
His research interests include CMOS RF circuits
and device modeling for wireless communication
systems.
Jeonghu Han (S’04) received the B.S. and M.S.
degrees in electrical engineering and computer
science at the Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, Korea, in 2000
and 2002, respectively. He is currently working
toward the Ph.D. degree at KAIST.
His research activities include CMOS/LDMOS de-
vice modeling and power amplifier design for wire-
less communication systems.
Hyungcheol Shin (S’92–M’93–SM’00) received
the B.S. (magna cum laude) and M.S. degrees in
electronics engineering from the Seoul National
University, Seoul, Korea, and the Ph.D. degree
in electrical engineering from the University of
California, Berkeley.
From 1992 to 1994 he was with Applied Materials,
Santa Clara, CA, as an intern and a Process Engineer,
working on plasma charging damage on gate oxide.
From 1994 to 1996, he was with Motorola, Mesa, AZ,
as a Senior Device Engineer, developing SOI device
technology for low power applications. From 1996 to 2003, he was an Assistant
and Associate Professor at the Korea Advanced Institute of Science and Tech-
nology (KAIST) in the Department of Electrical Engineering and Computer
Science. During his sabbatical leave from 2001 to 2002, he was with Berkana
Wireless, Inc., Irvine, CA, as a Staff Scientist in charge of CMOS RF modeling.
In 2003, he joined Seoul National University as an Associate Professor in the
School of Electrical Engineering. His current research interests include device
design and fabrication of nano-scale CMOS devices and RF modeling of both
active and passive devices. He has authored or coauthored three books and over
200 research papers.
Dr. Shin has served as a committee member on several international confer-
ences, including IEEE P2ID (1999–2001), IEEE Silicon Nanoelectronics Work-
shop (1999, 2001, and 2003), and IEEE IEDM (2003). He received the KAIST
Excellent Teaching Award in 1998 and has received three best paper awards. He
is listed in the Who’s Who in the World.
735
Choong-Ki Kim (S’69–M’70–SM’91–F’95) received
the B.S. degree from Seoul National University,
Seoul, Korea, in 1965 and the M.S. and Ph.D. degrees
in electrical engineering from Columbia University,
New York, NY, in 1967 and 1970, respectively.
From 1970 to 1975, he was with the Research and
Development Laboratory, Fairchild Camera and In-
strument, Inc., Palo Alto, CA, where he worked on
the development of linear/area CCD image sensors.
In 1975, he left Fairchild to join the faculty of the
Department of Electrical Engineering of Korea Ad-
vanced Institute of Science and Technology, Seoul, Korea, where he is presently
a Professor. His current research interest includes SOI, rapid thermal processing,
and HgCdTe photodiode.
Prof. Kim was the Chairman of the IEEE Korea Section in 1992. He was a
recipient of the third Hoam Prize in the field of science and technology in 1993.
He is a Life Member of KIEE, KITE, KPS, and SPIE.
Kwyro Lee (S’79–M’80–SM’90) received the B.S.
degree in electronics engineering from Seoul Na-
tional University, Seoul, Korea, in 1976 and the M.S.
and Ph.D. degrees from the University of Minnesota,
Minneapolis, in 1981 and 1983, respectively, where
he did many pioneering works for characterization
and modeling of AlGaAs/GaAs heterojunction field
effect transistors.
After graduation, he worked as an Engineering
General Manager with GoldStar Semiconductor
Inc., Korea, from 1983 to 1986, responsible for
development of first polysilicon CMOS products in Korea. He joined KAIST
in 1987 as an Assistant Professor in the Department of Electrical Engineering,
where he is now a Professor. He has more than 150 publications in major
international journals and conferences. He is the principal author of the book
Semiconductor Device Modeling for VLSI (Prentice-Hall, 1993) and one of the
co-developers of AIM-SPICE, the world’s first SPICE run under Windows.
Dr. Lee is a Life Member of IEEK. During 1990–1996, he served as the Con-
ference Co-Chair of Int. Semiconductor Device Research Symposium, Char-
lottesville, VA. During 1998–2000, he served as the KAIST Dean of Research
Affairs as well as the Dean of Institute Development and Cooperation. During
the same periods, he also served as the Chairman of IEEE Korea Electron Device
Chapter and is currently serving as the elected member of EDS AdCom. Since
1997, he has been working as the Director of MICROS (Micro Information and
Communication Remote Object-oriented Systems) Research Center, an Engi-
neering Center of Excellence supported by the Korea Science and Engineering
Foundation.