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Technique for Flicker Noise Up-Conversion Suppression in Differential LC

Oscillators

Article  in  Circuits and Systems II: Express Briefs, IEEE Transactions on · December 2007
DOI: 10.1109/TCSII.2007.904135 · Source: IEEE Xplore

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 959

Technique for Flicker Noise Up-Conversion

Suppression in Differential LC Oscillators
Nikolay N. Tchamov and Nikolay T. Tchamov

Abstract—A novel technique for the suppression of the flicker

noise up-conversion in a differential LC oscillator topology is
proposed. Relaxation mechanism and tunable noise filtering of
the relaxation thresholds provide simultaneous suppression of
differential pair and bias transistor flicker noise contributions.
The proposed technique is validated on a fully monolithic os-
cillator architecture and 0.35- m standard CMOS process by
Cadence SpectreRF for the frequency range of 2.9–5.9 GHz. The
phase noise improvement at 10 kHz offset versus a single-differen-
tial-pair LC oscillator is 6–15 dB across the tuning range.
Index Terms—Flicker noise, integrated oscillator, RF CMOS.

I. INTRODUCTION

N EAR-CARRIER phase noise in CMOS LC oscillators is

dominated by up-converted flicker (
porary submicron CMOS processes often have high
) noise. Contem-
-noise
Fig. 1. (a) Differential LC oscillator with noise sources. (b) Oscillator in [12].

corner frequencies. Consequently integrated oscillator phase

noise is deteriorated even in the presence of a phase locked
loop [1].
This brief proposes a novel technique for the suppression of
-noise up-conversion in the widely used single-differential-
pair LC oscillator shown in Fig. 1(a). Suppression of up-conver-
sion from simultaneously both differential pair and bias transis-
tors is achieved through the introduction of a relaxation mecha-
nism and filtering of the relaxation thresholds.
Section II reviews the mechanisms of flicker noise up-con-
version and relevant prior works. Section III introduces the pro-
posed technique and Section IV validates it through SpectreRF
simulations in a 0.35- m CMOS process.
II. MECHANISMS OF UP-CONVERSION AND PRIOR WORKS
The power spectral density of flicker noise in a CMOS tran-
sistor is given in [2] as
(1)
where is the flicker noise coefficient, and are the device
dimensions, is the device transconductance, and is gate
capacitance per unit area. For given and , a decrease of
intrinsic flicker noise requires the use of large-size devices and
Manuscript received July 24, 2006; revised June 8, 2007. This work was sup-
ported by Tampere University of Technology, Tampere, Finland. This paper was
recommended by Associate Editor P. P. Sotiriadis.
The authors are with the Institute of Communications Engineering, RF-ASIC
Design Laboratory, Tampere University of Technology, Tampere 33720, Finland
(e-mail: nikolay@cs.tut.fi).
Digital Object Identifier 10.1109/TCSII.2007.904135
1549-7747/$25.00 © 2007 IEEE
low . Undesirably, large devices increase the static capaci-
tance at the differential pair drain nodes in Fig. 1(a) and limit
the achievable frequency tuning range. Moreover, the lowered
decreases the oscillator loop gain.
Thus, suppressing up-conversion mechanisms rather than de-
creasing the intrinsic flicker noise would give potential design
benefits.
A. Mechanisms of Up-Conversion
The mechanisms of flicker noise up-conversion in the differ-
ential LC oscillator, shown in Fig. 1(a), have been identified in
[3]–[7] and for clarity are summarized below.
Flicker noise from bias transistor up-converts through:
1) AM-PM process in both varactor and differential pair de-
vice capacitances [3]–[5];
2) modulation of the harmonic content of the differential cur-
rent , i.e., Groszkowski effect [6], [7].
Flicker noise from differential pair - up-converts
through:
1) modulation of the duty-cycle and harmonic content of the
differential current [7];
2) induction of a noisy current in the tail capacitance
and consequent modulation of the effective capacitance
across the resonator [6].
Depending on the oscillator implementation, either the differ-
ential pair or bias transistor’s flicker noise contributions might
dominate the near-carrier phase noise.
B. Prior Works
Reference [3] proposes a comprehensive approach for de-
creasing both intrinsic flicker noise and up-conversion through
960 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007

Fig. 3. Proposed circuit half-period model with M on (solid lines) and M off
(shown in dashed lines). (a) Effect of differential pair flicker noise. (b) Effect of
bias transistor flicker noise.
V V
Fig. 2. (a) Proposed circuit with flicker noise sources. (b) Effects of noise on the
threshold levels and . (c) Differential current with noise-modulated
duty cycle.
jointly implements the flicker noise filtering function of the
relaxation thresholds.
optimization of device sizing. It does not require additional cir- Due to there is no common-mode capacitance at the
cuit components, but imposes certain restricting design trade- source nodes. Inductors also increase the impedance at the
offs, as discussed in Section I. In [5], novel varactor topologies fundamental and harmonic frequencies [14].
minimizing the amount of AM-PM conversion are presented. In Tanks - set the oscillation frequency. and are
[8], suppression of the up-conversion is achieved through sym- implemented with switched MIM capacitances. Varactors are
metry of the output waveform. The technique, however, is ap- omitted in order to remove the varactor AM-PM process, which
plicable to differential LC oscillators with complementary tran- has already been successfully treated in [5]. Thus, we concen-
sistors, but not to the LC oscillator in Fig. 1(a). In [1] and [7], trate on the removal of the remaining mechanisms of up-conver-
the intrinsic flicker noise of the bias (tail) transistor is decreased sion, summarized in Section I, by removing flicker noise con-
through periodic switching. tamination from the relaxation thresholds.
The time-reference capacitor in the emitter(source)-coupled
multivibrators [9]–[11] has been utilized in [12], Fig. 1(b), to B. Effects of Flicker Noise on the Relaxation Thresholds
suppress flicker noise up-conversion from the differential pair Flicker noise from the differential pair and bias transistor ex-
. Due to decoupling, there is no common tail capaci- ists on the relaxation thresholds of the voltage as shown in
tance, only two stray source capacitances . The bias tran- Fig. 2(b). As the thresholds and are crossed, com-
sistor is replaced by in order to eliminate one source mutation of the differential pair and differential current in the
of flicker noise. Phase noise in the region (with slope of circuit is triggered.
20 dB ) is improved by inductors providing high se- Thus, flicker noise contamination on the thresholds leads to
ries resistance on top of in accordance to [13]. a noisy duty cycle of the differential current ,
shunts thermal noise around . It is important to note that shown in Fig. 2(c). From [6] and [7], this is known to facilitate
[12] does not utilize a relation between the numerical values of two separate mechanisms for -noise up-conversion.
inductors and the decoupling capacitance . We will next show that for successful noise filtering of the
The works referred above in general decrease up-conversion relaxation thresholds a relation exists between the component
or intrinsic flicker noise from either the differential pair or bias values of inductors and decoupling capacitance .
transistor. The main goal of the present work is to suppress the
up-conversion from both the differential pair and bias transistor C. Technique for Filtering of Noisy Relaxation Thresholds
simultaneously. Flicker noise from the differential pair and bias transistor is
modeled as noise voltage sources in Fig. 2(a). Analysis of the
III. PROPOSED TECHNIQUE FOR SUPPRESSION OF FLICKER circuit in one half of the oscillation period is next performed in
NOISE UP-CONVERSION Fig. 3 with transistors: on, off, and vice versa in the other
half-period. In Fig. 3(a) we observe the effect of differential pair
A. Proposed Topology flicker noise, and in Fig. 3(b) the bias transistor’s respectively.
The proposed circuit for achieving suppression of flicker To provide noiseless switching on of for the next half-
noise up-conversion is shown in Fig. 2(a). It is based on [10] period, its gate–source voltage should be free of flicker
and modifies the differential LC oscillator to introduce a relax- noise. Its gate terminal is connected to the LC tank, tuned
ation mechanism and additional flicker noise filtering of the at the oscillation frequency , and thus, is free of flicker noise.
relaxation thresholds. Decoupling capacitance implements However its source terminal is susceptible to flicker noise
the relaxation mechanism and together with inductors contamination.
TCHAMOV AND TCHAMOV: TECHNIQUE FOR FLICKER NOISE UP-CONVERSION SUPPRESSION IN DIFFERENTIAL LC OSCILLATORS 961

In the two cases of Fig. 3(a) and (b), the flicker noise cur-
rent component should be diverted away from the abc-branch
in order not to contaminate the source node of . At the same
time the fundamental frequency current component should see
a low-impedance path in the abc-branch to facilitate the current
steering through the relaxation capacitor .
Diverting flicker noise current components from the differen-
tial pair, in Fig. 3(a), and bias transistor, in Fig. 3(b), away from
the abc-branch and into the ac-branch requires:

for
(2) Fig. 4. Small-signal analysis of the proposed circuit. (a) Model of the modified
differential pair. (b) Open loop model with resistive losses.
Supplying low impedance path for the fundamental frequency
current through the abc-branch necessitates
To minimize oscillation frequency dependence on the -
– network, the second term of (5) should be minimal in mag-
(3) nitude. When the optimal filtering of (4) is used, (5) becomes

at the oscillation frequency . (6)

From (3), the optimal value of at becomes
where preferably . Thus, from (6), large
(4) values for (or equivalently small values for from (4))
ensure that the oscillation frequency is mainly dependent on
With (4) satisfied, the duty cycle of the differential current and the values of and , as commonly used in the differential
its harmonic content are unaffected by flicker noise and thus the LC oscillator in Fig. 1(a).
mechanisms of flicker noise up-conversion from Section I are
suppressed. E. Effect on Open Loop Gain
Naturally, this is an approximation model of the exact pro- The expression for the open loop gain of the oscillator, in
cesses of differential pair switching. In the next section, using Fig. 4(b), taking into account losses, can be derived as:
this mechanism described above and the design formula in (4),
we will quantitatively evaluate through Cadence SpectreRF in
0.35- m CMOS process the effect of the proposed technique at (7)
RF frequencies.
The proposed mechanism is an improvement to the approach where
for the suppression of flicker noise up-conversion adopted in
[12], through the introduction of optimal noise filtering of the
relaxation thresholds. The circuit in [12] uses alone to de-
crease the -noise corner frequency of up-conversion only are the impedances at each drain and source node, respectively.
from the differential pair - in Fig. 1(b). In [12], addi- Since the – – network can be tuned in frequency,
tional filtering of the relaxation thresholds with and is it is vital that it does not reduce the loop gain of the circuit
not applied. If the circuit in [12] is to be designed in the fashion for the desired oscillation frequency. Using the optimal filtering
proposed by (4), inductance would become 8.3 nH with the condition in (4) for does not reduce the loop gain of the
implemented values of pF and GHz. The proposed circuit below unity, since the region of non-operation
implemented value for in [12] is 23 nH as shown in Fig. 1(b). can be derived to be at .
-

D. Effect on Oscillation Frequency

IV. CIRCUIT DESIGN AND SIMULATION RESULTS
The small-signal model in Fig. 4(a) shows that the modified
The proposed suppression technique is next validated
differential pair presents impedance in parallel to
through SpectreRF simulations on the 0.35- m CMOS mono-
the LC resonator:
lithic process of Austria Micro Systems, using Cadence 5.1.41
and AMS HitKit v.3.60.
(5) SpectreRF extracts the individual transistors’ flicker and
thermal noise contributions from the output phase noise and
while, in contrast, the differential pair of the differential thus can be used to verify the proposed technique.
LC oscillator in Fig. 1(a) presents only a pure negative resistance To provide a fair estimate of the performance enhancement
of . obtained by the use of (4), a comparison will be drawn with the
962 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007

Fig. 5. Circuits. (a) Proposed circuit. (b) LC oscillator with identical MOS de-
vices, tank, and bias.
Fig. 6. SpectreRF flicker noise contributions at f = 4:1 GHz and 10 kHz
offset versus C . Optimal flicker noise filtering is achieved for C = 0:98 pF
as predicted by (4).
LC oscillator, as shown in Fig. 1(a), having identical –
resonator tanks, differential pair, bias transistors, and bias
conditions.

A. Circuit Design
The two simulated circuits are shown in Fig. 5 and op-
erate from GHz to GHz over a
discrete-step
frequency tuning range. Each circuit consumes 5.2 mA from a
2-V supply, operating in the “current–limited” regime [13].
Since the proposed technique suppresses the mechanisms of
flicker noise up-conversion, sizing of transistor devices is re- Fig. 7. Simulation results. (a) Differential drain (output) and source (relax-
laxed and minimum feature sizes of 0.35 m can be used as gate ation) voltage waveforms. (b) Phase noise comparison of proposed circuit and
LC oscillator with L -C resonator tanks, differential pair, bias transistors, and
length for all transistors: - ( - ) are 25 m/0.35 m bias conditions.
and ( ) – 40 m/0.35 m devices.
According to the oscillation frequency set by and
and the design formula in (4), it is beneficial to choose passive
In Fig. 6, we plot the flicker noise contributions to the output
component values such that , to consequently have
spectrum at GHz from the bias transistor and differen-
over the frequency tuning range. Thus, the relax-
tial pair as a function of decoupling capacitance . The zeros
ation and noise filtering network – – can be realized
for up-converted differential pair and bias transistor flicker noise
with components identical to the ones in the resonator – .
coincide at 0.98 pF as predicted by (4), thus verifying the pro-
Capacitors and are implemented with switched banks of
posed technique.
MIM capacitors. The tunable implements the noise filtering
In Fig. 6, the flicker noise contribution from the bias transistor
function in (4) throughout the frequency tuning range. Induc-
is one order of magnitude smaller than the differential pair
tors and are design library components of 1.5 nH with a
- contribution. Importantly, if is not chosen in ac-
quality factor of 8–11 over the tuning range.
cordance to (4), significant rise of up-conversion is observed in
Fig. 6, thus indicating the importance of noise filtering of the
B. Simulation Results
relaxation thresholds.
The Periodic Steady-State and Phase Noise simulations in The simulated differential output voltage and decoupling ca-
SpectreRF are performed next. Due to the high degree of re- pacitor voltage are shown in Fig. 7(a). Phase noise plot is
liability of Cadence SpectreRF simulations, precision in phase shown in Fig. 7(b). The slope is at 20 dB dec signifying sup-
noise simulation is expected with error of less that few deci- pression of flicker noise up-conversion, while the basic LC os-
bels. Since the proposed approach will be next shown to de- cillator has a near-carrier 30 dB dec slope.
crease phase noise by as much as 6–15 dB at 10-kHz offset, the Secondly, we apply the proposed noise filtering, specified by
simulation results on Cadence can be considered as a very reli- (4), throughout the tuning range of the circuit by tuning the value
able test of the analysis approach described here. of . In Fig. 8 we compare the output phase noise at 10 kHz
Firstly, the proposed technique is verified at a single oscilla- offset of the LC oscillator and the proposed circuit throughout
tion frequency around the center of the tuning range. the tuning range of the circuits. The proposed circuit, designed
TCHAMOV AND TCHAMOV: TECHNIQUE FOR FLICKER NOISE UP-CONVERSION SUPPRESSION IN DIFFERENTIAL LC OSCILLATORS 963

The use of advanced varactor topologies [5] results in an

increase of up-converted bias transistor flicker noise contribu-
tions. In this case also, the design formula in (4) yields the
minimum of up-conversion. Smooth frequency tuning can also
be achieved through high-speed dithering of capacitance
values [15].
V. CONCLUSION
Through the joint use of relaxation mechanism and noise fil-
tering of the relaxation thresholds, the proposed approach di-
rectly addresses the mechanisms for up-conversion and permits
relaxed optimization of device bias and sizing.
Precise Cadence SpectreRF simulations on a 0.35- m fully
monolithic CMOS implementation show phase noise improve-
ment of 6–15 dB at 10-kHz offset across the 2.9–5.9-GHz tuning
range versus a single-differential-pair LC oscillator. The ap-
proach does not cause negative effect on the -region phase
noise.
Fig. 8. Phase noise comparison at 10 kHz-offset of the LC oscillator and pro-
posed circuit designed with optimal filtering. Tilted labels specify the optimal
decoupling used as calculated by (4). REFERENCES
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