Proceedings of the 50th European Microwave Conference

A High Sensitivity RF Energy Harvester for Diverse

Environments
Ibrahim Kagan Aksoyak#*1 , Adamantia Chletsou*2 , John Papapolymerou*3 , Ahmet Cagri Ulusoy#*4
# Institute of Radio Frequency Engineering and Electronics (IHE), Karlsruhe Institute of Technology, Karlsruhe, Germany
* Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI, USA
{1 ibrahim.aksoyak, 4 cagri.ulusoy}@kit.edu, {2 chletsou, 3 jpapapol}@egr.msu.edu

Abstract — This paper presents a design methodology for high

sensitivity RF energy harvesters operating at 915 MHz. The
energy harvester topology is composed of a receiver antenna,
M1 M2 M3 M4
a CMOS rectifier, an on-chip storage capacitor, a load and a M1 M2 M3 M4 M5 M6
power management unit. The antenna rectifier interface plays C C C C
C C C C C C
a crucial role in the energy harvester design, as it provides
a passive voltage boosting, impacting the sensitivity and the AC+ AC+
robustness against environmental variations. This paper discusses AC- AC-

the possible scenarios of mismatch between the antenna and the
rectifier, since the antenna impedance can change significantly due
to the environment. The design parameters are carefully analyzed,
and simulations are verified by measurements taken from energy
harvester chips fabricated in a 65-nm CMOS process.
Keywords — RF energy harvesters, CMOS rectifier, 915
MHz, sensitivity, power management unit, RF-powering, wireless
powering.
I. I NTRODUCTION
The advances in Internet of Things (IoT) lead to more
and more devices being connected to the cloud or to each
other in distributed networks. Expansion in the application
areas of IoT also raises the question of sustainability of
massive sensor usage and their power management in terms
of economic and environmental aspects. RF-powered devices
that make use of propagating wave energy instead of internal
power sources attract great attention for the development of
wireless sensor networks (WSN), since they do not need
any battery replacement or maintenance over the long run,
eliminating the environmental and economic concerns. The
primary function of RF energy harvesters is to convert the
received RF energy into DC voltage and store it across
a capacitor for further use. This also makes RF energy
harvesters especially attractive for wireless body area network
(WBAN) and implant communications. Most commonly, the
industrial, scientific and medical (ISM) band at 902-928 MHz
is employed for RF energy harvesting, although there are a
number of studies in literature that exploit different frequency
bands such as 2.45 GHz or 5.8 GHz [1].
The maximum distance at which a radio-frequency
identification (RF-ID) tag can operate is strongly dependent
on its sensitivity, i.e., the smallest RF input power necessary
for a desired output DC voltage. Multi-stage rectifiers are
incorporated in modern RF energy harvesters, mostly based
on the conventional Dickson multi-stage rectifier topology [2],
and its variations.
(a) (b)
Fig. 1. Self-compensation method: (a) single order; (b) higher order
For instance, a generalized self-compensation method is
employed in [3], where a bias offset is introduced to the gates
of each transistor through the drain voltage of the following
stages, see Fig. 1a. Here, the achievable bias offset voltage
equals approximately Vout /N , where N is the number of
stages. Depending on the threshold voltage of the process, and
the required output voltage, the order of compensation may
be increased by applying the drain to gate feedback across a
higher number of rectifying elements, as shown in Fig. 1b.
In this work, as illustrated in Fig. 2, the presented RF
energy harvester is composed of a receiver antenna, a full
wave rectifier, a power management unit (PMU), and a
load transistor acting as a current sink for demonstration.
Co-design of antenna, rectifier and power management unit
allows further optimization of each block to achieve an overall
better sensitivity. A particular goal of this work is to enhance
the robustness of the proposed design against environmental
variations, since future sensor technologies will need to operate
in various environments, including biological tissues.
II. D ESIGN M ETHODOLOGY
A. Antenna-Rectifier Interface
The interface model between the antenna and the rectifier
is shown in Fig. 3. The antenna is represented by an AC
voltage source, a resistor and an inductor, Rant and +jXant ,
and similarly, the rectifier is modelled by a capacitor and a
Wireless
Energy
Source Antenna VDC
Rectifier Rectifier PMU Load
Interface
Cstore
Fig. 2. Block diagram of a RF energy harvester

978-2-87487-059-0 © 2020 EuMA 444 12–14 January 2021, Utrecht, The Netherlands
Authorized licensed use limited to: Universiti Kebangsaan Malaysia. Downloaded on December 14,2021 at 10:01:30 UTC from IEEE Xplore. Restrictions apply.

resistor, Rrec and -jXrec . The relationship between the antenna
voltage source, Vant , and the voltage delivered to the rectifier,
Vrec , is given in the following equation:
Vrec Rrec + jXrec
= (1)
Vant (Rant + Rrec ) + j(Xant − Xrec )
The rectifier input voltage, Vrec , plays a crucial role in
the sensitivity of the rectifier, thus, needs to be maximized
for a given Vant . Equation (1) shows that a passive voltage
boosting can be achieved based on the relation between the
reactive and resistive components, further it can be shown that
the voltage boosting can be maximized under the resonant
condition (Xrec = Xant ). In order to relate the choice of
the component values to the available received power at the
antenna, we use the Thevenin equivalent voltage source, Vant ,
for the received available power, Pav , as following:
p In this work, multi-stage differential drive cross-connected
Vant = 8Rant Pav (2)
The magnitude of Pav can now be obtained in terms of
rectifier and antenna impedances along with the Vant using the
above equations.
2 2
(Rant + Rrec ) + (Xrec − Xant ) Vrec 2
|Pav | = (3)
Rrec 2 + Xrec 2 8Rant
Equation (3) relates Pav to Vrec for given impedances of
the antenna and the rectifier. Based on this equation, for a
given Pav , a higher Xrec , together with the resonance condition
maximizes Vrec . Therefore, the aim is to choose Xrec as high
as possible while designing an antenna with Xant = Xrec .
Further analysis has been conducted to observe the
degradation in sensitivity in case of mismatch between the
antenna and the rectifier. For this purpose, the real and the
imaginary part of the antenna impedance have been swept to
observe the degradation in sensitivity, assuming a desired Vrec
of 0.24 V, for an output voltage of 1.2 V, based on preliminary
rectifier designs.
An interesting part of this study is the impact of the quality
factor (Q = Xrec /Rrec ) on the sensitivity. To determine this,
Xrec is kept constant at -j496 Ω and Rrec has been varied to
acquire three different Q-factors.
In Fig. 4, the simulation results are provided for
mismatches in the imaginary and real parts of the
antenna-rectifier interface for various Q-factors. As can be
seen, although a high Q-factor impedance favors the peak
sensitivity when a perfect match exists, the sensitivity value
diminishes rapidly as the amount of mismatch increases. This
indicates that the Q-factor of the rectifier input impedance
can have an impact on the robustness against environmental
variations. Another interesting observation is that the mismatch
in the real part is not as crucial, as the voltage boosting is
mainly achieved by the reactive components.
Antenna Model Rectifier Model Storage / Load
+ +
Rant +jXant
-jXrec
Vant Vrec Cstore
Rrec
- -
Fig. 3. The antenna-rectifier interface
Authorized licensed use limited to: Universiti Kebangsaan Malaysia. Downloaded on December 14,2021 at 10:01:30 UTC from IEEE Xplore. Restrictions apply.
0
Sensitivity (dBm)
-10
-20
Q=16
-30
Q=40
Q=100
-40
0 0.5 1 1.5 2
Xant /Xrec
-10
Q=16
Sensitivity (dBm)
-15 Q=40
-20
Q=100
-25
-30
0 0.5 1 1.5 2
Rant /R rec
Fig. 4. Impedance mismatch vs. sensitivity for varying Q
B. Rectifier
rectifier topology, similar to the one presented in [4] is
employed. A single stage of the differential drive rectifier is
shown in Fig. 5a. Multi-stage rectifiers enable an additional
design freedom, namely the number of stages as this allows the
adjustment of the input impedance together with the choice of
the transistor dimensions. The rectifier input impedance scales
almost linearly with the increasing number of stages since it
is a parallel combination of the impedance of each stage.
Apart from the impedance considerations, ideally, a high
number of stages would favor the sensitivity, since the required
Vrec for a desired output voltage could be reduced significantly.
In reality, however, this comes at the expense of an increased
reverse leakage current that reduces the harvester efficiency. A
detailed analysis on reverse leakage can be found in [5].
Transistor sizing is another design parameter to control the
rectifier input impedance. Using larger transistors increases the
transconductance, while reducing Rrec and |Xrec |. There are
some studies in literature that report the optimum transistor
sizing for rectifier designs [6], [7]. In this work, the length
of each transistor is set to minimum allowed value of
L=60 nm and the total width of each transistor is W=6 µm
for NMOS and W=18 µm for PMOS transistors. These values
are chosen to optimize the antenna-rectifier interface in
terms of impedance without a significant compromise on the
transconductance capability of devices. Deep n-well layer in
the adopted process is exploited to provide isolated bodies, and
to allow the body to source connection for each device.
Coupling and storage (load) capacitances play a role
in determining the charging/discharging dynamics. Larger
storage capacitances have a capability to store more energy
at the expense of an increased charge time. A 20 pF on-chip
MIMCAP storage capacitance is employed for demonstration
purposes and the coupling capacitance value per stage is
chosen to be 170 fF, which is the smallest value without any
effect on the rectifier operation.
This work employs a 16-stage rectifier with the Q-factor
Vout
of 40, for an easier impedance matching between the custom
Rload
designed antenna and the rectifier to improve the tolerance
to environmental changes while sacrificing a maximized peak
sensitivity at a single medium.
445
 POWER MANAGEMENT UNIT BIAS CIRCUIT
LOAD
VDD FOR LOAD
AC+
Ccoupling M4 V N1
CTRL N2 N3 N4 N7 N8 M20
M1 M2
X M22
M3 M5 M19
M8 M11
VOUT VDIV VREF VCTRL
VDIV VREF VG
M18
Cstore Rload
M2 N5 N6
M7 M10 VG VCTRL
Y VCOMP_OUT M17
M3 M4 M21
M13 M15
M1 M14
Ccoupling M6 M9 M12 M16
VSS
AC- VOLTAGE DIVIDER VOLTAGE REFERENCE COMPARATOR

(a) (b)
Fig. 5. Circuit schematics of (a) single stage differential drive rectifier; (b) power management unit with load

C. Power Management Unit 1.4 80

VCOMP_OUT PMU Current

Current (nA)
Instead of directly connecting the rectifier output to the 1.2 VCTRL 60
VDD
load for a power delivery, this design employs an additional VG 40
1
unit to govern the entire power management scheme. This
20

Voltage (V)
power management unit prevents power delivery to the load 0.8 220 240 260 280 300
Time ( s)
until a desired upper threshold voltage Vth,high is reached. After 0.6 3
this threshold, the load starts to draw current, and the load Total Load Current

Current ( A)
0.4 2
capacitor starts discharging until a low threshold value Vth,low
is reached. Once the output level is at Vth,low , the power 0.2 1

management unit stops the load from drawing current and 0

0 220 240 260 280 300
prevents a complete discharge of the load (storage) capacitor. 220 240 260 280 300
Time ( s)
Time ( s)
The load capacitor starts charging again. This operation
continues in a similar manner and effectively improves the Fig. 6. Voltage and current waveforms in PMU
harvester sensitivity. transistors turn off causing VDIV to fall even lower. Meanwhile,
A complete schematic of the power management unit since VCTRL is high, M21 transistor turns on and pulls VG to
including the load can be seen in Fig. 5b. The power zero which effectively prevents the load transistor, M22 , from
management unit consists of a voltage divider, a voltage drawing current. VDD starts raising again.
reference circuit and a comparator. The power management
unit is designed to consume ultra-low power (65 nW while III. E XPERIMENTAL R ESULTS
on, 20 nW while off) in order not to degrade the sensitivity of The rectifier chip is connected to a very compact, custom
the energy harvester. In this study, a CMOS transistor based designed antenna through wire-bonding, as shown in Fig. 7a.
reference voltage circuit [8] is used, as the resistor based The antenna is implemented on 1.28 mm thick Rogers R3010
reference circuits require large resistors to keep the power substrate and its dimensions are 1.9 cm × 1.9 cm. The energy
consumption low. harvester is tested both in the air and in a mixture that mimics
Referring to Fig. 5b, VDD being VOUT of the 16-stage the human muscle with a permittivity of r = 54.99-j18.65
rectifier, suppose that the load capacitance of the rectifier is and a conductivity of σ = 0.95 S/m around 915 MHz. Since
charging and VDD is raising, as can be observed in Fig. 6. the losses in the mix are greater than the losses in the air,
The increase in VDD also gives a rise to VDIV . At the instant the goal was to match antenna’s impedance in the mixture
that VDIV exceeds VREF , the comparator output, VCOMP OUT , environment with the chip’s impedance. The antenna design
becomes high, as can be seen in Fig. 6, at the time instant of and the properties of the mixture are discussed in [9]. The
around 230 µs. Having a high comparator output sets VCTRL to rectifier chip micrograph and layout can be seen in Fig. 7b.
low value, at the time instant of around 230 µs again in Fig. 6,
allowing N1 transistor to turn on. Since N1 and M5 transistors IC Antenna
also draw current now, the voltage division ratio changes
and VDIV increases further to keep the load drawing current.
Meanwhile, since VCTRL is low, M21 transistor is turned off
which means that VG is high enough to let M22 transistor 1.9 cm
draw current. In this setup, M22 transistor is acting as a load
and sinks current for demonstration purposes. Eventually, the
load capacitor is discharged until Vth,low , around 270 µs in
Fig. 6. At this point, VDIV will fall below VREF due to the 1.9 cm
voltage division, leading the comparator output, VCOMP OUT , to (a) (b)
become low, hence, resulting in high VCTRL . Then, N1 and M5 Fig. 7. Photographs of: (a) Energy harvester board; (b) IC chip and layout

446
Authorized licensed use limited to: Universiti Kebangsaan Malaysia. Downloaded on December 14,2021 at 10:01:30 UTC from IEEE Xplore. Restrictions apply.
 1.2
Table 1. Measured impedances in air and in the mixture Vth,high Charging
1

Vout (V)
Z (Ω)
0.8
Air Mixture
0.6 Vth,low Discharging Mixture: 57 cm & Air: 90 cm
Rectifier 12.5 - j496 12.5 - j496
5.1 5.12 5.14 5.16 5.18 5.2 5.22 5.24 5.26 5.28
Antenna 0.3 + j304 19.75 + j477.5 Time (s)
1.4
Vth,high Charging
1.2
Before the antenna and the rectifier are wire-bonded,

Vout (V)
1
the input impedance of the rectifier is measured through a
0.8
performance network analyzer (PNA). These values, together
0.6 Vth,low Discharging Mixture: 25 cm & Air: 70 cm
with the antenna impedance are provided in Table 1.
0.835 0.84 0.845 0.85 0.855 0.86 0.865 0.87 0.875 0.88
After the wire-bonding, the output of the energy harvester Time (s)

is connected to an oscilloscope to observe the output
waveform. Zebra FX9500 fixed RF-ID reader is used as an
input source. The reader does not produce continuous signals
and toggles between interrogation and listening cycles with a
duty cycle close to 50%. For the wireless experiments, a Zebra
AN440 fixed RF-ID reader antenna with a gain of 6 dBi is
used, while the total loss due to the cables and connectors is
2.5 dB. The oscilloscope at the output of the energy harvester
has an input impedance of 1 MΩ k 30 pF that effectively loads
the energy harvester, and replaces ZLOAD in Fig. 5b resulting
in a charge-discharge time in the range of milliseconds (ms).
This setup is illustrated in Fig. 8.
The custom designed tag in this study and the
commercially available RF-ID tags with integrated antennas
are compared. The commercial tags, such as ALN 9713, ALN
9720, ALN 9770 from Alien Technologies, are optimized only
for the single medium of air. Therefore, they are not able
to perform well when the medium is severly changed. On
the other hand, the custom designed tag in this design can
operate in different environments with significantly different
characteristics such as the air and the mixture that mimics the
behavior of human muscle.
As shown in Fig. 9, for an output voltage of 1 V, the
operation distance is 57 cm in the mixture and 90 cm in the
air. The operation distance reduces to 25 cm in the mixture and
70 cm in the air for an output voltage of 1.2 V. The voltage
waveforms show a continuous rise and fall centering around
0.85 V and 1 V respectively, illustrating the charging and
discharging behavior of the storage capacitor. This dynamic
behaviour is controlled by the power management unit.
Oscilloscope
Zebra AN440 RFID
Reader Antenna
EH Tag
Air Air
Oscilloscope
Zebra FX9500 Mix
RFID Reader
d EH Tag
Mix
Fig. 8. Measurement setup in the air and in the mix
Fig. 9. Output voltage waveform of the proposed tag
IV. C ONCLUSION
A differential drive RF energy harvester with a power
management unit operating at 915 MHz is presented. The
chip is implemented in TSMC 65-nm CMOS technology
and wire-bonded to a custom designed antenna. The
benefits of antenna-rectifier co-design are explained. A power
management unit that governs the harvester power scheme
is introduced. Unlike conventional energy harvesters, the
proposed harvester is tolerant to environmental changes, thus,
capable of operating in the air and in the mixture that mimics
the human body. To the authors’ knowledge, the proposed tag
in this study is the only one that can operate in such strongly
varying environments.
R EFERENCES
[1] S. Radiom, M. Baghaei-Nejad, G. Vandenbosch, L. Zheng, and G. Gielen,
“Far-field RF powering system for RFID and implantable devices
with monolithically integrated on-chip antenna,” in 2010 IEEE Radio
Frequency Integrated Circuits Symposium, May 2010, pp. 113–116.
[2] J. F. Dickson, “On-chip high-voltage generation in MNOS integrated
circuits using an improved voltage multiplier technique,” IEEE Journal
of Solid-State Circuits, vol. 11, no. 3, pp. 374–378, June 1976.
[3] G. Papotto, F. Carrara, and G. Palmisano, “A 90-nm CMOS
Threshold-Compensated RF Energy Harvester,” IEEE Journal of
Solid-State Circuits, vol. 46, no. 9, pp. 1985–1997, Sep. 2011.
[4] K. Kotani, A. Sasaki, and T. Ito, “High-Efficiency Differential-Drive
CMOS Rectifier for UHF RFIDs,” IEEE Journal of Solid-State Circuits,
vol. 44, no. 11, pp. 3011–3018, Nov 2009.
[5] M. Stoopman, S. Keyrouz, H. J. Visser, K. Philips, and W. A. Serdijn,
“Co-design of a cmos rectifier and small loop antenna for highly sensitive
rf energy harvesters,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3,
pp. 622–634, March 2014.
[6] J. Yi, W. Ki, and C. Tsui, “Analysis and Design Strategy of UHF
Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications,”
IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54,
no. 1, pp. 153–166, Jan 2007.
[7] T. Le, K. Mayaram, and T. Fiez, “Efficient Far-Field Radio Frequency
Energy Harvesting for Passively Powered Sensor Networks,” IEEE
Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1287–1302, May 2008.
[8] G. De Vita, G. Iannaccone, and P. Andreani, “A 300 nW, 12 ppm//spl
deg/C Voltage Reference in a Digital 0.35 /spl mu/m CMOS Process,”
in 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.,
June 2006, pp. 81–82.
[9] A. Chletsou, J. Papapolymerou, A. C. Ulusoy, and I. Kagan Aksoyak, “Uhf
rectenna for implanted and free space communications,” in 2019 IEEE
International Symposium on Antennas and Propagation and USNC-URSI
Radio Science Meeting, July 2019, pp. 641–642.

447
Authorized licensed use limited to: Universiti Kebangsaan Malaysia. Downloaded on December 14,2021 at 10:01:30 UTC from IEEE Xplore. Restrictions apply.