Eetop - CN T018LODR001 2 8

SECURITY B
tsmc Taiwan Semiconductor Manufacturing Co., LTD

TSMC-RESTRICTED SECRET
Ver Eff_Date ECN No. Author Change Description

2.6 05-16-06 E070200616013 R. G. Wu 1.Add NP.R.3 and PP.R.3
2.Refine RPO.C.4, RPO.C.5, OD.W.3 and NT_N.I.3
3.Remove Old Doc. No. “TA-10A5-4001”
2.7 05-06-08 E070200817023 Y. M.Chenj See Appendix A
________________ TSMC Confidential Information 665121 VIA TECHNOLOGIES INC. 12/01/2009 ________________
2.8 07-16-09 E070200927032
TS S. L. Liu See Appendix A
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Reviser : S. L. Liu (PDS) Title

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Revising Line Manager : Y. C. Harn TSMC 0.18UM CMOS

LOGIC/MS/RF AND 0.16UM CMOS
Approvals: LOGIC/MS DESIGN RULE
(CL018G/LV/LP, CM018G, CR018G,
Please refer EDW workflow to see detail
approval records CL016G, CM016G)
Document No. : T-018-LO-DR-001
Contents : 328
Attach. :0
Total : 328
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in 1 of 328
whole or in part without prior written permission of TSMC.
SECURITY B

2.2 05-30-01 E011615 S. C. Kuo 1. Add redundancy guideline for embedded SRAM
and modify user guide
2. Add description of planar capacitor Emb-SRAM in
user guide
3. Delete metal fuse rule and alignment mark rule for
there’s a separate document
4. Modify NP.E.6/PP.E.6
5. Modify Seal-ring rule
6. Modify figure of NP/PP
7. Add layout grid 0.005um at 1X
2.3 11-02-01 F012402 S. J. Peng 1. Add planar capacitor Emb-SRAM rules

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2. Delete DSER guide Pait I item 17 (P.5), Planar

capacitor Emb-SRAM guidelines
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2.4 07-04-03 70325001 Alex Fanh 1. Revise NW resistor rule NWR.O.1. NW resistor
under STI add “NP to OD extension” rule.
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2. Merge section of “Redundancy Guideline for

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on 6 NO /2
Embedded SRAM” and “Dummy Layout for

Embedded SRAM” to “SRAM Guideline”.
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3. Keep no Polyimide(PM) over seal ring and

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assembly isolation . Seal ring rule add some

wordings.
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4. Add the section of “Guidelines for NC (No-Connect)

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pin during ESD testing”

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2.5 04-23-04 E070200416009 T. M. Fu 1. Revise wide metal and metal slot rules.
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2. Revise NTN.W.1.
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3. Move NTN section to the front.

4. Refine ESD guidelines and wording.
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Title
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TSMC 0.18UM CMOS

LOGIC/MS DESIGN RULE
CL016G, CM016G)
SECURITY B

0.1 05-13-98 T981419 C. C. Tsai Original
0.2 09-15-98 F983509 C. C. Tsai Increase manufacturability and make design rule
description more clear
1.0 10-09-98 F983951 C. C. Tsai Make design rule more compatible with Si data
1.1 11-05-98 F984419 C. C. Tsai Modify P5 to make process margin safer
1.2 03-23-99 F991129 C. C. Tsai 1.Make rule more clear and safer
(change items refer to P.5)
2.Change Document Number from "TA-10A5-4001" to
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"T-018-LO-DR-001"
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2.0 05-18-00 F001803 J. H. Hsu 1.Guideline for migration to CL018LV and poly
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resistor, P3V, RPO.C.6, antenna ratio for top metal,

native device rule, metal fuse rule
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2.Recommendation of NW resitor under STI,

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N2V/N3V/NP/PP.C.4, NP/PP.S.2, passivatioin rules

3.Ph layer, OD.W.3, CO.S.2, CO.C.2, A.R.3, A.R.6,
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ESD guideline
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2.1 09-29-00 F003714 C. P. Yeh 1.Use guide update

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2.Delete N2V/N3V/P2V/P3V
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3.Merge via rule/metal rule

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4.ESD guideline update

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Title
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TSMC 0.18UM CMOS

LOGIC/MS DESIGN RULE
CL016G, CM016G)
tsmc Confidential – Do Not Copy
Document No.
Version
: T-018-LO-DR-001
: 2.8
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TSMC 0.18UM CMOS LOGIC/MS/RF AND 0.16UM CMOS

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LOGIC/MS DESIGN RULE (CL018G/LV/LP, CM018G,

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CR018G, CL016G, CM016G)

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Document No.
Version
: T-018-LO-DR-001
: 2.8
Table of Contents
1. INTRODUCTION............................................................................................................................................ 10
1.1 OVERVIEW ................................................................................................................................................. 10
1.2 INTEGRATED DESIGN RULE MANUALS ......................................................................................................... 11
1.3 REFERENCE DOCUMENTATION.................................................................................................................... 12
1.4 GUIDELINES FOR CL016G/CM016G TECHNOLOGIES ................................................................................. 15
1.5 NOTE FOR HIGH RELIABILITY APPLICATIONS ............................................................................................... 15
2. TECHNOLOGY OVERVIEW ......................................................................................................................... 16
2.1 SEMICONDUCTOR PROCESS ....................................................................................................................... 16
2.1.1 Front-End Features............................................................................................................................ 16
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2.1.2 Back-End Features ............................................................................................................................ 17

2.1.3 MS/RF devices Features ................................................................................................................... 18
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2.2 POWER SUPPLY OF DEVICES ...................................................................................................................... 19

2.3 CROSS-SECTION ........................................................................................................................................ 20
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2.4 METALLIZATION OPTIONS ........................................................................................................................... 21

2.4.1 Logic Metallization Options................................................................................................................ 21
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2.4.2 Mixed Signal & RF Metallization Options .......................................................................................... 22

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2.5 USER GUIDE .............................................................................................................................................. 24

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2.5.1 Logic Design Recommendations ....................................................................................................... 24

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2.5.2 Mixed Signal Design Recommendations........................................................................................... 26

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3. GENERAL LAYOUT INFORMATION ........................................................................................................... 27

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3.1 MASK INFORMATION, KEY PROCESS SEQUENCE, AND CAD LAYERS INFORMATION ..................................... 27
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3.2 MASK REQUIREMENTS FOR DEVICE OPTIONS.............................................................................................. 38

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3.3 SPECIAL RECOGNITION CAD LAYER SUMMARY ........................................................................................... 39

3.4 DEVICE TRUTH TABLES .............................................................................................................................. 41
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3.4.1 CL018G 1.8V/3.3V............................................................................................................................. 42

3.4.2 CL018G 1.8V/5V................................................................................................................................ 43
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3.4.3 CL018LV 1.5V/2.5V ........................................................................................................................... 44

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3.4.4 CL018LV 1.5V/3.3V ........................................................................................................................... 45

3.4.5 CL018LP 1.8V/3.3V ........................................................................................................................... 46
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3.4.6 CL018LP 1.8V/5V .............................................................................................................................. 47

3.4.7 CM018G/CR018G 1.8/3.3V ............................................................................................................... 48
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3.4.8 CL016G 1.8V/3.3V............................................................................................................................. 50

3.4.9 CM016G 1.8V/3.3V............................................................................................................................ 50
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3.5 DEVICE LIST & SPEC .................................................................................................................................. 51

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3.5.1 CL018G 1.8V/3.3V............................................................................................................................. 51

3.5.2 CL018G 1.8V/5V................................................................................................................................ 52
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3.5.3 CL018LV 1.5V/2.5V ........................................................................................................................... 53

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3.5.4 CL018LV 1.5V/3.3V ........................................................................................................................... 54

3.5.5 CL018LP 1.8V/3.3V ........................................................................................................................... 55
3.5.6 CL018LP 1.8V/5V .............................................................................................................................. 56
3.5.7 CMG018/CR018G 1.8/3.3V ............................................................................................................... 57
3.5.8 CL016G 1.8V/3.3V............................................................................................................................. 58
3.5.9 CM016G 1.8V/3.3V............................................................................................................................ 58
4. LAYOUT RULES AND RECOMMENDATIONS............................................................................................ 59
4.1 LAYOUT RULE CONVENTION ....................................................................................................................... 59
4.2 SPECIAL GEOMETRIES USED IN PHYSICAL DESIGN RULES........................................................................... 60
4.2.1 Derived Geometries ........................................................................................................................... 60
4.2.2 Special Definition ............................................................................................................................... 60
4.3 DEFINITION OF LAYOUT GEOMETRICAL TERMINOLOGY ................................................................................ 61
4.4 MINIMUM PITCHES ...................................................................................................................................... 63
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5 LOGIC LAYOUT RULES AND GUIDELINES...................................................................................................... 64

4.5.1 N-Well (NW) Layout Rules (Mask ID: 192) ........................................................................................ 64
4.5.2 NW Resistor Layout Rules................................................................................................................. 65
4.5.3 Native Device (NT_N) Layout Rules.................................................................................................. 68
4.5.4 Thin Oxide (OD) Layout Rules (Mask ID: 120).................................................................................. 70
4.5.5 Thick Oxide (OD2) Layout Rules (Mask ID: 132) .............................................................................. 73
4.5.6 Poly (PO) Layout Rules (Mask ID: 130)............................................................................................. 76
4.5.7 Poly Resistor and OD Resistor Guidelines and Rule ........................................................................ 79
4.5.8 N+ S/D (NP) Layout Rules (Mask ID: 198) ....................................................................................... 82
4.5.9 P+ S/D (PP) Layout Rules (Mask ID: 197) ........................................................................................ 84
4.5.10 Resist Protection Oxide (RPO) Layout Rules (Mask ID: 155) ......................................................... 86
4.5.11 Contact (CO) Layout Rules (Mask ID: 156)..................................................................................... 88
4.5.12 Metal-1 (M1) Layout Rules (Mask ID: 160)...................................................................................... 90
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4.5.13 VIA1 to VIA4 (VIAx) Layout Rules (Mask ID: 178, 179, 173, 174) .................................................. 92
4.5.13.1 C018 VIA Array Layout Rules....................................................................................................... 93
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4.5.13.2 C016 VIA Array Layout Rules....................................................................................................... 97

4.5.14 Metal-2 to Metal-5 (Mx) Layout Rules (Mask ID: 180, 181, 184, 185) .......................................... 101
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4.5.15 Top VIA (VIAn) Layout Rule (Mask ID: 175).................................................................................. 103
4.5.16 Top Metal (Mn) Layout Rule (Mask ID: 186) ................................................................................. 104
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4.5.17 Product Labels and Logo Layout Rules......................................................................................... 105

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4.5.18 Passivation (CB), Polyimide (PM) & AP-MD Layout Rule (Mask ID: 107, 009 & 309)................. 107
4.5.19 Metal Fuse Rule............................................................................................................................. 107
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4.5.20 Seal-Ring Rule............................................................................................................................... 107

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4.5.21 Antenna Effect Prevention (A) Layout Rules ................................................................................. 109

4.5.22 Stress Release Rules .................................................................................................................... 111
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4.5.23 SRAM Guideline ............................................................................................................................ 121

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4.5.24 Planar Capacitor EMB-SRAM Rules ............................................................................................. 122

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4.6 MIXED SIGNAL & RF LAYOUT RULES AND GUIDELINES .............................................................................. 123
4.6.1 Deep N-Well (DNW) Layout Rules (Mask ID: 119).......................................................................... 123
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4.6.2 Medium Vt NMOS (VTM_N) Layout Rules (Mask ID: 118) ............................................................. 125
4.6.3 Medium Vt PMOS (VTM_P) Layout Rules (Mask ID: 117).............................................................. 126
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4.6.4 HRI Poly Resistor Rule .................................................................................................................... 127

4.6.5 Schottky Barrier Diode (SBD) Layout Rules.................................................................................... 130
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4.6.6 MIM Capacitor Layout Rules ........................................................................................................... 135

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4.6.7 Antenna Effect Prevention Layout Rules for MIM Capacitor ........................................................... 141
4.6.8 Ultra Thick Metal (UTM) Layout Rules (Mask ID: 186).................................................................... 147
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5. LAYOUT GUIDELINES FOR LATCH-UP AND I/O ESD ............................................................................ 150

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5.1 I/O ESD PROTECTION CIRCUIT DESIGN AND LAYOUT GUIDELINE .............................................................. 150
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5.1.1 General Guideline for ESD Protection ............................................................................................. 151

5.1.2 Additional Two ESD Structures ....................................................................................................... 154
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5.1.3 ESD Implantation Rule (Mask ID: 110, only for 5V NMOS device) ................................................. 162
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5.2 LAYOUT RULE AND GUIDELINES FOR LATCH-UP PREVENTION .................................................................... 164
5.2.1 Special Definition in Latch-up Prevention........................................................................................ 164
5.2.2 Latch-up Dummy Layers Summary ................................................................................................. 165
5.2.3 DRC methodology for Latch-up rules .............................................................................................. 166
5.2.4 Layout Rules and Guidelines for Latch-up Prevention .................................................................... 169
6. LAYOUT RULES, RECOMMENDATIONS, AND GUIDELINES FOR ANALOG CIRCUITS..................... 173
6.1 USER GUIDES...................................................................................................................................... 173
6.2 LAYOUT RULES, RECOMMENDATIONS, AND GUIDELINES FOR THE ANALOGY DESIGNS .......................... 173
6.2.1 General Guidelines..................................................................................................................... 173
6.2.2 MOS Recommendations ............................................................................................................ 174
6.2.3 Resistor & Bipolar Transistor (BJT) Recommendations ............................................................ 174
6.2.4 Guidelines for Capacitor Connections –Estimation of Minimum Metal Width and Minimum Via
Number 175
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3 LAYOUT RULES AND GUIDELINES FOR DEVICE PLACEMENT .................................................................. 176
6.3.1 General Rules and Guidelines ................................................................................................... 176
6.3.2 Matching Rules and Guidelines ................................................................................................. 177
6.3.3 Electrical Performance Rules and Guidelines............................................................................ 180
6.3.4 Noise .......................................................................................................................................... 182
6.3.5 Burn-in guidelines for analog circuits ......................................................................................... 185
6.4 GDA DIE SIZE OPTIMIZATION KIT......................................................................................................... 185
6.4.1 Recommended GDA criteria MFU >65% ................................................................................... 185
7. CURRENT DENSITY (EM) SPECIFICATIONS........................................................................................... 186
7.1 METAL/CO/VIA CURRENT DENSITY ........................................................................................................... 186
7.2 POLY CURRENT DENSITY ......................................................................................................................... 188
8. 0.16UM TECHNOLOGY (CL016G/ CM016G)............................................................................................. 189
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8.1 SPECIFICATIONS FOR CL016G AND CM016G TECHNOLOGY .................................................................... 189

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8.1.1 General Design Specifications......................................................................................................... 189

8.2 NON-SHRINKABLE RULES AND RECOMMENDATIONS .................................................................................. 190
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8.2.1 Non-shrinkable Layout Rules........................................................................................................... 190

8.2.2 ESD Guidelines................................................................................................................................ 192
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8.2.3 Current Density (EM) Specifications................................................................................................ 192

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8.2.4 Antenna Effect Prevention Layout Rules ......................................................................................... 192

8.2.5 Layout Guidelines for Latch-up Prevention ..................................................................................... 192
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8.3 DESIGN FLOW FOR TAPE-OUT ................................................................................................................... 193

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8.3.1 Overview .......................................................................................................................................... 193

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8.3.2 C016 Technology files ..................................................................................................................... 193

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8.3.3 Analog IP design.............................................................................................................................. 196

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8.3.4 Legacy IP porting ............................................................................................................................. 197

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8.3.5 Chip integration................................................................................................................................ 198

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9. ELECTRICAL PARAMETER....................................................................................................................... 201

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9.1 AVAILABLE MOS TRANSISTORS ................................................................................................................ 201

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9.1.1 CL018G 1.8/3.3V ............................................................................................................................. 201

9.1.2 CL018G 1.8/5V ................................................................................................................................ 202
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9.1.3 CL018LV 1.5/3.3V............................................................................................................................ 202

9.1.4 CL018LV 1.5/2.5V............................................................................................................................ 202
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9.1.5 CL018LP 1.8/3.3V............................................................................................................................ 202

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9.1.6 CL018LP 1.8/5V............................................................................................................................... 202

9.1.7 CM018G 1.8/3.3V ............................................................................................................................ 203
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9.1.8 CL016G 1.8/3.3V ............................................................................................................................. 203

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9.1.9 CM016G 1.8/3.3V ............................................................................................................................ 203

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9.2 KEY PARAMETERS OF MOS TRANSISTORS IN CL018G 1.8/3.3V............................................................... 204

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9.2.1 1.8V Standard Vt MOS .................................................................................................................... 204

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9.2.2 3.3V MOS ........................................................................................................................................ 205

9.2.3 1.8V Native MOS ............................................................................................................................. 206
9.2.4 3.3V Native MOS ............................................................................................................................. 207
9.3 KEY PARAMETERS OF MOS TRANSISTORS IN CL018G 1.8/5V.................................................................. 208
9.3.1 1.8V Standard Vt MOS .................................................................................................................... 208
9.3.2 5V MOS ........................................................................................................................................... 209
9.4 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LV 1.5/3.3V ............................................................. 210
9.4.1 1.5V Standard Vt MOS .................................................................................................................... 210
9.4.2 3.3V MOS ........................................................................................................................................ 211
9.4.3 1.5V Native MOS ............................................................................................................................. 212
9.4.4 3.3V Native MOS ............................................................................................................................. 213
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.5 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LV 1.5/2.5V ............................................................. 214

9.5.1 1.5V Standard Vt MOS .................................................................................................................... 214
9.5.2 2.5V MOS ........................................................................................................................................ 215
9.5.3 1.5V Native MOS ............................................................................................................................. 216
9.6 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LP 1.8/3.3V ............................................................. 217
9.6.1 1.8V Standard Vt MOS .................................................................................................................... 217
9.6.2 3.3V MOS ........................................................................................................................................ 218
9.7 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LP 1.8/5V ................................................................ 219
9.7.1 1.8V Standard Vt MOS .................................................................................................................... 219
9.7.2 5V MOS ........................................................................................................................................... 220
9.8 KEY PARAMETERS OF MOS TRANSISTORS IN CM018G 1.8/3.3V.............................................................. 221
9.8.1 1.8V Standard Vt MOS .................................................................................................................... 221
9.8.2 3.3V MOS ........................................................................................................................................ 222
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9.8.3 1.8V Native MOS ............................................................................................................................. 223

9.8.4 3.3V Native MOS ............................................................................................................................. 224
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9.8.5 1.8V Medium Vt MOS ...................................................................................................................... 225

9.8.6 3.3V Medium Vt MOS ...................................................................................................................... 226
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9.9 KEY PARAMETERS OF MOS TRANSISTORS IN CL016G 1.8/3.3V............................................................... 227

9.9.1 1.8V Standard Vt MOS .................................................................................................................... 227
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9.9.2 3.3V MOS ........................................................................................................................................ 228

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9.9.3 1.8V Native MOS ............................................................................................................................. 229

9.9.4 3.3V Native MOS ............................................................................................................................. 230
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9.10 KEY PARAMETERS OF MOS TRANSISTORS IN CM016G 1.8/3.3V ........................................................... 231

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9.10.1 1.8V Standard Vt MOS .................................................................................................................. 231

9.10.2 3.3V MOS ...................................................................................................................................... 232
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9.10.3 1.8V Native MOS ........................................................................................................................... 233

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9.10.4 3.3V Native MOS ........................................................................................................................... 234

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9.10.5 1.8V Medium Vt MOS .................................................................................................................... 235

9.10.6 3.3V Medium Vt MOS .................................................................................................................... 236
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9.11 KEY PARAMETERS FOR BIPOLAR ............................................................................................................ 237

9.11.1 CL018G 1.8/3.3V ........................................................................................................................... 237
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9.11.2 CL018G 1.8/5V .............................................................................................................................. 237

9.11.3 CL018LV 1.5/3.3V.......................................................................................................................... 238
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9.11.4 CL018LV 1.5/2.5V.......................................................................................................................... 238

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9.11.5 CL018LP 1.8/3.3V.......................................................................................................................... 239

9.11.6 CL018LP 1.8/5V............................................................................................................................. 239
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9.11.7 CM018G 1.8/3.3V .......................................................................................................................... 239

9.11.8 CL016G 1.8/3.3V ........................................................................................................................... 240
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9.11.9 CM016G 1.8/3.3V .......................................................................................................................... 240

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9.12 KEY PARAMETERS FOR JUNCTION DIODES .............................................................................................. 241

9.12.1 CL018G 1.8/3.3V ........................................................................................................................... 241
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9.12.2 CL018G 1.8/5V .............................................................................................................................. 241

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9.12.3 CL018LV 1.5/3.3V.......................................................................................................................... 242

9.12.4 CL018LV 1.5/2.5V.......................................................................................................................... 242
9.12.5 CL018LP 1.8/3.3V.......................................................................................................................... 243
9.12.6 CL018LP 1.8/5V............................................................................................................................. 243
9.12.7 CM018G 1.8/3.3V .......................................................................................................................... 244
9.12.8 CL016G 1.8/3.3V ........................................................................................................................... 244
9.12.9 CM016G 1.8/3.3V .......................................................................................................................... 245
Document No.
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: T-018-LO-DR-001
: 2.8
9.13 RESISTOR MODEL .................................................................................................................................. 246

9.13.1 CL018G 1.8/3.3V Resistor Model .................................................................................................. 246
9.13.2 CL018G 1.8/5V Resistor Model ..................................................................................................... 248
9.13.3 CL018LV 1.5/3.3V Resistance Model............................................................................................ 250
9.13.4 CL018LV 1.5/2.5V Resistance Model............................................................................................ 251
9.13.5 CL018LP 1.8/3.3V Resistor Model ................................................................................................ 252
9.13.6 CL018LP 1.8/5V Resistor Model ................................................................................................... 254
9.13.7 CM018G 1.8/3.3V Resistance Model ............................................................................................ 256
9.13.8 CL016G 1.8/3.3V Resistor Model .................................................................................................. 260
9.13.9 CM016G 1.8/3.3V Resistor Model ................................................................................................. 262
9.14 INTERCONNECT MODEL .......................................................................................................................... 265
9.14.1 Interconnection line-line capacitance............................................................................................. 265
9.14.2 TYPICAL INTERCONNECT CAPACITANCE TABLE ................................................................... 269
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9.14.3 Comparison of metal routing delay between measurement and simulation.................................. 280
9.15 MIM CAPACITOR MODEL ........................................................................................................................ 281
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9.15.1 CM018G......................................................................................................................................... 281

9.15.2 CR018G ......................................................................................................................................... 282
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9.16 INDUCTOR MODEL .................................................................................................................................. 294

9.16.1 Model Usage Guide ....................................................................................................................... 294
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9.16.2 Inductor Layout .............................................................................................................................. 295

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9.16.3 Equivalent Circuit Model ................................................................................................................ 296

9.16.4 Scaling Rules and Model Parameters ........................................................................................... 297
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9.16.5 Variable Metal Layer Model ........................................................................................................... 300

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9.16.6 Corner Model Table ....................................................................................................................... 300

9.16.7 Model Error Table .......................................................................................................................... 301
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9.16.8 Device Characteristics ................................................................................................................... 304

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9.16.9 Temperature Effect Model ............................................................................................................. 307

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APPENDIX A REVISION HISTORY .......................................................................................................... 308

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A.1 TSMC 0.18UM CMOS LOGIC/MS/RF AND 0.16UM CMOS LOGIC/MS DESIGN RULE
(CL018G/LV/LP, CM018G, CR018G, CL016G, CM016G) .......................................................................... 308
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A.1.1 From Version 2.7 to Version 2.8................................................................................................. 308

A.1.2 From Version 2.6 to Version 2.7................................................................................................. 311
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A.2 CL018G 1.8V/3.3V (GENERAL PURPOSE)........................................................................................... 314

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A.3 CL018G 1.8V/5V (GENERAL PURPOSE).............................................................................................. 317

A.4 CL018LV 1.5V/3.3V (LOW VOLTAGE) ................................................................................................. 317
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A.5 CL018LV 1.5V/2.5V (LOW VOLTAGE) ................................................................................................. 319

A.6 CL018LP 1.8V/3.3V (LOW POWER) .................................................................................................... 321
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A.7 CL018G 1.8V/5V (LOW POWER)......................................................................................................... 321

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A.8 CL016G & CM016G........................................................................................................................... 322

A.9 CM018G............................................................................................................................................. 323
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Document No.
Version
: T-018-LO-DR-001
: 2.8
1. Introduction
This chapter has been divided into the following topics:
1.1 Overview
1.2 Integrated Design Rule Manuals
1.3 Reference Documentation
1.4 Guidelines for CL016G/CM016G Technologies
1.5 Note for Reliability Applications
1.1 Overview
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This document provides all the rules and reference information for the design and layout of integration circuits
using TSMC 0.16um/0.18um COMS Logic & Mixed Signal/RF 1P6M (single poly, 6 metal layers), salicide,
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AlCu technology. These rules and information about other specifications apply to TSMC semiconductor
processes: CL018G, CL018LV, CL018LP, CM018G, CL016G and CM016GG:
C
• CL018G: A general-purpose product for applications with a 1.8V core design, and with 3.3V or 5V
capable I/O’s.
C
• CL018LV: A high-speed (low voltage) product for applications with a 1.5V core design, and with 2.5V
VI
on 6 NO /2
or 3.3V capable I/O’s.

A
• CL018LP: A low-power product for applications with a 1.8V core design, and with 3.3V or 5V capable
fid 65 LO 009
I/O’s.
TE
• CM018G: A mixed signal product for applications with a 1.8V core design, and with 3.3V capable
en 12 G
I/O’s.
C /0
• CR018G: A mixed signal & RF product for applications with a 1.8V core design, and with 3.3V
capable I/O’s.
tia 1 IES
H 1
• CL016G: Provide CL018G products with 90% shrinkage for die area saving purpose. CL016G offers
12
1.8V core design, and 3.3V capable I/O’s.

lI
• CM016G: Provide CM018G products with 90% shrinkage for die area saving purpose. CM016GG
nf
offers 1.8V core design, and 3.3V capable I/O’s.

or
For C016, customers must complete all GDS file and DRC related efforts in C018 level, i.e. follow C018
m
and non-shrinkable rules (Section 8.2) to tape out. TSMC will shrink the GDS file to C016 while mask making.
at
0.18um mixed signal & 0.16um logic/mixed signal process options are only supported in CL018G 1.8/3.3V
io
process.
IN
In this document, figures and tables are usually numbered with 3 digits. The first two digits indicate section
C
number and the last one is sequence number. For example, Table 1.2.1 is the first table in the section in the
section 1.2 of Chapter 1.
.
Note
C018: CMOS 0.18um technology
Document No.
Version
: T-018-LO-DR-001
: 2.8
1.2 Integrated Design Rule Manuals

This document contains 9 previously separate 0.18um & 0.16um Design Rule Manuals (DRMs).
Table 1.2.1 Consolidated document list
Document Number Title Ver.
T-018-LO-DR-001 TSMC 0.18um Logic 1P6M Salicide 1.8V/3.3V Design Rule (General Purpose) 2.6
T-018-LO-DR-011 TSMC 0.18um Logic 1P6M Salicide 1.8V/5V Design Rule (General Purpose) 2.2
T-018-LO-DR-003 TSMC 0.18um Logic 1P6M Salicide 1.5V/3.3V Design Rule (Low Voltage) 1.5
T-018-LO-DR-008 TSMC 0.18um Logic 1P6M Salicide 1.5V/2.5V Design Rule (Low Voltage) 2.1
T-018-LO-DR-009 TSMC 0.18um Logic 1P6M Salicide 1.8V/3.3V Design Rule (Low Power) 1.1
TS
T-018-CL-DR-001 TSMC 0.18um CMOS Logic Low Power 1P6M Salicide 1.8&5V Design Rule 1.1
T-018-MM-DR-001 TSMC 0.18um Mixed Signal/RF 1P6M Salicide 1.8V/3.3V Design Rule 1.5
M
TSMC 0.18um CMOS RF 1P6M Sacilide 1.8&3.3V Schottky Barrier Diode (SBD)
T-018-CR-DR-001 1.0
Design Rule
C
TSMC 0.16um CMOS 1P6M Salicide AL_FSG Design Rule (CL016G/

T-016-CL-DR-001 1.2
CM016GG)
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
1.3 Reference Documentation

Table 1.3.1 C018/C016 logic technology document mapping table
1.8/3.3V G 1.8/5V G 1.5/2.5V LV 1.5/3.3V LV 1.8/3.3V LP 1.8/5V LP
Wire bond and Flip
T-000-CL-DR-002
Chip related rules
Fuse design rule T-000-LO-DR-003
GDS layer usage T-018-LO-LE-003
T-018-LO-DR-001-X2*
Dummy pattern
T-018-LO-DR-001-X3*
generation utility
T-018-LO-DR-001-X4*
T-018-LO-DR-001-X1* (general & antenna rules)
TS
DRC T-000-CL-DR-002-X1* (assembly rules)

T-000-LO-DR-003-X1* (metal fuse rules)
M
T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-CL-SP-

SPICE
001 010 008 004 002 001
C
T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-LO-SP- T-018-CL-SP-

LVS
001-X1* 010-X1* 008-X1* 004-X1* 002-X1* 001-X1*
C
T-018-LO-PF- T-018-LO-PF- T-018-CL-PF- T-018-LO-PF- T-018-LO-PF- T-018-LO-PF-

VI
Brief process flow

on 6 NO /2
001 012 004 003 005 012

Masking layers and T-018-LO-MB- T-018-LO-MB- T-018-LO-MB- T-018-LO-MB- T-018-LO-MB- T-018-LO-MB-
A
bias 001 011 005 003 009 011

fid 65 LO 009
Mixed signal
TE
Yes
support No No No No No
en 12 G
(Section 4.6)
(CM018G/CR018G)
C /0
CL016G/CM016GG Yes
No No No No No
tia 1 IES
H 1
support (Chapter 8)
*: X is the code of EDA tool. Please refer to TSMC on-line for the details.
12
lI
nf
Table 1.3.2 CM018G/CR018G/CL016G/CM016G mixed signal technology document mapping table

CM018G CR018G CL016G CM016G
or
Wire bond and Flip Chip

T-000-CL-DR-002
related rules
m
GDS layer usage T-018-LO-LE-003

at
T-018-LO-DR-001-X2*
Dummy pattern generation
T-018-LO-DR-001-X3*
utility
io
T-018-LO-DR-001-X4*
IN
T-018-LO-DR-001-X1* (general & antenna rules)

n
DRC T-000-CL-DR-002-X1* (assembly rules)

C
T-000-LO-DR-003-X1* (metal fuse rules)

T-018-MM-SP-002
.
SPICE T-018-MM-SP-001 T-016-CL-SP-001 T-016-CM-SP-001

T-018-CM-SP-007
T-018-MM-SP-002-X1*
LVS T-018-MM-SP-001-X1* T-016-CL-SP-001-X1* T-016-CM-SP-001-X1*
T-018-CM-SP-007-X1*
Brief process flow T-018-MM-PF-001 T-018-MM-PF-001 T-016-CL-PF-001 T-016-CM-PF-001
Masking layers and bias T-018-MM-MB-001 T-018-MM-MB-001 T-016-CL-MB-001 T-016-CM-MB-001
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 1.3.3 0.18um & 0.16um document list

Content Reference Documentation Document Number
Wire bond and Flip TSMC WIRE BOND, FLIP CHIP AND INTERCONNECTION DESIGN
T-000-CL-DR-002
Chip related rules RULE
Fuse design rule TSMC AL METAL FUSE DESIGN RULE T-000-LO-DR-003
TSMC 0.18UM MIXED SIGNAL 1P6M+ SALICIDE 1.8V/3.3V RF
T-018-MM-SP-001-K1
PDK
TSMC 0.18UM MIXED SIGNAL GENERAL PURPOSE II 1P6M
PDK T-018-CM-SP-007-K1
SALICIDE 1.8V/3.3V PDK (CM018G)
TSMC 0.16 UM MIXED SIGNAL GENERAL PURPOSE 1P6M
T-016-CM-SP-001-K1
SALICIDE AL_FSG 1.8&3.3V PDK
GDS layer usage TSMC 0.18UM GDS LAYER USAGE DESCRIPTION FILE T-018-LO-LE-003
TSMC C018/C016 CMOS LOGIC/MS_RF DESIGN RULE DRC
DRC T-018-LO-DR-001-X1*
TS
COMMAND FILE
TSMC 0.18UM DUMMY OD/PO GENERATION UTILITY T-018-LO-DR-001-X2*
Dummy pattern
TSMC 0.18UM DUMMY METAL GENERATION UTILITY T-018-LO-DR-001-X3*
M
generation utility
TSMC 0.18UM REDUNDANT VIA INSERTION UTILITY T-018-LO-DR-001-X4*
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/3.3V SPICE MODELS T-018-LO-SP-001
C
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/3.3V SPICE

T-018-LO-SP-002
MODEL(LOW POWER)(WITH 3DISK)
C
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.5V/3.3V SPICE MODELS

VI
T-018-LO-SP-004
on 6 NO /2
(LOW VOLTAGE)
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.5V/2.5V SPICE
A
T-018-LO-SP-008
MODEL(LOW VOLTAGE)(WITH 3DISK)
fid 65 LO 009
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/5V SPICE

TE
T-018-LO-SP-010
MODEL(CL018G)
en 12 G
TSMC 0.18 UM CMOS LOGIC LOW POWER 1P6M SALICIDE

T-018-CL-SP-001
C /0
SPICE 1.8&5V SPICE MODEL

tia 1 IES
TSMC 0.18UM MIXED SIGNAL 1P6M+ SALICIDE 1.8V/3.3V RF

H 1
T-018-MM-SP-001
SPICE MODELS
12
TSMC 0.18UM MIXED SIGNAL 1P6M+ SALICIDE 1.8V/3.3V SPICE

lI
T-018-MM-SP-002
MODELS
nf
T-018-CM-SP-007
SALICIDE 1.8V/3.3V SPICE MODELS
or
TSMC 0.16 UM LOGIC GENERAL PURPOSE 1P6M SALICIDE

T-016-CL-SP-001
AL_FSG 1.8V/3.3V SPICE MODEL
TSMC 0.16 UM CMOS MIXED SIGNAL MS GENERAL PURPOSE
m
T-016-CM-SP-001
1P6M SALICIDE AL_FSG 1.8&3.3V SPICE MODEL
at
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/3.3V LVS COMMAND

T-018-LO-SP-001-X1*
FILE
io

T-018-LO-SP-002-X1 *
FILE (LOW POWER)
IN

T-018-LO-SP-004-X1 *
FILE (LOW VOLTAGE)
C
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.5/2.5V LVS COMMAND

T-018-LO-SP-008-X1 *
.
FILE (LOW VOLTAGE)

TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/5V LVS COMMAND
T-018-LO-SP-010-X1 *
FILE
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/5V LVS COMMAND
LVS T-018-CL-SP-001-X1*
FILE (LOW POWER)
TSMC 0.18UM MIXED SIGNAL 1P6M+ SALICIDE 1.8V/3.3V RF LVS
T-018-MM-SP-001-X1*
COMMAND FILE
TSMC 0.18 UM MIXED SIGNAL 1P6M SALICIDE 1.8V/3.3V LVS
T-018-MM-SP-002-X1*
COMMAND FILE
T-018-CM-SP-007- X1*
SALICIDE 1.8V/3.3V LVS COMMAND FILE
TSMC 0.16 UM CMOS LOGIC GENERAL PURPOSE 1P6M
T-016-CL-SP-001- X1*
SALICIDE AL_FSG 1.8&3.3V LVS COMMAND FILE
TSMC 0.16 UM MIXED SIGNAL GENERAL PURPOSE 1P6M
T-016-CM-SP-001- X1*
SALICIDE AL_FSG 1.8&3.3V LVS COMMAND FILE
Document No.
Version
: T-018-LO-DR-001
: 2.8
Content Reference Documentation Document Number

TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/3.3V BRIEF PROCESS
T-018-LO-PF-001
FLOW
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.5V/3.3V PROCESS FLOW
T-018-LO-PF-003
(LOW VOLTAGE)
FAB11 0.18UM LOGIC SALICIDE 1P4M 1.5/2.5V BRIEF PROCESS
T-018-CL-PF-004
FLOW
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/3.3V BRIEF PROCESS
T-018-LO-PF-005
Brief process flow FLOW (LOW POWER)
TSMC 0.18UM LOGIC 1P6M SALICIDE 1.8V/5V BRIEF PROCESS
T-018-LO-PF-012
FLOW
0.18UM MIXED SIGNAL 1P6M SALICIDE 1.8/3.3V BRIEF
T-018-MM-PF-001
PROCESS FLOW
T-016-CL-PF-001
SALICIDE AL_FSG 1.8&3.3V BRIEF PROCESS FLOW
TS

T-016-CM-PF-001
1P6M SALICIDE AL_FSG 1.8&3.3V BRIEF PROCESS FLOW
TSMC 0.18UM CMOS LOGIC GENERAL PURPOSE 1P6M
M
T-018-LO-MB-001
SALICIDE 1.8V/3.3V MASKING LAYERS AND BIAS
C
TSMC 0.18UM CMOS LOGIC LOW VOLTAGE 1P6M SALICIDE

T-018-LO-MB-003
1.5V/3.3V MASKING LAYERS AND BIAS
C
TSMC 0.18UM CMOS LOGIC LOW VOLTAGE 1P6M SALICIDE

T-018-LO-MB-005
VI
on 6 NO /2
TSMC 0.18UM CMOS LOGIC LOW POWER 1P6M SALICIDE

T-018-LO-MB-009
A

Masking layers and
fid 65 LO 009
TSMC 8 INCH 0.18UM LOGIC 1P7M SALICIDE 1.8V/5V MASKING

bias T-018-LO-MB-011
LAYERS AND BIAS
TE
TSMC 0.18UM CMOS MIXED SIGNAL MS GENERAL PURPOSE

en 12 G
T-018-MM-MB-001
1P6M SALICIDE 1.8V/3.3V MASKING LAYERS AND BIAS
C /0

T-016-CL-MB-001
tia 1 IES
SALICIDE AL_FSG 1.8&3.3V MASKING LAYERS & BIAS TABLE

H 1

12
STANDARD PROCESS AL_FSG 1P7M SALICIDE 1.8V/3.3V T-016-CM-MB-001

lI
MASKING LAYERS AND BIAS

nf
TSMC FAB4 0.18UM LOGIC 1P6M 1.8V/3.3V QUALIFICATION

T-018-LO-QR-001
REPORT
or
TSMC FAB5 0.18UM LOGIC 1P6M SALICIDE 1.8/5V

T-018-LO-QR-022
QUALIFICATION REPORT
m
TSMC FAB4 0.18UM LOGIC 1P6M 1.5V/3.3V RELIABILITY

T-018-LO-QR-002
QUALIFICATION REPORT(LOW VOLTAGE)
at
FAB11 0.18UM LV 1.5/2.5V QUALIFICATION REPORT T-018-CL-QR-022

TSMC FAB4 0.18UM LP LOGIC 1P6M SALICIDE 1.8/3.3V
T-018-LO-QR-011
io
PROCESS RELIABILITY QUALIFICATION REPORT(LOW POWER)

Qualification report
IN
TSMC FAB5 0.18UM LOGIC LOW POWER 1P6M SALICIDE 1.8/5V

n
T-018-LO-QR-020
TSMC FAB4 0.18UM MIXED-SIGNAL 1P6+M SALICIDE 1.8V/3.3V
C
T-018-MM-QR-001
.

T-016-CL-QR-001
SALICIDE AL_FSG 1.8&3.3V QUALIFICATION REPORT-FAB 5
1P6M SALICIDE AL_FSG 1.8&3.3V QUALIFICATION REPORT- T-016-CM-QR-001
FAB6
TSMC 0.15UM/0.18UM/0.25UM ENGINEER REPORT OF
SRAM T-018-SM-RP-001
"SRAM REDUNDANCY FOR C025/C018/C015"
Document No.
Version
: T-018-LO-DR-001
: 2.8
1.4 Guidelines for CL016G/CM016G Technologies

1. TSMC also offer 90% shrinkage technologies for die cost saving benefit. For example, CL018G
CL016G.
2. Design must follow all CL018G or CM018G rules and the non-shrinkable rules for CL016G and
CM016G respectively.
3. It is very important to follow non-shrinkable rules while using CL016G/CM016G technologies. That
is to say, you need to consider the possibility of applying the CL016G/CM016G technology while you
design the CL018G circuit. Please replace the associated layout with the non-shrinkable rules according
to Chapter 8 “0.16UM TECHNOLOGY (CL016G/ CM016G)”.
4. Except non-shrinkable rules, others are allowed 90% shrinkage
TS
1.5 Note for High Reliability Applications

M
C
If your products will be used in high reliability requirement applications, such as automotives, please contact
TSMC account manager for the associated document.
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
2. Technology Overview
This chapter provides information about the following:
2.1 Semiconductor Process
2.2 Power Supply of Devices
2.3 Cross-Section
2.4 Metallization Options
2.5 User Guide
2.1 Semiconductor Process

TS
The process consists of the features of front-end, back-end and MS/RF devices
M
2.1.1 Front-End Features

C
• Shallow trench isolation (STI)

C
Used for active isolation to reduce active pitch (OD pitch).

VI
Retrograde four well CMOS technology on <100> P- substrate wafer

on 6 NO /2
•
For a low well sheet resistance and enhancement of latch-up behavior (compared to conventionally
A
diffused wells). Also provides for a good control of short parasitic field transistors.
fid 65 LO 009
TE
• Dual gate oxide (DGO) process

en 12 G
• N+/P+ poly gate

C /0
• Self-aligned Co-salicided drain, source and gate

tia 1 IES
H 1
Salicide is necessary to short N+ and P+ gates. Furthermore, it drastically reduces gate and S/D serial
resistance. Self-aligned salicide on source/drain structures allows butting straps with only one minimally
12
lI
sized contact.
nf
• Unsalicided poly and OD resistors

Salicide protection (requires one additional mask, RPO) is used to prevent salicide formation over the
or
active and poly area.

• Native device is provided as following table
m
CM018G
CL016G CM016G
at
CL018G CL018G CL018LV CL018LV CL018LP CL018LP

CR018G
1.8/3.3V 1.8/5V 1.5/2.5V 1.5/3.3V 1.8/3.3V 1.8/5V 1.8/3.3V 1.8/3.3V
1.8/3.3V
io
Native device Yes No Yes Yes No No Yes Yes Yes

IN
n
C
• Two kinds of BJT are provided as following table

Table 2.1.1 BJT offering table
.
CM018G
CL018G CL018G CL018LV CL018LV CL018LP CL018LP CL016G CM016G
CR018G
1.8/3.3V 1.8/5V 1.5/2.5V 1.5/3.3V 1.8/3.3V 1.8/5V 1.8/3.3V 1.8/3.3V
1.8/3.3V
P+/NW/PSUB BJT Yes Yes Yes Yes Yes Yes No Yes No
N+/PW/DNW BJT No No No No No No Yes No Yes
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.1.2 Back-End Features

• Tungsten contact
Connect poly or OD to first metal level.
• Tungsten via
Connect first metal level to top metal level.
• Chemical mechanical polishing (CMP)
For enhanced planarization in STI, contact, via, inter-metal dielectric layers.
• AlCu interconnection
For metal-1 to the last (top) metal interconnect. Ultra thick top metal scheme is also supported.
TS
• Wire bond or flip chip

CUP design is supported. (Please refer to “TSMC WIRE BOND, FLIP CHIP AND INTERCONNECTION DESIGN
M
RULE” (Doc. No.T-000-CL-DR-002) for details.)

C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.1.3 MS/RF devices Features

The 0.18um MS/RF process (CM018G/CR018G) is based on 0.18um logic general purpose (CL018G) 1P6M,
1.8V/3.3V, salicide process. The major MS/RF process features of the additional offering devices/process are:
• Deep N-Well (DNW) is optional for isolating the noise from P-substrate. It is only offered in MS/RF process.
• Medium Vt NMOS and medium Vt PMOS are offered in the MS/RF application. Two extra implant masks
VTM_N/VTM_P and the associated implant process are required.
• The P-type HRI (high resistance without salicide) poly resistor is offered.
• The MIM capacitor is fabricated with two metals, which are separated by an insulator. TSMC provides
1fF/um2 & 2fF/um2 MIM capacitances. A CTM is used for capacitor top metal, where the bottom metal is
the M top-1 . For example, M5 is used as the bottom metal for the 1P6M process. Figure 2.1.1 provides an
TS
example of an MIM capacitor cross section. 1fF/um2 & 2fF/um2 MIM capacitances are not allowed used
simultaneously in the same chip.
M
• The ultra thick metal layer (UTM, 20KÅ or 40 KÅ thickness) is an optional layer for the inductor
C
application. UTM is not allowed used simultaneously with Mn (8KÅ thickness) in the same chip.
• Inductors are not allowed in CM016G. Because the UTM (thickness = 20KÅ, 40KÅ) is not provided in
C
CM016G process and SPICE model don’t support it, neither.

VI
on 6 NO /2
A
Table 2.1.2 Optional component/process mapping table

fid 65 LO 009
CM018G CR018G CM018G(GP2) CM016G

TE
SPICE BSIM3.24 BSIM3.24 BSIM4.5 BSIM3.24

en 12 G
DNW V V V V
C /0
VTM_N V V V V
tia 1 IES
H 1
VTM_P V V V V
HRI V V V V
12
MIM (1 fF/um2)
lI
V V V -
MIM (1.2 fF/um2) - - - V
nf
MIM (2 fF/um2) - V V -
20KÅ UTM - V - -
or
40KÅ UTM - V - -
m
Mn (or UTM)
at
io
VIAn
IN
CTM
n
Mtop-1(the last Mx)

C
.
VIAtop-1(the last VIAx)
Mtop-2
Figure 2.1.1 MIM capacitor cross section
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.2 Power Supply of Devices

CL018 CM018 CR018 CL016 CM016
G LV LP G G G G
Core (thin oxide)
1.8V / +10% 1.5V / +10% 1.8V / +10% 1.8V / +10% 1.8V / +10% 1.8V / +10% 1.8V / +10%
/Tolerance*
I/O (thick oxide) 3.3V / +10% 2.5V / +10% 3.3V / +10% 3.3V / +10% 3.3V / +10% 3.3V / +10% 3.3V / +10%
/Tolerance* 5V / +10% 3.3V / +10% 5V / +10%
TS
* Tolerance is for maximum operation voltage & maximum burn in voltage.

M
Warning: C018 only allows DGO device, i.e. device with only one core voltage and
C
one I/O voltage is allowed.

C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.3 Cross-Section
Cross-section (1P6M)
Polyimide(optional)
Passivation
TS
M6 W/S=
W/S=0.44/0.46
0.44/0.46
M
M6 (8K)
20K UTM W/S= 1.5/1.5 M6
C
M6
40K UTM W/S= 2.6/2.5
USG
C
VI
on 6~ NO /2
V5 W/S= 0.36/0.35
V5
A
fid ~65 LO 009
M5 W/S= 0.28/0.28 FSG

TE
M5
en 12 G
C /0
tia 1 IES
H 1
M3 W/S= 0.28/0.28
12
M3 M3
lI
FSG
nf
V2
V2 W/S= 0.26/0.26
or
M2 W/S= 0.28/0.28 M2 M2
m
FSG
at
V1
V1 W/S= 0.26/0.26
io
M1 W/S= 0.23/0.23 FSG

IN
M1 M1
n
C
CO W/S= 0.22/0.25 BPSG+PSG

PO W/S= 0.18/0.25, 0.18/0.375 W-Plug
.
OD W/S= 0.22/0.28
Poly Poly
Sacilide STI
Figure 2.3.1 Cross-section for 1P6M
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.4 Metallization Options

2.4.1 Logic Metallization Options
Please refer to the following tables for the metallization options of 0.18um technology:
Table 2.4.1 Naming for Different Metal Types Table 2.4.2 Naming for Different Via Types
Metal type Code Via type Code
M1 (4KÅ thickness) M1 Inter-layer Via Vx
Inter-layer Metal (4KÅ thickness) Mx Top Via Vn
TS
Top Metal (8KÅ thickness) Mn Via hole between MD and Mtop VIAD
Redistribution metal for flip chip MD
M
C
A: Typical metallization
Table 2.4.3 8KÅ Top Metal Metallization table
C
Metal Total Number of Metal Layers

VI
on 6 NO /2
/Via 3 4 5 6
A
M1 M1 M1 M1 M1
fid 65 LO 009
VIA1 Vx Vx Vx Vx
TE
M2 Mx Mx Mx Mx
VIA2 Vn Vx Vx Vx
en 12 G
M3 Mn Mx Mx Mx
C /0
VIA3 Vn Vx Vx
tia 1 IES
H 1
M4 Mn Mx Mx
VIA4 Vn Vx
12
lI
M5 Mn Mx
nf
VIA5 Vn
M6 Mn
or
B: Metallization of VD/MD layers

m
Table 2.4.3.1 8KÅ Top Metal with VD/MD layers.

at

/Via 3 4 5 6
io
M1 M1 M1 M1 M1
IN
VIA1 Vx Vx Vx Vx
n
M2 Mx Mx Mx Mx
C
VIA2 Vn Vx Vx Vx
.
M3 Mn Mx Mx Mx
VIA3 VIAD Vn Vx Vx
M4 MD Mn Mx Mx
VIA4 VIAD Vn Vx
M5 MD Mn Mx
VIA5 VIAD Vn
M6 MD Mn
Via 6 (VD) VIAD
Metal 7 (MD) MD
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.4.2 Mixed Signal & RF Metallization Options

• Table 2.4.6 provides the metallization options for the 8KÅ top metal (Mn) with MIM.
• Table 2.4.7 and Table 2.4.8 provides the metallization options for the ultra thick top metal (UTM, 20KÅ or
40KÅ thickness) without and with MIM, respectively.
• Table 2.4.9 provides the metallization options for the 8KÅ top metal (Mn) with MIM and MD/VD.
• “CTM” is the optional layer for capacitor top metal. And it is only allowed being placed at:
(1) between Mtop-1 and Mn; or (2) between Mtop-1 and UTM.
• UTM is not supported in CM016G technology.
Table 2.4.4 Naming for Different Metal Thicknesses

TS
Metal type Code

M1 (4KÅ thickness) M1
M
Inter-layer Metal (4KÅ thickness) Mx

C
Top Metal (8KÅ thickness) Mn

Ultra THICK Top Metal (20KÅ or 40KÅ thickness) UTM *
C
Redistribution metal for flip chip MD

VI
on 6 NO /2
* Please refer to Section 4.6.7 for the UTM deign rules.

A
fid 65 LO 009
Table 2.4.5 Naming for Different Via Types

TE
Via type Code

en 12 G
Inter-layer Via Vx
C /0
Top Via Vn
tia 1 IES
H 1
Via hole between MD and Mtop VIAD

12
lI
A: Typical metallization
nf
Table 2.4.6 8KÅ Top Metal with MIM

or
/Via 3 4 5 6
M1 M1 M1 M1 M1
m
VIA1 Vx Vx Vx Vx
at
M2 Mx + CTM Mx Mx Mx
VIA2 Vn Vx Vx Vx
io
M3 Mn Mx + CTM Mx Mx
IN
VIA3 Vn Vx Vx
M4 Mn Mx + CTM Mx
C
VIA4 Vn Vx
.
M5 Mn Mx + CTM
VIA5 Vn
M6 Mn
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 2.4.7 Ultra Thick Top Metal (20KÅ or 40KÅ thickness) without MIM
/Via 4 5 6
M1 M1 M1 M1
VIA1 Vx Vx Vx
M2 Mx Mx Mx
VIA2 Vx Vx Vx
M3 Mx Mx Mx
VIA3 Vn Vx Vx
M4 UTM Mx Mx
VIA4 Vn Vx
M5 UTM Mx
VIA5 Vn
TS
M6 UTM
M
Table 2.4.8 Ultra Thick Top Metal (20KÅ or 40KÅ thickness) with MIM
C
/Via 4 5 6
M1 M1 M1 M1
C
VIA1 Vx Vx Vx
VI
on 6 NO /2
M2 Mx Mx Mx
A
VIA2 Vx Vx Vx
fid 65 LO 009
M3 Mx + CTM Mx Mx
TE
VIA3 Vn Vx Vx
en 12 G
M4 UTM Mx + CTM Mx
C /0
VIA4 Vn Vx
tia 1 IES
H 1
M5 UTM Mx + CTM
VIA5 Vn
12
lI
M6 UTM
nf
B: Metallization of VD/MD layers

or
Table 2.4.9 8KÅ Top Metal with MIM and VD/MD layers
m
/Via 3 4 5 6
at
M1 M1 M1 M1 M1
VIA1 Vx Vx Vx Vx
io
M2 Mx + CTM Mx Mx Mx
IN
VIA2 Vn Vx Vx Vx
M3 Mn Mx + CTM Mx Mx
C
VIA3 VIAD Vn Vx Vx
.
M4 MD Mn Mx + CTM Mx
VIA4 VIAD Vn Vx
M5 MD Mn Mx + CTM
VIA5 VIAD Vn
M6 MD Mn
Via 6 (VD) VIAD
Metal 7 (MD) MD
Document No.
Version
: T-018-LO-DR-001
: 2.8
2.5 User Guide

1. The design rule layout grid is 0.005um at 1X
2. Recommend to use 1nm as layout database unit (DBU) when streaming out GDS. TSMC's technology
files adopt 1nm DBU by default. If different DBU setting is considered, please consult it with TSMC for
guidelines to modify default setting of TSMC's technology files to prevent from potential failure, for
example, job may be terminated.
3. This section lists the recommendations for users to design with high yield and better reliability.
2.5.1 Logic Design Recommendations

TS
1. To obtain more accurate resistance as in SPICE model, it is strongly recommended that the NW resistor
width 2.1um and the resistor square number Nsq 5.
M
2. For stacked structure (CO/VIA1, VIA1/VIA2, VIA2/VIA3, VIA3/VIA4, VIA4/VIA5, CO/VIA1/VIA2,

C
VIA1/VIA2/VIA3, VIA2/VIA3/VIA4, VIA3/VIA4/VIA5, CO/VIA1/VIA2/VIA3, VIA1/VIA2/VIA3/VIA4,

VIA2/VIA3/VIA4/VIA5, CO/VIA1/VIA2/VIA3/VIA4/VIA5 stacks), it is suggested to keep M1/2/3/4/5 as
C
0.45x0.45 um2 square shape, M6 as 0.9x0.9 um2 square, and contact/via at the center of metal island as
VI
much as possible.
on 6 NO /2
3. Follow antenna rules to ensure gate oxide reliability.

A
fid 65 LO 009
4. Add dummy metal pads at chip corners for better CMP planarization and assembly reliability.
TE
5. The chip corner power line layout is suggested for more resistance to thermal stress induced metal
en 12 G
delamination and oxide crack. The structure must be M6/VIA5/M5/VIA4/M4/VIA3/M3/VIA2/M2/VIA1

C /0
/M1/STI. For detail layout, please contact TSMC. (Refer section 4.5.22.3.1)
tia 1 IES
H 1
6. Use bigger metal end-of-line extension whenever possible.

7. Use redundant contacts and vias whenever possible. For redundant via insertion, it is recommended to
12
lI
use TSMC’s insertion utility. (Document number: T-018-LO-DR-001-C4)

nf
8. Use anchor at end of isolated long metal lines whenever possible. (The suggested anchor-shape is as
the shaded region in Fig. 2.5.R1)
or
A/2
m
A/2
at
Isolated Line A
io
IN
Added Anchor-shape
C
Figure 2.5.R1
.
9. Add dummy OD and poly patterns at edge of memory cell array to improve cell uniformity.
10. Increase PP.E.3/NP.E.3 up to 0.18 µm if OD width 0.42 um. It’s also recommended that the length of
such narrow pickup OD be less than 50 um.
0.18um 0.02um
um
If pickup OD 0.42um
Length < 50um
Figure 2.5.R2
Document No.
Version
: T-018-LO-DR-001
: 2.8
11. To prevent insufficient butted area from implant misalignment, it’s recommended to make the width of
butted diffusion larger than 0.42 um. Please also refer to OD.W.3.
Not allowed
Line-width < 0.42um
Butted diffusion OD
TS
M
Figure 2.5.R3
C
12. To minimize risk of current leakage resulting from LDD shadowing effect, keep 45º bent poly on OD as
short as possible and 90º bent poly layout shown below should be avoided.
C
PO PO
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
OD
12
lI
Figure 2.5.R4 L and U are not recommended due to electrical degradation.

nf
13. For 3.3V High Voltage Tolerant I/O designed by 2.5V NMOS (up to 3.3V at I/O pad), or 5V High Voltage
or
Tolerant I/O designed by 3.3V NMOS (up to 5V at I/O pad) ESD implant is required unless special design
by customer. TSMC will use ESD Dummy layer (ESD3DMY, see Rule ESD.28g) to generate ESD mask
m
(no. 111) by logic operation.

50um & W 2um) which enclose STI sharp polygon inside.
at
14. Avoid long narrow strip type of OD (L

Minimum STI width inside is 0.36um.
io
IN
> 50um
n
C
STI STI
.
> 0.36 um ~ 2um
OD
Figure 2.5.R5
Document No.
Version
: T-018-LO-DR-001
: 2.8
15. Apply/calculate current density rules after metal slots are added.
16. For accumulated SRAM density larger than 1.5M, redundancy is needed. Please refer to the most-
updated version of “TSMC 0.15um/0.18um/0.25um SRAM engineer report of SRAM redundancy for
C025/C018/C015” (document no. T-018-SM-RP-001) as embedded SRAM redundancy guideline.
17. For planar capacitor Emb-SRAM,

• Use RPO blocking on storage node to avoid silicide formation. The RPO overlay with WL poly should
be 0.03um & overlay with poly capacitor should 0.05um.
• Avoid using borderless contact (follow CO.E.1 0.1um).
• We suggest not using minimum OD width & PO width rules for pass gate (exceed 0.01um at least) to
avoid short channel & narrow width effects.
TS
18. Un-salicided poly resistor guidelines:

• Dummy layers (DMN2V, DMP2V) are required for the tapeout to perform logic operation during mask
M
making, and perform DRC on the poly resistor (please refer to T-018-LO-MB-001). Please refer to
section 4.5.7 “Poly Resistor and OD Resistor Guidelines”.
C
• Un-salicided poly resistor resistance is about 300 ohm/sq.

C
VI
on 6 NO /2
2.5.2 Mixed Signal Design Recommendations

A
fid 65 LO 009
TE
en 12 G
l It is recommended to use TSMC PDK cells to design your mixed signal circuit. These PDK cells have
C /0
been well characterized with silicon. Please refer to the document (T-018-MM-SP-001-K1) for layout
tia 1 IES
guideline.
H 1
HRI poly resistor guidelines:

12
l
lI
Dummy layers (RLPPDMY) are required for the tapeout to perform logic operation during mask making, and
nf
perform DRC on HRI poly resistor (please refer to T-018-MM-MB-001 and T-016-CM-SP-001). Please refer to
or
section 4.6.4 “HRI Poly Resistor Rule”.

HRI poly resistor resistance is about 1000 ohm/sq.
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3. General Layout Information

This chapter provides the following general layout information:
3.1 Mask Information, Key Process Sequence, and CAD layers Information
3.2 Mask Requirements for Device Options
3.3 Special Recognition CAD Layer Summary
3.4 Device Truth Tables
3.5 Device List & Spec
3.1 Mask Information, Key Process Sequence, and

TS
CAD Layers Information

M
The detailed masking layers are listed below in process sequence.

1. Except the optional masks, all other masks are must for TSMC 0.18um process. Optional masks include
C
DNW, VTM_N, VTM_P, HRI, ESD, CTM, FW, VIAD, MD and PM.
C
2. The Mask Name column lists the names, which are reserved for standard mask steps. These names
VI
should not be used for another purpose in tape out files without prior authorization from TSMC.
on 6 NO /2
3. The CAD Layer column lists CAD layer numbers during mask making. To obtain all related CAD layer
A
usage information, please refer to TSMC Document T-018-LO-LE-003. For the CAD layer with “Derived”,
fid 65 LO 009
the mask is generated by TSMC’s logical operation. Required layers for the logical operation are listed in
TE
Reference Layer in LOP (logical operation) column.

en 12 G
C /0
Table 3.1.1 lists the related mask information for CL018G (generic) 1.8V/3.3V design.
tia 1 IES
H 1
Table 3.1.2 lists the related mask information for CL018G (generic) 1.8V/5.0V design.
12
lI
Table 3.1.3 lists the related mask information for CL018LV (low voltage) 1.5V/2.5V design.
Table 3.1.4 lists the related mask information for CL018LV (low voltage) 1.5V/3.3V design.
nf
Table 3.1.5 lists the related mask information for CL018LP (low power) 1.8V/3.3V design.
or
Table 3.1.6 lists the related mask information for CL018LP (low power) 1.8V/5.0V design.
Table 3.1.7 lists the related mask information for CM018G 1.8V/3.3V design.
m
Table 3.1.8 lists the related mask information for CR018G 1.8V/3.3V design.
at
Table 3.1.9 lists the related mask information for C016G (generic) 1.8V/3.3V design.
io
Table 3.1.10 lists the related mask information for CM016G 1.8V/3.3V design.
IN
Warning: A CAD layer number must be ≤ 255. If the CAD layer number is > 255,
C
the mask making will fail.

.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.1 Mask Information, Key Process Sequence, and CAD Layers for CL018G 1.8V/3.3V
Key
Process
Mask Mask Digitized CAD
Sequence Reference Layer in LOP Description
Name ID Area Layer
* = optional
mask
Thin oxide for device, and
1 OD 120 D 3,11,12 -
interconnection.
2 ODR 121 C Derived OD Reverse thin oxide
3 PW 191 D Derived NW, NT_N P-Well.
4 NW 192 C 2 N-Well
5 OD2 132 D 4 - Thick oxide for device.
6 PO 130 D 13 - Poly for device, and interconnection.
TS
7 N2V 114 C Derived

NP, NW, OD2, DMN2V 1.8V NLDD implantation.
8 P2V 113 C Derived
PP, NW, OD2, DMP2V 1.8V PLDD implantation.
M
PP, NW, OD2, DMN2V,

9 P3V 115 C Derived 3.3V PLDD implantation.
DMP2V
C
NP, NW, OD2, DMN2V,

10 N3V 116 C Derived 3.3V NLDD implantation.
DMP2V
C
11 NP 198 C 8 PP, OD N+ implantation.

VI
on 6 NO /2
12 PP 197 C 7 NP, OD P+ implantation.

A
OD, NP, RPO, NW, PO,

13* ESD 111 C 30 ESD implantation.
fid 65 LO 009
ESD3DMY
TE
14 RPO 155 D 34 OD, PO, OD2, NP, NW, CO Salicide protection.

15 CO 156 C 15 - Contact window from M1 to OD or PO.
en 12 G
16 M1 160 D 16 - 1st metal for interconnection.

C /0
17 Via 1 178 C 17 - Via1 hole between M2 and M1

tia 1 IES
H 1
nd
18 M2 180 D 18 - 2 metal for interconnection.
12
19 Via 2 179 C 27 - Via2 hole between M3 and M2.

lI
rd
nf

th
or

th
m

th
at
26 M6 186 D 38 - 6 metal for interconnection

27* FW 108 C 235 - Fuse window
io
‡ ‡
28* VIAD C 167 Via hole between MD and Mtop
‡ ‡
IN
29* MD D 168 Redistribution metal for flip chip

n
CB 107 C 19 - Passivation pad opening for wire bond

30
C
CBD 107 C 169 - Passivation pad opening for flip chip

.
PM 009 D 89 CB, FW Polyimide window for wire bond

31*
PM 009 D 89 - Polyimide window for flip chip
‡
: Follow the mask and CAD layer ID of the metal/VIA layer above the Mtop/VIAtop.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
3 PW2V 191 D Derived OD2, NW 1.8V P-Well
4 PW5V 193 C Derived OD2, NW 5V P-Well
5 NW2V 192 C 2 OD2 1.8V N-Well
6 NW5V 194 C 2 OD2 5V N-Well
TS

M
9 N2V 114 C Derived

10 P2V 113 C Derived
C
PP, NW, OD2, DMN2V,

11 P5V 115 C Derived 5V PLDD implantation.
DMP2V
C
NP, NW, OD2, DMN2V,

VI
on 6 NO /2
12 N5V 116 C Derived 5V NLDD implantation.

DMP2V
A

fid 65 LO 009

TE
15* ESD 110 C 30 -- ESD implantation.

OD, PO, OD2, NP, NW,
en 12 G
16 RPO 155 D 34 Salicide protection.

CO
C /0

tia 1 IES
H 1

12
lI
nd
nf

rd
or

th
m

th
at

io
th
IN
‡ ‡
‡ ‡
C

.
32
33*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.3 Mask Information, Key Process Sequence, and CAD Layers for CL018LV 1.5V/2.5V
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
2 ODR 121 C Derived OD Reverse thin oxide.
3 PW2V 191 D Derived OD2, NW, NT_N 1.5V P-Well.
4 PW3V 193 C Derived OD2, NW, NT_N 2.5V P-Well and 2.5V NLDD.
5 NW2V 192 C 2 OD2 1.5V N-Well.
6 NW3V 194 C 2 OD2 2.5V N-Well and 2.5V PLDD.
TS
7 OD2 132 D 4 - Thick oxide for device

8 PO 130 D 13 OD, OD2 Poly for device, and interconnection.
M
9 N2V 114 C Derived NP, NW, OD2, DMN2V 1.5V NLDD.

10 P2V 113 C Derived PP, NW, OD2, DMP2V 1.5V PLDD.
C

C
VI

on 6 NO /2

A

fid 65 LO 009
ESD3DMY
TE
PO, OD, OD2, NP, NW,

en 12 G
CO,
17 CO 156 C 15 -
Contact window from M1 to OD or PO.
C /0
18 M1 160 D 16 -
1st metal for interconnection.
tia 1 IES
H 1
19 Via 1 178 C 17 -
Via1 hole between M2 and M1.
nd
12
20 M2 180 D 18 -
2 metal for interconnection.
lI
21 Via 2 179 C 27 -
nf
rd
22 M3 181 D 28 -
23 Via 3 173 C 29 -
or
th
24 M4 184 D 31 -
25 Via 4 174 C 32 -
m
th
26 M5 185 D 33 -
at
27 Via 5 175 C 39 -
th
28 M6 186 D 38 -
io
29* FW 108 C 235 -

Fuse window
‡ ‡
IN

n
‡ ‡
C

32
.

33*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.4 Mask Information, Key Process Sequence, and CAD Layers for CL018LV 1.5V/3.3V
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
3 PW2V 191 D Derived OD2, NW, NT_N 1.8V P-Well
5 NW2V 192 C 2 OD2 1.8V N-Well.
TS

M

C

C

VI
on 6 NO /2

A

fid 65 LO 009
ESD3DMY
TE

CO,
en 12 G
17 CO 156 C 15 -
C /0
18 M1 160 D 16 -
tia 1 IES
H 1
19 Via1 178 C 17 -
nd
20 M2 180 D 18 -
12
lI
21 Via 2 179 C 27 -
rd
nf
22 M3 181 D 28 -
23 Via 3 173 C 29 -
or
th
24 M4 184 D 31 -
25 Via 4 174 C 32 -
m
th
26 M5 185 D 33 -
27 Via 5 175 C 39 -
at
th
28 M6 186 D 38 -
io
29* FW 108 C 235 -

Fuse window
‡ ‡
IN
‡ ‡
C

32
.

33*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.5 Mask Information, Key Process Sequence, and CAD Layers for CL018LP 1.8V/3.3V
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
4 PW3V 193 C Derived OD2, NW 3.3V P-Well and 3.3V NLDD.
5 NW2V 192 C 2 NW, OD2 1.5V N-Well.
6 NW3V 194 C 2 NW, OD2 3.3V N-Well and 3.3V PLDD.
TS

M

C

12 PW3V 193 C Derived OD2, NW 3.3V P-Well and 3.3V NLDD.
C

VI
on 6 NO /2

A

fid 65 LO 009
ESD3DMY
TE

CO,
en 12 G
17 CO 156 C 15 -
C /0
18 M1 160 D 16 -
tia 1 IES
H 1
19 Via1 178 C 17 -
nd
20 M2 180 D 18 -
12
lI
21 Via 2 179 C 27 -
rd
nf
22 M3 181 D 28 -
23 Via 3 173 C 29 -
or
th
24 M4 184 D 31 -
25 Via 4 174 C 32 -
m
th
26 M5 185 D 33 -
27 Via 5 175 C 39 -
at
th
28 M6 186 D 38 -
io
29* FW 108 C 235 -

Fuse window
‡ ‡
IN

n
‡ ‡
C

32
.

33*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.6 Mask Information, Key Process Sequence, and CAD Layers for CL018LP 1.8V/5.0V
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
4 PW5V 193 C Derived OD2, NW 5V P-Well
5 NW2V 192 C 2 OD2 1.8V N-Well
6 NW5V 194 C 2 OD2 5V N-Well
TS

M
9 N2V 114 C Derived

10 P2V 113 C Derived
C
PP, NW, OD2, DMN2V,

11 P5V 115 C Derived 5V PLDD implantation.
DMP2V
C
NP, NW, OD2, DMN2V,

VI
on 6 NO /2
12 N5V 116 C Derived 5V NLDD implantation.

DMP2V
A

fid 65 LO 009

TE
15* ESD 110 C 30 -- ESD implantation.

OD, PO, OD2, NP, NW,
en 12 G

CO
C /0

tia 1 IES
H 1

12
lI
nd
nf

rd
or

th
m

th
at

io
th
IN
‡ ‡
‡ ‡
C

.
32
33*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.7 Mask Information, Key Process Sequence, and CAD Layers for CM018G 1.8V/3.3V
Key Process
Digitized Reference Layer in Logical
Sequence * = Mask Name Mask ID CAD Layer Description
Area Operation
Optional Mask
1* DNW 119 C 82 - Deep N-Well.
2 OD 120 D 3 - Thin oxide for device, and interconnection.
(1)
3 ODR 121 C Derived OD Trench.
(1)
(1)
5* VTM_N 118 C 24 NW, NT_N NMOS Vt implantation.
6 NW 192 C 2 - N-Well.
(1)
7* VTM_P 117 C 23 NW PMOS Vt implantation.
8 OD2 132 D 4 - 3.3V thick oxide.
TS
9 PO 130 D 13 - Poly-Si.
(1)
10 N2V 114 C Derived NW, OD2, NP, DMN2V, VARDMY 1.8V NLDD implantation.
NW, OD2, PP, DMP2V, VARDMY,
M
(1)
11 P2V 113 C Derived 1.8V NLDD implantation.
RLPPDMY
C
(1) NW, OD2, PP, DMN2V, DMP2V,

VARDMY, RLPPDMY
C
(1) NW, OD2, NP, DMN2V, DMP2V,

VI
VARDMY
on 6 NO /2
(1)
14 NP 198 C 8 OD, PP N+ S/D implantation.
A
(1)
15 PP 197 C 7 OD, NP, RLPPDMY P+ S/D implantation.
fid 65 LO 009
16* HRI 133 C 48 - High Resistor Implant

TE
(1)
17* ESD 111 C 30 NW, OD, PO, NP, RPO, ESD3DMY ESD implantation.
en 12 G
(1)
18 RPO 155 D 34 NW, OD, OD2, PO, NP, CO Resist protection oxide.
C /0
19 CO 156 C 15 - Contact hole between M1 and (OD or PO).

tia 1 IES
H 1

21 VIA1 178 C 17 - Via1 hole between M2 and M1.
12
lI
22 M2 180 D 18 - 2nd metal for interconnection.

nf
24 M3 181 D 28 - 3rd metal for interconnection.

or

26 M4 184 D 31 - 4th metal for interconnection.
m

28* CTM 182 D 67 - Capacitor top metal
at

io

IN

n

C
‡ ‡
‡ ‡
.

35
36*
Note:
(1) Please refer to document “T-018-MM-MB-001” for the detailed logical operation.
(2) More bond pad related offerings and rules are available in the bond pad design rule (Please refer to “TSMC WIRE
BOND, FLIP CHIP AND INTERCONNECTION DESIGN RULE” (Doc. No.T-000-CL-DR-002) for details.).
‡
(3) : Follow the mask and CAD layer ID of the metal/VIA layer above the Mtop/VIAtop.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.8 Mask Information, Key Process Sequence, and CAD Layers for CR018G 1.8V/3.3V
Key Process
Area Operation
Optional Mask
(1)
(1)
(1)
6 NW 192 C 2 - N-Well.
(1)
9 PO 130 D 13 - Poly-Si.
TS
(1)
(1) NW, OD2, PP, DMP2V, VARDMY,
RLPPDMY
M
(1) NW, OD2, PP, DMN2V, DMP2V,

VARDMY, RLPPDMY
C
(1) NW, OD2, NP, DMN2V, DMP2V,

VARDMY
C
(1)
VI
on 6 NO /2
(1)
A

(1)
fid 65 LO 009
(1)
TE
en 12 G

C /0

tia 1 IES
H 1

12
lI

nf

or

m

at
BEOL option-1 (Top metal, M6, 8KÅ thickness)

io

‡ ‡
33* VIAD C 167
IN
Via hole between MD and Mtop

n
‡ ‡
C

33
.

34*
BEOL option-2 (Ultra Thick top metal, UTM, 20KÅ or 40KÅ thickness)
31 UTM 186 D 38 - 6th metal for interconnection.
33
34*
Note:
(1) Please refer to document “T-018-MM-MB-001” for the detailed logical operation.
(2) More bond pad related offerings and rules are available in the bond pad design rule (Please refer to “TSMC WIRE BOND, FLIP
CHIP AND INTERCONNECTION DESIGN RULE” (Doc. No.T-000-CL-DR-002) for details.).
‡
(3) : Follow the mask and CAD layer of the metal/VIA layer above the Mtop/VIAtop.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Key
Process
Name ID Area Layer
* = optional
mask
1 OD 120 D 3,11,12 -
interconnection.
4 NW 192 C 2 - N-Well
6 PO 130 D 13
OD, OD2, NP, PP Poly for device, and interconnection.
TS
7 N2V 114 C Derived

8 P2V 113 C Derived
M
PP, NW, OD2, DMN2V,

DMP2V
C
NP, NW, OD2, DMN2V,

DMP2V
C

VI
on 6 NO /2

A

fid 65 LO 009
ESD3DMY
TE
14 RPO 155 D 34 OD, PO, OD2, NP, NW, CO Salicide protection.

en 12 G

C /0

tia 1 IES
H 1
nd
12

lI
rd
nf

th
or

th
m

th
at

io
‡ ‡
‡
IN
‡
n

30
C

.

31*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.1.10 Mask Information, Key Process Sequence, and CAD Layers for CM016G 1.8V/3.3V
Key Process
Area Operation
Optional Mask
6 NW 192 C 2 - N-Well.
TS
9 PO 130 D 13 OD, OD2, NP, PP Poly-Si.

NW, OD2, PP, DMP2V, VARDMY,
M
11 P2V 113 C Derived 1.8V NLDD implantation.

RLPPDMY
C
NW, OD2, PP, DMN2V, DMP2V,

VARDMY, RLPPDMY
C
NW, OD2, NP, DMN2V, DMP2V,

VI
VARDMY
on 6 NO /2

A

fid 65 LO 009

TE
en 12 G
C /0

tia 1 IES
H 1

12
lI

nf

or

m

at

io

IN

n

C
‡ ‡
‡ ‡
.

35
36*
‡
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.2 Mask Requirements for Device Options

Table 3.2.1 Mask Requirements for Device Options
Mask Requirements
Process
Well LDD
Two masks: Four masks:
1.8V/3.3V (G)
PW, NW P2V, P3V, N2V, N3V
Four masks: Four masks:
1.8V/5.0V (G)
PW2V, PW5V, NW2V, NW5V P2V, P5V, N2V, N5V
TS

1.5V/2.5V (LV)
M

1.5V/3.3V (LV)
C

C
1.8V/3.3V (LP)
VI
on 6 NO /2

1.8V/5.0V (LP)
A

fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.3 Special Recognition CAD Layer Summary

Table 3.3.1 lists special layers for CL018 DRC recognition or Tapeout required layer purpose and Table 3.3.2
lists special layers for CM018G/CR018G DRC recognition or Tapeout required layer purpose. If you do not
follow the TSMC default CAD layer number, make sure that you change the layer mapping in the relative deck,
like DRC/LVS and so on. Some CAD layer designators include a GDS datatype according to the GDS layer;
datatype format.
The column “ Tapeout required layer” indicates that this layer must be noted on the mask tapeout form, to
provide information for mask making.
Table 3.3.1 Special Layer Summary for CL018
TS
Tapeout
Special Layer TSMC Default CAD
Description Associated With DRC required
Name Layer
layer
M
Latch up rules and ESD

SDI 58;0 Dummy layer to cover ESD devices. V
guidelines
C
Dummy layer for N+ poly resistor (non-silicided N+

DMN2V 184 Poly resistor rules V V
C
poly resistor)
VI
Dummy layer for P+ poly resistor (non-silicided P+

on 6 NO /2
DMP2V 149 Poly resistor rules V V

poly resistor)
A
RWDMY 52 Dummy layer for NW resistor NW resistor rules V

fid 65 LO 009
RWDMY
52;1 Dummy layer to define 3-terminal NW resistors 3-terminal NW resistors V
TE
(drawing1)
RPDUMMY 54;0 Dummy for Poly/OD resistor device Poly/OD resistor device V V
en 12 G
RPDUMMY 3-terminal Poly/OD resistor

C /0
54;1 Dummy for 3-terminal Poly/OD resistor device V V

(drawing1) device
tia 1 IES
H 1
Dummy layer to cover IO ESD regionfor

5V/3.3V/2.5V NMOS used as power clmap (It is
12
ESD1DMY 136 ESD rules and guidelines V

lI
strongly recommended to adopt the structre

(described in section 5.1.1) for tapeout)
nf
Dummy layer to cover 3.3V/2.5V NMOS and

PMOS high voltage tolerant I/O,
or
ESD2DMY 137 ESD guidelines V

5V/3.3V/2.5V/1.8V/1.5V NMOS and PMOS
regular IO, 5V/3.3V/2.5V NMOS power clmap
m
ESD3DMY 234 ESD implant (mask 111) required dummy layer ESD guidelines V V
at
ESD implant (mask 110) Required drawing layer

ESD 30 ESD rules and guidelines V
for 5V ESD implant
io
DIODMY 56 Dummy layer to cover diode devices. LOGO rules V

IN
BJTDMY 49 Dummy layer to cover BJT devices. Analog layout rules V

n
LOGO 178 LOGO, dummy layer for product label and logo. LOGO rules V
C
DRC dummy layer to waive the latch up rule if the Latch up rules and
LUPWDMY 255;1 V
silicon is verified for latch up issue. guiedlines
.
Latch up rules and

VDDDMY 255;4 Dummy Layer for Power(Vdd) PAD V
guiedlines
Latch up rules and
VSSDMY 255;5 Dummy Layer for Ground(Vss) PAD V
guiedlines
DRC dummy layer for chip corner dummy pad.
DPDUMMY 65;0 Use DPDMY to exactly cover chip corner ADP rules V
dummy pad.
DRC dummy layer for chip corner power line. Use
PLDUMMY 66;0 PLDMY to cover whole chip corner power ADP rules V
line.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3.3.2 Special Layer Summary for CM018G/CR018G

Tapeout
Special TSMC Default
Description Associated With DRC required
Layer Name CAD Layer
layer
VTM_P 23
VTM_P blocking implant VTM_P rule V V
VTM_N 24
VTM_N blocking implant VTM_N rule V V
CTMDMY 131
LVS dummy layer for MIM capacitor
LVS dummy layer for MIiM
CTMDMY
131;10 capacitance with 1.0fF capacitance
(drawing2)
per unit area.
LVS dummy layer for MIM
CTMDMY
131;20 capacitance with 2.0fF capacitance
(drawing4)
per unit area.
TS
CTMDMY LVS dummy layer for three

131;21
(drawing1) terminals MiM capacitor.
M
CTMDMY Dummy layer for MIMCAP to allow

131;50
(drawing5) devices putting under it, LVS used
C
Dummy layer for HRI poly resistor HRI rule, Poly

RLPPDMY 134 V V
(non-silicided P- poly resistor) resistor rule
C
Dummy layer for both MOS and LOGO rules &

VI
VARDMY 138 V V
on 6 NO /2
junction type varactor PO.R.1

To recognize new RF device used
A
RFDUMMY 160 VAR & SBD rules

for LVS purpose.
fid 65 LO 009
Dummy layer for RF MIMCAP to

TE
RFDUMMY
160;50 allow devices putting under it, LVS
en 12 G
(drawing3)
used
C /0
Dummy layer for UTM in inductor

INDDMY 139 UTM rules V
tia 1 IES
H 1
application
A layer for DRC, LVS and creating
Schottky Barrier
12
lI
mask logic operation. Use

SBDDMY 144 Diode (SBD) Layout V V
"SBDDMY" to fully cover schottky
Rules
nf
barrier diode.
l Dummy layer (VARDMY) is needed for logical operation and DRC when varactor devices are
or
implemented in circuit.
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4 Device Truth Tables

This section contains the device truth tables for:
• Table 3.4.1 CL018 Logic General Purpose (G) 1.8V/3.3V technology
• Table 3.4.2 CL018 Logic General Purpose (G) 1.8V/5V technology
• Table 3.4.3 CL018 Logic Low Voltage (LV) 1.5V/2.5V technology
• Table 3.4.4 CL018 Logic Low Voltage (LV) 1.5V/3.3V technology
• Table 3.4.5 CL018 Logic Low Power (LP) 1.8V/3.3V technology
• Table 3.4.6 CL018 Logic General Purpose (LP) 1.8V/5V technology
• Table 3.4.7 CM018G mixed signal/RF 1.8/3.3V technology
TS
• Table 3.4.8 CL016 Logic General Purpose (G) 1.8V/3.3V technology

M
• Table 3.4.9 CM016G mixed signal 1.8V/3.3V technology

C
The following provides a legend for the following five device truth tables.
C
0 Does not cover the structures

VI
on 6 NO /2
1 Covers or matches the structures

* Don’t care
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.1 CL018G 1.8V/3.3V

Table 3.4.1 CL018 Logic General Purpose (G) 1.8V/3.3V technology
Design Levels Special Layer
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
ESD3DMY
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
Device SPICE name
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.8V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (1.8V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
NMOS (3.3V) nch3 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (3.3V) pch3 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Native NMOS (1.8V) nanch 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
TS
Native NMOS (3.3V) nanch3 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

pnp2 (Emitter area
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
= 2×2 µm )
M
pnp5 (Emitter area

1.8V P+/NW/PSUB vertical PNP bipolar 2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
= 5×5 µm )
C
pnp10 (Emitter
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
area = 10×10 µm )
C
pnp2_3 (Emitter
2 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1 0
area = 2×2 µm )
VI
on 6 NO /2
pnp5_3 (Emitter
area = 5×5 µm )
A
pnp10_3 (Emitter
1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1 0
fid 65 LO 009
2
area = 10×10 µm )
TE
1.8V P+/Nwell Junction Diode PDIO 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 1 0 0

1.8V N+/Pwell Junction Diode NDIO 0 0 1 0 0 1 1# 0 0 0 0 0 0 0 1 0 0
en 12 G
1.8V NW/Psub Junction Diode NWDIO 1 0 1 0 0 1# 1# 0 0 0 0 0 0 0 1 0 0

C /0
3.3V P+/Nwell Junction Diode PDIO_3 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 1 0 0

3.3V N+/Pwell Junction Diode NDIO_3 0 0 1 1 0 1 1# 0 0 0 0 0 0 0 1 0 0
tia 1 IES
H 1
3.3V NW/Psub Junction Diode NWDIO_3 1 0 1 1 0 1# 1# 0 0 0 0 0 0 0 1 0 0

3.3V ESD Junction Diode ENDIO_3 0 0 1 0 1 1 1# 1 0 0 0 0 0 0 1 0 1
12
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0

lI
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0
nf
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0

N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0
or
P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0

N-well. Under OD Resistor (440 Ohm/sq) rnwod 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0
m
N-well. Under STI Resistor (927 Ohm/sq) rnwsti 1 0 1# 0 0 1 0 0 0 0 1 0 0 0 0 0 0

N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
at
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0
P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0
io
N+ Poly w/o Silicide Resistor (292 Ohm/sq) rnpo1rpo 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0

IN
P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0

n

3T_N-well. Under OD Resistor rnwod_m 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0
C
3T_N+ OD w/i Silicide Resistor (W 2um) rnod_m 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0

3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0

.
3T_N+ OD w/o Silicide Resistor rnodrpo_m 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 0

3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0
3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0
3T_P+ OD w/o Silicide Resistor rpodrpo_m 0 0 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0
# For pick-up
Note: The resistor value listed in table is just Rpure value. Please get more detail information in the SPICE
document.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.2 CL018G 1.8V/5V

Table 3.4.2 CL018 Logic General Purpose (G) 1.8V/5V technology
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
Device SPICE name
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.8V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (1.8V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0
NMOS (5V) nch_5 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (5V) pch_5 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0
pnp2 (Emitter area =
TS
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
2×2 µm )
1.8V P+/NW/PSUB vertical PNP bipolar 2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
5×5 µm )
M

2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
10×10 µm )
C
1.8V P+/Nwell Junction Diode PDIO 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 1 0

1.8V N+/Pwell Junction Diode NDIO 0 0 1 0 0 1 1# 0 0 0 0 0 0 0 1 0
C
1.8V NW/Psub Junction Diode NWDIO 1 0 1 0 0 1# 1# 0 0 0 0 0 0 0 1 0

5V P+/Nwell Junction Diode PDIO_5 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 1 0
VI
on 6 NO /2
5V N+/Pwell Junction Diode NDIO_5 0 0 1 1 0 1 1# 0 0 0 0 0 0 0 1 0

5V NW/Psub Junction Diode NWDIO_5 1 0 1 1 0 1# 1# 0 0 0 0 0 0 0 1 0
A
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0

fid 65 LO 009
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0

TE
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0
en 12 G
N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0

C /0
P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0

N-well. Under OD Resistor (440 Ohm/sq) rnwod 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0
tia 1 IES
H 1
N-well. Under STI Resistor (927 Ohm/sq) rnwsti 1 0 1# 0 0 1 0 0 0 0 1 0 0 0 0 0

N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0
12
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0

lI
P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0
nf
N+ Poly w/o Silicide Resistor (311 Ohm/sq) rnpo1rpo 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0

P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0
or
3T_ N-well. Under OD Resistor

3T_N+ OD w/i Silicide Resistor (W 2um)
rnwod_m
rnod_m
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
m
3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0

3T_N+ OD w/o Silicide Resistor
rnodrpo_m 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0
at
3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0
# For pick-up
io
IN
document.
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.3 CL018LV 1.5V/2.5V

Table 3.4.3 CL018 Logic Low Voltage (LV) 1.5V/2.5V technology
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
Device SPICE name
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.5V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (1.5V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0
NMOS (2.5V) nch2 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (2.5V) pch2 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0
Native NMOS (1.5V) nanch 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
TS
pnp2 (Emitter area

2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
= 2×2 µm )
pnp5 (Emitter area
M

= 5×5 µm )
pnp10 (Emitter
C
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
area = 10×10 µm )
pnp2_2 (Emitter
2 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1
C
area = 2×2 µm )
pnp5_2 (Emitter
VI
2.5V P+/NW/PSUB vertical PNP bipolar 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1

on 6 NO /2
2
area = 5×5 µm )
pnp10_2 (Emitter
1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1
A
2
area = 10×10 µm )
fid 65 LO 009

TE

en 12 G
2.5V P+/Nwell Junction Diode PDIO_2 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 1 0

C /0
2.5V N+/Pwell Junction Diode NDIO_2 0 0 1 1 0 1 1# 0 0 0 0 0 0 0 1 0

2.5V NW/Psub Junction Diode NWDIO_2 1 0 1 1 0 1# 1# 0 0 0 0 0 0 0 1 0
tia 1 IES
H 1

12

lI

nf

or

m

at

io

rnwod_t 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0
IN
3T_ N+ OD w/i Silicide Resistor (W 2um) rn_t 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0

n
3T_N+ OD w/i Silicide Resistor (W < 2um) rns_t 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0

C
3T_N+ OD w/o Silicide Resistor rnrpo_t 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0

3T_P+ OD w/i Silicide Resistor (W 2um) rp_t 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0
.
3T_P+ OD w/i Silicide Resistor (W < 2um) rps_t 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0

3T_P+ OD w/o Silicide Resistor rprpo_t 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 0
# For pick-up
document.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.4 CL018LV 1.5V/3.3V

Table 3.4.4 CL018 Logic Low Voltage (LV) 1.5V/3.3V technology
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
ESD3DMY
Device SPICE name
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
OD_2
RPO
NW
OD
PO
NP
PP
NMOS (1.5V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (1.5V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
NMOS (3.3V) nch3 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (3.3V) pch3 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
Native NMOS (1.5V) nanch 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
TS
Native NMOS (3.3V) nanch3 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
2×2 µm )
M

5×5 µm )
C
pnp10 (Emitter area

2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
= 10×10 µm )
C
pnp2_3 (Emitter
2 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1 0
area = 2×2 µm )
VI
on 6 NO /2
pnp5_3 (Emitter
area = 5×5 µm )
A
pnp10_3 (Emitter
1 0 1 1 0 1# 1 0 0 0 0 0 0 0 0 1 0
fid 65 LO 009
2
area = 10×10 µm )
TE

en 12 G

C /0

tia 1 IES
H 1

12

lI

nf

P+ OD w/o Silicide Resistor (133
or
rpodrpo 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0
Ohm/sq)
m

N+ Poly w/i Silicide Resistor (5.7
rnpo1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
Ohm/sq)
at
N+ Poly w/i Silicide Resistor (7.4

rnpo1w 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
Ohm/sq)
io

IN

n
N+ Poly w/o Silicide Resistor (330

rnpo1rpo 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0
Ohm/sq)
C
P+ Poly w/o Silicide Resistor (341

rppo1rpo 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0
Ohm/sq)
.

3T_ N+ OD w/i Silicide Resistor (W
2um)
rnwod_t
rn_t
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
3T_N+ OD w/i Silicide Resistor (W <
rns_t 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0
2um)

3T_P+ OD w/i Silicide Resistor (W 2um) rp_t
3T_P+ OD w/i Silicide Resistor (W <
rnrpo_t 0
1
0
0
1
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
rps_t 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0
2um)
3T_P+ OD w/o Silicide Resistor rprpo_t 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
# For pick-up
document.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.5 CL018LP 1.8V/3.3V

Table 3.4.5 CL018 Logic Low Power (LP) 1.8V/3.3V technology
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
ESD3DMY
Device SPICE name
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.8V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (1.8V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
NMOS (3.3V) nch3 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (3.3V) pch3 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0
pnp2 (Emitter area
TS
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
= 2×2 µm )
pnp5 (Emitter area
= 5×5 µm )
M
pnp10 (Emitter
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1 0
area = 10×10 µm )
C

C

VI
on 6 NO /2

3.3V NW/Psub Junction Diode NWDIO_3 1 0 1 1 0 1# 1# 0 0 0 0 0 0 0 1 0 0
A

fid 65 LO 009

TE

en 12 G

C /0

P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo 1 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0
tia 1 IES
H 1

12
lI
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0

N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0
nf

N+ Poly w/o Silicide Resistor (292 Ohm/sq) rnpo1rpo 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0
or
P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0

rnwod_m 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0
m
3T_ N+ OD w/i Silicide Resistor (W 2um) rnod_m 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0

3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0
at

3T_P+ OD w/i Silicide Resistor (W 2um)
rnodrpo_m
rpod_m
0
1
0
0
1
1
0
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
io
3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0

3T_P+ OD w/o Silicide Resistor rpodrpo_m 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0
IN
# For pick-up
C
document.
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.6 CL018LP 1.8V/5V

Table 3.4.6 CL018 Logic General Purpose (LP) 1.8V/5V technology
RPDUMMY
RPDUMMY
(drawing 1)
(drawing 1)
Device SPICE name
DIODMY
BJTDMY
RWDMY
RWDMY
DMN2V
DMP2V
NT_N
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.8V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (1.8V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0
NMOS (5V) nch_5 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
PMOS (5V) pch_5 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0
TS
2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
2×2 µm )
5×5 µm )
M
pnp10 (Emitter area

2 1 0 1 0 0 1# 1 0 0 0 0 0 0 0 0 1
= 10×10 µm )
C

C

5V P+/Nwell Junction Diode PDIO_5 1 0 1 1 0 1# 1 0 0 0 0 0 0 0 1 0
VI
on 6 NO /2
5V N+/Pwell Junction Diode NDIO_5 0 0 1 1 0 1 1# 0 0 0 0 0 0 0 1 0

5V NW/Psub Junction Diode NWDIO_5 1 0 1 1 0 1# 1# 0 0 0 0 0 0 0 1 0
A

fid 65 LO 009

TE

en 12 G

C /0

tia 1 IES
H 1

12
lI

nf

or

3T_ N+ OD w/i Silicide Resistor (W 2um)
rnwod_m
rnod_m
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
m
3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0

rnodrpo_m 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0
at
3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0

3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0
io
3T_P+ OD w/o Silicide Resistor rpodrpo_m 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 0

IN
# For pick-up
n
C
document.
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.7 CM018G/CR018G 1.8/3.3V

Table 3.4.7.1 CM018G mixed signal/RF 1.8/3.3V technology
RPDUMMY(drawing 1)
CTMDMY(131;10)
CTMDMY(131;20)
CTMDMY(131;21)
Device SPICE name
RFDUMMY
RFDUMMY
RLPPDMY
CTMDMY
VARDMY
SBDDMY
DMN2V
DMP2V
NWELL
VTM_N
VTM_P
POLY
NT_N
DNW
CTM
RPO
OD2
HRI
OD
N+
P+
TS
1.8V Medium Vt NMOS Mench 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1.8V Medium Vt PMOS Mepch 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
3.3V Medium Vt NMOS mench3 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

C
NPN2 (Emitter area = 2×2 µm2) 1 1 1 0 0 0 0 0 1 1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1.8V N+/PW/DNW NPN5 (Emitter area = 5×5 µm2) 1 1 1 0 0 0 0 0 1 1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C
vertical NPN bipolar NPN10 (Emitter area = 10×10

1 1 1 0 0 0 0 0 1 1# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VI
µm2)
on 6 NO /2
HRI P-Poly w/o silicide

rppolyhri 0 0 0 0 0 0 0 1 0 1# 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0
A
W>1um(1075 Ohm/sq)
fid 65 LO 009
3T_P- Poly HRI w/o

TE
rppolyhri_dis 0 0 0 0 0 0 0 1 0 1# 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
silicide

en 12 G
3T_N+ Poly w/i silicide

rnpo1_dis 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
C /0
(W 2um)
3T_N+ Poly w/i silicide
tia 1 IES
H 1
rnpo1w_dis 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
(W < 2um)

12
3T_P+ Poly w/i silicide

lI
rppo1_dis 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
(W 2um)
nf
3T_P+ Poly w/i silicide

rppo1w_dis 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
(W < 2um)
or
3T_N+ Poly w/o silicide rnpo1rpo_dis 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0

3T_P+ Poly w/o silicide rppo1rpo_dis 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0
m
1.8V SBD with DNW sbd_rf 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

1.8V SBD without DNW sbd_rf_nw 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
at
CM018 Base Band mimcap

MIM capacitor (1fF/um2) mimcap
io
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0
CM018 (GP2) Base Band mimcap
IN
MIM capacitor (1fF/um2) mimcap_1p0_sin 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0

MIM capacitor (1fF/um2) mimcap_1p0_sin_3t 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 0 0 0
C
MIM capacitor (2fF/um2) mimcap_2p0_sin 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0

.
MIM capacitor (2fF/um2) mimcap_2p0_sin_3t 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0

CR018 Base Band mimcap
MIM capacitor (1fF/um2) mimcap 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0
MIM capacitor (1fF/um2) mimcap_3t 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0
MIM capacitor (2fF/um2) mimcap_2p0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0
MIM capacitor (2fF/um2) mimcap_2p0_3t 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0
CR018 RF mimcap
MIM capacitor (1fF/um2) mimcap_shield 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0
MIM capacitor (1fF/um2) mimcap_wos 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0
MIM capacitor (2fF/um2) mimcap_2p0_shield 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
MIM capacitor (2fF/um2) mimcap_2p0_wos 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0
Document No.
Version
: T-018-LO-DR-001
: 2.8
For the requirement of circuit or routing under MIM capacitor, please refer to the following table with
special dummy layer coverage for MIM capacitor. Then the circuit or routing under MIM are not
allowed if the MIM components is not list in the following table.
RFDUMMY(160;50)
CTMDMY(131;50)
CTMDMY(131;10)
CTMDMY(131;20)
CTMDMY(131;21)
RFDUMMY
CTMDMY
VARDMY
SBDDMY
NWELL
VTM_N
VTM_P
POLY
Device SPICE name
NT_N
DNW
CTM
RPO
OD2
HRI
OD
N+
P+
CR018G Base Band mimcap
MIM capacitor
2 mimcap 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
(1fF/um )
TS
MIM capacitor
2 mimcap_2p0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
(2fF/um )
CR018G RF mimcap
M
MIM capacitor
2 mimcap_shield 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1
(1fF/um )
C
MIM capacitor
2 mimcap_2p0_shield 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1
(2fF/um )
C
CM018G (GP2) Base Band mimcap

VI
MIM capacitor
on 6 NO /2
2 mimcap_1p0_sin 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0
(1fF/um )
MIM capacitor
A
2 mimcap_2p0_sin 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
(2fF/um )
fid 65 LO 009
CM018G Base Band mimcap

TE
MIM capacitor
2 mimcap 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
(1fF/um )
en 12 G
C /0
Table 3.4.7.2 CM018G Inductor Device Truth Table

tia 1 IES
H 1

12
RFDUMMY
lI
ESD3DMY
DIODMY
BJTDMY
INDDMY
RWDMY
RPDMY
DMN2V
DMP2V
Device SPICE name
NT_N
Via 1
Via 2
Via 3
Via 4
Via 5
RPO
OD2
NW
CO
OD
PO
NP
M1
M2
M3
M4
M5
M6
PP
nf
or
subckt spiral_s2_std 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
subckt spiral_s3_std 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
m
subckt spiral_s2_sym 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
subckt spiral_s3_sym 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
at
Inductor subckt spiral_s2_sym_ct 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1

subckt spiral_s3_sym_ct 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1
io
subckt spiral_std_40k 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
subckt spiral_sym_40k 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1
IN
subckt spiral_sym_ct_40k 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1
C
Table 3.4.7.3 CM018G Varactor Device Truth Table

.

CTMDMY(131;10)
CTMDMY(131;20)
CTMDMY(131;21)
RFDUMMY
RFDUMMY
RLPPDMY
CTMDMY
VARDMY
SBDDMY
NWELL
VTM_N
VTM_P
Device SPICE name

POLY
NT_N
DNW
RPO
CTM
OD2
HRI
OD
N+
P+
1.8V NMOSVAR moscap_rf 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0

3.3V NMOSVAR moscap_rf33 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0
# For pick-up
document.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.4.8 CL016G 1.8V/3.3V

Table 3.4.8 CL016 Logic General Purpose (G) 1.8V/3.3V technology
ESD3DMY
DIODMY
BJTDMY
RWDMY
RPDMY
DMN2V
DMP2V
Device SPICE name
NT_N
RPO
OD2
NW
OD
PO
NP
PP
NMOS (1.8V) nch 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0
PMOS (1.8V) pch 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
NMOS (3.3V) nch3 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0
PMOS (3.3V) pch3 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0
Native NMOS (1.8V) nanch 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0
TS
Native NMOS (3.3V) nanch3 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0

2
pnp2 (Emitter area = 2×2 µm ) 1 0 1 0 0 1# 1 0 0 0 0 0 0 1 0
2
1.8V P+/NW/PSUB vertical PNP bipolar pnp5 (Emitter area = 5×5 µm ) 1 0 1 0 0 1# 1 0 0 0 0 0 0 1 0
M
2
pnp10 (Emitter area = 10×10 µm ) 1 0 1 0 0 1# 1 0 0 0 0 0 0 1 0
1.8V P+/Nwell Junction Diode PDIO 1 0 1 0 0 1# 1 0 0 0 0 0 1 0 0
C
1.8V N+/Pwell Junction Diode NDIO 0 0 1 0 0 1 1# 0 0 0 0 0 1 0 0

1.8V NW/Psub Junction Diode NWDIO 1 0 1 0 0 1# 1# 0 0 0 0 0 1 0 0
C
3.3V P+/Nwell Junction Diode PDIO_3 1 0 1 1 0 1# 1 0 0 0 0 0 1 0 0

3.3V N+/Pwell Junction Diode NDIO_3 0 0 1 1 0 1 1# 0 0 0 0 0 1 0 0
VI
on 6 NO /2
3.3V NW/Psub Junction Diode NWDIO_3 1 0 1 1 0 1# 1# 0 0 0 0 0 1 0 0

3.3V ESD Junction Diode ENDIO_3 0 0 1 0 1 1 1# 1 0 0 0 0 1 0 1
A
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0

fid 65 LO 009
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0

TE
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0
en 12 G
N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0

C /0
P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0

N-well. Under OD Resistor (440 Ohm/sq) rnwod 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0
tia 1 IES
H 1
N-well. Under STI Resistor (927 Ohm/sq) rnwsti 1 0 1# 0 0 1 0 0 0 0 1 0 0 0 0

N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0
12
lI
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0
P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0
nf
N+ Poly w/o Silicide Resistor (292 Ohm/sq) rnpo1rpo 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0

P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0
or
# For pick-up
m
document.
at
io
3.4.9 CM016G 1.8V/3.3V

IN
Table 3.4.9 CM016G mixed signal 1.8V/3.3V technology

C
Special
Design Levels
.
Layer
RFDUMMY
CTMDMY
NWELL
VTM_N
VTM_P
Device SPICE name

POLY
NT_N
DNW
CTM
RPO
OD2
HRI
OD
N+
P+
1.8V Medium Vt NMOS Mench 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0

1.8V Medium Vt PMOS Mepch 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0
3.3V Medium Vt NMOS mench3 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0
DNW/PSUB DIODE DNWPSUB 1 1 0 0 0 0 0 0 1# 1# 0 0 0 0 0
PW/DNW DIODE PWDNW 1 1 0 0 0 0 0 0 1# 1# 0 0 0 0 0
HRI P-Poly w/o silicide rppo1rpo_rf 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0
2
NPN2 (Emitter area = 2×2 µm ) 1 1 1 0 0 0 0 0 1 1# 0 0 0 0 0
1.8V N+/PW/DNW vertical NPN 2
bipolar 2
2
MIM capacitor (1.2fF/um ) mimcap 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
# For pick-up
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5 Device List & Spec

This section lists all available devices and the related specs. The numbers in the table specify the range of
allowed typical operation voltage.
3.5.1 CL018G 1.8V/3.3V
Table 3.5.1 CL018G 1.8/3.3V Device Feature
|Reverse
Device SPICE Name |Vgs| |Vds| |Vbs| |Vce| |Delta V|
bias|
NMOS (1.8V) nch 0~1.8 0~1.8 0~1.8 - - -
PMOS (1.8V) pch 0~1.8 0~1.8 0~1.8 - - -
NMOS (3.3V) nch3 0~3.3 0~3.3 0~3.3 - - -
TS
MOS
PMOS (3.3V) pch3 0~3.3 0~3.3 0~3.3 - - -
Native NMOS (1.8V) nanch 0~1.8 0~1.8 0~1.8 - - -
Native NMOS (3.3V) nanch3 0~3.3 0~3.3 0~3.3 - - -
M
2
pnp2 (Emitter area = 2×2 µm ) - - - - 0~1.8 -
2
1.8V P+/NW/PSUB vertical PNP bipolar pnp5 (Emitter area = 5×5 µm ) - - - - 0~1.8 -
C
2
BJT 2
pnp2_3 (Emitter area = 2×2 µm ) - - - - 0~3.3 -
C
2
3.3V P+/NW/PSUB vertical PNP bipolar pnp5_3 (Emitter area = 5×5 µm ) - - - - 0~3.3 -
VI
2
on 6 NO /2
1.8V P+/Nwell Junction Diode PDIO - - - 0~1.8 - -

A
1.8V N+/Pwell Junction Diode NDIO - - - 0~1.8 - -

fid 65 LO 009
1.8V NW/Psub Junction Diode NWDIO - - - 0~1.8 - -

Diode 3.3V P+/Nwell Junction Diode PDIO_3 - - - 0~3.3 - -
TE
3.3V N+/Pwell Junction Diode NDIO_3 - - - 0~3.3 - -

en 12 G
3.3V NW/Psub Junction Diode NWDIO_3 - - - 0~3.3 - -

3.3V ESD Junction Diode ENDIO_3 - - - 0~3.3 - -
C /0
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod - - - - - 0~3.3

tia 1 IES
H 1
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw - - - - - 0~3.3

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod - - - - - 0~3.3
12
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw - - - - - 0~3.3

lI
N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo - - - - - 0~3.3

P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo - - - - - 0~3.3
nf
N-well. Under OD Resistor (440 Ohm/sq) rnwod - - - - - 0~3.3

N-well. Under STI Resistor (927 Ohm/sq) rnwsti - - - - - 0~3.3
or
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 - - - - - 0~3.3

N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w - - - - - 0~3.3
m
Resistor P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 - - - - - 0~3.3

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w - - - - - 0~3.3
at
N+ Poly w/o Silicide Resistor (292 Ohm/sq) rnpo1rpo - - - - - 0~3.3

P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo - - - - - 0~3.3
io

3T_N-well. Under OD Resistor rnwod_m - - - - - 0~3.3
3T_N+ OD w/i Silicide Resistor (W 2um) rnod_m - - - - - 0~3.3
IN
3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m - - - - - 0~3.3

3T_N+ OD w/o Silicide Resistor rnodrpo_m - - - - - 0~3.3
C
3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m - - - - - 0~3.3

.
3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m - - - - - 0~3.3

3T_P+ OD w/o Silicide Resistor rpodrpo_m - - - - - 0~3.3
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.2 CL018G 1.8V/5V

Table 3.5.2 CL018G 1.8/5V Device Feature
|Reverse
bias|
NMOS (1.8V) nch 0~1.8 0~1.8 0~1.8 - - -
PMOS (1.8V) pch 0~1.8 0~1.8 0~1.8 - - -
MOS
NMOS (5V) nch_5 0~5 0~5 0~5 - - -
PMOS (5V) pch_5 0~5 0~5 0~5 - - -
2
2
BJT 1.8V P+/NW/PSUB vertical PNP bipolar pnp5 (Emitter area = 5×5 µm ) - - - - 0~1.8 -
2
TS
Diode
5V P+/Nwell Junction Diode PDIO_5 - - - 0~5 - -
5V N+/Pwell Junction Diode NDIO_5 - - - 0~5 - -
5V NW/Psub Junction Diode NWDIO_5 - - - 0~5 - -
M
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod - - - - - 0~5

N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw - - - - - 0~5
C
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod - - - - - 0~5

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw - - - - - 0~5
C
N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo - - - - - 0~5

VI
P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo - - - - - 0~5

on 6 NO /2
N-well. Under OD Resistor (440 Ohm/sq) rnwod - - - - - 0~5

N-well. Under STI Resistor (927 Ohm/sq) rnwsti - - - - - 0~5
A
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 - - - - - 0~5

fid 65 LO 009
Resistor N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w - - - - - 0~5

TE
P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 - - - - - 0~5

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w - - - - - 0~5
en 12 G
N+ Poly w/o Silicide Resistor (311 Ohm/sq) rnpo1rpo - - - - - 0~5

C /0
P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo - - - - - 0~5
tia 1 IES
3T_ N-well. Under OD Resistor rnwod_m - - - - - 0~5

H 1
3T_N+ OD w/i Silicide Resistor (W 2um) rnod_m - - - - - 0~5

12
3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m - - - - - 0~5

lI
3T_N+ OD w/o Silicide Resistor rnodrpo_m - - - - - 0~5

3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m - - - - - 0~5
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.3 CL018LV 1.5V/2.5V

Table 3.5.3 CL018LV 1.5/2.5V Device Feature
|Reverse
bias|
NMOS (1.5V) nch 0~1.5 0~1.5 0~1.5 - - -
PMOS (1.5V) pch 0~1.5 0~1.5 0~1.5 - - -
MOS NMOS (2.5V) nch2 0~2.5 0~2.5 0~2.5 - - -
PMOS (2.5V) pch2 0~2.5 0~2.5 0~2.5 - - -
2
2
2
BJT 2
2
TS
2
M

Diode
2.5V P+/Nwell Junction Diode PDIO_2 - - - 0~2.5 - -
C

C

VI

on 6 NO /2

A

fid 65 LO 009

TE

en 12 G

C /0

tia 1 IES

H 1

12
lI
3T_ N-well. Under OD Resistor rnwod_t - - - - - 0~2.5

nf
3T_ N+ OD w/i Silicide Resistor (W 2um) rn_t - - - - - 0~2.5

3T_N+ OD w/i Silicide Resistor (W < 2um) rns_t - - - - - 0~2.5
or
3T_N+ OD w/o Silicide Resistor rnrpo_t - - - - - 0~2.5

3T_P+ OD w/i Silicide Resistor (W 2um) rp_t - - - - - 0~2.5
m
3T_P+ OD w/i Silicide Resistor (W < 2um) rps_t - - - - - 0~2.5

3T_P+ OD w/o Silicide Resistor rprpo_t - - - - - 0~2.5
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.4 CL018LV 1.5V/3.3V

Table 3.5.4 CL018LV 1.5/3.3V Device Feature
|Reverse
bias|
NMOS (1.5V) nch 0~1.5 0~1.5 0~1.5 - - -
PMOS (1.5V) pch 0~1.5 0~1.5 0~1.5 - - -
NMOS (3.3V) nch3 0~3.3 0~3.3 0~3.3 - - -
MOS
PMOS (3.3V) pch3 0~3.3 0~3.3 0~3.3 - - -
2
2
2
BJT 2
TS
2
2
M

C
Diode
3.3V P+/Nwell Junction Diode PDIO_3 - - - 0~3.3 - -
C

VI

on 6 NO /2

A

fid 65 LO 009

TE

en 12 G

C /0

tia 1 IES

H 1

12
lI

nf
3T_ N-well. Under OD Resistor rnwod_t - - - - - 0~3.3

3T_ N+ OD w/i Silicide Resistor (W 2um) rn_t - - - - - 0~3.3
or
3T_N+ OD w/i Silicide Resistor (W < 2um) rns_t - - - - - 0~3.3
3T_N+ OD w/o Silicide Resistor rnrpo_t - - - - - 0~3.3

m
3T_P+ OD w/i Silicide Resistor (W 2um) rp_t - - - - - 0~3.3

3T_P+ OD w/i Silicide Resistor (W < 2um) rps_t - - - - - 0~3.3
at
3T_P+ OD w/o Silicide Resistor rprpo_t - - - - - 0~3.3

io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.5 CL018LP 1.8V/3.3V

Table 3.5.5 CL018LP 1.8/3.3V Device Feature
|Reverse
bias|
NMOS (1.8V) nch 0~1.8 0~1.8 0~1.8 - - -
PMOS (1.8V) pch 0~1.8 0~1.8 0~1.8 - - -
MOS
NMOS (3.3V) nch3 0~3.3 0~3.3 0~3.3 - - -
PMOS (3.3V) pch3 0~3.3 0~3.3 0~3.3 - - -
2
2
2
TS

M

C

C

VI
on 6 NO /2

A

fid 65 LO 009

TE

en 12 G

C /0

tia 1 IES
H 1
3T_ N-well. Under OD Resistor rnwod_m - - - - - 0~3.3

12
lI
3T_ N+ OD w/i Silicide Resistor (W 2um) rnod_m - - - - - 0~3.3

3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m - - - - - 0~3.3
nf
3T_N+ OD w/o Silicide Resistor rnodrpo_m - - - - - 0~3.3

3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m - - - - - 0~3.3
or
3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m - - - - - 0~3.3

3T_P+ OD w/o Silicide Resistor rpodrpo_m - - - - - 0~3.3
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.6 CL018LP 1.8V/5V

Table 3.5.6 CL018LP 1.8/5V Device Feature
|Reverse
bias|
NMOS (1.8V) nch 0~1.8 0~1.8 0~1.8 - - -
PMOS (1.8V) pch 0~1.8 0~1.8 0~1.8 - - -
MOS
NMOS (5V) nch_5 0~5 0~5 0~5 - - -
PMOS (5V) pch_5 0~5 0~5 0~5 - - -
2
2
2
TS
Diode
5V P+/Nwell Junction Diode PDIO_5 - - - 0~5 - -
5V N+/Pwell Junction Diode NDIO_5 - - - 0~5 - -
5V NW/Psub Junction Diode NWDIO_5 - - - 0~5 - -
M
N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnod - - - - - 0~5

N+ OD w/i Silicide Resistor (6.82 Ohm/sq) rnodw - - - - - 0~5
C
P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpod - - - - - 0~5

P+ OD w/i Silicide Resistor (7.76 Ohm/sq) rpodw - - - - - 0~5
C
N+ OD w/o Silicide Resistor (59 Ohm/sq) rnodrpo - - - - - 0~5

VI
P+ OD w/o Silicide Resistor (133 Ohm/sq) rpodrpo - - - - - 0~5

on 6 NO /2
N-well. Under OD Resistor (410 Ohm/sq) rnwod - - - - - 0~5

N-well. Under STI Resistor (927 Ohm/sq) rnwsti - - - - - 0~5
A
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1 - - - - - 0~5

fid 65 LO 009
N+ Poly w/i Silicide Resistor (7.89 Ohm/sq) rnpo1w - - - - - 0~5

TE
Resistor P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 - - - - - 0~5

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1w - - - - - 0~5
en 12 G
N+ Poly w/o Silicide Resistor (311 Ohm/sq) rnpo1rpo - - - - - 0~5

C /0
P+ Poly w/o Silicide Resistor (311 Ohm/sq) rppo1rpo - - - - - 0~5
tia 1 IES
H 1
3T_ N-well. Under OD Resistor rnwod_m - - - - - 0~5

3T_ N+ OD w/i Silicide Resistor (W 2um) rnod_m - - - - - 0~5
12
3T_N+ OD w/i Silicide Resistor (W < 2um) rnodw_m - - - - - 0~5

lI
3T_N+ OD w/o Silicide Resistor rnodrpo_m - - - - - 0~5

3T_P+ OD w/i Silicide Resistor (W 2um) rpod_m - - - - - 0~5
nf
3T_P+ OD w/i Silicide Resistor (W < 2um) rpodw_m - - - - - 0~5

3T_P+ OD w/o Silicide Resistor rpodrpo_m - - - - - 0~5
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.7 CMG018/CR018G 1.8/3.3V

Table 3.5.7 CMG018/CR018G 1.8/3.3V Device Feature
1.8V Medium Vt NMOS Mench 0~1.8 0~1.8 0~1.8 - -
1.8V Medium Vt PMOS Mepch 0~1.8 0~1.8 0~1.8 - -
MOS 3.3V Medium Vt NMOS mench3 0~3.3 0~3.3 0~3.3 - -
1.8V SBD with DNW sbd_rf 0~1.8 0~1.8 0~1.8 - -
1.8V SBD without DNW sbd_rf_nw 0~1.8 0~1.8 0~1.8 - -
1.8V NMOSVAR moscap_rf 0~1.8
Varactor
3.3V NMOSVAR moscap_rf33 0~3.3
2
NPN2 (Emitter area = 2×2 µm ) - - - 0~1.8 -
2
BJT 1.8V N+/PW/DNW vertical NPN bipolar NPN5 (Emitter area = 5×5 µm ) - - - 0~1.8 -
2
NPN10 (Emitter area = 10×10 µm ) - - - 0~1.8 -
TS
HRI P-Poly w/o silicide W>1um (1075 Ohm/sq) rppolyhri - - - - 0~3.3
3T_P- Poly HRI w/o silicide rppolyhri_dis - - - - 0~3.3

3T_N+ Poly w/i silicide (W 2um) rnpo1_dis 0~3.3
M
3T_N+ Poly w/i silicide (W < 2um) rnpo1w_dis 0~3.3

Resistor
3T_P+ Poly w/i silicide (W 2um) rppo1_dis 0~3.3
C
3T_P+ Poly w/i silicide (W < 2um) rppo1w_dis 0~3.3

3T_N+ Poly w/o silicide rnpo1rpo_dis 0~3.3
C
3T_P+ Poly w/o silicide rppo1rpo_dis 0~3.3

2 2
VI
Capacitor MIM capacitor (1fF/um & 2fF/um ) mimcap - - - - 0~3.3

on 6 NO /2
Schottky barrier Schottky barrier diode with DNW sbd_rf 0~3.3

diodes
A
Schottky barrier diode with NW sbd_rf_nw 0~3.3

Standard model with space=2um subckt spiral_s2_std 0~3.3
fid 65 LO 009
Standard model with space=3um subckt spiral_s3_std 0~3.3

TE
Inductor for 20K Symmetric model with space=2um subckt spiral_s2_sym 0~3.3
en 12 G
UTM Symmetric model with space=3um subckt spiral_s3_sym 0~3.3

C /0
Symmetric model(CT) with space=2um subckt spiral_s2_sym_ct 0~3.3

tia 1 IES
Symmetric model(CT) with space=3um subckt spiral_s3_sym_ct 0~3.3

H 1
Standard model subckt spiral_std_40k 0~3.3

Inductor for 40K
12
Symmetric model subckt spiral_sym_40k 0~3.3

lI
UTM
Symmetric model(CT) subckt spiral_sym_ct_40k 0~3.3
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
3.5.8 CL016G 1.8V/3.3V

Table 3.5.8 CL016G 1.8/3.3V Device Feature
|Reverse
bias|
NMOS (1.8V) nch 0~1.8 0~1.8 0~1.8 - - -
PMOS (1.8V) pch 0~1.8 0~1.8 0~1.8 - - -
NMOS (3.3V) nch3 0~3.3 0~3.3 0~3.3 - - -
MOS
PMOS (3.3V) pch3 0~3.3 0~3.3 0~3.3 - - -
2
2
2
TS

M

C

C

VI
on 6 NO /2

A

fid 65 LO 009

TE

Resistor
en 12 G

C /0

P+ Poly w/i Silicide Resistor (7.9 Ohm/sq) rppo1 - - - - - 0~3.3
tia 1 IES
H 1

12
lI

nf
3.5.9 CM016G 1.8V/3.3V

or
Table 3.5.9 CM016G 1.8/3.3V Device Feature

m
|Reverse
bias|
at
1.8V Medium Vt NMOS Mench 0~1.8 0~1.8 0~1.8 - - -

MOS 1.8V Medium Vt PMOS Mepch 0~1.8 0~1.8 0~1.8 - - -
io
3.3V Medium Vt NMOS mench3 0~3.3 0~3.3 0~3.3 - - -

DNW/PSUB DIODE DNWPSUB - - - 0~1.8 - -
IN
Diode
n
PW/DNW DIODE PWDNW - - - 0~1.8 - -

2
NPN2 (Emitter area = 2×2 µm ) - - - - 0~1.8 -
C
2
BJT 1.8V N+/PW/DNW vertical NPN bipolar NPN5 (Emitter area = 5×5 µm ) - - - - 0~1.8 -
2
NPN10 (Emitter area = 10×10 µm ) - - - - 0~1.8 -
.
Resistor HRI P-Poly w/o silicide rppolyhri_rf - - - - - 0~3.3

Capacitor MIM capacitor (1.2fF/um2) mimcap - - - - - 0~3.3
Document No.
Version
: T-018-LO-DR-001
: 2.8
4. Layout Rules And Recommendations

This chapter provides the following general layout information:
4.1 Layout Rule Conventions
4.2 Special Geometries Used in Physical Design Rules
4.3 Definition of Layout Geometrical Terminology
4.4 Minimum Pitches
4.5 Logic Layout Rules and Guidelines
4.6 Mixed Signal Layout Rules and Guidelines
4.1 Layout Rule Convention

TS
Layout rules follow these conventions:

M
• Unless otherwise specified, all rules are of minimum dimension.

C
• The basic unit of measure is um; the basic area is um2.

• Process, product and reliability yields are expected to be improved when designs are relaxed from
C
minimum dimensions. Minimum dimensions showed only to be used to shrink the chip size or to improve
VI
on 6 NO /2
the circuit performance.

A
• Design rules requiring exact dimensions (“=” in the rule tables) are not to be relaxed.
fid 65 LO 009
• A registered symbol “U” is marked after the rule number as the rule cannot be checked by DRC.
TE
• Recommendations are designated by a registered symbol “®” after the rule number.
en 12 G
C /0
• Guidelines are designed by registered symbol “g” after the rule number.
tia 1 IES
Recommendation is used to improve device performance based on existing rule (better to have) and
H 1
•
guideline is just a reference (nice to have) without related rule.
12
lI
• Bracket usage is the rules should be noted carefully:

n Parentheses ( ) are used for explanations.
nf
n Square brackets [ ] are used for certain conditions.

or
n Curved brackets { } are used to indicate that an operation is performed.

m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.2 Special Geometries Used in Physical Design

Rules
The following definitions are used in the physical design rules:
4.2.1 Derived Geometries
Term Definition
ACTIVE N+ ACTIVE OR P+ ACTIVE
ALLOD OD OR DOD
TS
Butted_STRAP STRAP TOUCH ACTIVE

FIELD NOT OD
FIELD PO PO NOT OD
M
GATE PO AND OD
C
N+ ACTIVE (NP AND OD) NOT NW

N+OD NP AND OD
C
NW STRAP (NP AND OD) AND NW

VI
on 6 NO /2
NW2V NW NOT OD2

A
NW3V/NW5V NW AND OD2

fid 65 LO 009
NWROD (NW INTERACT RWDMY) INTERACT RPO

TE
NWRSTI (NW INTERACT RWDMY) NOT INTERACT RPO

en 12 G
PW NOT NW
C /0
OD2 OD_25, OD_33, OD_50

tia 1 IES
H 1
P+ ACTIVE (PP AND OD) AND NW

P+OD PP AND OD
12
lI
PW STRAP (PP AND OD) NOT NW

nf
STRAP NW STRAP OR PW STRAP

Dummy CTM CTM NOT Interact VIAn
or
m
4.2.2 Special Definition

at
Term Definition
io
NW N-WELL
IN
RW PW inside DNW
n
MOS Transistor structure consisting of a source, a drain, and a gate.

C
NMOS N type MOS

.
PMOS P type MOS

Mtop The last metal layer (either Mn or UTM)
Mtop-1 1st metal layer below Mtop, that is, the last Mx layer
VIAtop-1 1st VIA hole below VIAn, that is, the last VIAx layer
DOD Dummy OD
DPO Dummy PO
DMx Dummy Metal
Chip edge “Chip” doesn’t include seal ring and assembly isolation
Assembly isolation The region between the seal ring and chip edge
10um region with ring type CB from Gds window edge.
Sealring region If you have sealring inside Gds, DRC will use (CB ring in (CHIP NOT (CHIP
SIZING -10))) to check 10um sealring region
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.3 Definition of Layout Geometrical Terminology

Width: Distance of interior-facing edge for a single layer (W)

TS
Space: Distance of Exterior-facing edge for one or two layers (S)

S
M
S S
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
Clearance:
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
Extension: Distance of inside edge to outside edge (EX)

at
io
IN
n
C
.
Enclosure: Distance of inside edge to outside edge (Fully inside) (EN)
Document No.
Version
: T-018-LO-DR-001
: 2.8
Overlap: Distance of interior-facing edge for two layers (O)
Interact
TS
M
C
C
Cut
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
Inside
lI
nf
or
m
at
io
Outside
IN
n
C
.
Area (A):
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.4 Minimum Pitches

Layer Unit: um
OD transistor pitch 0.500 (W/S=0.22/0.28)
OD interconnect pitch 0.500 (W/S=0.22/0.28)
PO transistor pitch 0.43/0.555 (W/S=0.18/0.25, 0.18/0.375)
PO interconnect pitch 0.430 (W/S=0.18/0.25)
M1 pitch 0.460 (W/S=0.23/0.23)
TS
M2 pitch 0.560 (W/S=0.28/0.28)

M3 pitch 0.560 (W/S=0.28/0.28)
M
M4 pitch 0.560 (W/S=0.28/0.28)

C
M5 pitch 0.560 (W/S=0.28/0.28)

C
M6 pitch 0.900 (W/S=0.44/0.46)

VI
on 6 NO /2
Min. length of a transistor 0.180

A
Min. width of a transistor 0.220

fid 65 LO 009
PO interconnect width 0.180

TE
OD interconnect width 0.220

en 12 G
C /0
CO width 0.220
tia 1 IES
H 1
VIA1 width 0.260

VIA2 width 0.260
12
lI
VIA3 width 0.260

nf
VIA4 width 0.260

or
VIA5 width 0.360

N+/P+ spacing 0.860
m
DNW Pitch 8.00 (W/S= 3/5)

at
CTM Pitch 5.20 (W/S= 4/1.2)

io
20 KÅ UTM Pitch 3.00 (W/S= 1.5/1.5)

IN
40 KÅ UTM Pitch 5.10 (W/S= 2.6/2.5)

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5 Logic Layout Rules and Guidelines

4.5.1 N-Well (NW) Layout Rules (Mask ID: 192)
Layout
Rule No. Description Label
Rule
NW.W.1 Minimum dimension of a NW region A 0.860
NW.W.2
Minimum dimension of a hot NW region A1 2.100
TS
Please refer to NW resistor layout rule in the next page for detail layout rule
NW.S.1 Minimum space between two NW regions with different potential (*) B 1.400
M
NW.S.2
Minimum space between two NW regions with the same potential
C 0.600
C
Merge if space is less than 0.6um.

(Below guideline is referred from the ESD chapter)
C
VI
It is strictly prohitibied to butting or inserted Substrate/Well pick-up’s for ESD

on 6 NO /2
ESD.8g
N/PMOS.
A
* DRC implementation is on different net.

fid 65 LO 009
TE
N
NW
en 12 G
W
C /0
A
tia 1 IES
B
H 1
C A
12
lI
nf
A1
or
m
at
io
IN
NW PW NW
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.2 NW Resistor Layout Rules

For the SPICE simulation accuracy concern, it is strongly recommended that the NW resistor width ≥ 2.1 um
and the resistor square number Nsq ≥ 5. Please use 1.4 um as the minimum NW space to prevent from the
resistance decrease of NW resistor due to mergence of different regions.
NW NW
1.4 um
TS
M
C
NW Resistor
C
VI
on 6 NO /2
1.4 um
A
fid 65 LO 009
TE
en 12 G
Layout
C /0

Rule
tia 1 IES

H 1
NWR.E.1 Minimum extension of OD to NW A 1.000

12
lI
NWR.E.2 Minimum extension of salicide NW to CO B 0.300

nf
NWR.C.1 Minimum clearance from RPO to related NW C 0.300

or
NWR.C.2 Minimum clearance from RPO to related OD D 0.220

m
NWR.C.3 Minimum clearance from RPO to CO in RPO hole E 0.300

NWR.O.1 Minimum overlap of RPO to NP F 0.400
at
NWR.E.3 Minimum extension of a NP region beyond a OD region G 0.180

io
IN
NWR.R.1 P+/N+ implant inside NW resistance region is not allowed

n
NWR.R.3 Only one NW inside NWROD is allowed in one OD

C
.
NWR.R.4 Only two NPs in NWROD is allowed in one OD

NWR.R.5 Only two RPO holes(Sailcide) in NWROD are allowed in same OD
For U-shape or S-shape NWROD, both OD and NW must be U-shape or S-
shape and the OD edge must be parallel to the NW edge. DRC can only flag
NWR.R.6
the pattern without OD space while 2 edges of NW [NW space or notch <= 5
um] parallel length > 0 um
Document No.
Version
: T-018-LO-DR-001
: 2.8
Add RPO to prevent NW resistance region from forming salicide.

Dummy layer (RWDMY) is needed to for DRC, to avoid LDD and N+/P+ implanting into NW resistance region.
NWROD
RPO
OD
NP
F A F
TS
F F
M
F F C
C
B A
C
E NW
VI
on 6 NO /2
D F F D
A
fid 65 LO 009
TE
D
en 12 G
RWDMY
C /0
tia 1 IES
H 1
Figure 4.5.1A NW resistor within OD

12
lI
NWR.R.3
NWROD.R.3 NWR.R.4
NWROD.R.4 NWR.R.5
NWROD.R.5
nf
NP NP NP R PO
or
NW NW NW
m
OD
NW DM Y
at
NW NW
OD OD
io
N WD M Y N WD M Y
IN
n
C
NWR.R.6
NWRO D.R.6 NWR.R.6
NWROD.R.6 NWR.R.6
NWROD.R.6
.
OD
OD OD
NW NW
NW
NW DM Y N WD M Y
N WD MY The layout is uncheckable
Document No.
Version
: T-018-LO-DR-001
: 2.8
NWRSTI
NP NP
G G
G G G G
TS
M
NW
C
OD OD
C
G G
VI
on 6 NO /2
RWDMY
A
fid 65 LO 009
Figure 4.5.1B NW resistor under STI.

TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.3 Native Device (NT_N) Layout Rules

This layer is used for mask making rather than process requirements. If you use native NMOS devices in a
circuit design, please use this drawn layer with NW to generate PW.
Warning: Native device is not allowed in CL018G 1.8V/5.0V, CL018LP 1.8V/5.0V and CL018LP
1.8V/3.3V process.
Layout
Rule
NT_N – Implant Definition to block PW, channel_N and VT_N
Layer:
implant for NMOS native device.
TS
NT_N.I.1 NT_N interact DNW is not allowed. (Butted is allowed)

NT_N.I.2 Only one OD region is allowed to be put in an NT_N region
M
NT_N.I.3 A P+ Poly gate is not allowed to be put in an NT_N region

C
A bent Poly region is not allowed to be put in an NT_N region

NT_N.I.4
Exclude poly not interact {CO OR OD}
C
For CL018G 1.8V/3.3V & CL018LV 1.5V/2.5V, minimum

VI
0.740
on 6 NO /2
NT_N.W.1 dimension of a NT_N region. A

A
For CL018LV 1.5V/3.3V, minimum dimension of a NT_N region. 0.860

fid 65 LO 009
For CL018LV 1.5/2.5V & 1.5/3.3V, minimum Poly gate

TE
0.370
dimension of a 1.5V blocked NT_N device

en 12 G
NT_N.W.2 Minimum Poly gate dimension of a 1.8V blocked NT_N device B 0.500
C /0
For CL018G, CL018LV 1.5/2.5V & 1.5/3.3V, minimum Poly gate

1.200
tia 1 IES
H 1
dimension of a {2.5V or 3.3V} blocked NT_N device

NT_N.S.1 Minimum space between two NT_N regions. C 0.860
12

lI
Maximum and Minimum extension from a NT_N region beyond

NT_N.E.1 D 0.260
an NP OD region.
nf
NT_N.E.2
For CL018LV 1.5/2.5V & 1.5/3.3V, minimum extension from OD2
H 0.860
or
edge to an {2.5V or 3.3V} NT_N region inside OD2

NT_N.C.1 Minimum clearance from a NT_N region to nominal OD region. E 0.520

m
NT_N.C.2 Minimum clearance from a NT_N region to an N-well edge. F 1.660

at
For CL018LV 1.5/2.5V & 1.5/3.3V, minimum clearance from 1.5V

NT_N.C.3 I 0.860
NT_N region to OD2 edge
io
NT_N.PO.1
Minimum overlap of a PO region extended into field oxide
G 0.350
IN
(endcap)
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
N
NTT__N
N
NT_N
OD Nominal
A
Device OD
B
E
C
Poly
TS
NT_N
M
OD F
D
C
C
PW NW
VI
on 6 NO /2
G
A
fid 65 LO 009
TE
OD2
en 12 G
C /0
H
tia 1 IES
H 1
12
lI
nf
NT_N NT_N
or
I
m
at
io
O
Onnllyy ffoorr C
CLL001188LLV
V 11..55//22..55V
V&& 11..55//33..33V
V
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.4 Thin Oxide (OD) Layout Rules (Mask ID: 120)

Layout
Rule
Minimum width of an OD region to define the width of
OD.W.1 A 0.220
NMOS/PMOS
OD.W.2 Minimum width of an OD region for interconnect (N+/or P+) B 0.220
OD.S.1
Minimum space between two OD regions which can be either N+
to N+, P+ to P+ or N+ to P+
C 0.280
Minimum clearance from NW edge to a N+OD region which is

TS
OD.C.1 D 0.120
inside a NW

M
OD.C.2 E 0.430
outside a cold NW
C

For CL018G/LP 1.8/5V process, minimum clearance from NW
OD.C.2.1 edge to a N+OD region which is outside a cold NW and interacts K 0.600
C
with OD2
VI

on 6 NO /2

OD.C.3 E’ 0.430
outside a hot NW
A
fid 65 LO 009

TE
OD.C.3.1 edge to a N+OD region which is outside a hot NW and interacts K’ 0.600
en 12 G
with OD2

C /0
Minimum clearance from NW edge to a P+OD region which is

OD.C.4 F 0.430
tia 1 IES
inside a NW
H 1

12
lI
OD.C.4.1 edge to a P+OD region which is inside a NW and interacts with L 0.800
OD2
nf
OD.C.5
Minimum clearance from NW edge to a P+OD region (for PW pick
G 0.120
or
up) which is outside a NW

Minimum clearance from poly edge to the edge of butted diffusion

m
OD.C.6 H 0.320
OD region

at
OD.S.2 Minimum space of N+ OD to P+ OD for butted diffusion. I 0.000

a) Width (J) of at least one segment of the consecutive N+/P+

io
butted diffusion OD 0.42um.

IN
OD.W.3 J, T
n

b) When J < 0.42um, length (T) of OD (source) interact with
N+/P+ butted diffusion OD 0.8um.
C
OD.A.1 Minimum area of a stand-along OD region 0.202

.
If N-well and P-well pick-ups are put head-to-head each other

across well boundary, spacing between N-pickup OD and P-
Note:
pickup OD will be 0.36 um to meet implant layout rules (please
refer to correct and incorrect layouts in next page)
Document No.
Version
: T-018-LO-DR-001
: 2.8
O
ODD
B B A
OD
C P+ F E(E`) N+ C N+
P+
PO PO
PO
H P+ G
TS
N+
N+ N+ D P+
M
J P+
J
C
C
0.36um if n/p taps

VI
on 6 NO /2
I head to head
I
A
fid 65 LO 009
OD2 OD2
TE
L K(K`)
en 12 G
P+ OD N+ OD
C /0
tia 1 IES
H 1
N-Well P-Well
12
lI
nf
Butted diffusion region implant

or
OD
Butted diffusion region
m
at
PO
io
J < 0.42um
0.8um
IN
J T
C
PO
PO
.
Butted diffusion region
OD
Document No.
Version
: T-018-LO-DR-001
: 2.8
N+OD
0.43
OD 0.28
0.43 0.43
P+OD N+OD
Correct
0.44um(0.26+0.18) 0.28
G
N-Well D P+OD
P-Well
TS
N+OD
0.36um
M
C
C
VI
on 6 NO /2
Incorrect
A
fid 65 LO 009
OD
TE
P+OD 0.43 0.43 N+OD

en 12 G
C /0
tia 1 IES
H 1
0.28
12
lI
G
nf
D
N-Well N+OD
P-Well
P+OD
or
m
0.28um
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.5 Thick Oxide (OD2) Layout Rules (Mask ID: 132)

Define thick oxide area of 2.5V, 3.3V, or 5.0V I/O transistors.
Rule Layout
Description Label
No. Rule
OD2.E.1 Minimum extension of an OD2 region beyond an {active OD OR Gate} region A 0.320
For two well process (CL018G 1.8V/3.3V), minimum space between two
0.450
OD2 regions. Merge if the space is less than 0.45um.
For four well process (CL018LV 1.5V/3.3V , CL018LV 1.5V/2.5V, CL018LP B
1.8V/3.3V, CL018G/LP 1.8V/5.0V), minimum space between two OD2

OD2.S.1 0.860
TS
regions.
Merge if the space is less than 0.86um.
M
Larger OD2 space is needed for four well process to generate I/O N/P well masks by
logic operation.

C
OD2.C.1 Minimum clearance between OD region and an OD2 region C 0.320
0.400
C
Minimum clearance between OD2 region and {1.5V or 1.8V} transistor gate
OD2.C.2 D
VI
poly
on 6 NO /2
0.400
Minimum extension of OD2 region beyond {2.5V or 3.3V or 5V} transistor
A
fid 65 LO 009
OD2.E.2 gate poly in the source/drain OD direction (OD2 cut poly GATE is not E
TE
allowed. Please refer to the attached figure in this section.)
0.860
For four well process (CL018LV 1.5V/3.3V, CL018LV 1.5V/2.5V, CL018LP
en 12 G
OD2.E.4 1.8V/3.3V, CL018G/LP 1.8V/5.0V), minimum extension of an OD2 region F

C /0
beyond an NW region. Align if space is less than 0.86um

tia 1 IES
H 1
0.860
12
OD2.C.4 1.8V/3.3V, CL018G/LP 1.8V/5.0V), minimum clearance between an OD2 G

lI
region and an NW region. Align if space is less than 0.86um

0.860
nf

OD2.O.1 H
1.8V/3.3V, CL018G/LP 1.8V/5.0V), minimum overlap between OD2 and NW
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
O
ODD22
OD2
A C
OD
OD
TS
M
C
B
OD2
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
OD OD
H 1
12
PO PO
lI
nf
or
OD2 PO
m
OD
at
2.5V OD 1.5V
or or
io
3.3V E 1.8V
IN
or PO
PO
5.0V D PO
C
PO
.
OD2
OD2 cut gate is NOT allowed.
Document No.
Version
: T-018-LO-DR-001
: 2.8
GF
NW
OD2
NW
OD2
G F
F
G
GF
TS
G
M
NW
C
NW G
C
H OD2 F
G G
VI
H
on 6 NO /2
F
G
A
fid 65 LO 009
TE
G
en 12 G
OD2
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.6 Poly (PO) Layout Rules (Mask ID: 130)

All the un-doped poly region will be converted into P+ or N+ doped poly by logic operation at TSMC (please
refer to T-018-LO-MB-001.) If un-doped poly is to be reserved intentionally in your circuit design, please use a
dummy layer to define this region and contact our product engineer.
Layout
Rule
Minimum width of a PO region for the channel length of {1.5V or
1.8V} PMOS
A 0.180
PO.W.1 Minimum width of a PO region for the channel length of 2.5V PMOS 0.260

TS
Minimum width of a PO region for the channel length of 3.3V PMOS A1 0.300
Minimum width of a PO region for the channel length of 5.0 V PMOS 0.500

M
Minimum width of a PO region for the channel length of {1.5V or

B 0.180
1.8V} NMOS
C
PO.W.2 Minimum width of a PO region for the channel length of 2.5V NMOS 0.260
Minimum width of a PO region for the channel length of 3.3V NMOS B1 0.350
C
VI
Minimum width of a PO region for the channel length of 5V NMOS 0.60

on 6 NO /2
PO.W.3 Minimum width of a PO region for interconnect C 0.180

A
Minimum space between two PO regions on OD area with contacts

fid 65 LO 009
PO.S.1 D 0.375
(including butting contact) in the spacing
TE
Minimum space between two PO regions on OD area without

en 12 G
PO.S.2 D1 0.250
contacts (including butting contact) in the spacing.

C /0
PO.S.3 Minimum space between two PO regions on field oxide area. D2 0.250

tia 1 IES
H 1
PO.C.1 Minimum clearance from an OD region to an PO on field oxide. E 0.100

12
PO.C.2 Minimum clearance from an OD region to a related PO inside OD F 0.320

lI
PO.O.1 Minimum overlap of a PO region extended into field oxide (endcap) G 0.220
nf
(A) Below poly bent layouts are not allowed

or

PO.R.1 (B) Minimum channel length of {1.5V or 1.8V} NMOS and PMOS 45°
poly bent layout L 0.21 um.

m
Maximum length of salicide poly on STI between two contacts or

PO.R.2
between one contact and poly line end when poly width 0.24um H 50
at
Minimum poly density across full chip.

io
1.It is recommended to use TSMC’s auto-fill utilities (Document No.:

IN
T-018-LO-DR-001-X2) to add dummy PO if the poly density is less

n
PO.R.3 14%
than 14%.
C
2.Please be aware of the coupling capacitor effect while dummy PO

are added.
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
PO PO
PO must enter OD
region orthogonally
Not Allowed
OD
TS
M
C
C
VI
on 6 NO /2
L L
A
fid 65 LO 009
L OD
TE
en 12 G
L
C /0
tia 1 IES
H 1
Poly Poly
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
P
POOLLY
Y
A/B
PO
PO G
N+/P+ D1
N+/P+ OD
F
OD
OD Poly
E H M1
OD
PO
TS
D2
D2
M
C PO
C
PO
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
D
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.7 Poly Resistor and OD Resistor Guidelines and

Rule
RULE NO. Description Label Rule
The total resistance of the resistor is calculated based on the equation and
RES.1®U
data listed in SPICE model document (T-018-LO-SP-001.)
Recommended for the SPICE simulation accuracy:

(1) For poly resistor, it is strongly recommended that the poly resistor width
1.0 um and the resistor square number Nsq 5. For OD resistor, it is

TS
strongly recommended that the resistor width 2.0 um and the resistor
RES.2® square number Nsq 5. (DRC will check the width and length 1um
M
and 5um for poly resistor & 2um and 10um for OD resistor, respectively.
Nsq is un-checkable)
C
(2) For RF P+ poly resistor, please refer to the rule T-018-MM-SP-001 for
the model accuracy.
C
Extension of DMN2V/DMP2V to Poly resistor on field oxide should be

VI
on 6 NO /2
0.22um. (Figure 4.5.7.2 & 4.5.7.3)

A
fid 65 LO 009

The sheet resistance in SPICE model of non-salicided N+/P+ PO/OD
TE
RES.3® resistors is resulted from N2V/NP and P2V/PP combinations, respectively. D 0.22
To obtain precise resistance, dummy layers (DMN2V & DMP2V) are
en 12 G
required. If N2V/P2V/ N3V/P3V/N5V/P5V are derived from logical

C /0
operation, please ensure correct implants in case the resistor traverses

tia 1 IES
H 1
NW/PW, 1.8V/3.3V, 1.8/5V, 1.5V/3.3V or 1.5V/2.5V.

Recommend: the maximum and minimum clearance from a RPO to a

12
lI
RES.4® A 0.22
contact on the poly resistor and OD resistor

nf
Recommend: the minimum clearance from OD/Poly resistor to un-related

RES.5® B 0.26
implant regions

or
Recommend: the minimum clearance from an un-related RPO to the

RES.6® C 0.3
OD/Poly resistor
m
Recommend: Contact pickup of the OD/Poly resistor should be in a single

RES.7®
column.
at
Recommend: Do not to use dog bone at the end of the poly resistor and
RES.8®U
io
OD resistor for contact pickup.

IN
RES.9 DMN2V and DMP2V overlapped is not allowed.

n
RES.10 Minimum clearance from DMN2V to GATE (overalp is not allowed) E 0.35

C
RES.11 Minimum clearance from DMP2V to GATE (overalp is not allowed) F 0.35
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
CO CO
Poly or OD resistor
Dog-bond at the end of
resistor for contact pickup
is NOT recommended!!
TS
Figure 4.5.7.1
M
RES.9 RES.10,RES.11
C
POLY
C
VI
on 6 NO /2
F DMP2V
DMP2V
A
OD
fid 65 LO 009
TE
DMN2V E DMN2V
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
P
P++ ppoollyy // O
ODD rreessiissttoorr w
wiiddtthh w
wiitthh R
RPPO
O
DMP2V layer
D= 0.22um RPO
0.10um 0.18um P+
CO CO
Poly/ OD Resistor

0.10um 0.22um
E 1.0um 0.22um
Width 0.25um
TS
Contacts to pickup
0.26um 0.3um
M
Length Poly/ OD resistor

B C should be be single
C
column array!!
Un-related implant regions Un-related RPO regions

C
VI
on 6 NO /2
Figure 4.5.7.2
A
fid 65 LO 009
N
N++ ppoollyy // O
ODD rreessiissttoorr w
wiitthh R
RPPO
TE
O
en 12 G
DMN2V layer
C /0
tia 1 IES
H 1
D= 0.22um RPO
0.10um 0.18um N+
12
lI
nf
CO CO
Poly/ OD Resistor
0.10um 0.22um

or
E 1.0um 0.22um
Width
m
0.25um
at
io
Contacts to pickup
IN
0.26um 0.3um
Length Poly/ OD resistor
n
B C should be be single
C
column array!!
.
Figure 4.5.7.3
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.8 N+ S/D (NP) Layout Rules (Mask ID: 198)

Layout
Rule
NP.W.1 Minimum width of a NP region A 0.440
Minimum space between two NP regions. Merge if the space is
NP.S.1 B 0.440
less than 0.440 um
Minimum clearance from a NP region to a P+ active OD region
NP.C.1 C 0.260
(inside N-Well)
Minimum clearance from a NP region to a non-butted edge of P-
TS
NP.C.2 Well pick-up P+OD region if the distance between P+OD and N- C1 0.100
Well 0.43um.
M
Minimum clearance from a NP region to a non-butted edge of P-

NP.C.3 Well pick-up P+OD region if the distance between P+OD and N- C2 0.180
C
Well < 0.43um.

Minimum clearance from a NP edge to a P-Channel PO gate. This
C
rule must extend out of gate in the direction of PO by 0.35um. The

VI
NP.C.4 D 0.320
on 6 NO /2
equivalent P-Channel area must not be covered with NP: ((((PO

A
AND OD) SIZING 0.03) AND PO) SIZING 0.32)

fid 65 LO 009
Minimum clearance from a NP edge to a N-Channel PO gate. This

TE

NP.C.5 E 0.320
equivalent N-Channel area must be covered with NP: ((((PO AND
en 12 G
OD) SIZING 0.03) AND PO) SIZING 0.32)

C /0
tia 1 IES
NP.O.1 Minimum overlap from a NP edge to an OD region F 0.230

H 1
NP.E.1 Minimum extension of a NP region beyond a N+ active OD region G 0.180

12
lI
Minimum extension of a NP region beyond a N-Well pick-up N+OD

NP.E.3 H 0.020
region if the distance between N+OD and P-Well 0.43um.
nf
Minimum extension of a NP region beyond a N-Well pick-up N+OD

or
region if the distance between N+OD and P-Well < 0.43 um.
To follow this rule and NP.C.1 simultaneously, N+ tap OD to P+
m
NP.E.4 H1 0.180
active OD minimum spacing must increase up to 0.44um.
at
To follow this rule and NP.C.3 simultaneously, N+ tap OD to P+

tap OD minimum spacing must increase up to 0.36 um.
io
NP.C.6
Clearance from a NP region to the butted edge of a butted
I ! 0.000
IN
diffusion P+ OD (inside P-Well)

n
Minimum extension of a NP region along the edge of a butted

C
NP.E.5 H2 0.000
diffusion N+OD/P+OD
.
NP.A.1 Minimum area of NP region 0.3844

Minimum extension of NP region beyond a PO as a resistor. PRO
NP.E.6 L 0.180
PO without NP or PP implant is not allowed.
NP.R.1 NP overlapped with PP is not allowed
It is prohibited that NP is generated by reverse tone of PP, since
NP.R.2
this operation might violate NP.C.1 and NP.C.2
OD must be fully covered by {NP OR PP} except:
a) OD without interacting {CO OR PO}
NP.R.3
b) NW resistor
c) SBDDMY region
Document No.
Version
: T-018-LO-DR-001
: 2.8
N
NPP
0.43
N+ OD
H1
H
NP
H1
H NW
H
N+ OD
TS
NP 0.43 NP
H
0.43
M
N+
C
G
F
OD
A
C
VI
on 6 NO /2
B NP
0.35
A
fid 65 LO 009
C1
TE
P+ OD
en 12 G
E
N+ OD
C /0
P+
tia 1 IES
H 1
OD I
PP
12
0.35 C2
lI
0.43
PW
nf
POLY C2 >0.36
or
NW H H1
m
N+ NP H
at
OD
0.35 D N+ OD
io
NP
IN
H2 NP
n
P+OD C
L
C
N+OD
H
D
.
0.35 NP
POLY
Poly Resistor
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.9 P+ S/D (PP) Layout Rules (Mask ID: 197)

Layout
Rule
PP.W.1 Minimum width of a PP region A 0.440
Minimum space between two PP regions. Merge if the space is
PP.S.1 B 0.440
less than 0.440 um
Minimum clearance from a PP region to a N+ active OD region
PP.C.1 C 0.260
(inside P-Well)
Minimum clearance from a PP region to a non-butted edge of N-
PP.C.2 Well pick-up N+OD region if the distance between N+OD and P- C1 0.100
TS
Well 0.43um.
Minimum clearance from a PP region to a non-butted edge of N-
PP.C.3 Well pick-up N+OD region if the distance between N+OD and P- C2 0.180
M
Well < 0.43um.

C
Minimum clearance from a PP edge to a N-Channel PO gate. This

PP.C.4 D 0.320
C
equivalent N-Channel area must not be covered with PP: ((((PO

VI
on 6 NO /2
AND OD) SIZING 0.03) AND PO) SIZING 0.32)

A
Minimum clearance from a PP edge to a P-Channel PO gate. This

fid 65 LO 009

PP.C.5 E 0.320
TE
equivalent P-Channel area must be covered with PP: ((((PO AND

OD) SIZING 0.03) AND PO) SIZING 0.32)
en 12 G
C /0
Minimum overlap from a PP edge to an OD region (except

PP.O.1 F 0.230
tia 1 IES
SBDDMY region)
H 1
Minimum extension of a PP region beyond a P+ active OD region

PP.E.1 G 0.180
12
(except SBDDMY region)

lI
Minimum extension of a PP region beyond a P-Well pick-up P+OD

nf
PP.E.3 H 0.020
region if the distance between P+OD and N-Well 0.43um.
or
Minimum extension of a PP region beyond a P-well pick-up P+OD

region if the distance between P+OD and N-Well < 0.43 um.
m
To follow this rule and PP.C.1 simultaneously, P+ tap OD to N+

PP.E.4 H1 0.180
active OD minimum spacing must increase up to 0.44um.
at
To follow this rule and PP.C.3 simultaneously, P+ tap OD to N+ tap

io
OD minimum spacing must increase up to 0.36 um.
"
IN
Clearance from a PP region to the butted edge of a butted diffusion

n
PP.C.6 I 0.000
N+ OD (inside N-Well)
C
Minimum extension of a PP region along the edge of a butted

PP.E.5 H2 0.000
diffusion P+OD/N+OD
.
PP.A.1 Minimum area of PP region 0.3844

Minimum extension of PP region beyond a PO as a resistor. RPO
PP.E.6 L 0.18
PO without NP or PP implant is not allowed.
PP.R.1 PP overlapped with NP is not allowed
It is prohibited that PP is generated by reverse tone of NP, since
PP.R.2
this operation might violate PP.C.1, and PP.C.2
OD must be fully covered by {NP OR PP} except
a) OD without interacting {CO OR PO}
PP.R.3
b) NW resistor
c) SBDDMY region
Document No.
Version
: T-018-LO-DR-001
: 2.8
0.43
P+ OD
H1 H
PP
H1
H PW
H
P+ OD
TS
PP 0.43 PP
H
M
0.43
C
P+ G
F OD
C
A
VI
on 6 NO /2
B PP
A
0.35
fid 65 LO 009
C1
TE
en 12 G
N+ OD
C /0
E P+ OD
tia 1 IES
N+
H 1
OD I
12
lI
NP 0.35 C2 0.43
NW
nf
POLY C2 >0.36
or
m
PW H H1
at
P+ PP H
OD
io
0.35 D P+ OD
IN
PP
H2 C PP
C
N+OD L
.
H P+OD
D
0.35 PP
POLY
Poly Resistor
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.10 Resist Protection Oxide (RPO) Layout Rules

(Mask ID: 155)
Layout
Rule
#
RPO.W.1 Minimum RPO width A 0.430
RPO.S.1 Minimum RPO spacing B # 0.430
RPO.C.1 Minimum clearance from RPO to unrelated OD C # 0.220
RPO.C.2 Minimum clearance from RPO to CO D # 0.220
RPO.C.3 Minimum clearance from RPO to Poly on OD (except ESD cell region) E # 0.450
Minimum clearance from RPO to related OD (RPO fully inside OD is not
#
TS
RPO.C.4 F 0.220
allowed)
RPO.E.1 Minimum extension of OD to RPO G # 0.220
M
RPO.C.5
Minimum extension of RPO to Poly resistor on field oxide (RPO fully
H # 0.220
C
inside PO is not allowed)

RPO.C.6 Minimum clearance of RPO to unrelated Poly on field oxide I # 0.300
#
C
RPO.A.1 Minimum area of RPO 2

VI
on 6 NO /2
(Below items are referred from the ESD chapter)

A
NMOS and PMOS of I/O buffer should have a non-salicide area on drain
fid 65 LO 009
ESD.19g side, that is, RPO mask should block drain side of device (except contact
TE
region should keep silicided).

en 12 G
For high voltage tolerant I/O designed by 3.3V/2.5V NMOS (see N1 and
C /0
N2 in Fig.5a): 0.05 or
tia 1 IES
ESD.20g RPO should cover all inactive poly gates and extend to active region M = 0.06um
H 1
(Poly spacing= 0.25um). Minimum and maximum overlap from RPO to See Fig.5
12
the active poly gate. (see Fig.5b).

lI
For regular I/O designed by 5V, 3.3V, 2.5V, 1.8V and 1.5V NMOS (see
nf
0.05 or
N3 in Fig.6a):
ESD.21g N = 0.06um
Minimum and maximum overlap from RPO on the drain side to poly gate.
or
See Fig.6
(see Fig.6b)
m
For all PMOS (see P1 in Fig.5a and P3 in Fig.6a): 0.05 or

ESD.22g Minimum and maximum overlap from RPO on the drain side to poly gate. N = 0.06um
at
(see Fig. 6b) See Fig.6

For 5V, 3.3Vand 2.5V power clamp devices:
io
0.05 or
ESD.23g Minimum and maximum overlap from RPO on the drain side to poly gate. N =
IN
0.06um
n
(see Fig.6b)
1.95um
C
#
Minimum width of RPO on drain side (X) for 5V, 3.3V, 2.5V, 1.8V and
(in Fig.5b
ESD.24g 1.5V NMOS and PMOS, excluded 1.8V and 1.5V NMOS when used as X
.
and
power clamp device
Fig.6b)
ESD.32g
Minimum width of RPO on drain side (X) for 1.8V NMOS and
5V/3.3V/2.5V/1.8V/1.5V PMOS. (see Fig.7a)
X 1.5um #
*Please keep contacts be salicided in RPO block area.
** If poly resistor is used, please follow poly resistor guideline.
*** If RPO is used in ESD circuit, please follow ESD guideline.
**** Except ESD design application, RPO partially intersect OD (or PO) is NOT recommended. It is
recommended the RPO must intersect the related OD (or PO) and divide it into two or more regions.
(Please see the Fig.1 in this section). If such layouts were still used, please make sure the function of
circuit is correct.
Document No.
Version
: T-018-LO-DR-001
: 2.8
R
RPPO
O
G OD
OD
F RPO
CO
TS
B A
D E
M
C
PO
RPO
C
VI
on 6 NO /2
I
A
fid 65 LO 009
RPO
TE
H NP/PP
en 12 G
C /0
D PO Resistor D
tia 1 IES
CO CO
H 1
12
lI
nf
or
m
at
RPO RPO
RPO
OD
OD
io
(or PO)
(or PO)
IN
OD
(or PO)
C
Fig.1 RPO partially intersect OD (or

.
PO) is NOT recommended.

RPO.C.4 & RPO.C.5:
RPO fully inside OD
(or PO) is NOT allowed.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.11 Contact (CO) Layout Rules (Mask ID: 156)

Rule No. Description Label Layout Rule
CO.W.1
Minimum and maximum width of a CO region (except sealring
A $ 0.220
region).
CO.S.1 Minimum space between two CO regions B % 0.250
Minimum space between two CO regions in a contact array with
both row and column numbers equal to or larger than 4. As
CO.S.2 shown in shaded area, two contact regions within 0.3 um distance B1 % 0.280
is considered to be in the same array. (Ex. 2×8, 3×3, 3×8 use B,
TS
and 4×4, 4×5, 4×8 use B1)

CO.C.1 Minimum clearance from a CO on OD region to a PO gate C % 0.160
%
M
CO.C.2 Minimum clearance from a CO on PO region to an OD region D 0.200

%
C
CO.E.1 Minimum extension of an OD region beyond a OD CO region. E 0.100

CO.E.2 Minimum extension of a PO region beyond a Poly CO region. F % 0.100
C
%
VI
Minimum extension of a PP region beyond a OD CO region.

on 6 NO /2
CO.E.3 G 0.120
(except SBDDMY region)
%
A
CO.E.4 Minimum extension of a NP region beyond a OD CO region. H 0.120

fid 65 LO 009
TE
CO.R.1 CO on gate region is forbidden

en 12 G
CO.R.2 OD contact sitting on NP/PP boundary is not allowed.

C /0
CO.R.3 Non-salicided contacts are not allowed

tia 1 IES
H 1
(Below item is referred from the ESD Section)

& (in Fig.5b0.5um
12
Minimum clearance from poly edge to CO edge on source side for

lI
ESD.25g Z
NMOS and PMOS (Except ESD.26g) and Fig.6b )
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
C
COO
NP
E G
OD
PO
CO
PP
G
B
C
CO PO
H
A
TS
E
D PP
M
E
CO NP
C
F
H
P+
C
P+ G N+
VI
on 6 NO /2
A
fid 65 LO 009
TE
> 0.3 Not allowed

en 12 G
PP
C /0
CO
'0.3
tia 1 IES
H 1
B1
12
lI
'0.3
nf
or
'0.3
m
at
PP
io
IN
OD
n
C
Allowed
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.12 Metal-1 (M1) Layout Rules (Mask ID: 160)

Layout
Rule
(
M1.W.1 Minimum width of M1 region A 0.230
M1.S.1 Minimum space between two M1 regions B ( 0.230
M1.E.1 Minimum extension of M1 region beyond CO region C ( 0.005
Minimum extension of M1 end-of-line region beyond CO region.
M1.E.2.
For CO located at the 90 degree corner, at least one side of
metal extension must be treated as end-of-line and another side
C1 ( 0.060
TS
can follow M1.E.1 (see next page)

Minimum space between metal lines with one or both metal line
M
(
width and length are greater than 10um; the minimum space
M1.S.2 must be maintained between a metal line and a small piece of D 0.600
C
metal (<10um) that is connected to the wide metal within 1.0 um

range from the wide metal.
(
C
VI
M1.A.1 Minimum area of M1 region E 0.202

on 6 NO /2
Minimum density of M1 across full chip.

A
(
Density is calculated as Total metal layout area/chip area.
fid 65 LO 009
M1.R.1 It is recommended to use TSMC’s auto-fill utilities (Document 30%

TE
No.: T-018-LO-DR-001-C3) to add dummy metal if M1 density is

en 12 G
less than 30%.

C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
M
Meettaall--11
> 10 um
M1
D
D
M1
M1
TS
B B
M
1 um
C
C
M1
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
C C
12
lI
M1 CO CO C1 M1 E
nf
or
m
C
at
C1 CO M1
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.13 VIA1 to VIA4 (VIAx) Layout Rules (Mask ID: 178,

179, 173, 174)
In the following table, the x in VIAx refers to 1, 2, 3, and 4.
VIAx can be located at any region.
VIAx can be fully or partially stacked on any combination of stacked structure such as stacked VIAx-
1../CO.
Layout
Rule
VIAx.W.1
Minimum and maximum width of VIAx region (except sealring
A ) 0.260
TS
region).
VIAx.S.1 Minimum space between two VIAx regions B * 0.260
*
M
VIAx.E.1 Minimum extension of Mx region beyond VIAx region. C 0.010

C
Minimum extension of Mx end-of-line region beyond VIAx region.

VIAx.E.2
For VIAx located at the 90 degree corner, at least one side of
C1 0.060 *
C

VI
can follow VIAx.E.1 (see next page)

on 6 NO /2
Note:
A
VIAx can be located at any region.

fid 65 LO 009
VIAx can be fully or partially stacked on any combination of stacked structure such as stacked VIAx-
TE
1../CO.
en 12 G
C /0
V
VIIA
A11 ttoo V
VIIA
A44
tia 1 IES
H 1
12
C
lI
C1 CO
Mx
nf
C1
VIAx
or
VIAx A
m
at
C1
io
> C allowed
B
IN
n
C
C1
.
C
VIAx
C1
C
+C
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.13.1 C018 VIA Array Layout Rules

• In the following table, the x in VIAx refers to 1, 2, 3, and 4. The n in VIAn refers to 5.
Layout
Rule
Minimum space between two VIAx regions in 5-level continuous stacking VIA arrays B1 - 0.49 um
with below conditions.
a) Criteria of VIA array
,
a1) Only check VIA1~VIAn at same metal polygon
a2) Two VIA regions with space 3.2um are treated as same VIA array
TS
-
b) Conditions of 5-level continuous stacking VIA array check
VIAx.S.2
.
b1) Overlap area of 5-level continuous stacking VIA arrays 300um^2
M
-
b2) Parallel run length of 5-level continuous stacking VIA arrays 15um
,
b3) Width of 5-level continuous stacking VIA arrays 8um
C
-
b4) Spacing of 5-level continuous stacking VIA arrays 2.8um
b5) VIA density in each VIA array (5-level continuous stacking area) 10%
C
-
All of VIAx need to follow this rule, recommend VIAn follow this rule.
VI
on 6 NO /2
Minimum space between two VIAx regions in 4-level continuous stacking VIA arrays B2 0.49 um
A

fid 65 LO 009
,
TE
en 12 G
-
VIAx.S.3
C /0
-
-
tia 1 IES
H 1
,
-
12

lI
nf
-
or

m
,
at
-
VIAx.S.4
-
io
-
IN
,
n
-
C
.
-
,
-
VIAx.S.5
-
-
,
-
Document No.
Version
: T-018-LO-DR-001
: 2.8
Not Allowed
• Example: stacking layer from VIA1 to VIATop

/
/
Only change Via space 0.49um
New Layout Rule in one layer and one array
Recomm end: Via5 space 0.49um
/
in both arrays
/
Via4 space 0.49um in both arrays
Via3 space
/
0.49um in both arrays
/
Although layout pass DRC, we
requi re all the via space 0.49um
/
Via2 space 0.49um in both arrays for all layers
Not Allowed
Only change Via space / 0.49um

TS
in one layer
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.13.2 C016 VIA Array Layout Rules

• The rules listed in the below table are adjusted to avoid DRC false alarm on 110% size-up circuits.
In the following table, the x in VIAx refers to 1, 2, 3, and 4. The n in VIAn refers to 5.
Layout
Rule
Minimum space between two VIAx regions in 5-level continuous stacking VIA arrays B1 1 0.49 um
0
TS
1
VIAx.S.2
M
2
1
b2) Parallel run length of 5-level continuous stacking VIA arrays 16.7um
C
0
b3) Width of 5-level continuous stacking VIA arrays 8.9um
1
C
VI
on 6 NO /2
1
A

fid 65 LO 009

TE
0
en 12 G
C /0
1
VIAx.S.3
1
tia 1 IES

H 1
1
12
0
lI
1
nf
1
or
m
0
at
1
io
VIAx.S.4
1
IN
1
n
0
C
1
.
1
0
1
VIAx.S.5
1
1
0
1
Document No.
Version
: T-018-LO-DR-001
: 2.8
Not Allowed
• Example: stacking layer from VIA1 to VIATop

3
3
New Layout Rule Only change Via space 0.49um
in one layer and one array
Recommend: Via5 space 0.49um
in both arrays
3
3
Via3 space
3
0.49um in both arrays
3
Although layout pass DRC, we
require all the via space 0.49um
3
Via2 space 0.49um in both arrays for all layers
Not Allowed
Only change Via space 3 0.49um

TS
in one layer
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.14 Metal-2 to Metal-5 (Mx) Layout Rules (Mask ID:

180, 181, 184, 185)
In the following table, the x in Mx refers to 2, 3, 4, and 5.
Layout
Rule
Mx.W.1 Minimum width of Mx region A 4 0.280
Mx.S.1 Minimum space between two Mx regions B 4 0.280
Mx.E.1 Minimum extension of Mx region beyond VIAx-1 region C 4 0.010
Mx.E.2 Minimum extension of Mx end-of-line region beyond VIAx-1
TS
region.
For VIAx-1 located at the 90 degree corner, at least one side of C1 4 0.060
M

can follow Mx.E.1 (see next page)
C
Mx.S.2 Minimum space between metal lines with one or both metal line
C
width and length are >10um; the minimum space must be

4
VI
maintained between a metal line and a small piece of metal D 0.60

on 6 NO /2
(<10um) that is connected to the wide metal within 1.0 um range

A
from the wide metal

4
fid 65 LO 009
Mx.A.1 Minimum area of Mx region E 0.202

TE
Mx.R.1 Minimum density of Mx across full chip.

en 12 G
Density is calculated as Total metal layout area/chip area. IT IS

4
C /0
RECOMMENDED TO USE TSMC’S AUTO-FILL UTILITIES 30%

tia 1 IES
(DOCUMENT NO.: T-018-LO-DR-001-C3) TO ADD DUMMY

H 1
METAL IF Mx DENSITY IS LESS THAN 30%.

12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
M
Meettaall--22 ttoo M
Meettaall--55
> 10um
Mx
A A D
Mx Mx
<1.0um
TS
D
M
B
C
C
VI
on 6 NO /2
A
C C
fid 65 LO 009
TE
Mx VIAx-1 Mx
en 12 G
VIAx-1 C1 E
C /0
tia 1 IES
H 1
12
lI
C
nf
Mx
or
VIAx-1
C1
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.15 Top VIA (VIAn) Layout Rule (Mask ID: 175)

In the following table, the n in VIAn refers to 5.
Layout
Rule
VIAn.W.1
Minimum and maximum width of VIAn region (except sealring
region).
A 5 0.360
VIAn.S.1 Minimum space between two VIAn regions B 6 0.350
VIAn.E.1 Minimum extension of Mn region beyond a VIAn region C 6 0.010
Minimum extension of Mn line-end region beyond VIAn region
TS
For VIAn located at the 90 degree corner, at least one side of

VIAn.E.2
can follow VIAn.E.1 (See the attached figure of correct and
C1 6 0.060
M
incorrect layouts, rectangular instance shown in shaded area is

C
recommended)
Note:
C
VIAn can be fully or partially stacked on Via4, Via3, Via2, Via1, any combination of stacked structure such as
VI
on 6 NO /2
stacked Via5/Via4/Via3/Via2/Via1/CO.
V
VIIA
Ann
A
fid 65 LO 009
TE
C
en 12 G
C /0
C1 CO Mn
C1
tia 1 IES
H 1
VIA6
VIAn
12
A
lI
VIA6
VIAn
nf
or
C1
m
> C allowed
B
at
io
C1
IN
C
C
VIA6
VIAn
.
C
C1
7C
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.16 Top Metal (Mn) Layout Rule (Mask ID: 186)

In the following table, the n in Mn refers to 6.
Layout
Rule
Mn.W.1 Minimum width of Mn region A 6 0.440
Mn.S.1 Minimum space between two Mn regions B 6 0.460
Mn.E.1 Minimum extension of Mn region beyond a VIAn region C 6 0.090
Minimum space between metal lines with one or both metal line width and
Mn.S.2
length are greater than 10um; the minimum space must be maintained
between a metal line and a small piece of metal (<10um) that is connected to
D 6 0.600
the wide metal within 1.0 um range from the wide metal.
6
TS
Mn.A.1 Minimum area of Mn region E 0.562

Minimum density of Mn across full chip
6
Density is calculated as Total metal layout area/chip area.
M
Mn.R.1 It is recommended to use TSMC’s auto-fill utilities 30%

C
(Document No.: T-018-LO-DR-001-C3) to add dummy metal if Mn density is

less than 30%.)
C
VI
M
Mnn
on 6 NO /2
A
fid 65 LO 009
TE
< 10 um
en 12 G
Mn
C /0
D
tia 1 IES
H 1
12
lI
A
nf
D
Mn
M6
Mn
or
B B
m
1 um
at
io
M6
Mn
IN
n
C
.
C C
Mn E
Mn VIA5
VIAn-1 VIA5
VIAn-1
C
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.17 Product Labels and Logo Layout Rules

1. Using any of the following product labels must follow logo rules to prevent process defect:
• Copyright and year
• Company logo
• Part number
• Mask level names
• Other similar labels
2. Make sure to use dummy layer LOGO (CAD layer no. 178) to do DRC for product labels.
Product labels must be fully covered by LOGO dummy layer.
TS
3. It is not recommended to use dummy layer EXCL to exclude DRC in the LOGO region.
The region covered by (EXCL AND LOGO) will still be checked by DRC.
M
4. Make certain that the label design as DRC clean (free of all DRC violations).
C
5. Do not use circles, oval shapes, or logos of arbitrary geometry (Figure 4.5.17.1).
Use rectangular or 45-degree polygons to write words, logos, and other marks that are not part of the
C
circuit.
VI
on 6 NO /2
6. Form the product labels for the CO/Via layer by using squares with minimum width.
A
A big CO/Via polygon for a character (or a numeral) is not allowed. Besides, follow metal to CO/Via
fid 65 LO 009
extension rule to cover metal above CO/Via and under Via. (Figure 4.5.17.2)
TE
7. Don’t use minimum rules for the product labels, except for CO/Vias.
en 12 G
It is best to have greater than, or equal to, 1 µm of width and space for label. If the minimum width and
C /0
space is greater than 1 µm in the rule (for example, 20KÅ ultra thick metal layer), please use at least the
tia 1 IES
H 1
minimum width and space in the rule.

8. To protect the product labels, do not use a dummy OD/Poly/Metal in the LOGO regions.
12
lI
For process uniformity, keep the LOGO layer and the corresponding product labels at least 3 µm distant
nf
from the OD/PO/Metal geometry. Add dummy fill in this 3 µm border region.
or
Rule No. Description Label Rule

8
m
LOGO.S.1 Space to NW, OD, PO, or Metals (non-dummy patterns) A 3

Overlap of CB, CBD, FW, PM, UBM, DOD, DPO, or DMx is not
at
LOGO.O.1
allowed.
io
LOGO.R.1 A circuit in the LOGO is not allowed.

IN
The region covered by (EXCL AND LOGO) will still be checked

n
LOGO.R.2
all rules by DRC. (DRC will not waive (EXCL AND LOGO))
C
.
NW/OD/POLY/Metal
A
LOGO
Document No.
Version
: T-018-LO-DR-001
: 2.8
TS
M
C
C
Figure 4.5.17.1 Logo Geometry Example

VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
CO/Via
C
Metal
.
Figure 4.5.17.2 Logo Geometry Example
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.18 Passivation (CB), Polyimide (PM) & AP-MD

Layout Rule (Mask ID: 107, 009 & 309)
9
Please refer to TSMC WIRE BOND, FLIP CHIP AND INTERCONNECTION DESIGN RULE” (Doc. No.T-
000-CL-DR-002) for details.
4.5.19 Metal Fuse Rule

Please refer to “TSMC Al Metal Fuse Design Rule” (Doc. No.T-000-LO-DR-003) for details.
TS
4.5.20 Seal-Ring Rule

M
If seal ring is added by TSMC, TSMC will add assembly isolation and seal-ring structure at the same time.
C
Layout
Rule No. Description
Rule
C
Minimum assembly isolation. It also depends on the capability of assembly

VI
SR.S.1U 5.0
on 6 NO /2
house to require larger distance.

Minimum extension of metal to CO/VIA in guard ring. Propose to exactly
A
SR.E.1U 0.6
fid 65 LO 009
follow the dimensions in the figure below

TE
TSMC recommend scribe line seal and scribe seal ring rules as follows.
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Die Frame
Seal -Ring
Passivation M6
M6/UTM
1 MD5 VIA5
M5
1 MD4 VIA4
M4
1 MD3 VIA3
M3
1 MD2 VIA2
M2
1 MD1 VIA1
M1
ILD CO Silicide
Shallow Trench Isolation P + S/D
P-Well
Seal Ring Scribe
Assembly Isolation
10um Layers Line tone
10 um
TS
Dark tone DNW (119) D

OD (120) D
Clear tone ODR (121) C

P-Well (191) D
M
VTM_N (118) D
N-Well (192) D
VTM_P (117) D
C
OD2 (132) C
Poly (130) C
N2V (114) D
C
P2V (113) D
VI
P3V (115) D
on 6 NO /2
N3V (116) D
NP (198) D
A
PP (197) D
HRI (133) D
fid 65 LO 009
4.1 um
PRO (155) D
TE
ESD (111) D
ESD (110) D
1.08 um 1.58 um 1.58 um 5.1 um
CO (156) D
en 12 G
0.22 um 0.22 um 0.22 um 4.1um M1 (160) C

1.98 um 1.36 um 6.14 um D
C /0
VIA1 (178)
0.26 um 0.26 um 4.1 um
M2 (180) C
1.08 um
tia 1 IES
1.46 um 1.46 um 5.22 um

D
H 1
VIA2 (179)
0.26 um 0.26 um 0.26 um M3 (181) C
2.08 um 1.36 um 6.04 um
VIA3 (173) D
4.1 um
12
0.26 um 0.26 um M4 (184) C

lI
1.28 um 1.36 um 1.36 um 5.22 um

VIA4 (174) D
0.26 um 0.26 um 0.26 um
CTM (182) C
4.1 um
nf
M5 (185) C
1.98 um 1.26 um 6.04 um
VIA5 (175) D
0.36 um 0.36 um 4.1 um
M6 (186) C
or
Cross-section 8 um 2um
CB (107) C
Layout edge Window edge
0.36 0.36
Top view
m
IMD5
1.98 1.26
VIA5
0.26 0.26 0.26
M5
at
1.36 IMD4
VIA4 1.28 1.36
io
0.26 0.26
M4
IN
2.08 1.36 Space between 2 vias

VIA3 IMD3
0.26 0.26 0.26
M3
C
1.08 1.46 1.46 IMD2

.
VIA2
0.26 0.26
M2
1.98 1.36 IMD1

VIA1
0.22 0.22 0.22

M1
1.08 1.58 1.58 ILD

CO
*The shape of Contact/ VIA in sealring is line shape and surrounding with whole chip.
*For SPPM process, please skip metal5 and via4 layers.
*For SPQM process, please skip metal5, metal4, via4 and via3 layers
*For SPTM process, please skip metal5, metal4, metal3, via4, via3, and via2 layers.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.21 Antenna Effect Prevention (A) Layout Rules

Rule No. Description Ratio
Maximum drawn ratio of field poly perimeter area to the active poly :
A.R.1 gate area connected directly to it 200
A.R.2
When the protection OD is not used, the maximum ratio of single-
layer metal perimeter area to the active poly gate area. (for M1 to
: 400
M6)
When a protection OD with area larger than 0.203 um2 is used, the
maximum ratio of single-layer metal perimeter area to the active Poly
TS
gate area can be calculated by the following equation:

;
A.R.3
Ratio OD area * 400 + 2200 for M1, 2, 3, 4, and 5 single layer.
;
M
Ratio OD area * 8000 + 30000 for M6 single layer.

Maximum drawn ratio of CO area to the active Poly gate area :
C
A.R.4 connected directly to it. 10

:
C
When the protection OD is not used, the maximum single layer drawn
A.R.5 20
VI
ratio of Via area to the active Poly gate area connected directly to it.
on 6 NO /2
When a protection OD with area larger than 0.203 um2 is used, the
A
maximum drawn ratio of Via area to the active Poly gate area can be
fid 65 LO 009
A.R.6
calculated by the following equation:
;
TE
Ratio OD area * 83.33 + 75 for single layer

en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
The definition of Poly, M1-M6 antenna ratio for each layer is

Ratio ;
2 [(L +W1) x t ] / W2 x l
L : Floating metal length connected to gate
W1 : Floating metal width connected to gate
t : Metal thickness
W2 : Connected transistor channel width
l : Connected transistor channel length
The definition of CO, Via1-Via5 antenna ratio is
Ratio ;
{total contact (via) area}/ W2 x l
The thickness of poly is 2000Å
The thickness of M1-M5 is 5300Å.
The thickness of M6 is 9900Å.
The thickness of 20KÅ UTM is 23400Å.
TS

M
C
L
C
VI
on 6 NO /2
A
fid 65 LO 009
t PR
TE
en 12 G
Metal_1
C /0
W1
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
W2
C
.
STI Poly
STI
l
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.22 Stress Release Rules

4.5.22.1 Description
1. Power line around the chip corner and dummy pads should be set to prevent the thermal stress induced
problem. Please refer to the rule in Sec 4.5.22.3.1 “Chip Corner Power Line and Dummy Pad”.
2. Users must add open slot in the wide metal line where the metal is greater than 35.0um. Please refer to
the rule in Sec 4.5.22.3.2 “Metal Stress Relief – metal slot”.
3. Large chip need to follow the Sec 4.5.18 “Passivation & Polyimide Layout Rule” requirement rule.
4. Keep top metal space less than 10.0um. User should place dummy patterns on top metal layer for the
space grater than 10.0um. Please refer to the Sec 4.5.22.3.3 “Assembly Stress Protection – dummy
metal “.
TS
4.5.22.2 Terminology
M
Corners: For triangular regions in the corner whose sides are along the edge of the chip inside the seal-ring.
C
MT: Top metal layer for all processes. For example, M2 layer for 2LM process, M3 layer for 3LM process,
M4 layer for 4LM process, M5 layer for 5LM, or M6 layer for 6LM
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.22.3 Layout Definition

4.5.22.3.1 Chip Corner Power Line and Dummy Pad
These rules can reduce the impact of damage induced by thermal stress during packaging and field
application. Figure 4.5.22.1 is the general layout. Dummy pad must be constructed by
STI/M1/VIA1/M2/VIA2/…/MT. Detailed layouts and cross section are depicted in Figure 4.5.22.2, 3, 4. Figure
5 is chip size –dependent power line layout. Figure 4.5.22.6 is the case of power line outside bond pads.
Please cover dummy layer DPDUMMY(65;0) and PLDUMMY(66;0) on dummy pad/power line for DRC check.
(refer figure 4.5.22.5 and 4.5.22.2)
Layout
TS
Rule.
Rule
M
User must add dummy pads in the chip corners. The dummy pads should fill
U every chip corners as many as possible.
C
ADP.1
The layout is described as following spec. (From A to G; associated schematic
diagram is in Figure 4.5.22.2).
C
Power line must have “anchor” design that should be constructed by the following
VI
on 6 NO /2
ADP.2U rule. (I, J. and K; associated schematic diagram is in Figure 4.5.22.3).

If Vdd and Vss are stacked in this region. User can by-pass this rule.
A
There must be power line or wide metal line around the corner in top metal layer.
fid 65 LO 009
ADP.3U
<
(Figure 4.5.22.5).
TE
<
ADP.W.1 Minimum and maximum width of a VIA1 to 4 region G 0.26
en 12 G
=
ADP.W.2 Minimum and maximum width of VIA5 region G1 0.36
C /0
=
ADP.S.1 Minimum space between two Vias at the same level D, I 0.58
tia 1 IES
H 1
=
ADP.E.1 Minimum extension of Metal over VIA (chip corner dummy pad) F 3.0
=
ADP.E.2 Minimum extension of Metal over VIA (chip corner power line) K 0.2
12
lI
=
ADP.C.1 Minimum clearance between two Vias at different levels E, J 0.23
ADP.C.2 Minimum clearance between two VIA4 or VIA5 at different levels E1 0.16
nf
No active circuit is allowed inside the square region between the first two pads
ADP.R.1U
counted from the edge as shown in Figure 4.5.22.1.
or
ADP.R.2U No active circuit is allowed inside the square area fully covered the corners.
For large die, whose size is greater than 100mm2, power line or wide metal L
m
350
should be placed around every corner. The metal line should turn 45 degree from N 700
at
ADP.R.3U 350um(L) of the chip corner and turn 45 degree again from 350um of adjacent
edge. The metal also need to extend at least 700um(N) from the starting point of
io
turnaround (L, N in Figure 4.5.22.5).

IN
For small die, whose size is less than 100mm2, power line or wide metal should L1 125
n
be placed around every corner. The metal line should turn 45 degree from N1 400
C
ADP.R.4U 125um(L1) of the chip corners and turn 45 degree again from 125um of adjacent
edge. The metal also need to extend at least 400um(N1) from the starting point of
.
turnaround (L1, N1 in Figure 4.5.22.5).

For power line outside bond pads, dummy pattern (with the same structure as
ADP.R.5U
dummy pad) should be put in the region as shown in Fig 4.5.22.6.
=
Guideline
=
ADP.S.2g Minimum space between two dummy pads A 2.0
ADP.S.3gU
>
Minimum space between seal ring and outer dummy pads edge B 25.0
=
ADP.W.3g Maximum width of a dummy pad C 80.0
=
ADP.W.4g Minimum width of a dummy pad C 40.0
U For any kind of chip size, the length of inside edge of power line corner should be P 15
ADP.R.6g
larger than 15um (P in Figure 4.5.22.5).
Document No.
Version
: T-018-LO-DR-001
: 2.8
Not allowed layout (1) – without power line or wide metal on top metal around
corner
No power line or wide
metal on top metal
Top metal layer
TS
M
C
Underlayer metal
Power line
C
VI
on 6 NO /2
A
Not allowed layout (2) – wide metal turn 90 degree

fid 65 LO 009
Could not be 90 degree

TE
(should be 45 degree)
en 12 G
Wide metal
C /0
tia 1 IES
H 1
12
lI
nf
Could not be 90 degree

or
(should be 45 degree)
m
at
Not allowed Allowed

io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
II
TS
No active circuit is allowed

Within these regions
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
Figure 4.5.22.1 Chip Corner (I) and Power Line (II) Layout
en 12 G
C /0
VI A2 or VIA4
tia 1 IES
B DPDUMMY
H 1
VI A1 or VI A3
12
Seal Ring
lI
B VIA5
nf
F
F
or
Metal E
A D
D
m
E1
E
D
at
C
A
io
G1
IN
C G G1
C
G
.
Figure 4.5.22.2 Chip corner dummy pad layout, region I in Figure 4.5.22.1
Document No.
Version
: T-018-LO-DR-001
: 2.8
I
E1
I
I K
I
J J
K E1
TS
M
C
VIA1, VIA3
C
VIA2, VIA4
VI
on 6 NO /2
VIA5
A
fid 65 LO 009
TE
Figure 4.5.22.3 Chip corner power line layout, region II in Figure 1

en 12 G
C /0
M6
tia 1 IES
H 1
VIA5
12
lI
M5
nf
VIA4
or
M4
m
VIA3
at
M3
io
VIA2
IN
M2
n
C
VIA1
.
M1
STI
NW/P-substrate
Figure 4.5.22.4 Cross section of power line and dummy pad
Document No.
Version
: T-018-LO-DR-001
: 2.8
Chip Corner
N(N1) L(L1)
PLDUMMY
45 degree
L(L1)
TS
M
P N(N1)
C
C
VI
Figure 4.5.22.5 Chip corner power line layout for chip size >100mm2(L, N) and <100mm2(L1, N1)
on 6 NO /2
A
fid 65 LO 009
Chip Corner
TE
en 12 G
C /0
tia 1 IES
H 1
12
45 degree
lI
nf
or
m
2 um
at
io
Bond Pad
IN
n
C
Filled with dummy

.
pads
Figure 4.5.22.6 Chip corner dummy pads in case of power line outside bond pads.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.22.3.2 Metal Stress Relief – Metal Slot

Layout
Rule
Rule All metal layers must follow this rule
The metal “slot” must be placed for releasing stress of wide metal line. The
AMS.1 wide metal is defined as being > 35um*35um(both width and length). Only 35.0
bonding pads area are excluded.
Minimum slot density for the wide metal.
AMS.DN.Mx (Slot density is defined as the slot area dividing by the wide metal area.)
Open holes (>10um*10um) area is NOT included in the calculation of slot
? 1.5%
density.
TS
Guideline
Slot dimension could be > 1um (>4um) in width and 10um ( 30um & ? ?
M
max 300um for 40KÅ UTM) in length.

Slotting [NOTE] A, B
C
1. Mx.S.2 require >1um space for normal metal

2. UTM.S.2 require >4um space for ultra thick metal.
?
C
VI
Slot-to-slot spacing could be 10um. C, D

?
on 6 NO /2
Slot-to-metal edge spacing could be 10um. E, F

A
U To avoid EM problems resulting from current funneling due to slot, the

AM.R.1g
fid 65 LO 009
length of the slot should be parallel to current flow direction.

TE
AM.R.2gU The starting position of the parallel slots should be staggered.

en 12 G
C /0
S
Slloott ddeeffiinniittiioonnss
tia 1 IES
H 1
F
12
lI
nf
or
E
m
G
at
io
IN
n
C
F
.
A
C D
Document No.
Version
: T-018-LO-DR-001
: 2.8
N
Noott rreeccoom
mmmeennddeedd sslloott LLaayyoouutt ((11)) –– ssttaacckkiinngg sslloott
Top metal
Under layer metal
TS
M
C
Stacking slot
C
Top metal
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
Under layer metal

C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
N
Noott rreeccoom
mmmeennddeedd sslloott LLaayyoouutt ((22)) –– vveerrttiiccaall &
& ssiiddee bbyy ssiiddee sslloott
Current flow direction
TS
Length perpendicular Not staggered start

M
to current flow
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.22.3.3 Assembly Stress Protection – Dummy Metal

MT refers to normal top metal (8KÅ) and UTM (20KÅ or 40KÅ).
Layout Rule
Rule No. Description Label 8KÅ &
40KÅ
20KÅ
@
Maximum space between two MT (or UTM) features when the
AMT.S.1U width of either MT (or UTM) feature is less than 10um. A 10.0 10.0
User should add dummy metal to meet the requirement
AMT.W.1U Minimum width of a dummy MT (or UTM) block B A 2.0 4.0
@
TS
U
AMT.W.1 Maximum width of a dummy MT (or UTM) block B 4.0 8.0
U
AMT.L.1 Minimum length of a dummy MT (or UTM) block C A 2.0 4.0
@
M
U
AMT.L.1 Maximum length of a dummy MT (or UTM) block C 10.0 10.0
A
C
Minimum space between a MT (or UTM) feature and a dummy

AMT.S.2U D 2.0 3.0
MT (or UTM) block
@
C
Maximum space between a MT (or UTM) feature and a

AMT.S.3U D1 10.0 10.0
VI
dummy MT (or UTM) block

on 6 NO /2
AMT.S.4U
Minimum and maximum space between two neighbor dummy
B
A
E 2.0 3.0
MT (or UTM) blocks
fid 65 LO 009
Minimum number of dummy MT (or UTM) blocks to be put in a

A
TE
AMT.R.1U F 3.0 3.0

large open area beside a MT (or UTM) feature.
en 12 G
C /0
D
Duum
mmmyy M
MTT ((oorr U
UTTM
M)) ((TToopp M
Meettaall))
tia 1 IES
H 1
A
12
lI
MT
nf
or
m
c E
MT MT
at
F
io
IN
E D(D1)
C
.
Open
F area
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.23 SRAM Guideline

1. Customer-designed SRAM bit-cell must be approved by TSMC’s R&D and PE in order to guarantee
SRAM cell electrical performance
2. Please don’t use logic SPICE model to design SRAM unless it strictly follows logic design rule to design
SRAM and approved by TSMC’s R&D and PE.
3. For accumulated SRAM density > 1.5M bits, redundancy is needed. Please refer to the most updated
version of “TSMC 0.15um/0.18um/0.25um SRAM engineer report of SRAM redundancy for
C025/C018/C015” (document no.: T-018-SM-RP-001) as embedded SRAM redundancy guideline.
4. Dummy Layouts for Embedded SRAM
• If SRAM cell arrays are used, dummy layouts must be added to provide similar surrounding for every
TS
cell so as to evade proximity and loading effect.

• Please refer to these guidelines and their GDS-II examples in TSMC SRAM cell layout documents to
M
add dummy layouts, in both column and row, at array edge and at connection/tap in –between arrays
as follows.
C
C
VI
on 6 NO /2
Dummy layouts Dummy layouts

A
fid 65 LO 009
Dummy layouts
Dummy layouts
Dummy layouts
Dummy layouts
TE
en 12 G
SRAM SRAM
C /0
cell array cell array

tia 1 IES
H 1
12
lI

nf
or
m

at
Dummy layouts
Dummy layouts
Dummy layouts
Dummy layouts
io
SRAM
IN
SRAM
n
cell array cell array

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.5.24 Planar Capacitor EMB-SRAM Rules

Please use RPO blocking on storage node to avoid salicide formation. It is “must” for RPO on storage node
Layout
Rule
C
T1.O.1U RPO overlay with WL Poly A 0.03
T1.O.2U Minimum RPO overlay with capacitor Poly Cap B D 0.05
T1.R.1U Borderless CO is forbidden. (Please follow CO.E.1)
Use of minimum OD with(C) & poly width (D) for pass gate is
T1.R.2U forbidden (exceed at least 0.01um) to avoid short channel &
narrow width effects.
TS
P
Plleeaassee ffoolllloow
wRRP
POO ppiittcchh rruulleess R
RPPO
O..W
W11,, R
RPPO
O..S
S..11
M
C
C
VI
on 6 NO /2
A
OD
fid 65 LO 009
TE
B
A
en 12 G
C /0
tia 1 IES
H 1
D C
12
lI
nf
Storage
or
WL Poly Node
Capacitor
m
Poly Cap
at
io
IN
n
C
.
RPO
A
Abboovvee rruulleess aarree nnoott ssuuppppoorrtteedd bbyy D
DRRC
C ccoom
mmmeenndd ffiillee..
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6 Mixed Signal & RF Layout Rules and

Guidelines
4.6.1 Deep N-Well (DNW) Layout Rules (Mask ID: 119)
Deep N-Well (DNW) is an optional layer for isolating the noise from P-substrate.

E
TS
DNW.W.1 Minimum width of a DNW region. A 3.00

DNW.S.1 Minimum space between two DNW regions B E 5.00
E
M
DNW.S.2® Recommend: RW space to {RW OR PW} with different potential F 1.40

E
C
DNW.O.1 Minimum overlap from a NW edge to a DNW region. D 2.00

DNW.C.1 Minimum clearance from DNW to NW E E 3.50
C
Minimum clearance from DNW to {N+OD outside NW} (DNW cut

E
VI
DNW.C.4 G 3.0
on 6 NO /2
{N+OD outside NW} is not allowed)

Recommend: Minimum extension of NW beyond DNW for a better
A
E
fid 65 LO 009
noise isolation. The edge of DNW fully covered by NW has better

DNW.E.1® C 1.50
TE
noise isolation. Fig 4.6.2 is better than Fig. 4.6.1 from noise
isolation point of view. (except SBDDMY region)
en 12 G
Minimum extension of DNW region beyond {N+OD region outside

E
C /0
DNW.E.2 I 1.5
NW}
tia 1 IES
H 1
Recommend: Keep the tap of NW which is connected to DNW be in

DNW.R.3®U
reverse bias with RW or PW for low leakage application.
12
lI
DNW.R.4 It is not allowed to use DNW as a resistor.

nf
DNW.R.5 It is not allowed to use {NW interact DNW} as a resistor

(1) DNW and {NW interact with same DNW} must bias at same
or
DNW.R.6U potential.
(2) {NWs interact with same DNW} must bias at same potential.
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
N+
F
C
D N+
RW RW G
H
X X'
N+ I
H NW
E
RW(P-well in DNW) B
NW
A
DNW NW
TS
Cross Section (X-X') for NW, RW, and DNW relation

X X'
NW RW NW RW
M
NW N+
C
DNW PW
G
C
VI
on 6 NO /2
A
Fig. 4.6.1
fid 65 LO 009
TE
en 12 G
G
N+
C
C /0
D
tia 1 IES
RW RW
H 1
G
NW
X X'
12
lI
nf
B E
RW(P-well in DNW)
or
NW
A
m
DNW NW
Cross Section (X-X') for NW, RW, and DNW relation

at
X X'
NW RW NW RW NW
N+
io
IN
DNW PW
n
G
C
.
Fig. 4.6.2
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.2 Medium Vt NMOS (VTM_N) Layout Rules (Mask ID:

118)
VTM_N, Medium Vt NMOS Blocked Implant Definition
This layer is used to block VTM_N implant. If you use medium VT NMOS device in a circuit design,
TSMC will use this drawn layer with NW to generate VTM_N mask. VTM_N is a reverse tone of (NW
OR VTM_N).

TS
VTM_N.W.1 Minimum dimension of a VTM_N region. A H 0.74

H
M
VTM_N.W.2 Minimum PO gate dimension of a 1.8V medium Vt NMOS. B1 0.30

VTM_N.W.3 Minimum PO gate dimension of a 3.3V medium Vt NMOS. B2 H 0.60
C
VTM_N.S.1 Minimum space between two VTM_N regions. Merge if less than C H 0.44
C
0.44um.
H
VI
VTM_N.E.1 Minimum extension from a VTM_N region beyond an N+ OD region. D 0.26

on 6 NO /2
VTM_N.C.1 Minimum clearance from a VTM_N region to an N+ OD region. E H 0.70

A
H
fid 65 LO 009
VTM_N.C.2 Minimum clearance from a VTM_N region to an NW edge. (VTM_N F 0.43

TE
interact NW is not allowed.)

VTM_N.R.2 VTM_N interact NT_N is not allowed. (Butted is allowed)
en 12 G
C /0
VTM_N.R.3 A P+ GATE is not allowed in VTM_N region.

tia 1 IES
H 1
VTM_N.R.4 A bent PO region is not allowed in VTM_N region.

VTM_N.R.5 Minimum clearance from an OD region in VTM_N region to a PO on field I5 H 0.26
12
lI
oxide
nf
or
m
A Nominal
OD
at
Device OD
io
IN
VTM_N
n
C
C Poly E
.
VTM_N
I5
B1/B2
D
OD
F
PW NW
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.3 Medium Vt PMOS (VTM_P) Layout Rules (Mask ID:

117)
VTM_P, Medium Vt PMOS Blocked Implant Definition
This layer is used to block VTM_P implant. If you use medium VT PMOS device in a circuit design,
TSMC will use this drawn layer with NW to generate VTM_P mask. VTM_P is generated by (NW OR
VTM_N).
* Warning:
TS
3.3V medium Vt PMOS is not provided.

M

C
VTM_P.W.1 Minimum dimension of a VTM_P region. A I 0.74

I
C
VTM_P.W.2 Minimum PO gate dimension of a 1.8V medium Vt PMOS. B1 0.25

VI
I
on 6 NO /2
Minimum space between two VTM_P regions. Merge if less than

VTM_P.S.1 C 0.44
0.44um.
A
I
fid 65 LO 009
VTM_P.E.1 Minimum extension from a VTM_P region beyond a P+ OD region. D 0.26

I
TE
VTM_P.C.1 Minimum clearance from a VTM_P region to a P+ OD region. E 0.70

I
en 12 G
Minimum clearance from a VTM_P region to a PW edge. (VTM_P

VTM_P.C.2 F 0.43
C /0
interact PW is not allowed.)

tia 1 IES
VTM_P.R.2 VTM_P interact NT_N is not allowed.

H 1
VTM_P.R.3 VTM_P interact OD2 is not allowed.

12
lI
VTM_P.R.4 A N+ GATE is not allowed in VTM_P region.

A bent PO region is not allowed in a VTM_P region.
nf
VTM_P.R.5
VTM_P.R.6
Minimum clearance from an OD region in VTM_P region to a PO on
I5 I 0.26
or
field oxide
m
at
io
A Nominal
OD
IN
Device OD
n
C
VTM_P
.
C Poly E
VTM_P
I5
B1
D
OD
F
NW PW
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.4 HRI Poly Resistor Rule

Dummy layers RLPPDMY is required for performing logic operation and DRC HRI poly resistor
(please refer to T-018-MM-MB-001 and T-016-CM-MB-001).
PO.W.1_HRI Minimum width of a PO region for the high resistance poly resistor A J 1.00
RPO.O.1_HRI
Minimum and maximum overlap of a PP for high poly resistor (HRI) end
implant to a RPO region.
F K 0.30
It is strongly recommended that the HRI poly resistor width ≥ 1.0 um and
TS
RES.HRI.1® resistor number of square Nsq ≥ 2. (DRC will check the width and length
1um and 2um, respectively. Nsq is un-checkable)
M
RES.HRI.2®
Recommend: the maximum and minimum clearance from a RPO to a
B K 0.22
C
contact on HRI poly resistor

Recommend: the minimum clearance from HRI poly resistor to un-related
J
C
RES.HRI.3® C 0.26
implant regions
VI
on 6 NO /2
Recommend: the minimum clearance from a un-related RPO to HRI poly

J
A
RES.HRI.4® D 0.3
resistor
fid 65 LO 009
TE
Recommend: Contact pickup of HRI poly resistor should be in a single

RES.HRI.5®
column.
en 12 G
C /0
Recommend: Do not to use dog bone at the end of HRI poly resistor for
RES.HRI.6®U
tia 1 IES
contact pickup.
H 1
Recommend: the minimum clearance from a RLPPDMY to the HRI poly

J
12
lI
RES.HRI.7® E 0.26
resistor
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
CO CO
Poly Resistor /
HRI Resistor
Dog bone at the end of the poly
resistor and HRI poly resistor for
contact pickup is NOT suggested .
TS
** High Poly Resistor (HRI) with RPO

HRI
RPO P+ implant
M
L 0.26um0.26um
C
0.22
0.22um E 0.18um
C
0.10
0.10um
VI
CO CO
on 6 NO /2
0.10mm
0.10um Poly 0.3mm B=0.22um
F=0.3um B:0.22um
0.22
L
A
0.22
0.22um
A 1.0um
A:Width
Width
fid 65 LO 009
0.25mm
0.25um
TE
Contacts to pickup
en 12 G
poly resistor should be

C /0
Length a single column array !!
L0.3 um
tia 1 IES
L 0.26um
H 1
C D
12
RLPPDMY dummy layer

lI

nf
or
: RLPPDMY
m
at
: RPO
io
: PP
IN
: HRI
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.4.1 High Resistor Implant (HRI) Layout Rules (Mask ID: 133)
RLPPDMY (CAD layer: 134) is a dummy layer for HRI poly resistance of DRC and logic operation.

M
HRI.W.1 Minimum width of a HRI region. A 0.44
HRI.S.1 Minimum space between two HRI regions. Merge if less than 0.44um. B M 0.44
HRI.C.1 Minimum clearance from an HRI region to an NP region. C M 0.26
HRI.C.2 Minimum clearance from an HRI region to a PP region. D M 0.26
HRI.C.3 Minimum clearance from an HRI edge to an N-channel Poly gate. E M 0.32
M
TS
HRI.C.4 Minimum clearance from an HRI edge to a P-channel Poly gate. F 0.32
HRI.E.1 Minimum enclosure from an HRI region beyond a PO resistor region. G M 0.26
M
HRI.R.1 Overlap of NP and HRI is not allowed. H

C
HRI.R.2 Overlap of OD and HRI is not allowed. I

HRI.A.1 Minimum area of a HRI region. J M 0.3844
C
VI
on 6 NO /2
A
PP Poly HRI
HRI HRI
fid 65 LO 009
G
TE
en 12 G
B OD
C /0
OD Poly
F B
tia 1 IES
H 1
12
D
lI
nf
Poly
HRI C PP
or
A E
P+ OD
m
G N+ OD
at
NP
NP
io
H
IN
Poly
C
HRI
N-Well P-Well
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.5 Schottky Barrier Diode (SBD) Layout Rules

Dummy layer SBDDMY (CAD layer: 144;0))_is must in logic operation for 1.8V PLDD mask making.
SBD.W.1
Minimum width of an OD region to define the width of the P+ active
OD region of the SBD.
A M 1.00
SBD.W.1.1
Maximum width of an OD region to define the width of the P+ active
A’ N 16.00
SBD.W.2
Minimum length of an OD region to define the length of the P+ active
B M 1.00
TS
SBD.W.2.1
Maximum length of an OD region to define the length of the P+ active
B’ N 4.00
O
M
Minimum and maximum length of an OD region to define the length

SBD.W.3 C 0.42
of the NP OD region of the SBD.
C
The width of NP OD region of the SBD must be equal to P+ active

SBD.W.4 D
O
C
Space between P+ active OD region and NP OD region of the SBD.

VI
SBD.S.1 E 0.48
on 6 NO /2
SBD.E.1
Minimum and maximum extension from NW edge to an OD region
F O 0.80
A
used for the SBD.

fid 65 LO 009
Minimum extension of DNW beyond NW for a better noise isolation,

M
TE
SBD.E.1.1 G 0.60
as shown in Fig. 4.6.5.1
O
en 12 G
Minimum and maximum extension of a PP region beyond an

SBD.E.2 H 0.22
C /0
enclosed P+ active OD region of the SBD.

O
tia 1 IES
H 1
SBD.E.3 Minimum and maximum extension of “SBDDMY” beyond NW. I 0

Minimum and maximum overlap from a PP edge to a P+ active OD
O
12
SBD.O.1 J 0.22
lI
region of the SBD.

nf
The P+ active OD region of the SBD must be located between the NP

SBD.R.1 OD regions. The NP OD region must be located parallel with the
or
width of the P+ active OD region at left and right sides.

Maximum Finger Number (N) of the P+ active OD region of the SBD
N
m
SBD.R.2
should be 16, as shown in Fig. 4.6.5.3
at
Each NW of SBD should be surrounded by the P+ guard ring (P+

SBD.R.3
pickup ring).
io
Use "RFDUMMY" to fully cover SBD and P+ guard ring for LVS to
SBD.R.4
IN
recognize RF Device.
n
PP FOR SBD MUST BE A RECTANGLE RING. PP RECTANGLE RING MUST

SBD.R.5
C
SURROUND OD. OTHER SHAPE IS NOT ALLOWED.

.
Recommend: Use CO as many as possible on the SBD connection

SBD.R.7®U
for spice simulation accuracy.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Top View
P+ active OD region
NW
DNW F C
J
OD
F
NP H A(A’)
D
I
TS
PP
G E
CO
M
F B(B’)
C
SBDDMY
RFDUMMY
C
VI
on 6 NO /2
A
P+ Guard Ring
Cross-Section
fid 65 LO 009
TE
en 12 G
co
C /0
P+ N+ P+ P+ N+ P+
STI
tia 1 IES
H 1
Schottky Contact
12
NW
lI
nf
DNW
or
P Substrate
m
Fig. 4.6.5.1. SBD with DNW (single finger (N=1))

at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Top View
P+ active OD region
NW F C
J
OD
F
H A(A’)
TS
NP
D
I
PP
M
E
C
CO
F B(B’)
C
SBDDMY
VI
on 6 NO /2
RFDUMMY
A
fid 65 LO 009
TE
P+ Guard Ring
en 12 G
Cross-Section
C /0
tia 1 IES
H 1
co
12
lI
P+ N+ P+ P+ N+ P+
STI
nf
Schottky Contact
NW
or
m
P Substrate
at
io
IN
Fig. 4.6.5.2. SBD without DNW (single finger (N=1))

n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
NW OD SBDDMY CO
DNW NP PP RFDUMMY
Allowed
F C
J
TS
H
A(A’) I
D
F
M
E
C
G F B(B’)
C
VI
on 6 NO /2
Finger=1 Finger=N
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Not Allowed
Fig. 4.6.5.3. SBD with DNW (multi-finger (N>1)).
Document No.
Version
: T-018-LO-DR-001
: 2.8
NW OD SBDDMY CO
NP PP RFDUMMY
Allowed
F C
J
TS
H
A(A’) I
D
F
M
E
C
F B(B’)
C
VI
on 6 NO /2
Finger=1 Finger=N
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Not Allowed
Fig. 4.6.5.4 SBD without DNW (multi-finger (N>1))
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.6 MIM Capacitor Layout Rules

l The MIM capacitors must be placed between the top two metal layers (Mtop & Mtop-1). The
following layers are needed for MIM capacitor formation:
(a) Top plate of the MIM capacitor: A drawn CAD layer CTM (CAD layer: 67) is required. CTM
is not allowed for local interconnections.
(b) Bottom plate of the MIM capacitor: The M top-1 (the last Mx) is required to form the MIM
capacitors with CTM.
TS
l Vn is used for the connection between CTM and Mtop.

M
Three groups of layout rules are required for the MIM design:
a) Mx rules for MIM capacitor bottom metal; (Section 4.6.6.1)
C
b) CTM rules of the MIM capacitor top metal; (Section 4.6.6.2)

C
c) VIA rules of the MIM capacitor; (Section 4.6.6.3)

VI
on 6 NO /2
A
4.6.6.1 Mx Layout Rules for Capacitor Bottom Metal

fid 65 LO 009
TE
This section provides rules for the Mx (inter-metal layer) as the capacitor bottom metal. For 1P6M
en 12 G
process, the inter-metal layer M5 is used as the MIM capacitor bottom metal.
C /0
tia 1 IES
H 1
For DRC check, capacitor bottom metal is defined by SIZE CTM BY 2 INSIDE OF Mtop-1.
12
lI

P
nf
Maximum dimension (both width and length) of Mx as MIM

MIM_Mx.W.1 35
capacitor bottom metal
or
MIM_Mx.S.1
Minimum space between two Mx regions as MIM capacitor bottom
metal
B3 Q 0.80
m
Q
Minimum space between one Mx region as a dummy MIM capacitor
at
MIM_Mx.S.2 bottom metal and the other Mx region as MIM capacitor bottom B2 0.80
metal (Fig.4.6.6.2)
Q
io
Minimum extension of an Mx region as MIM capacitor bottom metal

MIM_Mx.E.3 E 0.40
IN
beyond a CTM region and dummy CTM region.

n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.6.2 Capacitor Top Metal (CTM) Layout Rules (Mask ID: 182)
Minimum width of a CTM region. R
R
CTM.W.1 A 4.00
CTM.W.2 Minimum width of a dummy CTM region. A1
R
0.40
CTM.S.1 Minimum space between two CTM regions. B 1.20
R
Minimum space between:
CTM.S.2 a) a dummy CTM and a CTM region (Fig.4.6.6.1) B1 0.80
b) a dummy CTM and a dummy CTM
S
Minimum density of all CTM (CTM+ dummy CTM) area
CTM.R.2
1. Density total CTM layout area/chip area.
2. Dummy CTM is required for those with CTM density less than 3.0% for
R 3%
better matching behavior and process uniformity.
TS
CTM.R.3 VIAn on dummy CTM is not allowed.

CTM.W.4
Maximum dimension (one side) of a CTM and dummy CTM region
T 30
M
R
For example, 26um x 31um CTM or dummy CTM is not allowed.
CTM.A.1 Minimum area of CTM region (include dummy CTM) 0.202
C
All CTM regions (include dummy CTM) cut Mx region as MIM capacitor bottom
CTM.R.1
metal is not allowed.
C
CTM.R.5 The MIM capacitor must be placed between the top two metal layers.
VI
on 6 NO /2
Circuit under MIM is allowed from process point of view.

But the parasistic and signal coupling effects should be considered by
A
designers. It is recommended to add metal shielding between MIM capacitor

fid 65 LO 009
U
CTM.R.4®
and underneath routing or circuit.
TE
One can refer to the section 4.6.6.4 for the circuit under MIM layout options for
en 12 G
model accuracy concern.

C /0
tia 1 IES
4.6.6.3 VIA Layout Rules for MIM Capacitor

H 1
12
lI
In this section, VIAn is the top VIA (size 0.36um) which follows the VIA5 rules. VIAtop-1 is the last inter
nf
VIA layer (size 0.26um) which follows the VIAx rules.

R
or
MIMVIA.S.1 Minimum space between two VIAn on the same CTM I 2.00
R
m
Minimum space between two VIAn on the same MIM capacitor bottom
MIMVIA.S.2 J 4.00
R
metal
at
MIMVIA.E.1 Minimum extension of a CTM region beyond a VIAn region. C 0.24

Minimum extension of an Mx region as MIM capacitor bottom metal
R
io
MIMVIA.E.2 D 0.12
R
beyond a VIA top-1 or a VIAn region.
IN
R
MIMVIA.C.1 Minimum clearance of a VIA top-1 or a VIAn to a CTM region. F 0.40
n
MIMVIA.R.1 Minimum density of VIAn on CTM 1%

C
MIMVIA.R.3 VIAtop-1 under CTM region is not allowed.

S
.
U Recommended: Minimum and maximum space between two VIAn on

MIMVIA.S.1® I 2.00
CTM for SPICE simulation accuracy.
MIMVIA.S.2®
U Recommended: Minimum and maximum space between two VIAn on
the MIM capacitor bottom metal for SPICE simulation accuracy.
J S 4.00
1. Please put the VIAn on the MIM capacitor bottom metal as many as
possible for the purpose of high Q value in high frequency
application.
U
MIMVIA.R.1® 2. Avoid using single VIAn to obtain lower parasitic resistance for more
S
accurate SPICE simulation.
S
3. VCC < 60 ppm is only guaranteed for VIAn space 4um (on MIM
capacitor bottom metal) and VIAn space 2um (on CTM).
Document No.
Version
: T-018-LO-DR-001
: 2.8
VIAn
VIAn F
E B J
C
I A B3
D
CTM D CTM
CTM F
VIA Top-1 M Top-1

M Top-1
TS
M Top-1 Inter-connection
M
C
Fig.4.6.6.1 Fig.4.6.6.2
C
VI
E
on 6 NO /2
B1 B2
A
fid 65 LO 009
CTM
TE
CTM A1 A1
en 12 G
C /0
tia 1 IES
Dummy CTM
H 1
Dummy CTM
12
lI
CTM.R.1
nf
Top plate metal

or
CTM
CTM
m
Bottom plate metal (include dummy CTM)

at
M top-1
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Layout Depiction of Rule MIMVIA.R.3
>> XX’ cross section <<
CTM
X X’
Mtop-1
VIAtop-1
VIAtop-1
TS
CTM
M
Mtop-1 Mtop-2
C
CTMDMY
C
VI
VIAtop-1 under CTM is NOT VIAtop-2

on 6 NO /2
A
ALLOWED !!
fid 65 LO 009
TE
en 12 G
¨ Layout Sample for MIM Capacitor (MIMVIA.S.1 &

C /0
MIMVIA.S.2):
tia 1 IES
H 1
12
lI
>> XX’ cross section <<

nf
or
X X’ Mn/UTM
m
at
VIAn
io
IN
CTM CTM
C
Mtop-1
.
Mtop-1
CTMDMY
VIAtop-1
VIAn
VIAtop-1
Mtop-2 Mtop-2
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.6.4 MIM Capacitor PDK Guidelines

The TSMC offered MIM spice model includes both RF and BB (base band) model, the user guideline of
the model are shown as following for better product yield, performance to achieve mixed-signal and RF circuit
design:
l The offered MIM model has 3T (three terminals) and 2T types. In the 3T case, the terminals are CTM,
CBM and ground terminal. In the 2T case, the terminals are CTM and CBM only.
l In the 3T case, it offers MIM with metal shielding layers and without metal shielding layers.
l The MIM with shield and without shield both include RF and BB models respectively.
l In order to keep the offered model accuracy, users cannot draw or generate any metal routing, dummy
metal or circuit into the region between the start and end layer region that had been defined by MIM
device model.
TS
The following table is the coverage of tsmc CM018G for RF SPICE model and PDK offerings of different
M
MIM type. It is separated by different model offering, one is for general purpose, the other one is for general
purpose II (GPII).
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
The special attention below are needed for the five MIM model types to enable MS/RF circuit design:
1. Type-a and Type-b allow metal routing under the shielding metal layers.
2. Type-c and type-d do not allow metal routing under Mx (as MIM bottom plate) region. In the
without shield MIM type (type-c and type-d), the substrate can be flexible such as: NW, PW, DNW
or NTN.
3. Type-e allows metal routing under the Mx (as MIM bottom plate) layer.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Type-a. In the RF 3T with shield MIM type, the model constructs from shield metal layer (Mx,top-2) to end
layer at Mtop. Under the shield metal layers of MIM, metal routing is allowed, but metal routing
above the end layer is not allowed.
Type-b. In the BB 3T with shield MIM type, the model constructs from shield inter metal layer (Mx,top-2) to
end at CTM layer. Metal routing under the shield metal layers or above the CTM layer is allowed.
Type-c. In the RF 3T without shield MIM type, the model constructs from substrate to end layer at Mtop.
Between the start and end layer region, user cannot draw any metal routing or dummy metal to
keep model accuracy.
Type-d. In the BB 3T without shield MIM type, the model constructs from substrate to end at CTM layer.
Between the start and end layer region, user cannot draw any metal routing or dummy metal.
Above the CTM layer, the metal routing is allowed.
Type-e. In the 2T MIM type, the model constructs from CBM to end at CTM layer. Metal routing under the
TS
Mcap-1 layer or above the CTM layer is allowed.

M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.7 Antenna Effect Prevention Layout Rules for MIM

Capacitor
4.6.7.1 Overview
Antenna effect for MIM capacitor should be taken into consideration for your MIM capacitor design. The layout
style of the MIM capacitor will impact its immunity to the antenna effect during process. Two major structures
are defined:
(A) Floating MIM capacitor:

Floating MIM capacitor means both nodes of the MIM capacitor do not connect to the OD region. This
structure offers high antenna ratio for both nodes. As illustrated in Fig.4.6.7.1, the MIM nodes can be either
TS
floating or tied to gate.

M
Floating
C
Mn or UTM
C
CTM
VI
on 6 NO /2
MIM Capacitor Bottom Metal

A
Good
fid 65 LO 009
TE
Fig.4.6.7.1 Schematic for floating MIM capacitor

en 12 G
C /0
(B) Single- node of the MIM capacitor is connected to the OD region:

tia 1 IES
H 1
The connection examples are illustrated in Fig.4.6.7.2. The plasma during top metal etching will stress MIM
capacitor more severely, as in Fig.4.6.7.2(A) -- the MIM capacitor bottom metal is connected to the OD
12
lI
region through VIAtop-1 and CTM is floating through VIAn.

nf
Floating or to gate Floating or to gate Floating or to gate

or
Mn or UTM
m
Mn or UTM Mn or UTM
CTM
at
CTM CTM CTM

MIM Capacitor MIM Capacitor MIM Capacitor MIM Capacitor
io
Bottom Metal Bottom Metal Bottom Metal Bottom Metal

IN
OD region OD region OD region OD region

C
.
(A) Bad (A’) Bad (B) Bad (C) Bad

Fig. 4.6.7.2 Schematic for single-node of the MIM capacitor connected to the OD region
Document No.
Version
: T-018-LO-DR-001
: 2.8
l To have better immunity for structure (B), it’s suggested adding protection diodes on the associated
terminal. In Fig.4.6.7.3, the protection diode is added on the CTM terminal and it can offer the other
plasma discharge path and therefore, the MIM capacitor can be less affected by plasma damage.
Floating or to gate
Mn or UTM
Mn or UTM
CTM CTM
MIM Capacitor MIM Capacitor

Bottom Metal Bottom Metal Protection
Diode
TS
OD region OD region
M
Bad Good
C
(Not allowed for 2fF MIM) (Not allowed for 2fF MIM)
C
VI
Fig. 4.6.7.3 Adding protection diode to improve the immunity to plasma damage
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.7.2 MIM Structure Recognition Methodology

MIM structure can be defined as balanced & unbalanced types and must follow different MIM antenna rules.
n Balanced MIM structure: A.R.MIM.1, A.R.MIM.4
n Unbalanced MIM structure: A.R.MIM.2, A.R.MIM.3, A.R.MIM.5
CBM (Capacitor Bottom Metal) = Mx as the capacitor bottom metal
For DRC check, capacitor bottom metal is defined by SIZE CTM BY 2 INSIDE OF Mtop-1
Below tables are for clear definition of balanced & unbalanced MIM structure.
A, B: Two terminals of MIM
All structure = balanced (float) + balanced (OD) + unbalanced
Unbalanced (A-OD): Unbalanced structure. Terminal A connected to OD and terminal B not connected to OD.
TS
Unbalanced (B-OD): Unbalanced structure. Terminal B connected to OD and terminal A not connected to OD.
Table 4.6.6.2.1 One metal layer above MIM

M
1st A, B Structure
C
Both A, B floating Balanced (float)

Both A, B connect to OD Balanced (OD)
C
VI
Others Unbalanced
on 6 NO /2
A
Table 4.6.6.2.2 Two metal layers above MIM

fid 65 LO 009
Recognization for
TE
1st A, B 2nd A, B
2nd Structure
en 12 G
Balanced (float) Balanced (float) Balanced

C /0
Balanced (OD) All structures Balanced

tia 1 IES
H 1
All structures Balanced (OD) Balanced

12
Unbalanced (A-OD) Unbalanced (B-OD) Balanced

lI
Other combinations Unbalanced

nf
Example of MIM structure recognition:

or
MD
MD
m
Mn Mn
at
CTM
CTM
io
CBM CBM
IN
OD region OD region
C
balance balance
.
Mn or UTM Mn or UTM
CTM CTM
CBM CBM
OD region OD region
balance balance
Fig. 4.6.7.2.1 Example for balance structure
Document No.
Version
: T-018-LO-DR-001
: 2.8
MD MD MD
Mn Mn Mn
CTM CTM CTM
CBM CBM CBM
OD region gate gate gate
OD region
unbalance unbalance unbalance

Mn or UTM Mn or UTM Mn or UTM
CTM CTM CTM
CBM CBM CBM

TS
OD region OD region gate gate gate
unbalance unbalance unbalance

M
Fig. 4.6.7.2.1 Example for unbalance structure

C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.7.3 Antenna Effect Prevention Layout Rules

The following table provides antenna effect prevention rules. The rules are for the metal layers above
the CTM. Take 1P4M process for example, only M4 should be checked.
Rule No. Description Antenna Ratio
CTM Node Capacitor bottom
A.R.MIM.1 Maximum ratio of UTM or cumulative Mn and MD (if 6000 6000

U metal node
used) perimeter area to the MIM capacitor when

neither CTM nor Mx as MIM capacitor bottom metal is
connected to OD.
TS
Both A.R.MIM.2 and A.R.MIM.3 must be followed simultaneously for the following conditions:
(1) Both CTM/CBM are connected to gate.
(2) One of CTM/CBM connects to gate and the other is floating.
U
M
A.R.MIM.2 Maximum ratio of UTM or cumulative Mn and MD (if OD area * 100

C
used) perimeter area to the MIM capacitor when 400 +

A) CTM is connected to OD. The OD area should be 2200
C
larger than, or equal to 0.203 um 2 . And

VI
on 6 NO /2
B) Mx as MIM capacitor bottom metal is floating or

connected to gate.
U
A
fid 65 LO 009
A.R.MIM.3 Maximum ratio of UTM or cumulative Mn and MD (if 100 OD area * 400 +
TE
used) perimeter area to the MIM capacitor when 2200

A) CTM is floating or connected to gate. And
en 12 G
B) Mx as MIM capacitor bottom metal is connected to

C /0
OD. The OD area should be larger than, or equal to

U
tia 1 IES
H 1
0.203 um 2 .
A.R.MIM.4 1. Maximum ratio of UTM or cumulative Mn and MD (if OD area * 400 + 2200
12
lI
used) perimeter area to the MIM capacitor when

CTM and Mx as MIM capacitor bottom metal are
nf
both connected to OD. The OD area should be

larger than, or equal to 0.203 um 2 .
or
A.R.MIM.5 Below conditions are not allowed For 2.0fF/um 2 MIM

m
capacitance.
A) CTM is not connected to OD and Mx as MIM
at
capacitor bottom metal is connected to OD.

B) CTM is connected to OD and Mx as MIM capacitor
io
bottom metal is not connected to OD.

IN
CBM directly connecting to OD through underneath

VIA is not allowed. For example, if M3 is CBM, CBM
C
through V2 directly connecting to OD is not allowed.

.
CBM should connect to M4 through V3 and then

connect to OD.
The thickness of M1-M5 is 5300Å.
The thickness of M6 is 9900Å.
Document No.
Version
: T-018-LO-DR-001
: 2.8
l The definition antenna ratio for each layer related to MIM capacitor:
(A) CTM node Antenna Ratio
ratio V
2 [(L1 +W1)x t ] / (W2 x L2)
L1 : metal length connected to CTM
W1 : metal width connected to CTM
t : metal thickness
W2 : connected CTM width
L2 : connected CTM length
Length (L1)
TS
t PR
Mn or UTM
M
W1
C
CTM
C
W2
VI
on 6 NO /2
MIM Capacitor
A
Bottom Metal
L2
fid 65 LO 009
TE
en 12 G
C /0
(B) The Antenna Ratio for Mx as MIM capacitor bottom metal

ratio V
2 [(L1 +W1)x t ] / (W2 x L2)
tia 1 IES
H 1
L1 : metal length connected to Mx as MIM capacitor bottom metal

12
W1 : metal width connected to Mx as MIM capacitor bottom metal

lI
t : metal thickness
nf
W2 : connected CTM width

L2 : connected CTM length
or
Note: For A.R.MIM.2 and A.R.MIM.4, only CTM connected to the OD will be calculated.
m
at
io
PR Length (L1)
IN
Mn or UTM
C
t PR
.
Mn or UTM
CTM
W1
W2
MIM Capacitor
Bottom Metal
L2
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.8 Ultra Thick Metal (UTM) Layout Rules (Mask ID:

186)
• UTM (20KÅ or 40KÅ thickness) is not allowed using with Mn (8KÅ thickness) in the same chip.
• UTM 20KÅ is not allowed using with UTM 40KÅ in the same chip.
• UTM is not supported in CM016G technology.
4.6.8.1 20KÅ UTM design rule

W
TS
UTM20K.W.1 Minimum width of a UTM region A 1.50

UTM20K.S.1 Minimum space between two UTM regions B W 1.50
W
M
UTM20K.E.1 Minimum extension of UTM region beyond VIAn C 0.30

Minimum extension of UTM region beyond VIAn at the end of
W
C
UTM20K.E.2 C1 0.45
UTM.
Minimum space between UTM metal lines with one or both
C
metal line width and length are greater than 16um; this also
W
VI
on 6 NO /2
UTM20K.S.2 includes all UTM metals attached to these areas or extending D 3.00
A
out for a distance of ≤ 1.0um (exclude the application for

fid 65 LO 009
inductor).
W
TE
UTM20K.A.1 Minimum area of a UTM region E 2.25

en 12 G
Minimum density of UTM area (exclude the application of

inductor).
C /0
W
1. Density is calculated as: Total metal layout area/ chip area.
tia 1 IES
H 1
UTM20K.R.1 2. Dummy pattern is required for those with UTM density less 30.0%
than 30 %. A dummy metal example, which TSMC used in
12
lI
qual. vehicle, is 2.0 um x 5.0 um dummy lines with line

nf
spacing of 2.0 um.

Minimum clearance from one UTM used as inductor device to
W
or
other UTM region. 50

UTM20K.C.1 ® F
1. IDDMY dummy layer is required to define the inductor device.
m
2. Three types of inductor layout are offered in TSMC PDK.

Minimum extension of dummy“layer ”INDDMY" region beyond
W
at
UTM20K.E.3 G 50
one UTM region which used as one inductor device.
io
Via and metal layers inside INDDMY region are not allowed except
UTM20K.I.1 underpass vias, metal interconnect and the substrate pick up node of
IN
the inductor.
C
Both active and passive devices inside INDDMY region are not
UTM20K.I.2
allowed.
.
note: For inductor devices offered in TSMC’s SPICE model, a native substrate region is adopted under the
inductor coil to minimize eddy currents. This native substrate is specified by use of an NT_N (CAD#129)
layer with the exact shape as the INDDMY layer. This NT_N drawn layer adds no process cost and no
extra mask. And it is included in the TSMC PDK and its associated sample layout document. For those
who prefer to draw inductors by themselves, designers have the option to draw a NT_N layer that exactly
matches the INDDMY dummy marker layer geometry.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4.6.8.2 40KÅ UTM design rule

UTM40K.W.1 Minimum width of a UTM region A W 2.60
UTM40K.S.1 Minimum space between two UTM regions B W 2.50
W
UTM40K.E.1 Minimum extension of UTM region beyond VIAn C 0.40
UTM40K.E.2
Minimum extension of UTM region beyond VIAn at the end of
UTM.
C1 W 0.45
Minimum space between UTM metal lines with one or both
metal line width and length are greater than 16um; this also
UTM40K.S.2 includes all UTM metals attached to these areas or extending D W 4.00
TS
out for a distance of ≤ 1.0um (exclude the application for

inductor).
W
M
UTM40K.A.1 Minimum area of a UTM region E 6.76

Minimum density of UTM area (exclude the application of
C
inductor).
W
1. Density is calculated as: Total metal layout area/ chip area.
C
UTM40K.R.1 2. Dummy pattern is required for those with UTM density less 30.0%
VI
on 6 NO /2
than 30 %. A dummy metal example, which TSMC used in

A
qual. vehicle, is 4.0 um x 4.0 um dummy lines with line

fid 65 LO 009
spacing of 3.0 um.

TE
Minimum clearance from one UTM used as inductor device to

other UTM region.
en 12 G
UTM40K.C.1
W 50
C /0
F
® 1. INDDMY dummy layer is required to define the inductor
tia 1 IES
H 1
device.
2. Three types of inductor layout are offered in TSMC PDK.
12
lI
Minimum extension of dummy“layer ”INDDMY" region beyond

nf
one UTM region which used as one inductor device.

Recommendations:
W
or
UTM40K.E.3 G 50
1. Keep this enclosure as small and as close to 50 um as possible.
m
2. Keep INDDMY regions for separate inductors located as

uniformly as possible over the whole chip area.
at
Via and metal layers inside INDDMY region are not allowed except
io
UTM40K.I.1 underpass vias, metal interconnect and the substrate pick up node of
the inductor.
IN
Both active and passive devices inside INDDMY region are not
UTM40K.I.2
allowed.
C
.
note: For inductor devices offered in TSMC’s SPICE model, a native substrate region is adopted under the
inductor coil to minimize eddy currents. This native substrate is specified by use of an NT_N (CAD#129)
layer with the exact shape as the INDDMY layer. This NT_N drawn layer adds no process cost and no
extra mask. And it is included in the TSMC PDK and its associated sample layout document. For those
who prefer to draw inductors by themselves, designers have the option to draw a NT_N layer that exactly
matches the INDDMY dummy marker layer geometry.
Document No.
Version
: T-018-LO-DR-001
: 2.8
A
A
> 16 um
UTM UTM D
B UTM
1.0 um
TS
VIAn
C
M
E
C
C1
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
Inductor (UTM)
C /0
tia 1 IES
H 1
UTM
12
lI
nf
F
or
G
m
Core circuit
at
io
IN
n
C
INDDMY/NT_N
.
Dummy layer “INDDMY” is needed when UTM is implemented as inductor.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5. Layout Guidelines for Latch-Up and I/O ESD

This chapter provides information about the following topics:
5.1 I/O ESD Protection Circuit Design and Layout Guideline
5.2 Layout Rule and Guideline for Latch-Up Prevention
If it is your first time to design ESD & Latch-Up circuit with TSMC design rules, it is strongly suggested treating
below guidelines as rules for higher successful rate of new design. If your design has been verified by silicon,
below content is guideline for your reference.
5.1 I/O ESD Protection Circuit Design and Layout

TS
Guideline
M
This Guideline is targeted to meet HBM>2KV and MM>200V ESD spec.

C
The ESD performance also depends on layout-style, which cannot be completely described in this guideline.
• The ESD implant mask ID is 110 for 5.0V I/O designed by 5.0V NMOS. This layer is a drawing layer.
C
VI
• The ESD implant mask ID is 111 for 3.3V and 5V High Voltage Tolerant I/O designed by 2.5V and
on 6 NO /2
3.3V NMOS.
A
• For 5V High Voltage Tolerant I/O designed by 3.3V NMOS (up to 5V at I/O pad) (abbreviated to 5VT
fid 65 LO 009
NMOS below) & 3.3V High Voltage Tolerant I/O designed by 2.5V NMOS (up to 3.3V at I/O pad)
TE
(abbreviated to 3VT NMOS below), ESD implant is required unless special design by customer.
en 12 G
TSMC will use ESD dummy layer (ESD3DMY, see Rule no. 28) to generate ESD mask (no. 111) by
C /0
logic operation.
tia 1 IES
H 1
n For customers who use tsmc-style ESD design structure, additional ESD implant (mask no.
111) is required to improve ESD performance.
12
lI
n For customers who use their own ESD design structure, or do not use 3VT & 5VT NMOS, it
nf
depends on customer’s option to implement ESD implant.

n Dummy layer in Rule no. 28 is required to guarantee ESD performance.
or
m
I/O design style CAD layer (234:0) ESD mask (no.111)

at
tsmc-style I/O w/i 3VT or 5VT NMOS Drawn Require Generated by tsmc Logic operation
io
tsmc-style I/O w/o 3VT or 5VT NMOS No No

IN
Non tsmc-style ESD Depend Depend

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.1.1 General Guideline for ESD Protection

It is not allowed to use thick oxide transistor to protect thin oxide circuit; cannot
ESD.1gU
use thin oxide transistor to protect thick oxide circuit.
NMOS and PMOS for ESD protection needs to follow the specific finger type
ESD.2gU See Fig.1
structure with unique finger dimension and layout style.
ESD.3gU
Minimum N/PMOS total finger width for 5.0V, 3.3V, 2.5V, 1.8V and 1.5V when
used as I/O buffer.
X 360um
ESD.4gU
Minimum NMOS total finger width for 5.0V, 3.3V and 2.5V when used as power
X 360um
X
clamp device.
TS
ESD.5gU
X
Minimum NMOS total finger width for 1.8V and 1.5V power clamp device. 720um
ESD.6g Unit finger width of NMOS and PMOS for I/O buffer and power clamp device. G 15 ~ 60um (Fig.1)
ESD protection device should be surrounded by the appropriate pick-up.The
M
ESD.7gU See Fig.1

other devices should be placed outside this pick-up as illustrated in Fig.1.
C
It is strictly prohitibied to butting or inserted Substrate/Well pick-up’s for ESD

ESD.8g See Fig.2
N/PMOS. (see Fig.2)
C
OD area of edge side of ESD devices or I/O buffers should be Source or Bulk
VI
ESD.9gU rather than Drain (see Fig.1), to avoid the unwanted parasitic bipolar effect or See Fig.1
on 6 NO /2
abnormal discharge path in ESD zapping.

A
Space between any two OD areas of the same type (N to N, or P to P) with one
fid 65 LO 009
of the following connections should be larger than 2.4um, or a base guard ring
TE
(pickup ring) should be inserted in between them:

ESD.10gU
en 12 G
One connects to a pad, and the other connects to another pad.

C /0
One connects to a pad, and the other connects to VDD or VSS.

One connects to VDD, and the other connects to VSS or another separated
tia 1 IES
H 1
VDD.
X 200 Ω
12
ESD.11gU Minimum resistance of I/O as R in Fig.3.

lI
See Fig.3
At least the NMOS4 in Fig.3 should be added after resistor R as the secondary
nf
ESD protection. For better ESD immunity, both PMOS to VDD and NMOS to
or
VSS should be used there if no conflict with circuit operation. ESD implant can
not be used in the secondary protecting devices. The suggested device sizes for
m
secondary protection are:

For 5.0V I/O: NMOS is 20/0.60 and PMOS is 20/0.60 (Use 5.0V devices)
ESD.12gU
at
io
IN
n
If the performance of CDM is concerned, the secondary protection should be put See Fig3
C
close to the device gate being protected.

Contacts and vias should be used as many as possible, and at least capable of
.
ESD.13gU
bearing 100mA DC current (please calculate it from EM data).
ESD.14gU
The minimum total width of metal lines connecting bond pad and ESD protecting
I X 20um (See Fig1)
X
devices. (see Fig.1)
U
ESD.15g The minimum VSS and VDD power ring metal width. 50um
Bypass discharge cells should be inserted between separated VDD’s and VSS’s
to ensure no ESD damage to internal circuits. It is of special importance to the
ESD.16gU isolated powers used only by a small circuit (<5K gates) The connections are
illustrated in Fig.4.
(For more details, please see “Tips for Power Bus”.)
All nodes directly connecting to ESD discharge path should follow ESD
ESD.17gU
dimension rules.
Minimum gate length for ESD device when used as I/O buffer and Power
ESD.18g Lg Table 1
Clamp.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 1 Lg for I/O buffer and Power Clamp

NMOS PMOS ESD IMP *
1.5V Device 0.2 0.2
1.8V Device 0.25 0.25
2.5V Device 0.3 0.25 0.3
3.3V Device 0.4 0.3 0.4
5.0V Device 0.6 0.6 0.9
- ESD IMP* for 2.5V & 3.3V device and below: ESD mask (no. 111) can be generated by tsmc internal
logic operation, using CAD layer (234:0), see ESD rule 28).
- ESD IMP* for 5.0V device: ESD mask (no. 110) is a drawing layer.
Table 2 RPO layout vs. ESD protection devices

TS
No. 1 2 3 4 5
3.3V/2.5V/1.8V/1.5V 5V/3.3V/2.5V/1.8V/1.
M
1.8V/1.5V
5.0V NMOS used in NMOS used in 5V PMOS used in
3.3V/2.5V cascade NMOS used in
Regular I/O & Regular I/O & Regular I/O &
C
Device Type NMOS used in High VDD/VSS

VDD/VSS Power 3.3V/2.5V NMOS 3.3V/2.5V PMOS
Voltage tolerant IO Power
protection used in VDD/VSS used in High
C
protection
Power protection Voltage tolerant I/O
VI
on 6 NO /2
RPO width on drain side

1.95 1.95 1.95 1.95 No
(min.)
A
fid 65 LO 009
st Completely cover Overlap poly by 0.05 Overlap poly by 0.05 Overlap poly by 0.05
RPO to 1 poly space No
TE
poly or 0.06 or 0.06 or 0.06

st nd
en 12 G
1 poly to 2 poly
0.25 - - - -
spacing
C /0
nd
tia 1 IES
Overlap 2 poly by
H 1
nd
RPOto 2 poly space - - - -
0.05 or 0.06
12
lI
SDI Must (58:0) Must (58:0) Must (58:0) Must (58:0) Must (58:0)
Dummy layer for DRC
nf
ESD2DMY (137:0) ESD2DMY (137:0) ESD2DMY (137:0) ESD2DMY (137:0) -

(see ESD rule 27)
or
ESD implant (mask 110)

Optional
Required drawing layer Forbidden Forbidden Forbidden Forbidden
m
(ESD: (30:0))
(see section 5.1.3)
at

Optional
Required dummy layer ESD3DMY (234:0) Forbidden Forbidden Forbidden
io
(ESD3DMY(234:0))
(see ESD rule 28)
IN
Illustration Fig.5b Fig.6b Fig.6b Fig.6b Fig.6c

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

NMOS and PMOS of I/O buffer should have a non-salicide area on
ESD.19g drain side, that is, RPO mask should block drain side of device
(except contact region should keep silicided).
For high voltage tolerant I/O designed by 3.3V/2.5V NMOS (see N1
and N2 in Fig.5a):
0.05 or 0.06um
ESD.20g RPO should cover all inactive poly gates and extend to active region M =
See Fig.5
(Poly spacing= 0.25um). Minimum and maximum overlap from RPO
to the active poly gate. (see Fig.5b).
For regular I/O designed by 5V, 3.3V, 2.5V, 1.8V and 1.5V NMOS
(see N3 in Fig.6a): 0.05 or 0.06um
=
TS
ESD.21g N
Minimum and maximum overlap from RPO on the drain side to poly See Fig.6
gate. (see Fig.6b)
M
For all PMOS (see P1 in Fig.5a and P3 in Fig.6a):

0.05 or 0.06um
C
ESD.22g Minimum and maximum overlap from RPO on the drain side to poly N =
See Fig.6
gate. (see Fig. 6b)
C
For 5V, 3.3Vand 2.5V power clamp devices:

VI
on 6 NO /2
ESD.23g Minimum and maximum overlap from RPO on the drain side to poly N = 0.05 or 0.06um
gate. (see Fig.6b)
A
fid 65 LO 009
Y
Minimum width of RPO on drain side (X) for 5V, 3.3V, 2.5V, 1.8V 1.95um
TE
ESD.24g and 1.5V NMOS and PMOS, excluded 1.8V and 1.5V NMOS when X (in Fig.5b and
en 12 G
used as power clamp device Fig.6b)

C /0
Y
0.5um
tia 1 IES
H 1
ESD.25g Z (in Fig.5b and

NMOS and PMOS (Except ESD.26g)
Fig.6b )
12
Y
lI
Minimum clearance from poly edge to CO edge on D/S side for 1.8V 0.25um
ESD.26g Y
and 1.5V used as power clamp device. in Fig.6c
nf
For RPO DRC purpose, we need a dummy layers in ESD protection

or
device. The layers should cover all ESD protection devices.

m
ESD2DMY is for the cascade NMOS in high voltage tolerant I/O

at
ESD.27g designed by 3.3V/2.5V NMOS (see Fig.5b), regular IO designed by

5V/3.3V/2.5V/1.8V/1.5V NMOS and PMOS (see Fig.6b), power
io
clmap designed by 5V/3.3V/2.5V NMOS.

IN
By definition, it is adopted CAD Layer (137:0) for ESD2DMY.

C
ESD implant is required for High Voltage Tolerant I/O designed by

.
3.3V NMOS device for 5V signal input or 2.5V NMOS device for
3.3V signal input at I/O pad.
ESD mask (No. 111) can be generated by logical operation. It is not
allowed to use ESD mask (No. 111) for 5V NMOS device.
ESD.28g
ESD3DMY is for the cascade NMOS in high voltage tolerant I/O
designed by 3.3V/2.5V NMOS (see Fig.5b).
By definition, it is adopted CAD layer (234:0) for ESD3DMY.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.1.2 Additional Two ESD Structures

(It is strongly recommended to adopt the structure (described in section 5.1.1) for tapeout.)
In this section, we keep supporting the two previous kinds of ESD structures (design rule before V2.7).
5.1.2.1 Regular I/O Buffer for 5.0V, 3.3V, 2.5V, 1.8V,1.5V PMOS
& 1.8V NMOS
ESD.38U
Minimum total finger width for 5.0V, 3.3V, 2.5V,1.8V,1.5V PMOS &
1.8V NMOS used as regular I/O buffer
Z 360um
TS
NMOS and PMOS of I/O buffer should have a non-salicide area on

ESD.29g drain side, that is, RPO mask should block drain side of device
(except contact region should keep silicided).
M
ESD.30g
For regular 1.8V I/O in NMOS region (see N3 in Fig.6a) :
P Z 0.45um
C
Minumum clearance from RPO to poly. (see Fig.7a) See Fig.7a
Z 0.45um
For 5V/3.3V/2.5V/1.8V/1.5V PMOS (see P1 in Fig.5a and P3 in
C
ESD.31g Fig.6a) : P
See Fig.7a
VI
Minumum clearance from RPO to poly. (see Fig.7a)

on 6 NO /2
Minimum width of RPO on drain side (X) for 1.8V NMOS and
Z 1.5um
A
ESD.32g X
5V/3.3V/2.5V/1.8V/1.5V PMOS. (see Fig.7a)
fid 65 LO 009

Z 0.5um (in Fig.7a)
TE
ESD.33g Z
NMOS and PMOS
en 12 G
ESD.18g Minimum gate length for ESD device when used as I/O buffer. Lg Table 1
C /0
tia 1 IES
H 1
5.1.2.2 Power Clamp (Ncs) for 5V, 3.3V, 2.5V

12

lI
ESD.39U
Minimum total finger width for 5V, 3.3V, 2.5V NMOS used as Power
Z 360um
nf
Clamp (Ncs)
5V, 3.3V and 2.5V NMOS devices when used as power clamp
or
devices (see Ncs in Fig.5a and Fig.6a), the RPO can fully cover the
ESD.34g Fig.7b
m
uncontacted poly gate, source/drain (except contact region should

keep silicided). (see Fig.7b)
at
Minimum width of RPO on drain side (X) for 5V, 3.3V and 2.5V
NMOS devices when used as power clamp devices.
Z 1.95um (in Fig.7b)
io
ESD.35g X
Ncs Drain is defined as (((OD INTERACT GATE) NOT PO) AND
IN
ESD1DMY) which not connect to PW Pickup

C
Z 0.5um (in Fig.5g)

5V, 3.3Vand 2.5V NMOS devices when used as power clamp
.
ESD.36g devices. Z
Ncs Source is defined as (((OD INTERACT GATE) NOT PO) AND
ESD1DMY) which connect to PW Pickup
Minimum gate length for ESD device when used as power clamp
ESD.18g Lg Table 1
devices.
For RPO DRC purpose, we need a dummy layers for 5V, 3.3Vand
2.5V NMOS devices when used as power clamp devices. The
ESD.37g layers should cover all ESD protection devices.
ESD1DMY is for this purpose (see Fig.7b).By definition, it is
adopted CAD layer (136:0) for ESD1DMY.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 3 RPO layout vs. ESD protection devices for section 5.1.2
No. A1 A1 A2 A3
5V/3.3V/2.5V/1.8V/1.
5V PMOS used in
5.0V NMOS used in 3.3V/2.5V NMOS
Regular I/O & 1.8V/1.5V NMOS
Device Type VDD/VSS Power used in VDD/VSS
3.3V/2.5V PMOS used in Regular I/O
protection Power protection
used in High
Voltage tolerant I/O
RPO width on drain side (min.) 1.5 1.5 1.95 1.95
st Completely cover Completely cover

Minimum RPO to 1 poly space 0.45 0.45
poly poly
SDI Must (58:0) Must (58:0) Must (58:0) Must (58:0)
TS
Dummy layer for DRC

- - ESD1DMY (136:0) ESD1DMY (136:0)
M
(see ESD rule 37)

C
Optional
Required drawing layer Forbidden Forbidden Forbidden
(ESD: (30;0))
C
(see section 5.1.3)

VI
on 6 NO /2

Optional
Required dummy layer Forbidden No required Forbidden
A
(ESD3DMY(234;0))
fid 65 LO 009
(see ESD rule 28)

TE
Illustration Fig.7a Fig.7a Fig.7b Fig.7b

en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
n Tips for Power Bus

The ESD Protection design is not only for the input, output, or power pins; but also for the whole chip
to avoid ESD damage to internal circuits. Especially in the mixed signal IC, separated digital and
analog powers are used, so the interface devices between the digital and analog circuits are
sensitive to ESD damage.
To prevent the problem, inter-power ESD protection circuits should be added according to the
following suggestions to have better ESD immunity:
1. Using ESD clamping circuits to provide discharge paths between VDD and VSS under ESD stress.
2. Use low voltage transistor in ESD clamp for low voltage circuit protection; high voltage transistor
TS
for high voltage circuit protection.

3. Using ESD conduction circuits connecting separated power lines, as illustrated in Fig. 4.
M
For applications of ESD conduction circuits, below approach is recommended.

C
If there are too many power pairs, structure in Fig.4 is recommended. All power lines are connected
C
through ESD conduction circuits to a Common VDD and VSS.

VI
on 6 NO /2
A
For VDD to VSS ESD clamping circuit, NMOS with gate soft-pulled to VSS is recommended.
fid 65 LO 009
TE
The recommended application guidelines for ESD conduction circuit and ESD clamping circuit are:
en 12 G
1. At least 1 Clamping and/or Conduction cell inserted every 1000um of power line.
C /0
tia 1 IES
H 1
2. All the layout guidelines are the same as those for IO buffers. An additional guideline is the source
12
side should be treated the same as drain side since ESD pulse can comes from either side.
lI
nf
3. The suggested width for the ESD clamping NMOS is 480um and length is the same as in Table 1.
or
4. The suggested layout for ESD conduction diodes is finger type with total area larger than 2500um2,
m
and periphery larger than 1100um. OD’s and Contacts for both ends of the diode should be inter-
digital layout to keep low series resistance and uniform current flow.
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
N Pick-up for PMOS I=i1+i2+i3+…

P Pick-up for NMOS
i1 i2 i3
Drain G
TS
Source
M
Source
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
FFiigg 11.. E
ESSD
DCCeellll LLaayyoouutt P
Paatttteerrnn ((FFiinnggeerr TTyyppee))
en 12 G
C /0
tia 1 IES
H 1
12
lI
RPO Pick-up Pick-up RPO Pick-up

nf
or
m
at
io
IN
n
C
.
Drain Source Drain

Source Source Source
To Pad To Pad
FFiigg 22.. B
Buuttttiinngg oorr iinnsseerrtteedd ppiicckkuupp bbeettw
weeeenn ssoouurrccee ddiiffffuussiioonn ooff E
ESSD
D ddeevviicceess aarree
pprroohhiibbiitteedd..
Document No.
Version
: T-018-LO-DR-001
: 2.8
VDD
P5 P5 P4
[)
R (≥200
RPO
PAD Ncs
N5 N5 N4 s
RPO
TS
M
Secondary protection
C
VSS
C
VI
on 6 NO /2
FFiigg 33.. E
ESSD
D pprrootteeccttiioonn cciirrccuuiitt
A
fid 65 LO 009
TE
VDD (Comm.)
en 12 G
C /0
tia 1 IES
H 1
ESD ESD ESD

Conduction Conduction Conduction
12
lI
Circuit VDDA Circuit VDDB Circuit VDDC

nf
or
m
ESD ESD ESD

Circuit I Clamp Circuit II Clamp Circuit III Clamp
at
io
IN
n
C
ESD ESD ESD

Conduction VSSA Conduction VSSB
.
Conduction VSSC
Circuit Circuit Circuit
VSS (Comm.)
FFiigg 44.. S
Scchheem
maattiicc ooff aa M
Muullttiippllee P
Poow
weerr E
ESSD
DPPrrootteeccttiioonn D
Deessiiggnn
Document No.
Version
: T-018-LO-DR-001
: 2.8
Only for 5VT & 3VT by using 3.3V device & 2.5V device
(a) High Voltage tolerant I/O Schematic (b) N1&N2 Layout Pattern
VDD
SDI for all ESD
Signal VDD Signal
Floating
Signal
RPO
TS
RPO RPO
P1 Ncs
PAD N1 Drain
M
N2 Source
C
RPO
N2 Source
X X
C
VDD
VI
on 6 NO /2
N1
Z
A
Z
fid 65 LO 009
\
TE
Signal 1K
N2
en 12 G
C /0
tia 1 IES
H 1
0.05um or
0.06um
12
lI
VS 0um
To Pad 0um M
nf
N1 Poly Gate (Inactive)

or
N2 Poly Gate
m
ESD2DMY for DRC check

at
ESD3DMY (generated ESD mask)

for 5VT and 3.3VT NMOS
io
IN
The Layout of P1 and Ncs are described in Fig6.b

C
.
FFiigg 55.. H
Hiigghh V
Voollttaaggee ttooeerraanntt II//O
OSScchheem
maattiicc &
&PPuullll ddoow
wnn C
Caassccooddee N
NMMO
OSS LLaayyoouutt
Document No.
Version
: T-018-LO-DR-001
: 2.8
(a) Regular I/O Schematic (b) P1, P3, N3 &Ncs Layout Pattern
RPO
Signal
RPO
RPO
P3 Ncs
PAD X X
Z Z
TS
RPO
\
M
Source
Signal 1K
Drain
Source
C
N3
C
VI
on 6 NO /2
A
0um N 0um
fid 65 LO 009
0.05um or
0.05um To Pad 0.06um
TE
en 12 G
C /0
ESD2DMY for DRC check

tia 1 IES
H 1
ESD3DMY for Mask 111 (optional)

ESD Mask 110 (optional)
12
lI
SDI for all ESD

nf
(c) Ncs for 1.8V & 1.5V Layout

or
m
Source Drain Drain Source

at
io
IN
L
C
L L L
.
SDI
Y
Y
FFiigg 66.. R
Reegguullaarr II//O
OSScchheem
maattiicc &
&MMO
OSS LLaayyoouutt
Document No.
Version
: T-018-LO-DR-001
: 2.8
(a) P1, P3 & N3 Layout Pattern (b) Ncs Layout Pattern
P1, P3, N3 Ncs
RPO RPO
X X
TS
Z Z X X
Z Z
M
C
Drain
Source
Source
Source
Drain
Source
C
VI
P
on 6 NO /2
0.45um
A
fid 65 LO 009
To VDD 0um
TE
To Pad 0.45um
en 12 G
0um
C /0
ESD1DMY
tia 1 IES
H 1
12
lI
SDI for all ESD

nf
SDI for all ESD

o rm
FFiigg 77.. A
Adddduuttiioonnaall LLaayyoouutt P Paatttteerrnn
at
IItt iiss S
Strongly recommended to adopt the structuress ((ddeessccrriibbeedd iinn sseeccttiioonn 55..11..11))
t ro n g l y re c o m m en d e d t o a d o p t t h e s t ru c t u re
ffoorr ttaappeeddoouutt
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.1.3 ESD Implantation Rule (Mask ID: 110, only for 5V

NMOS device)
This implantation layer is an optional layer to improve I/O ESD performance and it is only for 5V I/O NMOS
transistors. It is important that for 5V I/O NMOS transistors, customer has to draw the ESD layer (CAD layer
30) and follow the instructions in the following table to generate ESD mask (mask ID: 110) accordingly. For
2.5V and 3.3V I/O NMOS transistors, TSMC uses ESD3DMY (please refer ESD.28g) to generate ESD mask
(mask ID: 111) by logic operation. Customer does not have to draw the ESD layer. For example, 2.5V and
3.3V I/O NMOS transistors will be damaged if ESD (30;0) or 5V ESD mask (mask ID: 110) is used
TS

ESD.W.1 Minimum width of an ESD implant region. A ] 0.6 um
Minimum space between two ESD implant region.
] 0.6 um
M
ESD.S.1 B
Merge if the space is less than 0.6 um.
] 0.3 um
C
Minimum space between ESD implant and NP or PP

ESD.S.2 B1
region.
] 0.6 um
C
Minimum clearance from an ESD implant region to an

ESD.C.1 C
VI
on 6 NO /2
NP OD region
Minimum clearance from an ESD implant region to a N-
] 0.45 um
A
ESD.C.2 D
channel PO gate
fid 65 LO 009
Minimum overlap from an ESD implant edge to an OD

] 0.45 um
TE
ESD.O.1 E
region
en 12 G
ESD.C.4
Minimum clearance from an ESD implant region to an
F ] 0.6 um
C /0
ESD OD region
] 0.25 um
tia 1 IES
H 1
Minimum extension of an ESD implant region beyond

ESD.E.1 I
an ESD implant OD region.
12
^ 0.0 um
lI
Clearance of an ESD implant region over an OD with

ESD.C.5 J
PP region to define CO with the same potential.
nf
Overlap of ESD implant and PP on the same Poly

ESD.R.1
region is not allowed.
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
ESD IMP
I
ESD ESD
B1
OD OD OD
E
C
TS
NP
M
C
PO F B A
C
VI
on 6 NO /2
A
fid 65 LO 009
OD
TE
J OD
D
en 12 G
F
C /0
tia 1 IES
H 1
P+
ESD
12
lI
P-Well
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.2 Layout Rule and Guidelines for Latch-Up

Prevention
5.2.1 Special Definition in Latch-up Prevention
Term Definition
I/O pads Do not include Vdd pad and Vss pad.
Include NMOS, PMOS, de-coupling capacitors and varactor
Internal circuit
that do not connect to an IO pad.
Complete un-broken ring-type OD and M1 with CO as many
TS
Guard-ring
as possible, connected to Vdd or Vss.
Complete un-broken ring-type (NP AND OD) and M1 with CO
M
N+ guard-ring
as many as possible, connected to Vdd.
C
Complete un-broken ring-type (PP AND OD) and M1 with CO

P+ guard-ring
as many as possible, connected to Vss.
C
NMOS cluster A group of NMOSs

VI
on 6 NO /2
PMOS cluster A group of PMOSs

A
fid 65 LO 009
DRC uses the 2 following methods to recognize a MOS/ ACTIVE which connects to an I/O pad:
TE
1) MOS/ ACTIVE in SDI

en 12 G
2) MOS/ ACTIVE connect to an I/O pad by connection from pad metal

C /0
tia 1 IES
H 1
12
lI
NMOS NMOS S
nf
or
m
NMOS
at
io
IN
n
C
.
Fig. 5.2.1 Example of NMOS/PMOS cluster
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.2.2 Latch-up Dummy Layers Summary

5.2.2.1 SDI Dummy Layer
SDI (CAD layer: 58) is a DRC layer but not for mask making. It is required to cover all the OD regions of the
ESD related circuits (Regular IO, high voltage tolerant I/O, Power Clamp), including MOS and diode, that are
connected to the pads. SDI is not necessarily to cover and Well STRAP or ESD guard ring.
5.2.2.2 LUPWDMY Dummy Layer (CAD layer: 255;1)

LUPWDMY is a dummy layer to waive these guidelines, LUP.1g, LUP.2g, LUP.3.1g, LUP.3.2g, LUP.3.3g,
LUP.3.4g, LUP.3.5g, LUP.4g, LUP.5.1g, LUP.5.2g, LUP.5.3g, LUP.5.4g, LUP.5.5g.
l Condition:
n It is not recommended to use this layer before silicon is proven at the package.
TS
n Please consult TSCM if you would like to follow it as rules and have DRC violations before tapeout.
l Usage:
M
n Draw LUPWDMY to fully cover MOS/ACTIVE OD/ Diode regions that are connected to I/O pads,
C
including the source, gate, drain, and diode, but not necessarily to cover Well STRAP, guard-ring.
n It is for DRC usage but not a tapeout required CAD layer.
C
VI
on 6 NO /2
NP/PP
A
fid 65 LO 009
TE
OD
en 12 G
SDI, LUPWDMY
C /0
tia 1 IES
H 1
12
Source Drain
lI
PO Guard-ring
nf
or
Fig. 5.2.2 Example of SDI/LUPWDMY.

m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.2.3 DRC methodology for Latch-up rules

5.2.3.1 DRC methodology for LUP.1
• DRC use the following features to find out the devices for LUP.1:
1. The Active/MOS OD covered by SDI (58;0).
2. The Active OD which is connected to(#1) I/O PAD.(#2)
3. The following cases are excluded :
I. The Active OD is used for Resistor.
II. The Active/MOS OD is covered by LUPWDMY (255;1).
TS
• #1: DRC use the following features to check the connectivity :

M
1. Build-up the connection by Metal, Via, CB, and CBD

C
2. The connection is broken by NW resistor and OD/PO w/o Silicide resistors for Latch-Up rule checks.
C
VI
on 6 NO /2
• #2 : DRC use the following features to distinguish Power & I/O PAD :
A
1. By default, DRC will recognize power PAD according to the connectivity of MD, VIAD, CB and CBD to
fid 65 LO 009
STRAP.
TE
2. Check the PAD with “power text” to recognize power PAD.

en 12 G
C /0
I. Control by the switch of #DEFINE_PAD_BY_TEXT. The switch is off by default.

tia 1 IES
H 1
II. Default power text name is “Vdd” “Vss” “a Vdd” “a Vss” … (same as LVS)
12
3. Check the PAD with “power dummy layer” to recognize power PAD.
lI
I. VDDDMY(255;4): Dummy Layer for Power(Vdd) PAD

nf
II. VSSDMY(255;5): Dummy Layer for Ground(Vss) PAD

or
4. Except for recognized Power PAD, all the others are I/O PAD.
m
at
• The guard ring can not share for different type devices.
OD
io
IN
OD
n
NW
NW
C
Fail !
.
NMOS
Fig. 5.2.3.1 example of illegal guard ring
Document No.
Version
: T-018-LO-DR-001
: 2.8

• DRC use the following features to find out the devices for LUP.2:
1. The MOS OD within 20um space from the Active/MOS OD for LUP.1 check
2. The following cases are excluded:
I. The MOS OD is floating without any contact over gate and S/D.
II. The MOS OD is covered by LUPWDMY (255;1)
III. The NMOS is inside DNW, and the NW over DNW is the same as the NW of relative PMOS which
is 8um away from the NMOS.
IV. The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS,
TS
but these two NWs are connected.

M
III IV. M1
. NW NW
C
DNW DNW
C
VI
> 8um
on 6 NO /2
A
NMOS PMOS NMOS PMOS

fid 65 LO 009
TE
Fig. 5.5.3.2 example of LUP.2 III and IV

en 12 G
C /0
5.2.3.3 DRC methodology for LUP.3 group

tia 1 IES
H 1
• DRC use the following features to find out the devices for LUP.3 group:
12
lI
1. Find out the MOS OD for LUP.1 check

nf
2. The following cases are excluded:

I. The excluded case “I” and “II” in LUP.1.
or
II. The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS, but
m
these two NWs are connected.

at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

• DRC use the following features to check the guard-ring width.
1. Find out the Active/MOS OD for LUP.1 & LUP.2 check.
2. The devices should be placed inside a complete guard-ring with width >= 0.42um.
Fail Fail !
>= 0.42um >= 0.42um
!
OD NW
OD
TS
PMOS PMOS NW
<
M
0.42um
Pass
C
Pass
!
C
>= 0.42um >= 0.42um

!
VI
on 6 NO /2
OD <
A
0.42um >= 0.42um

fid 65 LO 009
OD
TE
PMOS PMOS
en 12 G
PMOS PMOS
NW
C /0
NW
tia 1 IES
H 1
Fig. 5.2.3.3 example of LUP.4

12
lI
nf
5.2.3.5 DRC methodology for LUP.5 group

or
• DRC use the following features to find out the devices for LUP.3 group:
1. Find out the MOS OD for LUP.1 & LUP.2 check.
m
2. The excluded cases are “I”, “II”, and “IV” in LUP.2.

at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
5.2.4 Layout Rules and Guidelines for Latch-up

Prevention
Rule No. Description Label Dimension
Any N+ACTIVE or an N+ACTIVE cluster connected to an I/O pad must be
surrounded by a P+ guard-ring. (Figure 5.2.3)
LUP.1g Any P+ACTIVE or a P+ACTIVE cluster connected to an I/O pad must be
surrounded by a N+ guard-ring. (Figure 5.2.3)
Please also refer to LUP.9g for further information.
Within 20um space from the MOS connected to an I/O pad, a P+ guard-ring is
required to surround an NMOS or an NMOS cluster. And an N+ guard-ring is
required to surround a PMOS or a PMOS cluster. (Figure 5.2.5)
TS
DRC excludes the guard-ring of NMOS as the following conditions come into
existence (Figure 5.2.4):
M
LUP.2g 1) When the NMOS is enclosed by a DNW, and the NW of the checked PMOS
[connected to an I/O pad and within 8um space from NMOS enclosed by a
C
DNW] is not interacted to the DNW.

2) If the voltage (Va) of the NW INTERACT DNW is ≥ the voltage (Vb) of the
C
NW of the checked PMOS. However, DRC can only waive same

VI
on 6 NO /2
connection.
LUP.3.1, LUP.3.2, LUP.3.3, LUP.3.4, LUP.5.1, LUP.5.2, LUP.5.3, LUP.5.4, are
A
fid 65 LO 009
exempted as the following conditions come into existence (Figure 5.2.4):

1) When the NMOS is enclosed by a DNW, and the NW of the checked PMOS
TE
is not interacted to the DNW.

en 12 G
2) If the voltage (Va) of the NW INTERACT DNW is ≥ the voltage (Vb) of the
C /0
NW of the checked PMOS. However, DRC can only waive same

tia 1 IES
H 1
connection.
_
For the 1.8V/1.5V N/PMOS which connects to an I/O pad directly, (Figure 5.2.3)
12
lI
LUP.3.1g 1) space between the 1.8V/1.5V NMOS and the 1.8V/1.5V PMOS A 3
2) space between the 1.8V/1.5V PMOS and the 1.8V/1.5V NMOS
nf
_
For the 2.5V N/PMOS which connects to an I/O pad directly, (Figure 5.2.3)
LUP.3.2g 1) space between the 2.5V NMOS and the 2.5V/1.5V PMOS A 6
or
2) space between the 2.5V PMOS and the 2.5V/1.5V NMOS
_
For the 3.3V N/PMOS which connects to an I/O pad directly, (Figure 5.2.3)
m
LUP.3.3g 1) space between the 3.3V NMOS and the 3.3V/1.8V/1.5V PMOS A 12
2) space between the 3.3V PMOS and the 3.3V/1.8V/1.5V NMOS
at
_
For the 5V N/PMOS which connects to an I/O pad directly, (Figure 5.2.3)
io
LUP.3.4g 1) space between the 5V NMOS and the 5V/1.8V PMOS A 23

2) space between the 5V PMOS and the 5V/1.8V NMOS
IN
_
Width of the N+ guard-ring and P+ guard-ring for the ACTIVE connected to an
LUP. 4g I/O pad, and also MOS within 20um space from the MOS connected to an I/O B 0.42
C
pad. (e. g. width of guard-ring of LUP.1 and LUP.2)

.
For the internal circuits within 20um space from 1.8V/1.5V MOS which connects
to an I/O pad directly,
LUP.5.1g
1) space between the 1.8V/1.5V NMOS connected to an I/O pad and the PMOS
in the internal circuit (Figure 5.2.5)
C _ 3
2) space between the 1.8V/1.5V PMOS connected to the I/O pad and the
NMOS in the internal circuit (Figure 5.2.5)
For the internal circuits within 20um space from 2.5V MOS which connects to
an I/O pad directly,
LUP.5.2g
1) space between the 2.5V NMOS connected to an I/O pad and the PMOS in
the internal circuit (Figure 5.2.5)
C _ 6
2) space between the 2.5V PMOS connected to the I/O pad and the NMOS in
_
For the internal circuits within 20um space from 3.3V MOS which connects to
LUP.5.3g an I/O pad directly, C 12
1) space between the 3.3V NMOS connected to an I/O pad and the PMOS in
Document No.
Version
: T-018-LO-DR-001
: 2.8
Rule No. Description Label Dimension

2) space between the 3.3V PMOS connected to the I/O pad and the NMOS in
For the internal circuits within 40um space from 5V MOS which connects to an
I/O pad directly,
LUP.5.4g
2) space between the 5V NMOS connected to an I/O pad and the PMOS in the
C _ 23
internal circuit (Figure 5.2.5)
2) space between the 5V PMOS connected to the I/O pad and the NMOS in the
internal circuit (Figure 5.2.5)
1) Any point inside NMOS source/drain {(N+ACTIVE INTERACT PO) NOT
`
PO} space to the nearest PW STRAP in the same PW. (Figure 5.2.6)
LUP.6 2) Any point inside PMOS source/drain {(P+ACTIVE INTERACT PO) NOT D 30
PO} space to the nearest NW STRAP in the same NW. (Figure 5.2.6)
TS
In SRAM bit cell region, the rule is relaxed from 30um to 40um.
U All the guard-rings and STRAPs should be connected to VDD/VSS with very
LUP.7g
low series resistance. Use as many contacts and vias as possible.
M
U
LUP.8g A P+ guard-ring should separate a large capacitor and MOS.
C
Additional one N+ STRAP and one P+ STRAP are required to be inserted

between the P+ guard-ring and N+ guard-ring for LUP.1 (Figure 5.2.3). And the
C
U
LUP.9g N+ STRAP should isolate the P+ STRAP and the P+ guard-ring. And the P+
VI
STRAP should isolate the N+ STRAP and the N+ guard-ring. DRC cannot
on 6 NO /2
check the additional one N+ STRAP and one P+ STRAP.

A
fid 65 LO 009
TE
Vss Vdd
en 12 G
A
C /0
Function Function
tia 1 IES
I/O I/O
H 1
12
lI
STRAP
STRAP
Guard-Ring
Guard-Ring
Guard-Ring
Guard-Ring
N+
P+
N+
N+
P+
P+
nf
N+ N+ P+ P+
or
NMOS PMOS
m
PW NW PW NW
at
io
B B B B
IN
n
C
N+ guard-ring (Vdd)
.
P+ guard-ring (Vss)
P+ STRAP (Vss)
N+ STRAP (Vdd)
Function I/O
PAD
LUP.1g LUP.9g LUP.1g

Figure 5.2.3
Document No.
Version
: T-018-LO-DR-001
: 2.8
If the NW of the checked

NW PMOS is interacted to the
DNW
DNW, the space needs to
PW follow A or C.
A A
C C
PMOS NMOS PMOS
TS
If voltage Va >= Vb,

the space can be < A or < C
M
Vb Va
C
C
NW NW
VI
on 6 NO /2
DNW
A
fid 65 LO 009
PW
TE
P+
en 12 G
STRAP
C /0
tia 1 IES
NMOS
H 1
PMOS
12
lI
N+STRAP (N+ guard-ring) N+STRAP

nf
or
Guard-ring is not necessary Va >=

Vb Vb Va Vb, but P+ STRAP is still required.
m
Vd
at
io
P+ N+ P+ P+ N+ PW N+ N+ N+ P+ N+
IN
NW NW PW NW
PW
C
.
Guard-ring DNW
Guard ring and P+ STRAP
are not necessary Va >= Vb.
For LUP.2, LUP.3.1, LUP.3.2, LUP.3.3, LUP.3.4, LUP.5.1, LUP.5.2, LUP.5.3, LUP.5.4, if voltage
Va >= Vb, it is excluded that the NMOS is enclosed by a DNW and the NW of the checked PMOS
is not interacted to the DNW, however, DRC can only waive same connection.
Figure 5.2.4
Document No.
Version
: T-018-LO-DR-001
: 2.8
C
ƙ 20um
B B B B B B B B
P+ guard-ringVss)
N+guard-ring(Vdd)
N+guard-ring(Vdd)
P+ guard-ringVss)
N+guard-ring(Vdd)
N+ strap(Vdd)
P+ strap(Vss)
P+ guard-ringVss)
TS
M
C
C
A C
VI
on 6 NO /2
Active connects to IO pads directly Internal circuit

A
fid 65 LO 009
TE
Figure 5.2.5
en 12 G
C /0
tia 1 IES
H 1
12
lI
OD OD OD
nf
PO PO PO
or
m
at
D D D
io
IN
n
C
.
STRAP
Figure 5.2.6
Document No.
Version
: T-018-LO-DR-001
: 2.8
6. Layout Rules, Recommendations, and

Guidelines for Analog Circuits
This chapter provides information about the following topics:
6.1 User Guides
6.2 Layout Rules, Recommendations, and Guidelines for The Analog Design
6.3 Layout rules and guidelines for device placement
6.4 GDA Die Size Optimization Kit
6.1 User Guides

TS
1. Use these rules, recommendations, and guidelines to achieve better analog device performance and
M
matching. In analog circuits, good device matching provides good performance margin and production
yield.
C
2. The examples of analog circuits:

• Operational Amplifier: includes differential input pair, bias circuit, and current mirror.
C
VI
• DAC: includes constant current source, amplifier using external Rset to adjust full range current and
on 6 NO /2
bias circuit.
A
• ADC: includes comparator, amplifier, sample/hold switches, switching capacitor, and reference
fid 65 LO 009
voltage resistor ladder.

TE
• PLL: includes VCO (delay stage) and charge pump (current mirror, buffer/opamp).
en 12 G
C /0
• Bandgap: includes BJT, current mirror, bias circuit, differential amplifier, and ratioed resistor.
tia 1 IES
• LNA and mixer.

H 1
• Sense amplifiers in memories.

12
lI
• Matching pair includes active and passive device.

nf
6.2 Layout Rules, Recommendations, and

or
Guidelines for the Analogy Designs

m
at
6.2.1 General Guidelines

io
Guideline No. Description

IN
U
n
AN.R.1mg If possible, use devices with large widths. Do not use minimum widths and lengths for
performance-critical device.
C
Using current source device as an example, a designer should refer to the device I-V curve to
.
check at which W/L range, the drain saturation current reaches a constant level.
U
AN.R.2mg Use larger areas for transistors, resistors, and capacitor devices for better mismatch..
Refer to the square root area model ( 1 WL ) (Figure 6.2.1).
However, Figure 6.2.1 is not always suitable for every kind of MOS. Please contact TSMC to
access the detail mismatch characterization report.
Mismatch
1 WL (1/um)
Figure 6.2.1 Mismatch vs. square root of area
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.2.2 MOS Recommendations

Recommendation
Description
No.
Recommended to use large OD extension on PO (F) for preventing Id
PO.EX.2mU
degradation due to high Rs at device S/D area.
OD F
PO
TS
Figure 6.2.2
M
C
6.2.3 Resistor & Bipolar Transistor (BJT)

C
VI
Recommendations
on 6 NO /2
A
6.2.3.1 Resistor
fid 65 LO 009
TE
1. Besides silicide resistors, 6 kinds of non-silicided resistors are provided: N+_OD(RPO), P+_OD(RPO),
N+_PO(RPO), P+_PO(RPO), NW_OD, NW_STI.
en 12 G
2. In order to have precise SPICE model prediction, please have the width/length of these resistors within
C /0
the valid range of SPICE model. Avoid using small width of OD & PO non-silicded resistors which high
tia 1 IES
H 1
accuracy performance is required.

6.2.3.2 BJT
12
lI
1. Two kinds of vertical bipolar transistors are provided, PNP bipolar (P+/NW/PSUB) and NPN bipolar
nf
(N+/PW/DNW).
2. In order to have precise SPICE model prediction, it is strongly recommended to apply the TSMC
or
standard bipolar transistor layouts. Please refer to the bipolar transistor GDS in (1) SPICE sample layout
document of each technology or (2) PDK sample layout.
m
at

AN.R.34mgU Avoid using BJT with emitter area 2x2 um2 due to large current variation potentially. It
io
will impact bandgap distribution.

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.2.4 Guidelines for Capacitor Connections –Estimation

of Minimum Metal Width and Minimum Via Number
Ideal current curve
Real current curve
TS
T
M
C
Figure 6.2.4 Transient peak current.

C
VI
For estimation of minimum metal line width and the minimum number of vias connecting to capacitor terminals,
on 6 NO /2
we assume that the charging up or discharge time is a quarter of clock period T.

A
ab
• In calculation:
fid 65 LO 009
TE
t T/4 to charge up to VDD or discharge from VDD to ground.

T b1/f, f is the clock frequency.
en 12 G
C /0
• The current to charge or discharge capacitor is

b b b
tia 1 IES
H 1
Imax Cdv/dt C* VDD/(1/4f) 4f*VDD*C

12
C is the capacitance extracted from layout

lI
f (is the clock frequency) and VDD are provided by designer.

nf
• The minimum metal line width is

b b
or
W(metal width in um) Imax/Jmax, where Jmax EM current density for metal line per um.
• The minimum number of via is
m
b
N(Via number) Imax/Jvia, Jvia b EM current density for each Via.
at
Both Jmax and Jvia are provided by process specifications to avoid EM (electro migration).
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3 Layout Rules and Guidelines for Device

Placement
6.3.1 General Rules and Guidelines
AN.R.3mU You need to insert the dummy patterns in the empty area
Insert the dummy patterns properly.
The recommended steps for this AN.R.3m are:
1st Insert identical geometric dummy cells manually to minimize the proximity effect
TS
(Figure 6.3.1)
2nd Use TSMC’s utility to fill dummy patterns on the rest of the empty space.
M
3rd Do electrical or silicon characterization.

C

AN.R.4mg U Avoid any sparse poly gate.
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
Dummy patterns (blue)

tia 1 IES
H 1
Figure 6.3.1 Example of manual DOD, DPO, or unit cell.

12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3.2 Matching Rules and Guidelines

AN.R.5mU Be sure that the areas and shapes of matching pairs are identical.
Do not use matching pairs with different proximities, nor with different widths and areas,
and different shapes of equal areas.
AN.R.6mU Elements of the matching pair should have the same orientation (Figure 6.3.2).
AN.R.7mU Avoid routing metal over a matching pair. M1 is the most critical. If it is unavoidable, then
use identical routing metal with same potential, over the matching pair. (Figure 6.3.3).
AN.R.35mU In critical matching pair, if gate should connect to long metal line, it would be better
through higher metal/via layers to reduce process charge possibility. (Figure 6.3.4).
Guideline
Description
No.
TS
AN.R.8mgU Place the matching devices close together and, if possible, use “common-centroid” or
“inter-digitated” placement for better matching.
M
“Common-centroid” architecture is recommended for those devices that cannot be placed

close together (Figure 6.3.5).
C
AN.R.9mgU Regardless of any device dimensions for matching pairs with constant resistance
concerns, use the symmetrical number of contacts the same CO to PO gate space.
C
(Figure 6.3.10).
VI
on 6 NO /2
The layout of interconnection routing should be symmetrical with respect to each branch.
AN.R.10mgU
A
Pay attention to the associated routing layout of the matching pair. (Figure 6.3.6)
AN.R.11mgU
fid 65 LO 009
Pay attention to the matching topology of the resistor layout (Figure 6.3.7)
AN.R.12mgU
TE
The PO gate must connect to a protection diode by M1 to reduce the antenna effects in
matching pairs. Also, gates connected with OD for this matching pair should be at the
en 12 G
same metal stage. Using lower metal layer for connection would get better immunity for
C /0
antenna effect. M1 was preferred. (Figure 6.3.2.1)

tia 1 IES
H 1
AN.R.13mgU In order to avoid drift of electrical parameter matching, it is important to maintain identical
DC biasing of matched transistors (NMOS or PMOS) in all operation conditions (eg,
12
lI
standby conditions).
AN.R.37mgU Mesh poly is not preferred. (Figure 6.3.2.2)
nf
AN.R.38mgU Stack via with long metal (>650um) routing link to high-density poly is not preferred.
Especially no well GND path underneath.
or
m
Better matching layout : same orientation

Poor matching layout : different orientation
at
PO gates are all along x-direction (or y-direction)

io
IN
n
C
.
Figure 6.3.2 Example of same or different orientation for matching pairs.

Poor Good Poor Good
OD M1 OD
Resistor Resistor
PO PO
M1 over MOS affecting Vt M1 over resistor affecting resistance
Figure 6.3.3 Example of routing metal over a matching pair.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Poor process charge immunity Good process charge immunity

Higher-level metal
Long metal line Long metal line Higher level VIA
CO CO
Gate Gate
Figure 6.3.4 Example of gate connected to long metal for matching pairs
TS
better matching layout not suitable for

M
critical matching
C
common-centroid interdigitated
C
different OD (ABBA) common OD (ABAB)

VI
A
on 6 NO /2
A A
A
A
A B A or
fid 65 LO 009
A B B B
TE
B A B B
en 12 G
B A B
C /0
B
A
tia 1 IES
H 1
12
lI
Dummy array (blue)

nf
Figure 6.3.5 Example of common-centroid or inter-digitated layout for matching pairs

or
Poor Good
m
at
io
Matching pairs Matching pairs

IN
n
C
Figure 6.3.6 Example of the associated routing layout of the matching pair.
.
Poor Good Good Better
R R R
2R R R R R R R R R
Figure 6.3.7 Example of matching topology of resistor layout for matching pairs
Document No.
Version
: T-018-LO-DR-001
: 2.8
VDD
Vo
Diode
Diode
TS
AN.R.12mgU
M
Figure 6.3.2.1
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
Figure 6.3.2.2 AN.R.37mgU

tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3.3 Electrical Performance Rules and Guidelines

Avoid placing the matching pairs or performance-critical devices at the chip corner and
AN.R.14mU
chip edge. (Figure 6.3.8)
Avoid using silicided-OD connected between well strap and the MOS source node
AN.R.15mgU
(butted junction) in analog, matching and performance-critical devices. (Figure 6.3.9)
Maximize CO number at both source and drain sides of performance-critical devices.
AN.R.16mgU
(Figure 6.3.10)
AN.R.17mgU Do not use maximum latch-up rule near narrow region between wells. (Figure 6.3.11)
Place PO resistor on an N-well for better noise immunity.
TS
AN.R.18mgU
A P+ PO resistor is recommended for overall performance.
AN.R.19mgU Do not use single via for high current or resistance sensitive wire. (Figure 6.3.12)
M
CB and CBD are not recommended to put on the top of matching pairs or performance-
AN.R.20mgU
critical devices.
C
For the matching sensitive circuits with DC bias at low Vgs regions; the layout style
AN.R.21mgU
effects (such as device orientation) should be carefully reviewed.
C
VI
A = die width
on 6 NO /2
B = die length
A
C = die diagonal length

fid 65 LO 009
Length and width of die includes seal ring

TE
and part of scribe line after die saw

en 12 G
A
C
C /0
tia 1 IES
H 1
a*B
12
lI
nf b*
C
B
Proposed zone
or
m
a*B
at
io
a*A a*A
IN
For the bottom die/upper in a stacked-die wirebond PBGA package

n
1) a: away from die edge ≥ 10% of the chip edge length

C
2) b: away from die corner ≥ 15% of the chip diagonal dimension

.
For a single-die wirebond PBGA package

For a single-die flip chip PBGA package

The above numbers may be changed by several factors, e.g. die size, die thickness, package type, package
material, package size, and circuit design margin, please contact TSMC for more details.
Figure 6.3.8 Proposed zone for matching pair
Document No.
Version
: T-018-LO-DR-001
: 2.8
Poor Poor Good
Source Well Strap

Well Strap Well Strap
Source Source
TS
Figure 6.3.9 Example of avoiding using silicided-OD connected between well strap and the MOS
source node
M
Poor Good
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
Figure 6.3.10 Maximize CO number at both source and drain sides

tia 1 IES
H 1
NMOS Do not use maximum latch-up PMOS

12
lI
rule (reduce the space)

nf
PW PW
or
NW NW
m
Narrow well space

at
Well Strap (narrow ravine) Well Strap

io
IN
Figure 6.3.11 Example of maximum latch-up rule near narrow ravine between wells
n
C
Poor Good
.
Viax Viax
Mx+1 Mx Mx+1 Mx
Figure 6.3.12 Example of not using single via for high current or resistance sensitive wire
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3.4 Noise
6.3.4.1 Power and Ground
Guideline Description
No.
For the low noise circuit, a P-Well ring, which is tied to VSS, is recommended to
AN.R.22mgU
surround all PMOS devices in each analog circuit block.
For the low noise circuit, a N-Well ring, which is tied to VDD, is recommended to
AN.R.23mgU
surround all NMOS devices in each analog circuit block.
Putting NMOS in RW (PW in DNW) is a good practice of isolating critical circuit from
TS
AN.R.24mgU substrate noise (Figure 6.3.13). Make sure every NW connected to DNW must have the
same potential (refer to DNW.R.6).
M
Use NT_N layer, as a high resistance region, to isolate two high frequency circuits, to
reduce the noise or signal coupling from substrate (Figure 6.3.14).
C
AN.R.25mgU n minimize the signal lines crossing the high resistance NT_N region
n maximize the distance between metal lines from the substrate above the NT_N
C
region (use upper level metal).

VI
on 6 NO /2
AN.R.26mgU Use separate power supplies and ground buses for the noisy and sensitive circuit.
A
AN.R.27mgU Keep enough distance between the noisy and sensitive areas.
fid 65 LO 009
AN.R.28mgU Use a wide guard ring to stabilize substrate and well potential.
TE
If transistors within sensitive circuit must be tied together with source and body, do not
en 12 G
AN.R.29mgU
tie them in the local area by shorter metal line. (Figure 6.3.15)
C /0
tia 1 IES
H 1
Poor Good
12
lI
Sensitive circuit Noisy circuit Sensitive circuit Noisy circuit

nf
NMOS NMOS NMOS NMOS

or
NW NW
m
at
DNW
Noise Noise is isolated.
io
IN
Figure 6.3.13 Example of NMOS in RW

n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
NT_N Poor
PW Guard ring
Sensitive circuit Noisy circuit
NW Guard ring
PW
NW NW
Sensitive circuit
R_PW
Guard ring
Noise
TS
M
Good
C
Sensitive circuit Noisy circuit

C
Sensitive circuit Nosiy circuit

VI
on 6 NO /2
NT_N
A
NW PW (Psub) PW NW
R_Psub
fid 65 LO 009
R_Psub
TE
Guard ring Guard ring

en 12 G
Noise
C /0
Guard ring
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H 1
Because R_Psub is larger than R_PW, NT_N is better than

12
PW in the noise isolation.

lI
nf
or
Figure 6.3.14 Example of NT_N layer as a high resistance region

m
Use longer metal line to

at
connect source and body

io
IN
n
C
Poor Good
.
Figure 6.3.15 Example of transistors within sensitive circuit tied together with source and body
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3.4.2 Signal
Guideline
Description
No.
AN.R.30mgU Keep high frequency signal in high level metal layer.
AN.R.31mgU Use metal shield for victim line that is noise sensitive.
AN.R.32mgU Use metal and poly shield for attacker line that travels through long distance.
Prevent feedback path through chip seal ring between critical input and output. Use
AN.R.33mgU
additional guard ring to isolate signal coupling. (Figure 6.3.16)
Feedback Path
Seal ring
TS
Use additional guard Vdd

ring to isolate the or Vss
M
Input
coupling.
C
Output Output
C
Guard ring
VI
on 6 NO /2
Vdd
A
or Vss
fid 65 LO 009
TE
Seal ring
en 12 G
C /0
Figure 6.3.16 Example of prevention from feedback path through chip seal ring
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H 1
12
lI
nf
or
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at
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IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
6.3.5 Burn-in guidelines for analog circuits

1. For the sensitive circuit, e.g. differential input pair, which needs precise device mismatching
parameter control such as c c
Vt and Isat, you must avoid imbalanced DC bias stress
during burn-in period.
d d
For example, VA Vdd or GND & VB 1/2Vdd, which causes current supplied from current source
flowing differently on the differential input pair (IA≠IB), this will make differential pair matching worse after
burn-in stress.
TS
VA VB
M
IA IB
C
2. Be sure that analog circuit operates at the normal operational condition during burn-in.
C
For example, avoid P1 floating (when R is external) and make it be biased at the normal condition during
VI
on 6 NO /2
burn-in.
A
fid 65 LO 009
+
TE
-
P1 P2 P3
en 12 G
C /0
R
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H 1
12
lI
nf
3. Add the protection diode connection in the sensitive circuit to reduce plasma-induced damage
during wafer processing.
or
6.4 GDA Die Size Optimization Kit

m
at
• Gross Die Advisor (GDA) is to optimize die size x-y for both mask field allocation and gross die
maximization.
io
• The function of GDA is based on user input die size, target gross die and TSMC generic fabrication
IN
condition to estimate gross die count, and recommend a list of the other die size combination (X / Y)
C
with higher gross die and MFU>65% criterion. Based on GDA result, user can choose the best
combination of die size and gross die to meet the project need in the early design phase.
.
• Use GDA function from TSMC on-line

n TSMC On-line Directory: Home/Design Portal/Design Assistance/Die Size Planning
6.4.1 Recommended GDA criteria MFU >65%

• The benefits from GDA:
n Simulate gross die count base on initial die size x-y at the early design stage.
n Advise die size x-y for better gross die count and MFU>65% simultaneously.
• The MFU ratio is calculated by (die size + assembly isolation + sealring + scribe-line Area) /
(maximum scanner field size).
Document No.
Version
: T-018-LO-DR-001
: 2.8
7. Current Density (EM) Specifications

7.1 Metal/CO/Via Current Density
(1) Jmax of Metal Line (at 110°C)
M1 M2 M3 M4 M5 M6 UTM (20KÅ) UTM (40KÅ)
Jmax (mA/um) 1 1 1 1 1 1.6 4 9.2
(2) Jmax per Contact and Vias (at 110°C)

TS
Contact Via1 Via2 Via3 Via4 Via5

Jmax (mA/ct, mA/Via) 0.53 0.28 0.28 0.28 0.28 0.706
M
(3) Jmax per Stack Contact/Via (at 110°C)

C
Stack Type Jmax Unit

C
CV1 0.28 mA/Via

VI
on 6 NO /2
CV12 0.28 mA/Via

A
CV123 0.28 mA/Via

fid 65 LO 009
TE
CV1234 0.28 mA/Via

en 12 G
CV12345 0.28 mA/Via

C /0
V12 0.28 mA/Via

tia 1 IES
H 1
V23 0.28 mA/Via

V34 0.28 mA/Via
12
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V45 0.28 mA/Via

nf
V123 0.28 mA/Via

or
V234 0.28 mA/Via

V345 0.28 mA/Via
m
V1234 0.28 mA/Via

at
V2345 0.28 mA/Via

io
V12345 0.28 mA/Via

IN
Jmax is maximum DC current allowed per um of metal line width or per via or per contact. The number is
C
based on 0.1% point of measurement data at 20% resistance increase after 10 years continuous operation.
.
Use the following table to convert Jmax from one temperature to another.
Rating Fator of Jmax vs. Temperature
Temp. 70 Ce 85 Ce 100 Ce 110 C e 125 Ce 150 C e e
175 C
Rating factor of Jmax 3.44 2.10 1.33 1 0.671 0.367 0.215
Example: Jmax at 125°C f 0.671 * Jmax at 110°C f 0.671 * 1mA/um f 0.671mA/um for M1 to M5.
Document No.
Version
: T-018-LO-DR-001
: 2.8
AC operation guideline (this guideline is not applicable to flip chip package)

Jpeak_ac
J(t)
Current
Time
0 τ nτ
g
Jrms { (∫0 to τJ2(t)dt )/τ}1/2,
TS
g
Jav { (∫0 to τJ (t)dt )/τ},
Where J(t) is the current density flowing through a metal line.
M
C
Jav is AVERAGE current density through a metal line. The numbers given below are for 10% resistance
increase after 10-year continuous operation at 110°C.
C
h 1mA/um ( g 2.5 x 10 A/cm ) for M1 to M5 (4 KÅ thickness),

VI
5 2
on 6 NO /2
Jav
Jav h 1.6mA/um ( g 2.0 x 10 A/cm ) for M6 (8 KÅ thickness)
5 2
h 4.0mA/um ( g 2.0 x 10 A/cm ) for UTM (20 KÅ, 40 KÅ thickness)

A
5 2
fid 65 LO 009
Jav
TE
It’s nominal AlCu thickness instead of genuine total thickness.

en 12 G
Jrms is root-mean-square current density through a metal line. The numbers given below are for <10 °C Joule
C /0
heating.
tia 1 IES
h 8mA/um ( g 2 x10 A/cm ) for M1

H 1
6 2
Jrms
h 4mA/um ( g 1 x10 A/cm ) for M2 to M5,
12
6 2
lI
Jrms
Jrms h 8mA/um ( g 1 x10 A/cm ) for M6
6 2
h 20mA/um ( g 1 x10 A/cm ) for UTM (20 KÅ, 40 KÅ thickness)

nf
6 2
Jrms
or
Jpeak_ac is the current density at which metal line will start MELTING due to excessive Joule heating. Design
m
should stay away from Jpeak_ac as far as possible. Jpeak_ac can be calculated as follows:
g 5 x10 /sqrt(Duty cycle), in A/cm

at
6 2
Jpeak_ac for M1 to M6
g 4 x10 /sqrt(Duty cycle), in A/cm
6 2
io
Jpeak_ac for UTM (20 KÅ, 40 KÅ thickness)

IN
Duty cycle is the ratio of pulse width of Jpeak_ac to period. For convenience, one could measure the pulse width
C
of Jpeak_ac at half of the peak.

.
Example:
If pulse width is 1ns and period is 10ns, duty cycle is 0.1 or 10%. Square root of 0.1 is 0.31.
Jpeak_ac g
5 x106/0.31 g
1.5 x107 A/cm2,
No Jrms and Jpeak are given for contact and via because Joule heating mainly comes from metal line, and metal
line starts melting earlier than via in this technology.
Note: If space permits, it is preferable to have more contacts or vias than required by EM rules. This will
reduce interconnect resistance and also improve reliability. Avoid using only one contact or via in one metal
line unless it is absolutely necessary and allowed by rules.
Document No.
Version
: T-018-LO-DR-001
: 2.8
7.2 Poly Current Density

The maximum current density for poly resistor (unsilicided) is 0.5 mA/µm at a junction temperature of 110°C.
This density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K
hours of continuous operation.
Use the following table to calculate Imax if the junction temperature differs from 110°C. For a junction
temperature below 105°C, use the rule at 105°C.
Junction temperature 105°C 110°C 125°C

Rating factor of Jmax 1.03 1.00 0.927
TS
For example, Imax (at 125°C) = 0.927 × Imax (at 110°C).

M
This rule is applicable to N+, and P+ unsilicided poly resistors.

C
C
For silicided poly, the maximum DC current density should be less than 6mA/um at a junction temperature of
VI
110°C. This density is calculated using 0.1% point of measurement data at a 5% resistance increase after
on 6 NO /2
100K hours of continuous operation.

A
For diffusion (OD) unsilicided resistors and/or silicided interconnect, no Imax rule is given. Since diffusion (OD)
fid 65 LO 009
is crystalline silicon with implantation, no electromigration or Joule heating problems occur. If the design
TE
follows contact, metal, and via current density rules, there will be no reliability concern for diffusion (OD)
en 12 G
C /0
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H 1
12
lI
nf
or
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IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8. 0.16um TECHNOLOGY (CL016G/ CM016G)

This chapter contains the following topics:
8.1 Specifications for CL016G and CM016G Technology
8.2 Non-Shrinkable Rules and Recommendations
8.3 Design Flow for Tape-Out
8.1 Specifications for CL016G and CM016G

Technology
TS
8.1.1 General Design Specifications

• All CL016G and CM016G layout dimension need to be drawn in C018 level, then doing
M
90% shrinkage by TSMC mask making.

C
• Design must follow all CL018G or CM018G rules and the non-shrinkable rules for
CL016G and CM016G respectively.
C
VI
• Designers must assess the shrinkage impact on critical circuits, such as PLL, analog and
on 6 NO /2
IO/ESD circuits. Generally, ESD will degrade after shrink. Customer may modify the layout
A
structure or adding ESD implant to prevent such ESD degradation.

fid 65 LO 009
• For some analog circuits, designer may consider directly 110% size-up at C018 level to
TE
keep the circuit performance (for example: matching circuits, current-driving at IO circuits).
en 12 G
Please refer to the section 8.3.4 “110% Size-up” for details. Customer could also consult with
C /0
TSMC Design Support Department about the size-up procedure.

tia 1 IES
H 1
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8.1.1.1 Mixed Signal Design Specifications

lI
• Inductors are not allowed in CM016G. Because the UTM (thickness 20KÅ, 40KÅ) is not i
nf
provided in CM016G process and SPICE model don’t support it, neither.
or
• HRI resistors are not allowed in CM016G. Because SPICE model don’t support HRI
resistors.
m
at
8.1.1.2 SRAM Design Specifications

io
• C018G SRAM cell (HD) can be directly shrunk to C016. Designers need to assess 10% shrink
IN
impact on SRAM macro performance. For self-owned SRAM cell, please contact TSMC to
C
perform a mandatory bit cell review.

.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.2 Non-Shrinkable Rules and Recommendations

8.2.1 Non-shrinkable Layout Rules
8.2.1.1 Purpose:
A set of non-shrinkable rules is refined to meet the requirements below:
• The limitation of the test probing, laser repair, bonding and assembly.
8.2.1.2 General Logic Rules:

TS
j
Rule No Rule description Rule (um)
Minimum Po1y gate dimension (channel length) of a 1.8V blocked NT_N
0.55
M
j
device.
NTN.W.2
Minimum Po1y gate dimension (channel length) of a 3.3V blocked NT_N
C
j
1.32
device.
C
j
NTN.W.3 Minimum OD width of 1.8V/3.3V blocked NT_N device. 0.245
VI
Minimum assembly isolation. It also depends on the capability of assembly

on 6 NO /2
SR.S.1 5.5
house to require layer distance
A
fid 65 LO 009
8.2.1.3 Mixed Signal Rules:

TE
j
en 12 G
Rule No Rule description Rule (um)

j
C /0
DNW.W.1 Minimum width of a DNW region. 3.3

tia 1 IES
DNW.S.1 Minimum spacing between two DNW regions 5.5

H 1
12
lI
8.2.1.4 Pad Rule for Wire Bond

nf
• Please refer to “TSMC WIRE BOND, FLIP CHIP AND INTERCONNECTION DESIGN RULE”
(Doc. No.T-000-CL-DR-002) for details.
or
• Since the pad rule is limited by testing and assembly capability, customer has to check
m
the layout dimension before 90% shrink.

at
• Single in-line and stagger pad rule is non-shrinkable. Please follow the non-shrink rule of the
below rule table.
io
• The design rules of 80µm pitch tri-tiers pad are shrinkable. Please follow the related rules of
IN
the reference document.

C
• Please be noted that if VIA array size < bonding ball after shrink without bonding recipe
.
fine tuned, there might be oxide crack concern.
Rule (µm)
Rule No Description Single in-line Stagger
j ‡ ‡
Pitch ≥ 50µm Pitch ≥ 55µm Pitch≥ 60um
‡
CB.W.1 Width (except sealring region)

Width of (the edge perpendicular to j 47.3 52.8 58
66† 66 †
CB.W.2
nearby chip edge)
88
j
CB.S.1
CB.P.1
Space
Pitch of (4 pitches at each chip corner)
7†
88
j 7†
88
7.7
110
Table notes:
‡
The pitch is the real pad pitch after 90% shrink.
†
This rule is same with CL018G, and it is a shrinkable rule.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.2.1.5 Flip Chip Bump Rules

• Please refer to “TSMC WIRE BOND, FLIP CHIP AND INTERCONNECTION DESIGN RULE”
(Doc. No.T-000-CL-DR-002) for details.
• The bumping rules for flip-chip design are critical on the bumping ball formation.
Customers must check the following items before 90% shrink, and meet the non-shrinkable
rules as the table below.
• The bump height and diameter would decrease due to UBM shrinking. Customers must
evaluate this bump height change by themselves.
Rule No Description
j Rule (µm)
j
TS
UBM.EN.1 Enclosure by chip edge 88

UBM.S.1 Space to metal fuse protection ring
j 55
UBM.S.2 Space to L target protection ring
j 66
M
Area (without UBM in the chip center, for test inking requirement. Not
j
UBM.A.1 825*825
C
necessary for inkless sorting)

UBM.P.1* Pitch
j 165
C
BP.W.1 Width of CBD under UBM area.

j 44
VI
on 6 NO /2
BP.W.2 Width of PM under UBM area

j 33
A
BP.W.3 Width of UBM

j 88
fid 65 LO 009
BP.EN.1 PM enclosure by UBM

j 16.7
TE
BP.EN.2 CBD enclosure by UBM

j 11.2
en 12 G
BP.EN.4 PM enclosure by CBD 11.2

C /0
tia 1 IES
H 1
* Warning: For the design with a bump pitch 150~175um (after shrink), please
12
consult with your assembly house in advance. Make sure that your assembly house is
lI
able to provide such substrates and the associated service for your smaller bump
nf
pitch design.
or
8.2.1.6 Metal Fuse Rules

m
• Reference document: T-000-LO-DR-003 “TSMC AL METAL FUSE DESIGN RULE”

at
Rule No Description Rule (µm)

k
io
FUSE.W.1 Width of metal fuse

j 1.32
IN
j
n
FUSE.S.1 Minimum space of metal fuse 3.96

j
C
FUSE.L.1 Length of metal fuse 5.5

Minimum extension of fuse window to nearest metal fuse Generic 3.85
.
j
FUSE.E.3
parallel to fuse length Non-generic 8.8
Minimum width of fuse window. Fuse metal center should Generic 5.94
j
FUSE.W.2
be aligned to fuse window center. Non-generic 9.9
LW.E.1 Minimum extension of L target window to L target. 16.5
Table note:
• Generic: The generic process.
• Non-generic: Top metal layer is thicker than the generic process. The larger fuse window is required for
remaining oxide thickness uniformity.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.2.2 ESD Guidelines

ESD relative guidelines are shrinkable. Please refer to all the guidelines described in the section 5.1
“I/O ESD PROTECTION CIRCUIT DESIGN AND LAYOUT GUIDELINE”.
8.2.3 Current Density (EM) Specifications
DC and AC specifications are shrinkable if customer follows all spec described in the Chapter 7
“Current Density (EM) Specifications”.
TS
8.2.4 Antenna Effect Prevention Layout Rules

M
The antenna effect protection related rules are shrinkable. Please refer to all the rules description in
C
the section 4.5.21 “Antenna Effect Prevention (A) Layout Rules”.

C
VI
on 6 NO /2
8.2.5 Layout Guidelines for Latch-up Prevention

A
fid 65 LO 009
The latch-up guidelines are shrinkable. Please refer to all the guidelines description in the section
TE
5.2 “Layout Guidelines for Latch-up Prevention” of CL018 logic design rule manual.
en 12 G
C /0
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H 1
12
lI
nf
or
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IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3 Design flow for Tape-out

This section contains the following topics:
8.3.1 Overview
8.3.2 C016 technology files
8.3.3 New IP design
8.3.4 Legacy IP porting
8.3.5 Chip integration
8.3.1 Overview
TS
The C016 process is shrank from the C018 process, and the design rules are almost the same. Follow the
four steps bellow, and it's easy to translate the existing C018 design to C016 process.
M
1. Use the correct tech files in C016.

C
2. Check the DRC violations with the non-shrinkable rules, and modify the layout if there is any violation.
3. Add ".option scale=0.9" in spice simulation.
C
4. Add scaling factor in RC extraction in LPE flow.

VI
on 6 NO /2
A
Most of the IP in C018 process can be used in C016 process without any modification, for example, the
fid 65 LO 009
standard cell, the standard IO, and the SRAM certified in C016 process. The circuit performance in the chip
TE
level should be close in C018 process and C016 process, except the ESD performance and the analog
en 12 G
circuits. In the same standard IO library, the ESD performance in C016 process should be different from the
C /0
ESD performance in C018 process due to the smaller discharge area. The analog circuit should be verified
with the spice model card in C016 process to make sure the design margin is enough in C016 silicon.
tia 1 IES
H 1
12
lI
According to the resistance of VIA-hole and contact-hole, and the sheet resistance (Rs) of metal line higher in
C016 as compared to C018, it’s necessary to perform the full-chip timing/leakage simulation and
nf
characterization to ensure the chip functionality and the robustness in C016 (with enough design margin)
or
8.3.2 C016 Technology files

m
tsmc offers technology files for the digital and analog design. Please contact CE and FAE to get the latest
at
version.
io
IN
Input layout Output data

n
Categories Tools
dimension dimension
C
Spice model
.
Calibre 0.18um 0.18um

DRC Hercules 0.18um 0.18um
Assura 0.18um 0.18um
Calibre 0.18um 0.18um
LVS/LPE Hercules 0.18um 0.18um
Assura 0.18um 0.18um
Star-RCXT 0.18um 0.16um
Calibre-xRC 0.18um 0.16um
RCX
Fire&Ice QX/QRC 0.18um 0.16um
Assura RCX 0.18um 0.16um
PDK 0.18um 0.18um /0.16 um
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.2.1 Spice model and simulation

Using the C016 spice model card in the spice simulation, the option ".option scale=0.9" must be added in the
spice netlist to make the spice simulator to scale the device as the correct silicon size. Since the spice netlist
in the half-node process is kept as the spice netlist in the full-node process, the scaling option is used to make
the spice simulator to scale the device as the real silicon size in the half-node process. The spice model is
customized for such approach, so that the user must not scale the spice netlist as the silicon dimension in the
half-node process.
The following table shows the simulation behaviors when the spice simulator, Hspice and Spectre, reads the
scaling option:
TS
W L PD PS AD AS
Geometric parameters
0.9 0.9 0.9 0.9 0.81 0.81
M
MOS
NRS NRD
Electrical parameters
C
1 1
AREA
C
DIO Geometric parameters

0.81
VI
on 6 NO /2
BJT No parameter No impact because only fixed layout/models are provided

A
Design No impact because they are modeled by Macro (Sub-circuit)

Geometric parameters
fid 65 LO 009
resistor/capacitor Scaling factors set in SPICE model header

TE
Parasitic R, C Parasitic values No impact because no geometric parameters

en 12 G
C /0
Design input:
tia 1 IES
H 1
Pre-layout or post-layout spice netlist:

Pre-layout: C018 netlist
12
lI
Post-layout: LPE netlist in C018 device dimension and C016 parasitic.

nf
Insert the ".option scale=0.9" in the netlist.

Design output:
or
Meet timing or not?

m
tsmc offering:
C016 Spice model
at
io
8.3.2.2 DRC
IN
n
C
There are few non-shrinkable rules in the half-node process, so that the design must be verified with the
correct DRC deck in the half-node process. The layout is drawn in the full-node process environment, and the
.
DRC tool will verify the layout with the half-node design rules in the half-node DRC deck. The DRC report
shows the DRC violations, if any, in the full-node environment.
Design input: Layout (GDSII) in C018 dimension

Design output: DRC violation or not?
tsmc offering:
C016 DRC deck with the shrinkable and non-shrinkable rules
Antenna and package rules including the wire-bond pad and flip-flop RDL
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.2.3 LVS/LPE
Use the LVS deck for the half-node process to verify the layout in the full-node dimension and the spice netlist
in the full-node dimension. For the LPE extraction, use the LVS/LPE combo deck to extract the layout as the
database for the RC extraction tool. The NRS/NRD for the device is different in the full-node process and in
the half-node process, so that the resistance table in the half-node LVS/LPE combo deck is different from the
LVS/LPE combo deck in the full-node process.
Design input:
Layout (GDSII) in C018 dimension
Spice netlist in C018 dimension
TS
Design output:
LVS matched or not?
M
LPE database for the RC extraction

C
tsmc offerings:
C016 LVS/LPE combo deck
C
VI
on 6 NO /2
8.3.2.4 RCX
A
fid 65 LO 009
TE
The scaling in the device is modeled in the spice simulation with the scaling option, and the scaling in the
metal/VIA is handled in the RC extraction. One scaling option must be specified in the RC extraction script to
en 12 G
scale the metal/VIA of the design in the RC extractor, and one option must be specified in the RC extraction
C /0
script to prevent the devices be scaled. Only metal/VIA is scaled in the RC extraction, and the devices are
tia 1 IES
H 1
scaled in the spice simulation.

12
lI
Design input:
nf
Layout (GDSII) in C018 dimension

LPE database in C018 dimension
or
Design output:
m
Parasitic R/C in C016

at
LPE spice netlist with C018 device dimension and C016 parasitic
tsmc offerings:
io
C016 RC extraction technology files

IN
User's setting:
C
LVS Tools Hercules Calibre Assura LVS

.
RCX Tools Star-RCXT Calibre-xRC Assura RCX

Interconnect (In Star-RCXT command (In Calibre-xRC run script) capgen –c –scale 0.9
file) setenv To generate a C016
scaling
magnification_factor: 0.9
magnify_device_params: PEX_FMT_NO_MAGNIFY deck
NO ON
(For cross-reference in
output netlist) (In xRC rule file)
XREF: YES
PEX MAGNIFY 0.9
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.3 Analog IP design

The design flow is almost the same as the design flow in the full node process. Just add the ".option
scale=0.9" in the spice netlist for the spice simulation, and use the correct tech files in the design. The details,
such as Spice simulation, DRC, LVS, and RCX, can be referred to details in the previous section.
Here is the basic flow for C016 process, and it can be used in applying 90% shrinkage from an existing C018
design or developing a new C016 design.
Design input Design output tsmc offering

TS
M
Spice netlist in C016 Cadence

Spec Schematic entry C018 dimension PDK
C
C
C018G netlist with Pre-layout spice Meet timing or C016 Cadence PDK &
VI
(.option scale=0.9) simulation not? C016 spice model

on 6 NO /2
A
fid 65 LO 009
Custom or semi- Layout in C018 C016 Cadence

C018 netlist
TE
custom layout dimension PDK

en 12 G
C /0
Layout in C018 DRC violaion or

tia 1 IES
DRC C016 DRC deck

H 1
dimension not?
12
lI
Layout and spice (1) LVS matched or not?

C016 LVS combo
(2) LPE spice netlist with
nf
netlist in C018 LVS/LPE/RCX C018 device and C016

deck & C016 RCX
dimension tech file
parasitic
or
LPE spice netlist with Post-layout spice Meet timing or

m
C016 spice model

(.option scale=0.9) simulation not?
at
io
Once the IP is verified in the post-layout spice simulation with the correct tech files and the correct usage, the
IP can be put in the test chip and verified in the C016 shuttle.
IN
n
C
There are two notices about C016 design:

.
Inductor and HRI resistor are not allowed in C016. Because the M6T (thickness=20KÅ) is not provided in
C016 process and SPICE models also does not support these devices.
C018 SRAM cell (HD) can be directly shrunk to C016. Designers need to assess 10% shrink impact on SRAM
macro performance. For self-owned SRAM cell, please contact TSMC to perform a mandatory bit cell review.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.4 Legacy IP porting

For most of the IP design, the circuits can be shrunk directly. If there is no DRC violation related to the non-
shrinkable rules, the IP can be shrunk; if there are DRC violations related to the non-shrinkable rules, the
layout of such IP should be modified to avoid the DRC violations. The IP should be simulated with the spice
model in the half-node process, so that the timing can be analyzed before the tapeout.
For the sensitive legacy circuits such as the analog IP, the IP should be verified in the C016 environment
again after fixing the DRC violations if any. If the spice simulation results in the half-node process are not as
good as the results in the full-node process, or the tapeout schedule is too critical to tune the layout, there is
TS
another way to port the IP in the half-node process by blowing-up the IP. The following blow-up procedure can
be used to reduce the working time to meet the tapeout schedule, but the silicon area is larger in such
approach.
M
C
C
Swap the scaled

C018 IP GDSII C018 IP spice
VI
BJT to the original

on 6 NO /2
min grid 5nm netlist

BJT
A
fid 65 LO 009
TE
C018 DRC/ Flatten and merge Scale all devices

en 12 G
LVS polygons 110%

C /0
Pass
tia 1 IES
H 1
Stream In Layout
Stream Out with C016 IP spice
12
Editor with 0.1nm

lI
1nm grid netlist

grid and 110%
nf
Fail
or
Size down CO/VIA C016 Flatten

C016 IP DRC/ Custom Layout
with the same GDSII with min
LVS Effort
center grid 1nm
m
at
io
There are several items to be noticed:

IN
Smaller layout grid for the stream-in and the stream-out is to avoid the mismatch due to the layout snapping in
the scaling.
C
Sizing down the CO/VIA size is to keep the CO/VIA size in the whole chip to be identical.
.
To flatten and merge polygons is to avoid the open due to the scaling in the layout editor.
The blown-up BJT is not modeled in the spice model card, so that the blown-up BJT is recommended to be
swap to the BJT in the original size.
In the silicon, the poly CD in the C016 process is equivalent to the poly CD in the C018 process, so that there
will be an offset in the channel length after the optical shrink, for example, 180nm x 0.9 + offset = 180nm. If
the channel length after being blown-up is 198nm, the channel length in the C016 silicon will be 198nm x 0.9
+ offset. If such offset is critical to the IP performance, please consult tsmc for the detailed solution.
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.5 Chip integration

8.3.5.1 Introduction
The design flow is almost the same as the design flow in the full node process. If the design kits are ready for
the half-node process, such as the .lib or .db, use these half-node design kits in the design; if the design kits
are not ready for the half-node process, such as the .lib or .db, use the design kits in the full-node process
with additional margins.
Here is the basic flow for C016 process. It can be used in applying 90% shrinkage from an existing C018
design or developing a new C016 design. There is no timing design kit for C016 process, so that the design
kits in C018 is used in the static timing analysis and the post-layout verilog simulation.
TS
tsmc/3rd party
Design input Design output offering
M
.lib/.db for IP &

C
Spec
Synthesis Gate level netlist wire-load model in
(RTL design) C018
C
VI
on 6 NO /2
Pre-layout Meet timing or Verilog and timing

A
Gate level netlist model for IP

simulation/STA not?
fid 65 LO 009
TE
en 12 G
Layout in C018 IP P&R kits in

Gate level netlist Place & Route
C /0
dimension C018
tia 1 IES
H 1
Layout in C018 DRC violaion or

12
lI
dimension
DRC not?
C016 DRC deck
nf
Layout and spice (1) LVS matched or not? C018 LVS combo
or
netlist in C018 LVS/RCX (2) SPEF/DSPF with deck & C018 RCX
dimension C018 parasitic tech file
m
at
Gate level netlist & Post-layout Meet timing or Verilog & timing model
SPEF/DSPF simulation/STA not? for C018 IP
io
IN
8.3.5.2 Synthesis
C
If there are design kits for the half-node process, such as .lib or .db, use these design kits in the synthesis to
.
compile the RTL code and the timing constraints; if there is no design kit for the half-node process, such
as .lib or .db, use the design kits in the full-node process in the synthesis to compile the RTL code and the
timing constraints with additional reasonable timing margins.
Design input: RTL and timing constraint

Design output: Gate level netlist
Current environment:
C018 standard IO library
C018 3rd party IP & Library, such as standard cell, SRAM
C018 wire load model for interconnect RC estimation
Reasonable timing margin
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.5.3 Simulation/STA
If there are design kits for the half-node process, such as .lib or .db, use these design kits in the STA and the
verilog simulation; if there is no design kit for the half-node process, such as .lib or .db, use the design kits in
the full-node process in the STA and the verilog simulation with additional timing margins.
Design input:
For pre layout simulation/STA: Gate level netlist
For post layout simulation/STA: Gate level netlist or SPEF or DSPF with C018 parasitic
Design output:
Meet timing or not?
TS
Pass simulation/STA or not?

M
C018 timing kits in IP and Library

Reasonable timing margin
C
C
8.3.5.4 Place and Route

VI
on 6 NO /2
If there are physical design kits in the half-node process, such as the lef or the Milkyway FRAM view, use
A
these design kits in the place/route. If there is no physical design kit in the half-node process, such as the lef
fid 65 LO 009
or the Milkyway FRAM view, using the physical design kits in the full-node process is fine since the layout
TE
dimension is the same in the full-node process and in the half-node process. Additional timing margins are
en 12 G
necessary when using the physical design kits in the full-node process.
C /0
tia 1 IES
H 1
Design input: Gate level netlist and floorplan in C018 dimension

12
Design output: Layout in C018 dimension

lI
nf
C018 P&R kit

or
LEF or Milkyway FRAM in C018 dimension

Electrical/timing model in C018 dimension
m
P&R tech file and RCX files for implementation

at
Reasonable timing margin is necessary

io
8.3.5.5 DRC
IN
The DRC deck in the half-node process is used to verify the layout in the half-node dimension, so is the
C
Antenna deck/bond pad deck in the half-node process.

.
Design input: Layout (GDSII) in C018 dimension

Design output: DRC violation or not?
tsmc offering:
C016 DRC deck
Antenna and package rules including the wire-bond pad and flip-flop RDL
Document No.
Version
: T-018-LO-DR-001
: 2.8
8.3.5.6 LVS/RCX
The LVS deck in the half-node process is used to verify the layout vs the schematic. For the RC extraction, if
there are design kits for the half-node process, such as .lib or .db, use these design kits in the STA and the
verilog simulation, and use the RC tech file in the half-node process to get the RC in the half-node process; if
there is no design kit for the half-node process, such as .lib or .db, use the RC tech file in the full-node
process to get the RC in the full-node process, and use the design kits in the full-node process in the STA and
the verilog simulation with additional timing margins.
Design input:
Layout (GDSII, DEF, and Milkyway) in C018 dimension
Spice netlist in C018 dimension
TS
Design output:
LVS matched or not?
M
SPEF or DSPF gate level netlist with C018 parasitic

C
tsmc offering:
C018 LVS deck
C
VI
C018 RCX technology file for sign-off

on 6 NO /2
A
8.3.5.7 IR/EM Analysis

fid 65 LO 009
TE
If there are design kits for the half-node process, such as .lib or .db, use these design kits in the power
en 12 G
calculation, and use the RC tech file in the half-node process to analyze the IR/EM behavior in the design; if
C /0
there is no design kit for the half-node process, such as .lib or .db, use the design kits in the full-node process
tia 1 IES
H 1
to calculate the power consumption, and use the RC tech file in the full-node process to analyze the IR/EM
behavior in the design with the tighten signoff criteria.
12
lI
Design input: P&R layout database (DEF or Milkyway) in C018 dimension

nf
Design output:
or
Chip power analysis in C018 dimension

m
Chip IR/EM analysis result in C018 dimension

at
C018 library kits with C018 timing, power views

io
C016 EM rules
IN
Reasonable IR drop margin

n
C
8.3.5.8 Package
.
Since the minimum pad or bump pitch of the assembly house is usually described in the silicon dimension, the
LVS pin coordinates in the half-node process has to be scaled as 90% to derive the package pin locations for
the assembly house.
Design input: Chip LVS I/O pin location file in C018 drawn dimension
Design output: Package pin location file in C016 silicon dimension
tsmc offering: Pad, bump, and RDL design rules
Customer’s setting:
Notice that minimum pad or bump pitch of assembly house is usually described in silicon dimension.
Scale chip LVS pin text coordinates by 0.9 in spreadsheet to derive package pin locations for assembly
house.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9. Electrical Parameter
This chapter contains the following topics:
9.1 AVAILABLE MOS TRANSISTORS
9.2 KEY PARAMETERS OF MOS TRANSISTORS IN CL018G 1.8/3.3V
9.3 KEY PARAMETERS OF MOS TRANSISTORS IN CL018G 1.8/5V
9.4 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LV 1.5/3.3V
9.5 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LV 1.5/2.5V
9.6 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LP 1.8/3.3V
9.7 KEY PARAMETERS OF MOS TRANSISTORS IN CL018LP 1.8/5V
9.8 KEY PARAMETERS OF MOS TRANSISTORS IN CM018G 1.8/3.3V
9.9 KEY PARAMETERS OF MOS TRANSISTORS IN CL016G 1.8/3.3V
TS
9.10 KEY PARAMETERS OF MOS TRANSISTORS IN CM016G 1.8/3.3V

9.11 KEY PARAMETERS FOR BIPOLAR
9.12 KEY PARAMETERS FOR JUNCTION DIODES
M
9.13 RESISTOR MODEL

C
9.14 INTERCONNECT MODEL

9.15 MIM CAPACITOR MODEL
C
9.16 INDUCTOR MODEL

VI
on 6 NO /2
A
All the dimensions in this chapter are wafer dimensions, unless specified otherwise. The electrical
fid 65 LO 009
parameters are given for T=25°C, unless specified otherwise.

TE
The electrical parameters in this chapter are dependent on the following documents. Please be sure to use
en 12 G
the most update version for circuit design.

C /0
tia 1 IES
H 1
Technology Core/IO Doc NO. Version

1.8/3.3V T-018-LO-SP-001 V2.1
12
G
lI
1.8/5V T-018-LO-SP-010 V1.1

1.5/2.5V T-018-LO-SP-008 V1.0
nf
CL018 LV
1.5/3.3V T-018-LO-SP-004 V1.4
or
1.8/3.3V T-018-LO-SP-002 V1.3

LP
1.8/5V T-018-CL-SP-001 V1.2
m
CL016 G 1.8V/3.3V T-016-CL-SP-001 V1.2

T-018-MM-SP-002 V2.1
at
CM018G G for MS 1.8/3.3V

T-018-CM-SP-007 V1.1
CR018G G for RF 1.8/3.3V T-018-MM-SP-001 V1.5
io
CM016G G for MS 1.8/3.3V T-016-CM-SP-001 V1.4

IN
n
C
9.1 Available MOS Transistors

.
9.1.1 CL018G 1.8/3.3V

Model Name Electric_Tox (Å) l
Minimum Length ( m)
NMOS PMOS NMOS PMOS NMOS PMOS
1.8V Standard Vt MOS nch pch 40.8 40.8 0.18 0.18
3.3V MOS nch3 pch3 68 67.7 0.35 0.3
1.8V Native MOS nanch - 40.8 - 0.5 -
3.3V Native MOS nanch3 - 68 - 1.2 -
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.1.2 CL018G 1.8/5V

Model Name Electric_Tox (Å) Minimum Length ( lm)
5V MOS nch_5 pch_5 133 131 0.6 0.5
9.1.3 CL018LV 1.5/3.3V

TS

M
3.3V MOS nch3 pch3 68 67.7 0.35 0.3

C

C
3.3V Native MOS nanch3 - 68.8 - 1.2 -

VI
on 6 NO /2
A
9.1.4 CL018LV 1.5/2.5V

fid 65 LO 009
lm)
TE
Model Name Electric_Tox (Å) Minimum Length (

en 12 G

C /0

tia 1 IES
H 1
2.5V MOS nch2 pch2 52 50 0.26 0.26

12
lI
1.5V Native MOS nanch napch 35.6 - 0.37 -

nf
9.1.5 CL018LP 1.8/3.3V

or

m

at

io
3.3V MOS nch3 pch3 68 67.7 0.35 0.3

IN
n
C
9.1.6 CL018LP 1.8/5V

.

5V MOS nch_5 pch_5 133 131 0.6 0.5
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.1.7 CM018G 1.8/3.3V

3.3V MOS nch3 pch3 68 67.7 0.35 0.3
3.3V Native MOS nanch3 - 68 - 1.2 -
1.8V Medium Vt MOS mench mepch 40.8 40.8 0.3 0.25
3.3V Medium Vt MOS mench3 - 70 - 0.6 -
TS
9.1.8 CL016G 1.8/3.3V

M

C

C
VI

on 6 NO /2
3.3V MOS nch3 pch3 68 67.7 0.315 0.27

A
fid 65 LO 009

TE
3.3V Native MOS nanch - 68 - 1.2 -

en 12 G
C /0
9.1.9 CM016G 1.8/3.3V

tia 1 IES
H 1
Model Name Electric_Tox (Å) Minimum Length( lm)

12
lI

nf

or
3.3V MOS nch3 pch3 68 67.7 0.315 0.27

m
3.3V Native MOS nanch - 68 - 1.188 -

at
1.8V Medium Vt MOS mench mepch 40.8 40.8 0.27 0.225

io
3.3V Medium Vt MOS mench3 - 70 - 0.54 -

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.2 Key Parameters of MOS Transistors in CL018G

1.8/3.3V
9.2.1 1.8V Standard Vt MOS
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CL018G process.
mL (xl +/-dxl) W (µm) L (µm) Unit NMOS PMOS Definition
mW(xw+/-dxw) um
um
-0.02±0.0133
0±0.022
-0.02±0.0133
0±0.022
TS
Electrical_ Tox Å 40.8±1.330 40.8±1.330

0.42 -0.43
10 10
M
0.07 -0.07 -0.07 0.07

0.49 -0.49
C
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0

0.07 -0.06 -41.98 0.06
C
0.44 -0.49
0.22 0.18
VI
0.08 -0.08 -0.06 0.06

on 6 NO /2
0.35 -0.44
A
10 10
0.07 -0.07 -0.07 0.07
fid 65 LO 009
0.42 -0.5
TE
Vt_lin 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0

0.07 -0.07 -0.07 0.07
en 12 G
0.35 -0.5
C /0
0.22 0.18
0.09 -0.09 -0.07 0.07
tia 1 IES
H 1
10 10 0.35 -0.44
Vt_sat 10 0.18 V 0.38 -0.46 Vg @Vd=Vdd, Vs=Vb=0
12
lI
0.22 0.18 0.3 -0.47

nf
DIBL 10 0.18 V 0.044 -0.037 Vb=0, Vt_lin-Vt_sat

10 0.18 1.67E+02 4.14E+01
or
Id_lin uA/um Id @Vg=Vdd, Vd=0.1V, Vs=Vb=0

0.22 0.18 2.06E+02 4.85E+01
6.01E+02 2.61E+02
m
10 0.18
-14.30% 16.20% -17.50% 21.00%
Id_sat uA/um Id @Vg=Vdd, Vd=Vdd, Vs=Vb=0
at
7.52E+02 2.81E+02
0.22 0.18
-22.30% 27.00% -22.00% 27.90%
io
1.98E+01 6.70E+00
IN
Ioff 10 0.18 pA/um Id @Vg=0, Vd=1.1Vdd, Vs=Vb=0

n
0.131 7.782 0.145 6.751

Slope @Vd=Vdd, Vs=Vb=0,
C
Sub Vt slope 10 0.18 mV/dec 8.99E+01 1.07E+02 Vg1=Vt_sat-0.05, Vg2=Vt_sat-0.06

nVt_sat @Vb=-Vdd/2 and Vb=0
.
Body effect 10 0.18 V 0.185 -0.239

Isub 10 0.18 nA/um 8.55E+01 1.48E-01 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
Covl 10 0.18 fF/um 3.67E-01 3.28E-01 Cgd @Vg=0, Vd=Vdd, Vs=Vb=0
Cj fF/um2 1 1.121 Vrev=0V
Inverter FO=1 Wn/Wp= 28. 1 RO_Td(ring oscillator delay time) @
0.18 ps/gate V=Vdd (Fan_out=1)
Delay 4/10 6.1 -5
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.2.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CL018G process.
oL (xl +/-dxl) W (µm) L (µm) Unit NMOS PMOS Definition

oW(xw+/-dxw) um -0.02±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.74 -0.70
10 10
0.10 -0.10 -0.10 0.10
0.78 -0.65
Vt_gm 10 0.35/0.3 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11 -27.65 0.11
0.68 -0.62
TS
0.22 0.35/0.3
0.09 -0.09 -0.10 0.10
0.68 -0.73
10 10
M
0.10 -0.10 -0.11 0.11

0.72 -0.68
C
Vt_lin 10 0.35/0.3 V Vg @Vd=0.1V, Vs=Vb=0

0.11 -0.11 -0.11 0.12
C
0.63 -0.64
0.22 0.35/0.3
VI
0.10 -0.10 -0.11 0.11

on 6 NO /2
10 10 0.67 -0.73
A
Vt_sat 10 0.35/0.3 V 0.67 -0.65 Vg @Vd=Vdd, Vs=Vb=0

fid 65 LO 009
0.22 0.35/0.3 0.58 -0.61

TE
DIBL 10 0.35/0.3 V 0.050 -0.025 Vb=0, Vt_lin-Vt_sat

en 12 G
10 0.35/0.3 7.99E+01 2.69E+01

C /0
0.22 0.35/0.3 1.02E+02 3.13E+01

6.02E+02 3.01E+02
tia 1 IES
H 1
10 0.35/0.3
-12.7% 14.6% -15.6% 18.3%
12
7.72E+02 3.15E+02
lI
0.22 0.35/0.3
-20.7% 25.7% -24.1% 30.6%
nf
2.17E-02 3.98E-02
Ioff 10 0.35/0.3 pA/um Id @Vg=0, Vd=1.1Vdd, Vs=Vb=0
0.131 10.097 0.107 11.224
or

Sub Vt slope 10 0.35/0.3 mV/dec 1.04E+02 1.08E+02 Vg1=Vt_sat-0.05, Vg2=Vt_sat-0.06
p
m
Body effect 10 0.35/0.3 V 0.399 -0.617 Vt_sat @Vb=-Vdd/2 and Vb=0

Isub 10 0.35/0.3 nA/um 1.678E+03 4.789E+01 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at
Covl 10 0.35/0.3 fF/um 3.17E-01 2.76E-01 Cgd @Vg=0, Vd=Vdd, Vs=Vb=0

Cj fF/um2 0.896 1.035 Vrev=0V
io
Inverter FO=1 Wn/Wp= Ln/Lp= 40.3 RO_Td(ring oscillator delay time) @

IN
ps/gate
n
Delay 4/10 0.35/0.3 5.8 -5 V=Vdd (Fan_out=1)

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.2.3 1.8V Native MOS

The following table summarizes the key parameters for 1.8V Native MOS.
oL (xl +/-dxl) W (µm) L (µm) Unit NMOS Definition

oW(xw+/-dxw) um 0.04±0.04
um 0.15±0.06
Electrical_ Tox Å 75±5.000
-0.02
10 10
0.08 -0.08
0.07
Vt_gm 10 0.5 V Vg @Vd=0.1V, Vs=Vb=0
0.08 -0.08
TS
0.02
0.22 0.5
0.07 -0.07
-0.06
M
10 10
0.08 -0.08
C
0.02
0.08 -0.08
C
-0.04
0.22 0.5
VI
0.08 -0.08
on 6 NO /2
10 10 -0.08
A
Vt_sat 10 0.5 V -0.06 Vg @Vd=Vdd, Vs=Vb=0

fid 65 LO 009
0.22 0.5 -0.24

TE
DIBL 10 0.5 V 0.085 Vb=0, Vt_lin-Vt_sat

en 12 G
10 0.5 9.31E+01
C /0
0.22 0.5 1.04E+02

tia 1 IES
5.97E+02
H 1
10 0.5
-10.9% 11.8%
12
7.15E+02
lI
0.22 0.5
-16.8% 19.6%
nf
1.20E+06
0.096 5.995
or

Sub Vt slope 10 0.5 mV/dec 6.89E+01 Vg1=Vt_sat-0.05, Vg2=Vt_sat-0.06
p
m
Body effect 10 0.5 V 0.012 Vt_sat @Vb=-Vdd/2 and Vb=0

Isub 10 0.5 nA/um 1.042E+01 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at
Covl 10 0.5 fF/um 5.53E-01 Cgd @Vg=0, Vd=Vdd, Vs=Vb=0

io
Cj fF/um2 1.01893 Vrev=0V

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 3.3V Native MOS.

oW(xw+/-dxw) um 0.04±0.04
um 0.15±0.06
-0.11
10 10
0.10 -0.10
-0.16
0.10 -0.10
TS
-0.26
0.22 1.2
0.09 -0.09
-0.12
M
10 10
0.10 -0.10
-0.18
C

0.10 -0.10
C
-0.30
0.22 1.2
VI
0.09 -0.10
on 6 NO /2
10 10 -0.15
A

fid 65 LO 009
0.22 1.2 -0.44

TE

en 12 G
10 1.2 4.53E+01
0.22 1.2 5.21E+01
C /0
6.05E+02
tia 1 IES
10 1.2
H 1
-11.3% 13.0%
6.84E+02
12
0.22 1.2
lI
-19.1% 23.3%
1.15E+07
nf

0.395 1.956
or
Slope @Vd=Vdd, Vs=Vb=0, Vg1=Vt_sat-

Sub Vt slope 10 1.2 mV/dec 7.20E+01 0.05, Vg2=Vt_sat-0.06
p
m

at

io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

1.8/5V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CL018G_5V process.

oW(xw+/-dxw) um
um
-0.02±0.0133
0±0.022
-0.02±0.0133
0±0.022
Electrical_ Tox Å 40.8±1.330 40.8±1.330
TS
0.42 -0.43
10 10
0.07 -0.07 -0.07 0.07
M
0.49 -0.49
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
0.07 -0.06 -41.98 0.06
C
0.44 -0.49
0.22 0.18
0.08 -0.08 -0.06 0.06
C
VI
0.35 -0.44
on 6 NO /2
10 10
0.07 -0.07 -0.07 0.07
A
0.42 -0.50
fid 65 LO 009
0.07 -0.07 -0.07 0.07

TE
0.35 -0.50
0.22 0.18
0.09 -0.09 -0.07 0.07
en 12 G
10 10 0.35 -0.44
C /0

tia 1 IES
H 1
0.22 0.18 0.30 -0.47

12
lI
10 0.18 1.67E+02 4.14E+01

nf
0.22 0.18 2.06E+02 4.85E+01

6.01E+02 2.61E+02
10 0.18
or
-14.3% 16.2% -17.5% 21.0%

7.52E+02 2.81E+02
0.22 0.18
m
-22.3% 27.0% -22.0% 27.9%

1.98E+01 6.70E+00
at

0.131 7.782 0.145 6.751
io

p
IN
Body effect 10 0.18 V 0.185 -0.239 Vt_sat @Vb=-Vdd/2 and Vb=0

C

.
Cj fF/um2 1.000 1.121 Vrev=0V

Inverter FO=1 Wn/Wp= 28.1 RO_Td(ring oscillator delay time) @
Delay 4/10 6.1 -5
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.3.2 5V MOS
The following table summarizes the key parameters for 5V MOS in CL018G_5V process.

oW(xw+/-dxw) um -0.03±0.03 -0.03±0.03
um 0.01±0.03 0.01±0.03
Electrical_ Tox Å 133±13.000 131±13.000
0.79 -0.82
10 10
0.10 -0.10 -0.09 0.09
0.79 -0.80
Vt_gm 10 0.6/0.5 V Vg @Vd=0.1V, Vs=Vb=0
0.10 -0.10 -18.81 0.10
0.55 -0.78
TS
0.22 0.6/0.5
0.10 -0.10 -0.10 0.10
0.76 -0.87
10 10
M
0.10 -0.10 -0.09 0.09

0.76 -0.85
C

0.11 -0.11 -0.11 0.11
0.51 -0.84
C
0.22 0.6/0.5
0.11 -0.11 -0.13 0.12
VI
on 6 NO /2
10 10 0.75 -0.82
A

fid 65 LO 009
0.22 0.6/0.5 0.47 -0.73

TE

en 12 G
10 0.6/0.5 6.33E+01 1.79E+01

0.22 0.6/0.5 6.88E+01 1.65E+01
C /0
5.72E+02 2.61E+02
tia 1 IES
H 1
10 0.6/0.5
-11.7% 13.8% -13.7% 16.9%
6.98E+02 2.35E+02
12
lI
0.22 0.6/0.5
-18.4% 24.5% -29.9% 41.3%
7.11E-04 3.55E-03
nf

0.000 11.001 0.000 8.998
or

p
m

at

Cj fF/um2 0.910 1.170 Vrev=0V
io

IN
ps/gate
n
Delay 4/10 0.6/0.5 8.76 -7.94 V=Vdd (Fan_out=1)

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.4 Key Parameters of MOS Transistors in

CL018LV 1.5/3.3V
The following table summarizes the key parameters for 1.5V Standard Vt MOS in CL018LV process.
oW(xw+/-dxw) um
um
-0.045±0.01
0±0.022
-0.045±0.01
0±0.022
TS
Electrical_ Tox Å 35.6±0.933 36.2±0.933

0.40 -0.37
10 10
0.05 -0.05 -0.04 0.04
M
0.48 -0.41
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
C
0.05 -0.05 -44.77 0.03

0.45 -0.43
0.22 0.18
C
0.04 -0.04 -0.03 0.03

VI
0.34 -0.38
on 6 NO /2
10 10
0.05 -0.05 -0.04 0.04
A
0.42 -0.42
fid 65 LO 009
0.05 -0.05 -0.04 0.04

TE
0.36 -0.41
0.22 0.18
en 12 G
0.05 -0.05 -0.05 0.04

C /0
10 10 0.34 -0.37
tia 1 IES
H 1
0.22 0.18 0.30 -0.33

12

lI
10 0.18 1.68E+02 4.43E+01

nf
0.22 0.18 1.99E+02 5.21E+01

5.75E+02 2.55E+02
10 0.18
or
-13.1% 14.7% -14.0% 16.5%

6.29E+02 2.93E+02
0.22 0.18
m
-19.8% 23.4% -22.0% 27.8%

1.15E+02 7.47E+01
at

0.235 4.234 0.302 3.444
io

p
IN

C

.
Cj fF/um2 1.003 1.151 Vrev=0V

Delay 4/10 4.6 -3.9
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.4.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CL018LV process.

oW(xw+/-dxw) um -0.02±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.74 -0.70
10 10
0.10 -0.10 -0.10 0.10
0.78 -0.65
Vt_gm 10 0.35/0.3 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11 -27.57 0.11
TS
0.76 -0.72
0.22 0.35/0.3
0.10 -0.10 -0.11 0.11
0.68 -0.73
M
10 10
0.10 -0.10 -0.11 0.11
C
0.72 -0.68
0.11 -0.11 -0.11 0.12
C
0.71 -0.75
0.22 0.35/0.3
VI
0.11 -0.11 -0.12 0.12

on 6 NO /2
10 10 0.67 -0.73
A

fid 65 LO 009
0.22 0.35/0.3 0.66 -0.72

TE

en 12 G
10 0.35/0.3 7.96E+01 2.68E+01

C /0
0.22 0.35/0.3 8.55E+01 2.75E+01

tia 1 IES
6.00E+02 3.00E+02
H 1
10 0.35/0.3
-12.7% 14.6% -15.6% 18.3%
12
6.31E+02 2.65E+02
lI
0.22 0.35/0.3
-22.8% 28.5% -25.7% 32.7%
nf
2.17E-02 3.98E-02
0.131 10.083 0.107 11.214
or

p
m

at

io
Cj fF/um2 0.896 1.035 Vrev=0V

Inverter FO=1 Wn/Wp= Ln/Lp= 42.6
IN
RO_Td(ring oscillator delay time) @

ps/gate
n
Delay 4/10 0.35/0.3 6.7 -5.6 V=Vdd (Fan_out=1)

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 1.5V Native MOS in CL018LV process.

oW(xw+/-dxw) um -0.045±0.01
um 0±0.022
Electrical_ Tox Å 35.6±0.933
0.01
10 10
0.12 -0.12
0.15
Vt_gm 10 0.37 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11
TS
0.10
0.22 0.37
0.11 -0.11
M
-0.03
10 10
0.12 -0.12
C
0.09
0.12 -0.12
C
0.03
VI
0.22 0.37
on 6 NO /2
0.12 -0.12
10 10 -0.07
A

fid 65 LO 009
0.22 0.37 -0.06

TE

en 12 G
10 0.37 1.17E+02
Id_lin uA/um
C /0
Id @Vg=Vdd, Vd=0.1V, Vs=Vb=0

0.22 0.37 1.60E+02
tia 1 IES
H 1
6.06E+02
10 0.37
-16.2% 17.7%
Id_sat uA/um
12
Id @Vg=Vdd, Vd=Vdd, Vs=Vb=0

lI
8.47E+02
0.22 0.37
-21.4% 25.0%
nf
6.00E+05
0.040 13.777
or

p
m

at

io

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 3.3V Native MOS in CL018LV process.

oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.09
10 10
0.12 -0.12
-0.14
0.12 -0.12
TS
-0.17
0.22 1.2
0.12 -0.12
-0.12
M
10 10
0.12 -0.12
C
-0.17
0.12 -0.12
C
-0.19
0.22 1.2
VI
on 6 NO /2
0.12 -0.12
10 10 -0.14
A

fid 65 LO 009
0.22 1.2 -0.30

TE

en 12 G
10 1.2 4.42E+01
C /0
0.22 1.2 5.56E+01

tia 1 IES
H 1
5.91E+02
10 1.2
-12.4% 14.4%
12
lI
6.76E+02
0.22 1.2
-19.8% 24.6%
nf
9.21E+06
0.270 2.252
or

p
m

at

io

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CL018LV 1.5/2.5V
The following table summarizes the key parameters for 1.5V Standard Vt MOS in CL018LV_2d5V process.
oW(xw+/-dxw) um
um
-0.045±0.01
0±0.022
-0.045±0.01
0±0.022
TS
Electrical_ Tox Å 35.6±0.933 36.2±0.933

0.40 -0.37
10 10
0.05 -0.05 -0.04 0.04
M
0.48 -0.41
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
C
0.05 -0.05 -44.77 0.03

0.45 -0.43
0.22 0.18
C
0.04 -0.04 -0.03 0.03

VI
0.34 -0.38
on 6 NO /2
10 10
0.05 -0.05 -0.04 0.04
A
0.42 -0.42
fid 65 LO 009
0.05 -0.05 -0.04 0.04

TE
0.36 -0.41
0.22 0.18
en 12 G
0.05 -0.05 -0.05 0.04

C /0
10 10 0.34 -0.37
tia 1 IES
H 1
0.22 0.18 0.30 -0.33

12

lI
10 0.18 1.68E+02 4.43E+01

nf
0.22 0.18 1.99E+02 5.21E+01

5.75E+02 2.55E+02
10 0.18
or
Id_sat uA/um -13.1% 14.7% -14.0% 16.5% Id @Vg=Vdd, Vd=Vdd, Vs=Vb=0

6.29E+02 2.93E+02
m
0.22 0.18
-19.8% 23.4% -22.0% 27.8%
1.15E+02 7.47E+01
at

0.235 4.234 0.302 3.444
io

p
IN

C

.
Cj fF/um2 1.003 1.151 Vrev=0V

Delay 4/10 4.61 -3.9
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.5.2 2.5V MOS

The following table summarizes the key parameters for 2.5V MOS in CL018LV_2d5V process.

oW(xw+/-dxw) um -0.02±0.01 -0.02±0.01
um 0±0.0147 0±0.0147
Electrical_ Tox Å 52±4.000 50±4.000
0.50 -0.61
10 10
0.07 -0.07 -0.05 0.05
0.57 -0.55
Vt_gm 10 0.26 V Vg @Vd=0.1V, Vs=Vb=0
0.07 -0.07 -35.09 0.06
TS
0.54 -0.56
0.22 0.26
0.07 -0.07 -0.06 0.06
0.44 -0.63
M
10 10
0.07 -0.07 -0.05 0.05
C
0.52 -0.56
0.07 -0.07 -0.06 0.06
C
0.49 -0.57
0.22 0.26
VI
0.08 -0.08 -0.07 0.07

on 6 NO /2
10 10 0.44 -0.62
A

fid 65 LO 009
0.22 0.26 0.42 -0.52

TE

en 12 G
10 0.26 1.10E+02 3.45E+01

C /0
0.22 0.26 1.23E+02 3.24E+01

tia 1 IES
6.30E+02 3.00E+02
H 1
10 0.26
-10.8% 12.1% -13.4% 15.8%
12
6.75E+02 2.71E+02
lI
0.22 0.26
-17.2% 20.4% -20.2% 25.2%
nf
3.13E+00 1.54E+00
0.206 5.051 0.263 4.221
or

p
m

Isub 10 0.26 nA/um 4.614E+02 5.328E+00 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at

io
Cj fF/um2 0.939 1.054 Vrev=0V

IN

n
ps/gate V=Vdd (Fan_out=1)

Delay 4/10 0.35/0.3 4.1 -3.6
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 1.5V Native MOS in CL018LV_2d5V process.

oW(xw+/-dxw) um -0.045±0.01
um 0±0.0147
0.01
10 10
0.12 -0.12
0.15
Vt_gm 10 0.37 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11
TS
0.10
0.22 0.37
0.11 -0.11
M
-0.03
10 10
0.12 -0.12
C
0.09
0.12 -0.12
C
0.03
0.22 0.37
VI
on 6 NO /2
0.12 -0.12
10 10 -0.07
A

fid 65 LO 009
0.22 0.37 -0.06

TE

en 12 G
10 0.37 1.17E+02
C /0
0.22 0.37 1.60E+02

tia 1 IES
H 1
6.06E+02
10 0.37
-16.2% 17.7%
12
lI
8.47E+02
0.22 0.37
-21.4% 25.0%
nf
6.00E+05
0.040 13.777
or

p
m

at

io

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CL018LP 1.8/3.3V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CL018LP process.
oW(xw+/-dxw) um
um
-0.02±0.0133
0±0.022
-0.02±0.0133
0±0.022
TS
Electrical_ Tox Å 41.1±1.330 41.5±1.330

0.61 -0.64
10 10
0.05 -0.05 -0.04 0.04
M
0.67 -0.60
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
C
0.06 -0.06 -33.87 0.05

0.58 -0.59
0.22 0.18
C
0.04 -0.05 -0.04 0.04

VI
0.55 -0.65
on 6 NO /2
10 10
0.05 -0.05 -0.04 0.04
A
0.60 -0.61
fid 65 LO 009
0.06 -0.06 -0.05 0.06

TE
0.51 -0.59
0.22 0.18
en 12 G
0.05 -0.06 -0.05 0.05

C /0
10 10 0.55 -0.65
tia 1 IES
H 1
0.22 0.18 0.45 -0.56

12

lI
10 0.18 1.40E+02 3.32E+01

nf
0.22 0.18 1.70E+02 3.74E+01

5.01E+02 1.85E+02
10 0.18
or

6.02E+02 2.12E+02
m
0.22 0.18
-20.6% 25.4% -22.4% 29.6%
3.44E-01 2.30E-01
at

0.202 5.333 0.254 4.326
io

p
IN

C

.
Cj fF/um2 1.239 1.051 Vrev=0V

Delay 4/10 7.3 -6.1
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.6.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CL018LP process.

oW(xw+/-dxw) um -0.02±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.74 -0.70
10 10
0.10 -0.10 -0.10 0.10
0.78 -0.65
Vt_gm 10 0.35/0.3 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11 -27.65 0.11
TS
0.68 -0.62
0.22 0.35/0.3
0.09 -0.09 -0.10 0.10
0.68 -0.73
M
10 10
0.10 -0.10 -0.11 0.11
C
0.72 -0.68
0.11 -0.11 -0.11 0.12
C
0.63 -0.64
0.22 0.35/0.3
VI
0.10 -0.10 -0.11 0.11

on 6 NO /2
10 10 0.67 -0.73
A

fid 65 LO 009
0.22 0.35/0.3 0.58 -0.61

TE

en 12 G
10 0.35/0.3 7.99E+01 2.69E+01

C /0
0.22 0.35/0.3 1.02E+02 3.13E+01

tia 1 IES
6.02E+02 3.01E+02
H 1
10 0.35/0.3
-12.7% 14.6% -15.6% 18.3%
12
7.72E+02 3.15E+02
lI
0.22 0.35/0.3
-20.7% 25.7% -24.1% 30.6%
nf
2.17E-02 3.98E-02
0.131 10.097 0.107 11.224
or

p
m

at

io
Cj fF/um2 0.896 1.035 Vrev=0V

IN

n

Delay 4/10 0.6/0.5 5.8 -5
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CL018LP 1.8/5V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CL018LP_5V process.
oW(xw+/-dxw) um
um
-0.02±0.0133
0±0.022
-0.02±0.0133
0±0.022
TS
Electrical_ Tox Å 41.1±1.330 41.5±1.330

0.61 -0.64
10 10
0.05 -0.05 -0.04 0.04
M
0.67 -0.60
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
C
0.06 -0.06 -33.87 0.05

0.58 -0.59
0.22 0.18
C
0.04 -0.05 -0.04 0.04

VI
0.55 -0.65
on 6 NO /2
10 10
0.05 -0.05 -0.04 0.04
A
0.60 -0.61
fid 65 LO 009
0.06 -0.06 -0.05 0.06

TE
0.51 -0.59
0.22 0.18
en 12 G
0.05 -0.06 -0.05 0.05

C /0
10 10 0.55 -0.65
tia 1 IES
H 1
0.22 0.18 0.45 -0.56

12

lI
10 0.18 1.40E+02 3.32E+01

nf
0.22 0.18 1.70E+02 3.74E+01

5.01E+02 1.85E+02
10 0.18
or
-13.7% 15.5% -16.0% 19.0%

6.02E+02 2.12E+02
0.22 0.18
m
-20.6% 25.4% -22.4% 29.6%

3.44E-01 2.30E-01
at

0.202 5.333 0.254 4.326
io

p
IN

C

.
Cj fF/um2 1.239 1.051 Vrev=0V

Delay 4/10 7.3 -6.1
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.7.2 5V MOS
The following table summarizes the key parameters for 5V MOS in CL018LP_5V process.

oW(xw+/-dxw) um -0.03±0.03 -0.03±0.03
um 0.01±0.03 0.01±0.03
Electrical_ Tox Å 133±13.000 131±13.000
0.79 -0.82
10 10
0.10 -0.10 -0.09 0.09
0.79 -0.84
0.10 -0.10 -15.45 0.10
TS
0.55 -0.78
0.22 0.6/0.5
0.10 -0.10 -0.10 0.10
0.76 -0.87
M
10 10
0.10 -0.10 -0.09 0.09
C
0.76 -0.89
0.11 -0.11 -0.10 0.10
C
0.51 -0.84
0.22 0.6/0.5
VI
0.11 -0.11 -0.13 0.12

on 6 NO /2
10 10 0.75 -0.82
A

fid 65 LO 009
0.22 0.6/0.5 0.47 -0.73

TE

en 12 G
10 0.6 6.33E+01 1.45E+01

C /0
0.22 0.6/0.5 6.88E+01 1.65E+01

tia 1 IES
5.72E+02 2.25E+02
H 1
10 0.6
12
6.98E+02 2.35E+02
lI
0.22 0.6/0.5
-18.4% 24.5% -29.9% 41.3%
nf
7.11E-04 2.13E-03
0.000 11.001 0.000 4.000
or

p
m

Isub 10 0.6 nA/um 7.131E+03 8.794E+02 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at

io
Cj fF/um2 0.910 1.170 Vrev=0V

Inverter FO=1 Wn/Wp= Ln/Lp= 65.37
IN
RO_Td(ring oscillator delay time) @

n

Delay 4/10 0.6/0.5 8.76 -7.94
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.8 Key Parameters of MOS Transistors in CM018G

1.8/3.3V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CM018G process.

oW(xw+/-dxw) um
um
-0.02±0.0133
0±0.022
-0.02±0.0133
0±0.022
Electrical_ Tox Å 40.8±1.330 40.8±1.330
TS
0.42 -0.43
10 10
0.07 -0.07 -0.07 0.07
M
0.49 -0.49
Vt_gm 10 0.18 V Vg @Vd=0.1V, Vs=Vb=0
0.07 -0.06 -41.98 0.06
C
0.44 -0.49
0.22 0.18
0.08 -0.08 -0.06 0.06
C
VI
0.35 -0.44
on 6 NO /2
10 10
0.07 -0.07 -0.07 0.07
A
0.42 -0.50
fid 65 LO 009
0.07 -0.07 -0.07 0.07

TE
0.35 -0.50
0.22 0.18
0.09 -0.09 -0.07 0.07
en 12 G
10 10 0.35 -0.44
C /0

tia 1 IES
H 1
0.22 0.18 0.30 -0.47

12
lI
10 0.18 1.67E+02 4.14E+01

nf
0.22 0.18 2.06E+02 4.85E+01

6.01E+02 2.61E+02
10 0.18
or
-14.3% 16.2% -17.5% 21.0%

7.52E+02 2.81E+02
0.22 0.18
m
-22.3% 27.0% -22.0% 27.9%

1.98E+01 6.70E+00
at

0.131 7.782 0.145 6.751
io

p
IN

Ibmax @Vs=Vb=0, Vd=Vdd, sweep
C
Isub 10 0.18 nA/um 8.549E+01 1.477E-01 Vg

.

Cj fF/um2 1.000 1.121 Vrev=0V
Inverter FO=1 Wn/Wp= 28. 1 RO_Td(ring oscillator delay time)
0.18 ps/gate @ V=Vdd (Fan_out=1)
Delay 4/10 6.1 -5
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.8.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CM018G process.

oW(xw+/-dxw) um -0.02±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.74 -0.70
10 10
0.10 -0.10 -0.10 0.10
0.78 -0.65
Vt_gm 10 0.35/0.3 V Vg @Vd=0.1V, Vs=Vb=0
0.11 -0.11 -27.65 0.11
TS
0.68 -0.62
0.22 0.35/0.3
0.09 -0.09 -0.10 0.10
0.68 -0.73
M
10 10
0.10 -0.10 -0.11 0.11
C
0.72 -0.68
0.11 -0.11 -0.11 0.12
C
0.63 -0.64
0.22 0.35/0.3
VI
0.10 -0.10 -0.11 0.11

on 6 NO /2
10 10 0.67 -0.73
A

fid 65 LO 009
0.22 0.35/0.3 0.58 -0.61

TE

en 12 G
10 0.35/0.3 7.99E+01 2.69E+01

C /0
0.22 0.35/0.3 1.02E+02 3.13E+01

6.02E+02 3.01E+02
tia 1 IES
H 1
10 0.35/0.3
-12.7% 14.6% -15.6% 18.3%
12
7.72E+02 3.15E+02
lI
0.22 0.35/0.3
-20.7% 25.7% -24.1% 30.6%
nf
2.17E-02 3.98E-02
0.131 10.097 0.107 11.224
or

p
m

at
Isub 10 0.35/0.3 nA/um 1.678E+03 4.789E+01 Vg

io
Cj fF/um2 0.896 1.035 Vrev=0V

IN
Inverter FO=1 Wn/Wp= Ln/Lp= 40.3 RO_Td(ring oscillator delay time)

ps/gate @ V=Vdd (Fan_out=1)
Delay 4/10 0.35/0.3 5.8 -5
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 1.8V Native MOS in CM018G process.

oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.02
10 10
0.08 -0.08
0.07
0.08 -0.08
0.02
TS
0.22 0.5
0.07 -0.07
-0.06
10 10
M
0.08 -0.08
0.02
C

0.08 -0.08
-0.04
C
0.22 0.5
0.08 -0.08
VI
on 6 NO /2
10 10 -0.08
A

fid 65 LO 009
0.22 0.5 -0.24

TE

10 0.5 9.31E+01
en 12 G

0.22 0.5 1.04E+02
C /0
5.97E+02
tia 1 IES
10 0.5
H 1
-10.9% 11.8%
7.15E+02
12
0.22 0.5
lI
-16.8% 19.6%
1.20E+06
nf

0.096 5.995
or

p
m

at

io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8


oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.11
10 10
0.10 -0.10
-0.16
0.10 -0.10
TS
-0.26
0.22 1.2
0.09 -0.09
-0.12
M
10 10
0.10 -0.10
-0.18
C

0.10 -0.10
C
-0.30
0.22 1.2
VI
0.09 -0.10
on 6 NO /2
10 10 -0.15
A

fid 65 LO 009
0.22 1.2 -0.44

TE

en 12 G
10 1.2 4.53E+01
0.22 1.2 5.21E+01
C /0
6.05E+02
tia 1 IES
10 1.2
H 1
-11.3% 13.0%
6.84E+02
12
0.22 1.2
lI
-19.1% 23.3%
1.15E+07
nf

0.395 1.956
or

p
m

at

io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.8.5 1.8V Medium Vt MOS

The following table summarizes the key parameters for 1.8V Medium Vt MOS in CM018G process.

oW(xw+/-dxw) um -0.02±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 40.8±1.330 40.8±1.330
0.29 -0.13
10 10
0.10 -0.09 -0.07 0.07
0.31 -0.24
Vt_gm 10 0.3/0.25 V Vg @Vd=0.1V, Vs=Vb=0
0.10 -0.10 -35.95 0.06
TS
0.27 -0.29
0.22 0.3/0.25
0.09 -0.09 -0.06 0.06
0.22 -0.15
M
10 10
0.10 -0.10 -0.07 0.07
C
0.26 -0.26
0.10 -0.10 -0.06 0.06
C
0.18 -0.29
0.22 0.3/0.25
VI
0.10 -0.10 -0.07 0.07

on 6 NO /2
10 10 0.22 -0.13
A

fid 65 LO 009
0.22 0.3/0.25 0.14 -0.24

TE

en 12 G
10 0.3/0.25 1.35E+02 3.57E+01

C /0
0.22 0.3/0.25 1.58E+02 3.58E+01

5.62E+02 2.76E+02
tia 1 IES
H 1
10 0.3/0.25
-14.4% 15.8% -12.3% 13.7%
12
6.81E+02 2.69E+02
lI
0.22 0.3/0.25
-20.9% 24.6% -21.1% 25.0%
nf
6.79E+02 1.11E+03
0.061 16.100 0.138 6.835
or

p
m

Isub 10 0.3/0.25 nA/um 2.760E+01 1.532E-01 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at

io
Cj fF/um2 0.928 1.016 Vrev=0V

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8


oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
0.46
10 10
0.10 -0.10
0.48
0.10 -0.10
TS
0.41
0.22 0.6
0.09 -0.09
0.41
M
10 10
0.10 -0.10
C
0.44
0.10 -0.10
C
0.37
0.22 0.6
VI
0.10 -0.10
on 6 NO /2
10 10 0.41
A
Vt_sat 10 0.6 V 0.43 Vg @Vd=Vdd, Vs=Vb=0

fid 65 LO 009
0.22 0.6 0.35

TE

en 12 G
10 0.6 7.20E+01
C /0
0.22 0.6 1.01E+02

5.59E+02
tia 1 IES
H 1
10 0.6
-12.0% 13.6%
12
6.64E+02
lI
0.22 0.6
-19.5% 23.7%
nf
2.16E+00
0.093 12.119
or

pVt_sat @Vb=-Vdd/2 and Vb=0
m
Body effect 10 0.6 V 0.475

at

io

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

1.8/3.3V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CL016G process.
oW(xw+/-dxw) um
um
-0.002±0.0133
0±0.022
-0.002±0.0133
0±0.022
TS
Electrical_ Tox Å 40.8±1.330 40.8±1.330

0.42 -0.43
10 10
0.07 -0.07 -0.07 0.07
M
0.49 -0.49
Vt_gm 10 0.162 V Vg @Vd=0.1V, Vs=Vb=0
C
0.07 -0.06 -41.98 0.06

0.43 -0.49
0.198 0.162
C
0.08 -0.08 -0.06 0.06

VI
0.35 -0.44
on 6 NO /2
10 10
0.07 -0.07 -0.07 0.07
A
0.42 -0.50
fid 65 LO 009
0.07 -0.07 -0.07 0.07

TE
0.34 -0.50
0.198 0.162
en 12 G
0.09 -0.09 -0.07 0.07

C /0
10 10 0.35 -0.44
tia 1 IES
H 1
0.198 0.162 0.29 -0.47

12

lI
10 0.162 1.67E+02 4.14E+01

nf
0.198 0.162 2.12E+02 5.11E+01

6.01E+02 2.61E+02
10 0.162
or
-14.3% 16.2% -17.5% 21.0%

7.71E+02 2.90E+02
0.198 0.162
m
-23.0% 27.9% -21.8% 28.0%

1.98E+01 6.70E+00
at

0.131 7.782 0.145 6.751
io

p
IN

C

.
Cj fF/um2 1.000 1.121 Vrev=0V

Inverter FO=1 Wn/Wp=
0.162 ps/gate
28.1 RO_Td(ring oscillator delay time) @
Delay 4/10 6.1 -5 V=Vdd (Fan_out=1)
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.9.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CL016G process.
oW(xw+/-dxw) um -0.0146±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.72 -0.69
10 10
0.10 -0.10 -0.09 0.09
Vt_gm V 0.78 -0.65 Vg @Vd=0.1V, Vs=Vb=0
10 0.315/0.27
0.10 -0.11 -26.83 0.10
TS
0.67 -0.61
0.198 0.315/0.27
0.08 -0.09 -0.09 0.09
0.66 -0.72
M
10 10
0.10 -0.10 -0.10 0.10
C
0.73 -0.68
0.11 -0.11 -0.10 0.10
C
0.61 -0.64
0.198 0.315/0.27
VI
on 6 NO /2
0.09 -0.10 -0.10 0.10

10 10 0.66 -0.72
A

fid 65 LO 009
0.198 0.315/0.27 0.55 -0.62

TE

en 12 G
10 0.315/0.27 7.77E+01 2.61E+01

C /0
0.198 0.315/0.27 1.16E+02 3.07E+01

tia 1 IES
H 1
6.03E+02 2.89E+02
10 0.315/0.27
-12.8% 14.8% -14.6% 16.6%
12
lI
8.59E+02 3.42E+02
0.198 0.315/0.27
-20.6% 25.2% -22.6% 28.8%
nf
1.49E-02 1.07E-01
0.119 9.618 0.132 8.705
or

Sub Vt slope 10 0.315/0.27 mV/dec 1.05E+02 1.15E+02 Vg1=Vt_sat-0.05, Vg2=Vt_sat-
m
p
0.06
at
Ibmax @Vs=Vb=0, Vd=Vdd,

Isub 10 0.315/0.27 nA/um 1.833E+03 4.041E+02 sweep Vg
io
Covl 100.315/0.27 fF/um 3.18E-01 2.77E-01 Cgd @Vg=0, Vd=Vdd, Vs=Vb=0

IN
Cj fF/um2 0.896 1.035 Vrev=0V

C

Delay 4/10 0.315/0.27 5.7 -4.8
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 1.8V Native MOS in CL016G process.

oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.02
10 10
0.08 -0.08
0.07
0.08 -0.08
TS
0.02
0.22 0.5
0.07 -0.07
-0.06
M
10 10
0.08 -0.08
C
0.02
0.08 -0.08
C
-0.04
0.22 0.5
VI
0.08 -0.08
on 6 NO /2
10 10 -0.08
A

fid 65 LO 009
0.22 0.5 -0.24

TE

en 12 G
10 0.5 9.31E+01 Id @Vg=Vdd, Vd=0.1V,

Id_lin uA/um
C /0
0.22 0.5 1.04E+02 Vs=Vb=0

tia 1 IES
5.97E+02
H 1
10 0.5
-10.9% 11.8%
12
7.15E+02
lI
0.22 0.5
-16.8% 19.6%
nf
1.20E+06
0.096 5.995
or

Sub Vt slope 10 0.5 mV/dec 6.89E+01 Vg1=Vt_sat-0.05, Vg2=Vt_sat-
m
p
0.06
at

Isub 10 0.5 nA/um 1.042E+01 sweep Vg
io

IN

n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

The following table summarizes the key parameters for 3.3V Native MOS in CL016G process.
oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.11
10 10
0.10 -0.10
-0.16
0.10 -0.10
TS
-0.16
0.22 1.2
0.10 -0.10
-0.12
M
10 10
0.10 -0.10
-0.18
C

0.10 -0.10
C
-0.20
0.22 1.2
VI
0.11 -0.11
on 6 NO /2
10 10 -0.15
A

fid 65 LO 009
0.22 1.2 -0.34

TE

en 12 G
10 1.2 4.52E+01
C /0
0.22 1.2 5.02E+01

6.04E+02
tia 1 IES
H 1
10 1.2
-11.3% 12.9%
12
6.51E+02
lI
0.22 1.2
-19.5% 23.8%
nf
1.14E+07
0.392 1.961
or

m

at
Isub 10 1.2 nA/um 2.936E+01 Vg

io

IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CM016G 1.8/3.3V
The following table summarizes the key parameters for 1.8V Standard Vt MOS in CM016G process.
oW(xw+/-dxw) um
um
-0.002±0.0133
0±0.022
-0.002±0.0133
0±0.022
TS
Electrical_ Tox Å 40.8±1.330 40.8±1.330

0.42 -0.43
10 10
0.07 -0.07 -0.07 0.07
M
0.49 -0.49
Vt_gm 10 0.162 V Vg @Vd=0.1V, Vs=Vb=0
C
0.07 -0.06 -41.98 0.06

0.43 -0.49
0.198 0.162
C
0.08 -0.08 -0.06 0.06

VI
0.35 -0.44
on 6 NO /2
10 10
0.07 -0.07 -0.07 0.07
A
0.42 -0.50
fid 65 LO 009
0.07 -0.07 -0.07 0.07

TE
0.34 -0.50
0.198 0.162
en 12 G
0.09 -0.09 -0.07 0.07

C /0
10 10 0.35 -0.44
tia 1 IES
H 1
0.198 0.162 0.29 -0.47

12

lI
10 0.162 1.67E+02 4.14E+01

nf
0.198 0.162 2.12E+02 5.11E+01

6.01E+02 2.61E+02
10 0.162
or
-14.3% 16.2% -17.5% 21.0%

7.71E+02 2.90E+02
0.198 0.162
m
-23.0% 27.9% -21.8% 28.0%

1.98E+01 6.70E+00
at

0.131 7.782 0.145 6.751
io

p
IN

C

.
Cj fF/um2 1.000 1.121 Vrev=0V

Inverter FO=1 Wn/Wp=
0.162 ps/gate
28.1 RO_Td(ring oscillator delay time) @
Delay 4/10 6.1 -5 V=Vdd (Fan_out=1)
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.10.2 3.3V MOS

The following table summarizes the key parameters for 3.3V MOS in CM016G process.
oW(xw+/-dxw) um -0.0146±0.0133 -0.02±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å 68±7.000 67.7±7.000
0.72 -0.69
10 10
0.10 -0.10 -0.09 0.09
Vt_gm V 0.78 -0.65 Vg @Vd=0.1V, Vs=Vb=0
10 0.315/0.27
0.10 -0.11 -26.83 0.10
TS
0.67 -0.61
0.198 0.315/0.27
0.08 -0.09 -0.09 0.09
0.66 -0.72
M
10 10
0.10 -0.10 -0.10 0.10
C
0.73 -0.68
0.11 -0.11 -0.10 0.10
C
0.61 -0.64
0.198 0.315/0.27
VI
on 6 NO /2
0.09 -0.10 -0.10 0.10

10 10 0.66 -0.72
A

fid 65 LO 009
0.198 0.315/0.27 0.55 -0.62

TE

en 12 G
10 0.315/0.27 7.77E+01 2.61E+01

C /0
0.198 0.315/0.27 1.16E+02 3.07E+01

tia 1 IES
H 1
6.03E+02 2.89E+02
10 0.315/0.27
-12.8% 14.8% -14.6% 16.6%
12
lI
8.59E+02 3.42E+02
0.198 0.315/0.27
-20.6% 25.2% -22.6% 28.8%
nf
1.49E-02 1.07E-01
0.119 9.618 0.132 8.705
or

Sub Vt slope 10 0.315/0.27 mV/dec 1.05E+02 1.15E+02 Vg1=Vt_sat-0.05, Vg2=Vt_sat-
m
p
0.06
at

Isub 10 0.315/0.27 nA/um 1.833E+03 4.041E+02 sweep Vg
io
Covl 100.315/0.27 fF/um 3.18E-01 2.77E-01 Cgd @Vg=0, Vd=Vdd, Vs=Vb=0

IN
Cj fF/um2 0.896 1.035 Vrev=0V

C

Delay 4/10 0.315/0.27 5.7 -4.8
.
Document No.
Version
: T-018-LO-DR-001
: 2.8


oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.02
10 10
0.08 -0.08
0.07
0.08 -0.08
TS
0.02
0.22 0.5
0.07 -0.07
-0.06
M
10 10
0.08 -0.08
C
0.02
0.08 -0.08
C
-0.04
0.22 0.5
VI
0.08 -0.08
on 6 NO /2
10 10 -0.08
A

fid 65 LO 009
0.22 0.5 -0.24

TE

en 12 G
10 0.5 9.31E+01 Id @Vg=Vdd, Vd=0.1V,

Id_lin uA/um
C /0
0.22 0.5 1.04E+02 Vs=Vb=0

tia 1 IES
5.97E+02
H 1
10 0.5
-10.9% 11.8%
12
7.15E+02
lI
0.22 0.5
-16.8% 19.6%
nf
1.20E+06
0.096 5.995
or

Sub Vt slope 10 0.5 mV/dec 6.89E+01 Vg1=Vt_sat-0.05, Vg2=Vt_sat-
m
p
0.06
at

Isub 10 0.5 nA/um 1.042E+01 sweep Vg
io

IN

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Document No.
Version
: T-018-LO-DR-001
: 2.8

oW(xw+/-dxw) um -0.02±0.0133
um 0±0.022
-0.11
10 10
0.10 -0.10
-0.16
0.10 -0.10
TS
-0.16
0.22 1.2
0.10 -0.10
-0.12
M
10 10
0.10 -0.10
-0.18
C

0.10 -0.10
C
-0.20
0.22 1.2
VI
0.11 -0.11
on 6 NO /2
10 10 -0.15
A

fid 65 LO 009
0.22 1.2 -0.34

TE

en 12 G
10 1.2 4.52E+01
C /0
0.22 1.2 5.02E+01

6.04E+02
tia 1 IES
H 1
10 1.2
-11.3% 12.9%
12
6.51E+02
lI
0.22 1.2
-19.5% 23.8%
nf
1.14E+07
0.392 1.961
or

m

at
Isub 10 1.2 nA/um 2.936E+01 Vg

io

IN
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Document No.
Version
: T-018-LO-DR-001
: 2.8

oL (xl +/-dxl) W( qm) L( qm) Unit NMOS PMOS Definition
oW(xw+/-dxw) um
-0.002±0.0133 -0.002±0.0133
um 0±0.022 0±0.022
Electrical_ Tox Å40.8±1.330 40.8±1.330
0.29 -0.13
10 10
0.10 -0.09 -0.07 0.07
0.31 -0.25
Vt_gm 10 0.27/0.225 V Vg @Vd=0.1V, Vs=Vb=0
0.10 -0.10 -36.85 0.06
TS
0.28 -0.30
0.198 0.27/0.225
0.09 -0.09 -0.07 0.06
0.22 -0.15
M
10 10
0.10 -0.10 -0.07 0.07
C
0.26 -0.26
0.10 -0.10 -0.06 0.06
C
0.17 -0.30
0.198 0.27/0.225
VI
0.10 -0.10 -0.08 0.07

on 6 NO /2
10 10 0.22 -0.13
A

fid 65 LO 009
0.198 0.27/0.225 0.15 -0.25

TE

en 12 G
10 0.27/0.225 1.24E+02 3.65E+01

C /0
0.198 0.27/0.225 1.80E+02 3.66E+01

tia 1 IES
5.57E+02 2.81E+02
H 1
10 0.27/0.225
-15.2% 17.0% -12.3% 13.7%
12
7.74E+02 2.72E+02
lI
0.198 0.27/0.225
-17.5% 24.2% -22.1% 26.3%
nf
3.46E+02 1.06E+03
0.062 16.116 0.139 6.777
or

p
m

Isub 10 0.27/0.225 nA/um 2.449E+01 1.597E-01 Ibmax @Vs=Vb=0, Vd=Vdd, sweep Vg
at

io
Cj fF/um2 0.928 1.016 Vrev=0V

IN
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Document No.
Version
: T-018-LO-DR-001
: 2.8

oL (xl +/-dxl) W( qm) L( qm) Unit NMOS Definition
oW(xw+/-dxw) um -0.0146±0.0133
um 0±0.022
0.46
10 10
0.10 -0.10
0.49
Vt_gm 10 0.54 V Vg @Vd=0.1V, Vs=Vb=0
0.10 -0.10
TS
0.39
0.198 0.54
0.09 -0.09
0.41
M
10 10
0.10 -0.10
C
0.45
0.10 -0.10
C
0.36
0.198 0.54
VI
0.10 -0.10
on 6 NO /2
10 10 0.41
A
Vt_sat 10 0.54 V 0.43 Vg @Vd=Vdd, Vs=Vb=0

fid 65 LO 009
0.198 0.54 0.33

TE

en 12 G
10 0.54 7.98E+01
C /0
0.198 0.54 1.26E+02

tia 1 IES
6.10E+02
H 1
10 0.54
-12.1% 13.9%
12
7.59E+02
lI
0.198 0.54
-20.0% 24.4%
nf
2.25E+00
0.096 11.691
or

p
m

at

io

IN
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Document No.
Version
: T-018-LO-DR-001
: 2.8
9.11 Key Parameters for Bipolar

9.11.1 CL018G 1.8/3.3V
The following table summarizes the key parameters for bipolar.
Device Parameter TT SS FF
Vbe 0.639 0.650 0.630
PNP10
beta 2.601 2.213 2.989
Vbe 0.643 0.654 0.634
PNP5
beta 2.681 2.278 3.083
TS
Vbe 0.631 0.642 0.622

PNP2
beta 2.608 2.219 2.997
M
Vbe : VB=VC=0, IE=-1e-8*Area

C
Beta : VB=VC=0, IE=-1e-8*Area

C
VI
on 6 NO /2
Vbe 0.639 0.650 0.630

PNP10_3
beta 2.621 2.230 3.011
A
Vbe 0.641 0.653 0.632

fid 65 LO 009
PNP5_3
beta 2.639 2.243 3.035
TE
Vbe 0.633 0.644 0.624

en 12 G
PNP2_3
beta 2.615 2.225 3.004
C /0
tia 1 IES
H 1

12
lI
nf
9.11.2 CL018G 1.8/5V

or

m
Vbe 0.6385 0.6498 0.6295
at
PNP10
beta 2.6006 2.2125 2.9885
io
Vbe 0.6428 0.6541 0.6337

PNP5
IN
beta 2.6805 2.2782 3.0828

n
Vbe 0.6306 0.6419 0.6216

PNP2
C
beta 2.6082 2.2190 2.9971

.

Document No.
Version
: T-018-LO-DR-001
: 2.8
9.11.3 CL018LV 1.5/3.3V

Device Parameter
Vbe 0.6302
PNP10
beta 2.1110
Vbe 0.6347
PNP5
beta 2.0843
Vbe 0.6249
PNP2
beta 1.9495

TS

M
Device Parameter
C
Vbe 0.6390
PNP10_3
beta 2.2049
C
Vbe 0.6348
PNP5_3
VI
beta 2.1752
on 6 NO /2
Vbe 0.6219
A
PNP2_3
beta 1.9797
fid 65 LO 009
TE

en 12 G

C /0
tia 1 IES
H 1
9.11.4 CL018LV 1.5/2.5V

12
lI

nf
Device Parameter
or
Vbe 0.6302
PNP10
beta 2.1110
m
Vbe 0.6347
PNP5
beta 2.0843
at
Vbe 0.6249
PNP2
beta 1.9495
io
IN

C
.
Device Parameter
Vbe 0.6453
PNP10_2
beta 2.9846
Vbe 0.6379
PNP5_2
beta 3.0482
Vbe 0.6323
PNP2_2
beta 3.0483
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.11.5 CL018LP 1.8/3.3V

Vbe 0.6456 0.6571 0.6365
PNP10
beta 2.8994 2.4667 3.3319
Vbe 0.6385 0.6498 0.6294
PNP5
beta 2.8845 2.4541 3.3147
Vbe 0.6303 0.6415 0.6212
PNP2
beta 2.8807 2.4512 3.3100
TS

M
9.11.6 CL018LP 1.8/5V

C

C
VI
on 6 NO /2
Vbe 0.646 0.657 0.636

PNP10
A
beta 2.889 2.459 3.318

fid 65 LO 009
Vbe 0.639 0.650 0.629

PNP5
TE
beta 2.875 2.447 3.302

Vbe 0.630 0.642 0.621
en 12 G
PNP2
beta 2.881 2.451 3.310
C /0

tia 1 IES
H 1

12
lI
nf
9.11.7 CM018G 1.8/3.3V

or

m
Vbe 0.639 0.650 0.630

PNP10
at
beta 2.601 2.213 2.989

Vbe 0.679 0.690 0.670
PNP5
io
beta 2.677 2.275 3.079

IN
Vbe 0.715 0.726 0.705

n
PNP2
beta 2.606 2.215 2.997
C

.
Vbe 0.629 0.641 0.619
NPN10
beta 17.984 15.790 20.182
Vbe 0.663 0.675 0.653
NPN5
beta 19.244 16.827 21.674
Vbe 0.700 0.713 0.690
NPN2
beta 21.381 18.593 24.190
Vbe : VB=VC=0, IE=1e-8*Area
Beta : VB=VC=0, IE=1e-8*Area
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.11.8 CL016G 1.8/3.3V

Vbe 0.6440 0.6553 0.6349
PNP10
beta 2.6010 2.2127 2.9892
Vbe 0.6482 0.6596 0.6391
PNP5
beta 2.6801 2.2778 3.0824
Vbe 0.6361 0.6474 0.6271
PNP2
beta 2.6087 2.2193 2.9980
TS

M
9.11.9 CM016G 1.8/3.3V

C

C
VI
on 6 NO /2
Vbe 0.644 0.655 0.635

PNP10
beta 2.601 2.213 2.989
A
fid 65 LO 009
Vbe 0.684 0.696 0.675

PNP5
TE
beta 2.676 2.274 3.078

Vbe 0.720 0.732 0.711
en 12 G
PNP2
beta 2.605 2.214 2.995
C /0

tia 1 IES
H 1

12
lI
nf
Vbe 0.634 0.647 0.625

NPN10
beta 16.576 14.497 18.657
or
Vbe 0.668 0.681 0.658

NPN5
beta 17.160 14.942 19.388
m
Vbe 0.706 0.718 0.695

NPN2
beta 17.772 15.381 20.177
at
Vbe : VB=VC=0, IE=1e-8*Area

io
Beta : VB=VC=0, IE=1e-8*Area

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Document No.
Version
: T-018-LO-DR-001
: 2.8
9.12 Key Parameters for Junction Diodes

9.12.1 CL018G 1.8/3.3V
Device Junction CJ CJSW BV N RS IS
(F/m2) (F/m) V ohm/m2 A/m2
N+/PW 1.00E-03 2.04E-10 1.11E+01 1.03E+00 1.00E-10 3.50E-07
1.8V P+/NW 1.12E-03 2.48E-10 1.01E+01 1.03E+00 1.00E-10 2.50E-07
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07
TS
N+/PW 8.96E-04 2.51E-10 1.08E+01 1.00E+00 1.00E-10 3.93E-07

3.3V P+/NW 1.04E-03 2.23E-10 1.03E+01 1.00E+00 1.00E-10 1.90E-07
M
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07

C
ESD N+/PW 1.42E-03 NA NA NA NA NA

C
VI
on 6 NO /2
The area and perimeter components of junction capacitance listed in the table are at V=0 and T=25C.
A
l CJ = Area component of junction capacitance (F/m2).

fid 65 LO 009
TE
l CJSW = STI perimeter component of junction capacitance (F/m).

en 12 G
l BV = Reverse-Biased Breakdown Voltage of STI-Bounded Junction (V).

C /0
l N, RS, IS, and ISW are forward bias related diode parameters.
tia 1 IES
H 1
12
9.12.2 CL018G 1.8/5V

lI
nf

or
N+/PW 1.00E-03 2.04E-10 1.11E+01 1.03E+00 1.00E-10 3.50E-07

m
1.8V P+/NW 1.12E-03 2.48E-10 1.01E+01 1.03E+00 1.00E-10 2.50E-07

at
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07

io
N+/PW 9.10E-04 1.98E-10 1.15E+01 1.05E+00 5.00E-09 4.50E-07

IN
5V P+/NW 1.17E-03 2.46E-10 9.75E+00 1.01E+00 5.00E-09 1.30E-07

n
NW/PSUB 1.18E-04 5.16E-10 1.55E+01 1.05E+00 5.00E-09 9.95E-07

C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.12.3 CL018LV 1.5/3.3V

N+/PW 1.00E-03 2.68E-10 1.11E+01 1.30E+00 2.13E-07 5.02E-06
1.5V P+/NW 1.15E-03 2.81E-10 1.00E+01 1.20E+00 2.03E-07 1.80E-06
NW/PSUB 1.16E-04 5.10E-10 1.48E+01 1.15E+00 2.27E-07 4.56E-07
N+/PW 8.58E-04 2.06E-10 1.13E+01 1.48E+00 1.85E-07 1.00E-05
3.3V
P+/NW 1.03E-03 2.41E-10 1.05E+01 1.43E+00 1.71E-07 2.03E-04
TS
ESD - 1.44E-03 - - - - -
M
C

C

VI
on 6 NO /2

A
fid 65 LO 009
TE
9.12.4 CL018LV 1.5/2.5V

en 12 G
C /0

tia 1 IES
H 1

12
lI
N+/PW 1.00E-03 2.68E-10 1.11E+01 1.30E+00 2.13E-07 5.02E-06

1.5V
nf
P+/NW 1.15E-03 2.81E-10 1.00E+01 1.20E+00 2.03E-07 1.80E-06

NW/PSUB 1.16E-04 5.10E-10 1.48E+01 1.15E+00 2.27E-07 4.56E-07
or
N+/PW 9.39E-04 2.06E-10 1.17E+01 1.24E+00 3.95E-07 3.56E-06

m
2.5V P+/NW 1.05E-03 2.51E-10 1.08E+01 1.26E+00 1.60E-07 8.22E-06

at
NW/PSUB 1.20E-04 5.28E-10 1.46E+01 1.28E+00 3.81E-07 9.82E-06

io
IN
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.

Document No.
Version
: T-018-LO-DR-001
: 2.8
9.12.5 CL018LP 1.8/3.3V

N+/PW 1.24E-03 2.88E-10 1.05E+01 1.03E+00 1.00E-10 4.00E-07
1.8V P+/NW 1.05E-03 2.40E-10 1.03E+01 1.03E+00 1.00E-10 2.88E-07
NW/PSUB 1.15E-04 4.48E-10 1.46E+01 1.03E+00 1.00E-10 8.30E-07
N+/PW 8.96E-04 2.51E-10 1.08E+01 1.00E+00 1.00E-10 3.93E-07
5V P+/NW 1.04E-03 2.23E-10 1.03E+01 1.00E+00 1.00E-10 1.90E-07
TS
NW/PSUB 1.16E-04 5.27E-10 1.46E+01 1.00E+00 1.00E-10 9.03E-07

ESD 1.42E-03 NA NA NA NA NA
M
C
C

VI
on 6 NO /2

A

fid 65 LO 009
TE
en 12 G
C /0
9.12.6 CL018LP 1.8/5V

tia 1 IES
H 1

12
lI

nf
N+/PW 1.24E-03 2.88E-10 1.05E+01 1.03E+00 1.00E-10 4.00E-07

1.8V P+/NW 1.05E-03 2.40E-10 1.03E+01 1.03E+00 1.00E-10 2.88E-07
or
NW/PSUB 1.15E-04 4.48E-10 1.46E+01 1.03E+00 1.00E-10 8.30E-07

m
N+/PW 9.10E-04 1.98E-10 1.15E+01 1.05E+00 5.00E-09 4.50E-07

at
5V P+/NW 1.17E-03 2.46E-10 9.75E+00 1.01E+00 5.00E-09 1.30E-07

io
NW/PSUB 1.18E-04 5.16E-10 1.55E+01 1.05E+00 5.00E-09 9.95E-07

IN
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Document No.
Version
: T-018-LO-DR-001
: 2.8
9.12.7 CM018G 1.8/3.3V

N+/PW 1.00E-03 2.04E-10 1.11E+01 1.03E+00 1.00E-10 3.50E-07
1.8V P+/NW 1.12E-03 2.48E-10 1.01E+01 1.03E+00 1.00E-10 2.50E-07
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07
N+/PW 8.96E-04 2.51E-10 1.08E+01 1.00E+00 1.00E-10 3.93E-07
3.3V P+/NW 1.04E-03 2.23E-10 1.03E+01 1.00E+00 1.00E-10 1.90E-07
TS
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07

M
DNW/PSUB 1.40E-04 1.12E-09 1.47E+01 1.03E+00 1.00E-10 1.40E-06

DNW-PSUB
C
PW/DNW 6.80E-04 5.33E-10 1.45E+01 1.03E+00 1.00E-10 1.20E-06

C
VI
on 6 NO /2
A

fid 65 LO 009
TE

en 12 G

C /0
tia 1 IES
H 1
12
9.12.8 CL016G 1.8/3.3V

lI
nf

or
N+/PW 1.00E-03 2.04E-10 1.11E+01 1.03E+00 1.00E-10 3.50E-07

m
1.8V P+/NW 1.12E-03 2.48E-10 1.01E+01 1.03E+00 1.00E-10 2.50E-07

at
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07

io
N+/PW 8.96E-04 2.51E-10 1.08E+01 1.00E+00 1.00E-10 3.93E-07

IN
3.3V
n
P+/NW 1.04E-03 2.23E-10 1.03E+01 1.00E+00 1.00E-10 1.90E-07

NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10 6.50E-07
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.12.9 CM016G 1.8/3.3V

Device Junction CJ CJSW BV N RS
(F/m2) (F/m) V ohm/m2
N+/PW 1.00E-03 2.04E-10 1.11E+01 1.03E+00 1.00E-10
1.8V P+/NW 1.12E-03 2.48E-10 1.01E+01 1.03E+00 1.00E-10
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10
N+/PW 8.96E-04 2.51E-10 1.08E+01 1.00E+00 1.00E-10
3.3V P+/NW 1.04E-03 2.23E-10 1.03E+01 1.00E+00 1.00E-10
TS
NW/PSUB 1.34E-04 5.33E-10 1.48E+01 1.03E+00 1.00E-10

ESD 1.42E-03 NA NA NA NA
M
DNW/PSUB 1.40E-04 1.12E-09 1.47E+01 1.03E+00 1.00E-10

DNW-PSUB
C
PW/DNW 6.80E-04 5.33E-10 1.45E+01 1.03E+00 1.00E-10

C
VI
on 6 NO /2
A

fid 65 LO 009

TE

en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13 Resistor Model

9.13.1 CL018G 1.8/3.3V Resistor Model
The measurement results from the testchip are listed below:
(a) Sheet Resistance Table :
film Valid Rsh Unit TC1 TC2 VC1 VC2 deltaW

Width Mean/Range (µm)
P+ Poly w/i Silicide W≥2.0 7.9±2.5 Ω/sq 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.025
TS
P+ Poly w/i Silicide 0.18≤W<2.0 7.9± 2.5 Ω/sq 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.025
N+ Poly w/i Silicide W≥2.0 7.89± 2 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
M
N+ Poly w/i Silicide 0.18≤W<2.0 7.89± 2 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
N+ Diff. w/o Silicide W≥2.0 59±5.8 Ω/sq 1.47E-3 8.32E-7 7.55E-4 1.97E-4 -
C
N+ Diff. w/i Silicide W≥2.0 6.82± 2.5 Ω/sq 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.0765
C
N+ Diff. w/i Silicide 0.22≤W<2.0 6.82± 2.5 Ω/sq 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.0765
VI
P+ Diff. w/o Silicide W≥2.0 133±19 Ω/sq 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
on 6 NO /2
P+ Diff. w/i Silicide W≥2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
A
P+ Diff. w/i Silicide 0.22≤W<2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
fid 65 LO 009
N-well. Under OD W≥20 440±100 Ω/sq 3.68E-3 9.54E-6 2.77E-3 2.49E-4 0.141
TE
N-well. Under STI W≥20 927±132 Ω/sq 2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
en 12 G
M1 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

C /0
M2 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

tia 1 IES
M3 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

H 1
M4 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

12
M5 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

lI
M6 - 0.036±0.009 Ω/sq 3.60E-3 -1.16E-7 NA NA 0.04

nf
RC_N+ - 11 (<30) Ω/ct 1.31E-3 3.16E-7 - - -

RC_P+ - 10 (<30) Ω/ct 1.44E-3 1.46E-6 - - -
or
RC_PO(N+) - 7.8 (<30) Ω/ct 1.53E-3 -5.7E-8 - - -

RC_PO(P+) - 7.8 (<30) Ω/ct 1.44E-3 1.7E-7 - - -
m
RC_VIA1 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

at
RC_VIA2 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA3 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -
io
RC_VIA4 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

IN
RC_VIA5 - 2.54 (<13) 4.94E-4 1.19E-6 - - -

n
Ω/ct
C
The Model valid range of NW resistor is W>20 um, Square>5

.
* The Model valid range of OD resistor is W>2 um, Square>5

* RSH values for N+ and P+ Diff. w/i silicide are geometry dependent. Metal sheet
resistances are measured from bridge-type resistors.
* The resistor values can be written as follows for the resistors, N+/P+ poly w/i silicide, N+, NW and P+:
R= R0*[1+ VC1 * dV + VC2]* (dV)2]*[1+ TC1 * dT + TC2]* (dT)2]; where d– = T - Tnominal (25 °C).
The resistors are functoin of temperature and the valid range is –40 °C ~ 125 °C.
Also, the resistors are function of voltage and the valid range: N+/P+ poly w/i silicide : -3.3 ~ 3.3V
N+ , NW : 0 ~ 3.3V
P+ : -3.3 ~ 0 V
The resistance is measured with one node of resistor grounded, whereas the other node is applied by V and
dV is the voltage across the resistor.
R0 is layout-dependent and calculated from sheet resistance. The equation is:
R0 = Rsh * (L –deltaL)/ ( W – deltaW ) ; L is the drawn Length(um) and W is the drawn width(um).
l The deltaW listed and deltaL in the above table are all electrical values.
Document No.
Version
: T-018-LO-DR-001
: 2.8
(b) Resistor Equivalent Circuit Model for P+ & N+ poly w/o silicide
The following figure describes the circuit model of N+/P+ poly resistor w/o silicide. Two types
of sub-resistors usually are used to model these N+/P+ poly resistors. The Rend sub-resistors
represent the contributions from the interface resistance (Rint, due to the depletion of dopant
near the interface between RPO and silicide) and the contact resistance (Rc) from both ends
where the contacts are formed in a single column format as recommend by the design rule,
while the Rpure sub-resistor represents the primary contribution of RPO.
The model valid range of poly RPO resistors is W>1 um Square>2.
n1 n2 n1 Ren Rpure Ren n2

CoSi2 CoSi2 d d
N+ or P+ Poly w/o Silicide
TS
Circuit model
Cross-section of N+ or P+ poly w/o silicide resistor
M
Resistor size(drawn):L,W
C
R=2*Rend+Rpure
Rend=Rend0/(W-DeltaW)
C
Rpure=Rsh*(L-DeltaL)/(W-DeltaW)
VI
on 6 NO /2
Film
A
P+ poly w/o silicide N+ poly w/o silicide

fid 65 LO 009
Parameters
TE
Rsh(Ohm/square) 311±46.65 292±43.8

Rend0(Ohm-m) 7.2135E-5 3.2586E-5
en 12 G
For Rpure (Tcp1) -7.541E-5 -1.184E-3

C /0
TC1
For Rend (Tce1) -1.692E-3 -1.372E-3
tia 1 IES
H 1
For Rpure (Tcp2) 3.561E-7 1.3835E-6

TC2
For Rend (Tce2) -9.616E-6 -1.680E-5
12
lI
For Rpure (Vcp1) -1.10E-3 -1.87E-2

VC1
nf
For Rend (Vce1) -1.45E-2 2.7643E3

For Rpure (Vcp2) 3.2532E-5 1.6513E-5
VC2
or
For Rend (Vce2) 62.8187 1.40E-3

For Rpure (Vcp3) -4.3249 -2.0496
m
VC3 For Rend (Vce3) -2.2165 0.3712

at
dl(um) 0.0006 -0.04225

*
dw(um) 0.06165 0.091373
io

IN
*The resistor values can be expressed as follows for N+/P+ poly w/o silicide resistors:
n
R= 2*Rend+Rpure;
where Rend=Rend0/(W-dW)*{1+vce1*[tanh(vce2*| dVe|+vce3)-tanh(vce3)]}*[1+ TCE1 * dT + TCE2 * (dT)2]
C
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+
.
TCP1 * dT + TCP2 * (dT)2]
dT = T – Tnormal (25 °C)

dL: Delta L
dVe: voltage drop acorss Rend; dVp: voltage drop across Rpure.
l The resistance measured is a function of temperature and the valid range is –40 ~ 125 °C. In addition, it is
also a function of voltage and the valid current density range is 0 ~ 0.5mA/um.
l The resistance is measured with one node of resistor grounded, whereas the other node is applied by
current.
l The models are only valid when resistor layout follows the corresponding design rule.
l Because of using different modeling methodology, the voltage coefficients are different from the report T-
018-MMRP-004 and T-018-MMRP-007. However, both models can describe the resistor behavior well.
l The P+ poly w/o silicide test pattern includes both P+ and PLDD (P2V) implants.
The N+ poly w/o silicide test pattern includes both N+ and NLDD (N2V) implants.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.2 CL018G 1.8/5V Resistor Model

Film Valid Rsh Unit TC1 TC2 VC1 VC2 deltaW
N+ Diff. w/o Silicide - 59±5.8 Ω/sq 1.47E-3 8.32E-7 7.55E-4 1.97E-4 -
TS
M
P+ Diff. w/o Silicide - 133±19 Ω/sq 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -

C
P+ Diff. w/i Silicide 0.22≤W<2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
N-well. Under OD - 440±100 Ω/sq 3.68E-3 9.54E-6 2.77E-3 2.49E-4 0.141

VI
N-well. Under STI - 927±132 Ω/sq 2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
on 6 NO /2
M1 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

A
M2 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

fid 65 LO 009
M3 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

TE
M4 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

en 12 G
M5 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

C /0
M6 - 0.036±0.009 Ω/sq 3.60E-3 -1.16E-7 NA NA 0.04

tia 1 IES
H 1
RC_N+ - 11 (<30) Ω/ct 1.31E-3 3.16E-7 - - -

RC_P+ - 10 (<30) Ω/ct 1.44E-3 1.46E-6 - - -
12
lI
RC_PO(N+) - 7.8 (<30) Ω/ct 1.53E-3 -5.7E-8 - - -

RC_PO(P+) - 7.8 (<30) Ω/ct 1.44E-3 1.7E-7 - - -
nf
RC_VIA1 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA2 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -
or
RC_VIA3 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

m
RC_VIA4 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA5 - 2.54 (<13) Ω/ct 4.94E-4 1.19E-6 - - -
at
io

IN
C
.
Also, the resistors are function of voltage and the valid range: N+/P+ poly w/i silicide : -5 ~ 5V
N+ , NW : 0 ~ 5V
P+ : -5 ~ 0 V
*The mean values of resistors are obtained based on limited statistical data, whereas the range values are
obtained from statistical data of about 3*sigma.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CoSi2 CoSi2 d d
TS

Circuit model
M

C
R=2*Rend+Rpure
C
VI
on 6 NO /2
A
Film
fid 65 LO 009

Parameters
TE
Rsh(Ohm/square) 311±46.65 311.3±46.8

en 12 G
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

C /0
For Rpure (Tcp1) -7.541E-5 -1.184E-3

TC1
tia 1 IES
H 1
For Rend (Tce1) -1.692E-3 -1.372E-3

For Rpure (Tcp2) 3.561E-7 1.3835E-6
12
TC2
lI
For Rend (Tce2) -9.616E-6 -1.680E-5

For Rpure (Vcp1) -1.10E-3 -1.87E-2
nf
VC1
For Rend (Vce1) -1.45E-2 2.7643E3
For Rpure (Vcp2) 3.2532E-5 1.6513E-5
or
VC2
For Rend (Vce2) 62.8187 1.40E-3
VC3 For Rpure (Vcp3) -4.3249 -2.0496
m
For Rend (Vce3) -2.2165 0.3712

at
dl(um) 0.0006 -0.04225

dw(um) 0.06165 0.091373
io
IN
R= 2*Rend+Rpure;
C

.
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+ TCP1

* dT + TCP2 * (dT)2]
dL: Delta L
current.
l The mean values of resistors are obtained based on limited statistical data, whereas the range values are
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.3 CL018LV 1.5/3.3V Resistance Model

Valid Rs Rint deltaW
Film Unit TC1 TC2 VC1 VC2
Width Mean/Range (Ω-µm) (µm)
P+ Poly w/o Silicide - 341±50Ω/sq TBD
-2.58E-4 8.32E-7 -7.99E-5 -6.71E-5 -
P+ Poly w/i Silicide W≥2.0 7.8±2.5
Ω/sq -
2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
P+ Poly w/i Silicide 0.18≤W ≤2.0 6.7±3.5
Ω/sq -
2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
N+ Poly w/o Silicide - 330±62Ω/sq TBD
-1.46E-3 2.35E-6 -1.10E-4 -1.29E-4 -
N+ Poly w/i Silicide W≥2.0 7.4±2Ω/sq -
2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
N+ Poly w/i Silicide 0.18≤W ≤2.0 5.7±4.2
Ω/sq -
2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
TS
N+ Diff. w/o Silicide - 65±6.4Ω/sq -

1.44E-3 7.58E-7 9.66E-4 1.53E-4 -
N+ Diff. w/i Silicide W≥2.0 6.8±2.5
Ω/sq -
3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
M
N+ Diff. w/i Silicide 0.22≤W ≤2.0 4.1±2.75

Ω/sq -
3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
P+ Diff. w/o Silicide - 133±19Ω/sq -
1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
C
P+ Diff. w/i Silicide W≥2.0 7.2±3Ω/sq -

3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.148
P+ Diff. w/i Silicide 0.22≤W ≤2.0 4.4±2Ω/sq -
3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.148
C
N-well. Under OD - 450±100Ω/sq -

3.68E-3 9.54E-6 2.77E-3 2.49E-4 0.141
VI
on 6 NO /2
N-well. Under STI - 927±132Ω/sq -

2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
A
M1 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
fid 65 LO 009
M2 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
TE
M3 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
M4 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
en 12 G
M5 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
C /0
M6 - 0.036±0.009
Ω/sq -
3.60E-3 -1.16E-7 NA NA 0.04
tia 1 IES
H 1
RC_N+ - 11 (<30)
Ω/ct -
1.31E-3 3.16E-7 - - -
RC_P+ - 10 (<30)
Ω/ct -
1.44E-3 1.46E-6 - - -
12
lI
RC_PO(N+) - 7.8 (<30)

Ω/ct -
1.53E-3 -5.7E-8 - - -
nf
RC_PO(P+) - 7.8 (<30)

Ω/ct -
1.44E-3 1.7E-7 - - -
RC_VIA1 - 6.4 (<20)
Ω/ct -
9.58E-4 -4.63E-7 - - -
or
RC_VIA2 - 6.4 (<20)

Ω/ct -
9.58E-4 -4.63E-7 - - -
RC_VIA3 - 6.4 (<20)
Ω/ct -
9.58E-4 -4.63E-7 - - -
m
RC_VIA4 - 6.4 (<20)

Ω/ct -
9.58E-4 -4.63E-7 - - -
RC_VIA5 - 2.54 (<13)
Ω/ct -
4.94E-4 1.19E-6 - - -
at
*RSH values for N+ and P+ Diff. w/i silicide are geometry dependent. Metal sheet resistance are measured from bridge-
type resistors.
io
* Rint is described in Resistor Equivalent Circuit Model.

IN
* NW diffusion resistor under STI strongly depends on CMP variation. Users are recommended to use NW resistor under
n
OD type for design. Please refer to tsmc design rule for detailed layout guideline.
C
* The resistor values are functions of temperature as follows:

R(T)= R0 * [1+ TC1 * dT + TC2]* (dT)2]; where d– = T - Tnominal (25 °C)
.
Valid range : -40 °C ~ 125 °C

* The resistor values are functions of voltage as follows:
R(V)= R0 * [1+ VC1 * dV + VC2]* (dV)2]
Valid range : N+/P+ poly : -3.3 ~ 3.3V
N+ , NW : 0 ~ 3.3V
P+ : -3.3 ~ 0 V
The resistance is measured with one node of resistor grounded, whereas the other node is applied by V and dV is the
voltage across the resistor.
* R0 is layout-dependent and calculated from sheet resistance. The equation is :
R0 = RSH * L / ( W – deltaW ) ; W is the drawn width.
* The deltaW listed in the above table are all electrical values.
* The mean values of resistors are obtained based on limited statistical data, whereas the range values are obtained
based on ~six standard deviation of statistical data.
TBD: To be determined from test structures by 8/31/99
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.4 CL018LV 1.5/2.5V Resistance Model

(b) Sheet Resistance Table :
Valid Rs Rint deltaW
Film Unit TC1 TC2 VC1 VC2
P+ Poly w/o Silicide - 341±50
Ω/sq TBD
-2.58E-4 8.32E-7 -7.99E-5 -6.71E-5 -
P+ Poly w/i Silicide W≥2.0 7.8±2.5
Ω/sq -
2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
P+ Poly w/i Silicide 0.18≤W ≤2.0 6.7±3.5
Ω/sq -
2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
N+ Poly w/o Silicide - 330±62
Ω/sq TBD
-1.46E-3 2.35E-6 -1.10E-4 -1.29E-4 -
N+ Poly w/i Silicide W≥2.0 7.4±2
Ω/sq -
2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
N+ Poly w/i Silicide 0.18≤W ≤2.0 5.7±4.2
Ω/sq -
2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
TS
N+ Diff. w/o Silicide - 65±6.4

Ω/sq -
1.44E-3 7.58E-7 9.66E-4 1.53E-4 -
N+ Diff. w/i Silicide W≥2.0 6.8±2.5
Ω/sq -
3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
M
N+ Diff. w/i Silicide 0.22≤W ≤2.0 4.1±2.75

Ω/sq -
3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
P+ Diff. w/o Silicide - 133±19
Ω/sq -
1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
C
P+ Diff. w/i Silicide W≥2.0 7.2±3

Ω/sq -
3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.148
P+ Diff. w/i Silicide 0.22≤W ≤2.0 4.4±2
Ω/sq -
3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.148
C
N-well. Under OD - 450±100

Ω/sq -
3.68E-3 9.54E-6 2.77E-3 2.49E-4 0.141
VI
on 6 NO /2
N-well. Under STI - 927±132

Ω/sq -
2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
A
M1 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
fid 65 LO 009
M2 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
TE
M3 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
M4 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
en 12 G
M5 - 0.078±0.023
Ω/sq -
3.43E-3 -1.08E-6 NA NA 0.03
C /0
M6 - 0.036±0.009
Ω/sq -
3.60E-3 -1.16E-7 NA NA 0.04
tia 1 IES
H 1
RC_N+ - 11 (<30)
Ω/ct -
1.31E-3 3.16E-7 - - -
RC_P+ - 10 (<30)
Ω/ct -
1.44E-3 1.46E-6 - - -
12
lI
RC_PO(N+) - 7.8 (<30)

Ω/ct -
1.53E-3 -5.7E-8 - - -
nf
RC_PO(P+) - 7.8 (<30)

Ω/ct -
1.44E-3 1.7E-7 - - -
RC_VIA1 - 6.4 (<20)
Ω/ct -
9.58E-4 -4.63E-7 - - -
or
RC_VIA2 - 6.4 (<20)

Ω/ct -
9.58E-4 -4.63E-7 - - -
RC_VIA3 - 6.4 (<20)
Ω/ct -
9.58E-4 -4.63E-7 - - -
m
RC_VIA4 - 6.4 (<20)

Ω/ct -
9.58E-4 -4.63E-7 - - -
RC_VIA5 - 2.54 (<13)
Ω/ct -
4.94E-4 1.19E-6 - - -
at
* RSH values for N+ and P+ Diff. w/i silicide are geometry dependent. Metal sheet resistance are
measured from bridge-type resistors.
io
* Rint is described in Resistor Equivalent Circuit Model.

IN
* NW diffusion resistor under STI strongly depends on CMP variation. Users are recommended to use NW resistor under
n
OD type for design. Please refer to tsmc design rule for detailed layout guideline.
C
* The resistor values are functions of temperature as follows:

R(T)= R0 * [1+ TC1 * dT + TC2]* (dT)2]; where d– = T - Tnominal (25 °C)
.

* The resistor values are functions of voltage as follows:
R(V)= R0 * [1+ VC1 * dV + VC2]* (dV)2]
Valid range : N+/P+ poly : -2.5 ~ 2.5V
N+ , NW : 0 ~ 2.5V
P+ : -2.5 ~ 0 V
The resistance is measured with one node of resistor grounded, whereas the other node is applied by V and dV is the
voltage across the resistor.
* R0 is layout-dependent and calculated from sheet resistance. The equation is :
R0 = RSH * L / ( W – deltaW ) ; W is the drawn width.
* The deltaW listed in the above table are all electrical values.
* The mean values of resistors are obtained based on limited statistical data, whereas the range values are obtained
based on ~six standard deviation of statistical data.
* TBD: To be determined from test structures by 8/31/99
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.5 CL018LP 1.8/3.3V Resistor Model

(c) Sheet Resistance Table :
Film Valid Rs Unit Rint TC1 TC2 VC1 VC2 deltaW
P+ Poly w/I Silicide W≥2.0 7.9±2.5 Ω/sq - 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
P+ Poly w/I Silicide 0.18≤W ≤2.0 7.9± 3.5 Ω/sq - 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.051
N+ Poly w/I Silicide W≥2.0 7.89± 2 Ω/sq - 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
N+ Poly w/I Silicide 0.18≤W ≤2.0 7.89 ± 4.2 Ω/sq - 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.065
N+ Diff. w/o Silicide - 59±5.8 Ω/sq - 1.47E-3 8.32E-7 7.55E-4 1.97E-4 -
N+ Diff. w/I Silicide W≥2.0 6.82± 2.5 Ω/sq - 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
TS
N+ Diff. w/I Silicide 0.22≤W ≤2.0 6.82 ± 2.5 Ω/sq - 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.165
P+ Diff. w/o Silicide - 133±19 Ω/sq - 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
M
P+ Diff. w/I Silicide W≥2.0 7.76± 3 Ω/sq - 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
P+ Diff. w/I Silicide 0.22≤W ≤2.0 7.76± 3 Ω/sq - 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
N-well. Under OD - 410±100 Ω/sq - 2.72E-3 7.70E-6 4.42E-3 -2.64E-4 0.141

C
N-well. Under STI - 927±132 Ω/sq - 2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
VI
M1 - 0.078±0.023 Ω/sq - 3.43E-3 -1.08E-6 NA NA 0.03

on 6 NO /2
M2 - 0.078±0.023 Ω/sq - 3.43E-3 -1.08E-6 NA NA 0.03

A
M3 - 0.078±0.023 Ω/sq - 3.43E-3 -1.08E-6 NA NA 0.03

fid 65 LO 009
M4 - 0.078±0.023 Ω/sq - 3.43E-3 -1.08E-6 NA NA 0.03

TE
M5 - 0.078±0.023 Ω/sq - 3.43E-3 -1.08E-6 NA NA 0.03

en 12 G
M6 - 0.036±0.009 Ω/sq - 3.60E-3 -1.16E-7 NA NA 0.04

C /0
RC_N+ - 11 (<30) Ω/ct - 1.31E-3 3.16E-7 - - -

RC_P+ - 10 (<30) Ω/ct - 1.44E-3 1.46E-6 - - -
tia 1 IES
H 1
RC_PO(N+) - 7.8 (<30) Ω/ct - 1.53E-3 -5.7E-8 - - -

12
RC_PO(P+) - 7.8 (<30) Ω/ct - 1.44E-3 1.7E-7 - - -

lI
RC_VIA1 - 6.4 (<20) Ω/ct - 9.58E-4 -4.63E-7 - - -

nf
RC_VIA2 - 6.4 (<20) Ω/ct - 9.58E-4 -4.63E-7 - - -

RC_VIA3 - 6.4 (<20) Ω/ct - 9.58E-4 -4.63E-7 - - -
or
RC_VIA4 - 6.4 (<20) Ω/ct - 9.58E-4 -4.63E-7 - - -

RC_VIA5 - 2.54 (<13) Ω/ct - 4.94E-4 1.19E-6 - - -
m
at
io
IN
n
N+ , NW : 0 ~ 3.3V
C
P+ : -3.3 ~ 0 V
.
l the mean values of resistors are obtained based on limited statistical data, whereas the range values are
Document No.
Version
: T-018-LO-DR-001
: 2.8

CoSi2 CoSi2 d d
TS
Circuit model
M
R=2*Rend+Rpure
C
C
VI
on 6 NO /2
Film
A

Parameters
fid 65 LO 009
Rsh(Ohm/square) 311±46.65 292±43.8

TE
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

en 12 G
For Rpure (Tcp1) -7.541E-5 -1.184E-3

TC1
C /0
For Rend (Tce1) -1.692E-3 -1.372E-3

tia 1 IES
For Rpure (Tcp2) 3.561E-7 1.3835E-6

H 1
TC2
For Rend (Tce2) -9.616E-6 -1.680E-5
12
For Rpure (Vcp1) -1.10E-3 -1.87E-2

lI
VC1
For Rend (Vce1) -1.45E-2 2.7643E3
nf
For Rpure (Vcp2) 3.2532E-5 1.6513E-5

VC2
For Rend (Vce2) 62.8187 1.40E-3
or
For Rpure (Vcp3) -4.3249 -2.0496

VC3 For Rend (Vce3) -2.2165 0.3712
m
dl(um) 0.0006 -0.04225

dw(um) 0.06165 0.091373
at
io
R= 2*Rend+Rpure;
IN

n
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+ TCP1

C
* dT + TCP2 * (dT)2]
.

dL: Delta L
current.
l Because of using different modeling methodology, the voltage coefficients are different from the report T-
018-MMRP-004 and T-018-MMRP-007. However, both models can describe the resistor behavior well.
l the mean values of resistors are obtained based on limited statistical data, whereas the range values are
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.6 CL018LP 1.8/5V Resistor Model

(d) Sheet Resistance Table :
Film Valid Rs Unit TC1 TC2 VC1 VC2 deltaW
P+ Poly w/i Silicide 0.18≤W≤2.0 7.9±2.5 Ω/sq 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.025
N+ Poly w/i Silicide 0.18≤W≤2.0 7.89± 2 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
N+ Diff. w/o Silicide - 59±5.8 Ω/sq 1.47E-3 8.32E-7 7.55E-4 1.97E-4 -
TS
N+ Diff. w/i Silicide 0.22≤W≤2.0 6.82± 2. 5 Ω/sq 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.0765
M
P+ Diff. w/o Silicide - 133±19 Ω/sq 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -

C
P+ Diff. w/i Silicide 0.22≤W≤2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
N-well. Under OD - 410±120 Ω/sq 2.72E-3 7.70E-6 4.42E-3 -2.64E-4 0.141

VI
N-well. Under STI - 927±132 Ω/sq 2.97E-3 1.10E-5 8.06E-3 -3.32E-4 0.182
on 6 NO /2
M1 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

A
M2 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

fid 65 LO 009
M3 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

TE
M4 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

en 12 G
M5 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

C /0
M6 - 0.036±0.009 Ω/sq 3.60E-3 -1.16E-7 NA NA 0.04

tia 1 IES
H 1
RC_N+ - 11 (<30) Ω/ct 1.31E-3 3.16E-7 - - -

RC_P+ - 10 (<30) Ω/ct 1.44E-3 1.46E-6 - - -
12
lI
RC_PO(N+) - 7.8 (<30) Ω/ct 1.53E-3 -5.7E-8 - - -

RC_PO(P+) - 7.8 (<30) Ω/ct 1.44E-3 1.7E-7 - - -
nf
RC_VIA1 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA2 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -
or
RC_VIA3 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

m
RC_VIA4 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA5 - 2.54 (<13) Ω/ct 4.94E-4 1.19E-6 - - -
at
io

IN
C
.
Also, the resistors are function of voltage and the valid range: N+/P+ poly w/i silicide :-5~5V
N+ , NW : 0 ~ 5V
P+ : -5 ~ 0 V
l The mean values of resistors are obtained based on limited statistical data, whereas the range values are
obtained from statistical data of about 3*sigma
*
Document No.
Version
: T-018-LO-DR-001
: 2.8

CoSi2 CoSi2 d d
TS

Circuit model
M
C
R=2*Rend+Rpure
C
VI
on 6 NO /2
A
Film
fid 65 LO 009

Parameters
TE
Rsh(Ohm/square) 311±46.65 311.3±46.8

en 12 G
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

C /0
For Rpure (Tcp1) -7.541E-5 -1.184E-3

TC1
tia 1 IES
For Rend (Tce1) -1.692E-3 -1.372E-3

H 1
For Rpure (Tcp2) 3.561E-7 1.3835E-6

TC2
12
For Rend (Tce2) -9.616E-6 -1.680E-5

lI
For Rpure (Vcp1) -1.10E-3 -1.87E-2

VC1
nf
For Rend (Vce1) -1.45E-2 2.7643E3

For Rpure (Vcp2) 3.2532E-5 1.6513E-5
or
VC2
For Rend (Vce2) 62.8187 1.40E-3
For Rpure (Vcp3) -4.3249 -2.0496
m
VC3 For Rend (Vce3) -2.2165 0.3712

dl(um) 0.0006 -0.04225
at
dw(um) 0.06165 0.091373

io
IN
R= 2*Rend+Rpure;
C
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+ TCP1 * dT +

.
TCP2 * (dT)2]
dL: Delta L
l The resistance measured is a function of temperature and the valid range is –40 ~ 125 °C. In addition, it is also a
function of voltage and the valid current density range is 0 ~ 0.5mA/um.
l The resistance is measured with one node of resistor grounded, whereas the other node is applied by current.
l Because of using different modeling methodology, the voltage coefficients are different from the report T-018-MMRP-
004 and T-018-MMRP-007. However, both models can describe the resistor behavior well.
l The mean values of resistors are obtained based on limited statistical data, whereas the range values are obtained
from statistical data of about 3*sigma
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.7 CM018G 1.8/3.3V Resistance Model

Film Valid Rsh Unit TC1 TC2 VC1 VC2 deltaW
P+ Poly w/i Silicide W≥2.0 7.9± 2.5 Ω/sq 2.88E-3 5.01E-7 -7.89E-4 6.19E-3 -0.025
TS
N+ diff. w/o Silicide W≥2.0 59± 5.8 Ω/sq 1.47E-3 8.32E-7 7.55E-4 1.97E-4 -
N+ diff. w/i Silicide W≥2.0 6.82± 2.5 Ω/sq 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.0765
M
N+ diff. w/i Silicide 0.22≤W<2.0 6.82± 2.5 Ω/sq 3.35E-3 4.31E-7 7.56E-5 1.24E-3 -0.0765
P+ diff. w/o Silicide 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
C
W≥2.0 133±19 Ω/sq

P+ diff. w/i Silicide W≥2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
P+ diff. w/i Silicide 0.22≤W<2.0 7.76± 3 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
VI
on 6 NO /2
A
M1 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

fid 65 LO 009
M2 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

TE
M3 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

en 12 G
M4 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

C /0
M5 - 0.078±0.023 Ω/sq 3.43E-3 -1.08E-6 NA NA 0.03

tia 1 IES
M6 - 3.60E-3 -1.16E-7 NA NA 0.04

H 1
0.036±0.009 Ω/sq
RC_N+ - 11 (<30) Ω/ct 1.31E-3 3.16E-7 - - -
12
lI
RC_P+ - 10 (<30) Ω/ct 1.44E-3 1.46E-6 - - -

RC_PO(N+) - 7.8 (<30) Ω/ct 1.53E-3 -5.7E-8 - - -
nf
RC_PO(P+) - 7.8 (<30) Ω/ct 1.44E-3 1.7E-7 - - -

RC_VIA1 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -
or
RC_VIA2 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -

RC_VIA3 - 6.4 (<20) 9.58E-4 -4.63E-7 - - -
m
Ω/ct
RC_VIA4 - 6.4 (<20) Ω/ct 9.58E-4 -4.63E-7 - - -
at
RC_VIA5 - 2.54 (<13) Ω/ct 4.94E-4 1.19E-6 - - -

io
* The Model valid range of NW resistor is W>20 um, Square>5

IN

n
RSH values for N+ and P+ diff. w/i silicide are geometry dependent.
C
* Metal sheet resistances are measured from bridge-type resistors.

.
R= R0*[1+ VC1 * dV + VC2 * (dV)2]*[1+ TC1 * dT + TC2 * (dT)2]; where dT = T - Tnominal (25 °C).
The resistors are functoin of temperature and the valid range is -40 °C ~ 125 °C.
N+ , NW : 0 ~ 3.3V
P+ : -3.3 ~ 0 V
* The deltaW listed and deltaL in the above table are all electrical values.
Document No.
Version
: T-018-LO-DR-001
: 2.8

CoSi2 CoSi2 d d
TS
Circuit model
M
R=2*Rend+Rpure
C
C
VI
on 6 NO /2
Film
A

Parameters
fid 65 LO 009
Rsh(Ohm/square) 311±46.65 292±43.8

TE
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

en 12 G
For Rpure (Tcp1) -7.541E-5 -1.184E-3

C /0
TC1
For Rend (Tce1) -1.692E-3 -1.372E-3
tia 1 IES
H 1
For Rpure (Tcp2) 3.561E-7 1.3835E-6

TC2
For Rend (Tce2) -9.616E-6 -1.680E-5
12
lI
For Rpure (Vcp1) -1.10E-3 -1.87E-2

VC1
For Rend (Vce1) -1.45E-2 2.7643E3
nf
For Rpure (Vcp2) 3.2532E-5 1.6513E-5

VC2
For Rend (Vce2) 62.8187 1.40E-3
or
For Rpure (Vcp3) -4.3249 -2.0496

VC3 For Rend (Vce3) -2.2165 0.3712
m
dl(um) 0.0006 -0.04225

at
dw(um) 0.06165 0.091373

io
* The model valid range of poly RPO resistors is W>1 um Square>2.

IN
n
R= 2*Rend+Rpure;
C

.

TCP2 * (dT)2]
dT = T - Tnormal (25 °C)
dL: Delta L
* The resistance measured is a function of temperature and the valid range is -40 ~ 125 °C. In addition, it is
* The resistance is measured with one node of resistor grounded, whereas the other node is applied by current.
* The models are only valid when resistor layout follows the corresponding design rule.
* Because of using different modeling methodology, the voltage coefficients are different from the report T-018-
MMRP-004 and T-018-MMRP-007. However, both models can describe the resistor behavior well.
* The P+ poly w/o silicide test pattern includes both P+ and PLDD (P2V) implants.
Document No.
Version
: T-018-LO-DR-001
: 2.8
(c) Resistor Equivalent Circuit Model for Diffused and Ion-Implanted Resistor
This model is designed for the AC effect of diffused and ion-implanted resistor. The model
accounts for the effects of geometry, temperature, bias, and includes parasitic p-n junction
model. The following figures are the equivalent circuit models.
* The following functions have been implemented into the model :
(1) resistor values are functions of temperature :
R(T)= R0 * [1+ TC1 * dT + TC2 * (dT)2]; where dT = T - Tnominal (25 °C)
(2) resistor values are functions of voltage :
R(V)= R0 * [1+ VC1 * dV +VC2 * (dV)2];
Valid range : N+/P+ poly : -3.3 ~ 3.3 V
N+, NW : 0 ~ 3.3 V
TS
P+ : -3.3 ~ 0 V

M
rst u vws xyz{{

X
xws vyz{{
C
Y vyz{{s x|}~
C
|| |z }|z {zz||

VI
on 6 NO /2
A

fid 65 LO 009

TE
r r r r
en 12 G
C /0
DA DB DB DB DA DA DB DB DB DA
tia 1 IES
H 1
v r r r r

12
lI
} z{ u vw vyz{{ z|| } z{ u xw z||
nf
or
§¨£ ¦ ¡

« ¢¦¢¬¤®
£ ¤¥¦ ¯° ¦ « ¦¢ ²¬¤®
© ª
§³£ £ ´« ©¦¶¬¤
«·¬¦¢¬¤® ¯° ª ±
©²¬¤®
©
m
ª
µ© ¦ª«¦¢¢
at
io
Model usage guideline:

IN
It is necessary to call Junction Diode model when using the equivalent circuit models.
Equivalent circuit model table:
C
There are three different libraries in this model: res_t, res_b and res_w represent three cases:
.
typical, best and worst respectively.
Resistor type Subckt name

N+ diff. w/i silicide (W≥2.0) rnod_m
N+ diff. w/i silicide (0.22≤W<2.0) rnodw_m
P+ diff. w/i silicide (W≥2.0) rpod_m
P+ diff. w/i silicide (0.22≤W<2.0) rpodw_m
N+ diff. w/o silicide rnodrpo_m
P+ diff. w/o silicide rpodrpo_m
NW diffusion (under OD) rnwod_m
All equivalent circuit models are included in the file “ResModel.spi” stored in the 3”1/2 floppy.
The values of sheet resistance for typical case, best case and worst case are the mean values,
low spec. and high spec. in Sheet Resistance Table (section 7.4), respectively.
Document No.
Version
: T-018-LO-DR-001
: 2.8
(d) Circuit Model for HRI P- Poly Resistors w/o Silicide

The following figure describes the circuit model of HRI P- poly resistor w/o silicide. Two types
of sub-resistors are used to model the HRI P- poly resistors. The Rend sub-resistors represent
the contributions from the interface resistance (i.e. Rint, due to the depletion of dopant near the
interface between RPO and silicide.) and the contact resistance (i.e. Rc) from both ends where
contacts are opened in a single column as recommended in the Design Rule. The Rpure sub-
resistor represents the primary contribution of HRI RPO. The model valid range of poly RPO
resistors is W>1 um Square>2.

CoSi2 CoSi2 d d
HRI P- Poly w/o Silicide
TS
Circuit model
Cross-section of HRI P- poly w/o silicide resistor
M
R=2*Rend+Rpure
C
C
VI
on 6 NO /2
A
fid 65 LO 009
Film
HRI P- poly w/o silicide
TE
Parameters
en 12 G
Rsh(Ohm/square) 1075.37±161.3
Rend0(Ohm-m) 4.944E-5
C /0
For Rp (Tcp1) -1.112E-3

tia 1 IES
H 1
TC1
For Rend (Tce1) -2.335E-3
For Rpure (Tcp2) 2.775E-6
12
lI
TC2
For Rend (Tce2) 3.933E-6
nf
For Rpure (Vcp1) -6.353E-2

VC1
For Rend (Vce1) -2.909E-1
or
For Rpure (Vcp2) 2.979E-6

VC2
For Rend (Vce2) -39.02
m
VC3 For Rpure (Vcp3) -1.486

For Rend (Vce3) 8.339E-1
at
dl(um) 0.0145
dw(um) 0.07382
io
IN
* The model valid range of poly RPO resistors is W>1 um Square>2.

C
R= 2*Rend+Rpure;
.

TCP2 * (dT)2]
dT = T - Tnormal (25 °C)
dL: Delta L
* The resistance measured is a function of temperature and the valid range is -40 ~ 125 °C. In addition, it is
* The resistance is measured with one node of resistor grounded, whereas the other node is applied by current.
l * The models are only valid when resistor layout follows the corresponding design rule.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.8 CL016G 1.8/3.3V Resistor Model

(a) Sheet Resistance Table:
N+ Poly w/i Silicide W≥2.0 7.4± 1.88 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
N+ Poly w/i Silicide 0.18≤W<2.0 7.4± 1.88 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
TS
M
P+ Diff. w/o Silicide W≥2.0 133±19 Ω/sq 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
C
P+ Diff. w/i Silicide W≥2.0 7.1± 2.75 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
P+ Diff. w/i Silicide 0.198≤W<2.0 7.1± 2.75 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
VI
on 6 NO /2
M1 - 0.111±0.033 Ω/sq 3.10E-3 -3.89E-7 NA NA 0.02

A
M2 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

fid 65 LO 009
M3 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

TE
M4 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

en 12 G
M5 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

C /0
M6 - 0.036±0.009 Ω/sq 3.50E-3 2.19E-7 NA NA 0.03

tia 1 IES
H 1
RC_N+ - 10.5 (<30) Ω/ct 4.97e-4 1.13e-6 - - -

RC_P+ - 10.8 (<30) Ω/ct 7.99e-4 3.84e-7 - - -
12
lI
RC_PO(N+) - 9.3 (<30) Ω/ct 7.56e-4 5.52e-7 - - -

RC_PO(P+) - 9.7 (<30) Ω/ct 7.76e-4 5.58e-7 - - -
nf
RC_VIA1 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -

RC_VIA2 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -
or
RC_VIA3 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -

m
RC_VIA4 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -

RC_VIA5 - 2.8 (<13) Ω/ct 7.93e-4 -5.53e-8 - - -
at

io

IN
n
resistances are
C
measured from bridge-type resistors.

.
N+ , NW : 0 ~ 3.3V
P+ : -3.3 ~ 0 V
The resistance is measured with one node of resistor grounded, whereas the other node is applied by V
and dV is the voltage across the resistor.
Document No.
Version
: T-018-LO-DR-001
: 2.8
n1 n2 Rpure Ren n2
n1 Ren
CoSi2 CoSi2 d d
TS

Circuit model
M
R=2*Rend+Rpure
C
C
VI
on 6 NO /2
Film
A
Parameters
fid 65 LO 009
Rsh(Ohm/square) 311±46.65 292±43.8

TE
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

For Rpure (Tcp1) -7.541E-5 -1.184E-3
en 12 G
TC1
C /0
-1.692E-3
For Rpure (Tcp2) 3.561E-7 1.3835E-6
tia 1 IES
H 1
TC2
For Rend (Tce2) -9.616E-6 -1.680E-5
12
For Rpure (Vcp1) -1.10E-3 -1.87E-2

lI
VC1
For Rend (Vce1) -1.45E-2 2.7643E3
nf
For Rpure (Vcp2) 3.2532E-5 1.6513E-5

VC2
For Rend (Vce2) 62.8187 1.40E-3
or
For Rpure (Vcp3) -4.3249 -2.0496

VC3 For Rend (Vce3) -2.2165 0.3712
m
dl(um) 0.0006 -0.04225

at
dw(um) 0.06165 0.091373

io
IN
*The model valid range of poly RPO resistors is W>1 um Square>2.

n
R= 2*Rend+Rpure;
C

.
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+ TCP1 * dT

+ TCP2 * (dT)2]

dL: Delta L
current.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.13.9 CM016G 1.8/3.3V Resistor Model

(a) Sheet Resistance Table:
N+ Poly w/i Silicide W≥2.0 7.4± 1.88 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
N+ Poly w/i Silicide 0.18≤W<2.0 7.4± 1.88 Ω/sq 2.92E-3 2.66E-7 1.35E-3 7.15E-3 -0.057
TS
M
P+ Diff. w/o Silicide Ω/sq 1.43E-3 7.82E-7 -1.19E-3 -1.80E-4 -
C
W≥2.0 133±19
P+ Diff. w/i Silicide W≥2.0 7.1± 2.75 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
C
P+ Diff. w/i Silicide 0.198≤W<2.0 7.1± 2.75 Ω/sq 3.44E-3 5.02E-7 -2.51E-4 1.03E-3 -0.08
VI
on 6 NO /2
A
M1 - 0.111±0.033 Ω/sq 3.10E-3 -3.89E-7 NA NA 0.02

fid 65 LO 009
M2 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

TE
M3 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

en 12 G
M4 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

C /0
M5 - 0.078±0.023 Ω/sq 3.26E-3 -1.53E-6 NA NA 0.03

tia 1 IES
M6 - 0.036±0.009 Ω/sq 3.50E-3 2.19E-7 NA NA 0.03

H 1
RC_N+ - 10.5 (<30) Ω/ct 4.97e-4 1.13e-6 - - -

12
lI
RC_P+ - 10.8 (<30) Ω/ct 7.99e-4 3.84e-7 - - -

RC_PO(N+) - 9.3 (<30) Ω/ct 7.56e-4 5.52e-7 - - -
nf
RC_PO(P+) - 9.7 (<30) Ω/ct 7.76e-4 5.58e-7 - - -

RC_VIA1 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -
or
RC_VIA2 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -

RC_VIA3 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -
m
RC_VIA4 - 6.4 (<20) Ω/ct 7.93e-4 -5.53e-8 - - -

at
RC_VIA5 - 2.8 (<13) Ω/ct 7.93e-4 -5.53e-8 - - -

io

IN

n
C

.
N+ , NW : 0 ~ 3.3V
P+ : -3.3 ~ 0 V
Document No.
Version
: T-018-LO-DR-001
: 2.8
n1 n2 Rpure Ren n2
n1 Ren
CoSi2 CoSi2 d d
¸¹ º» ¼¹ ¼º½¾ ¿Àº ÁÂ½ÂÃÂÄÅ
TS
Circuit model
M
R=2*Rend+Rpure
C
C
VI
on 6 NO /2
Film
A
Parameters
fid 65 LO 009
Rsh(Ohm/square) 311±46.65 292±43.8

TE
Rend0(Ohm-m) 7.2135E-5 3.2586E-5

For Rpure (Tcp1) -7.541E-5 -1.184E-3
en 12 G
TC1
C /0
-1.692E-3
For Rpure (Tcp2) 3.561E-7 1.3835E-6
tia 1 IES
H 1
TC2
For Rend (Tce2) -9.616E-6 -1.680E-5
12
For Rpure (Vcp1) -1.10E-3 -1.87E-2

lI
VC1
For Rend (Vce1) -1.45E-2 2.7643E3
nf
For Rpure (Vcp2) 3.2532E-5 1.6513E-5

VC2
For Rend (Vce2) 62.8187 1.40E-3
or
For Rpure (Vcp3) -4.3249 -2.0496

VC3 For Rend (Vce3) -2.2165 0.3712
m
dl(um) 0.0006 -0.04225

at
dw(um) 0.06165 0.091373

io
IN
l The model valid range of poly RPO resistors is W>1 um Square>2.

n
C
R= 2*Rend+Rpure;
.
Rpure=Rsh(L-dL)/(W-dW)*{1+vcp1*[tanh(vcp2*| dVp|/(L-dL)+vcp3)-tanh(vcp3)]}*[1+
TCP1 * dT + TCP2 * (dT)2]

dL: Delta L
l The resistance measured is a function of temperature and the valid range is –40 ~ 125 °C. In
addition, it is also a function of voltage and the valid current density range is 0 ~ 0.5mA/um.
l The resistance is measured with one node of resistor grounded, whereas the other node is
applied by current.
l The N+ poly w/o silicide test pattern includes both N+ and NLDD (N2V) implants.
Document No.
Version
: T-018-LO-DR-001
: 2.8
(c) Circuit Model for HRI P- Poly Resistors w/o Silicide

The following figure describes the circuit model of P- HRI poly resistor w/o silicide. Two
types of sub-resistors usually are used to model the P- HRI poly resistors. The Rend sub-
resistors represent the contributions from the interface resistance (Rint, due to the depletion
of dopant near the interface between RPO and silicide.) and the contact resistance (Rc)
from both ends where contacts are opened in a single column as recommended in the
Æ Æ
Design Rule, while the Rpure sub-resistor represents the primary contribution of RPO.
These poly RPO resistors valid range is W 0.9 um Square 2.
n1 n2
CoSi2 CoSi2
TS
P- HRI Poly w/o Silicide
Cross-section of P- HRI poly w/o silicide resistor

M
C
The model equations are expressed in terms of the dependence of voltage, temperature and
C
dimension.
VI
on 6 NO /2
Rend = Rend 0 /(W − δWend ) ⋅ (1 + tce1 ⋅ δT + tce 2 ⋅ δT 2 ) ⋅ (VCR _ end (Ve ))

A
(6-1)
fid 65 LO 009
2
R p = R sh ⋅ ( L − δL ) /(W − δW ) ⋅ (1 + tcp1 ⋅ δT + tcp 2 ⋅ δT ) ⋅ (VCR _ main (Vp ))
TE
(6-2)
en 12 G
where δT = T – 25 (in °C), Vp and Ve (in volt) are the voltage drops across Rp and
C /0
Rend components, respectively. Rend0 is the Rend resistance value at 25 °C and an

tia 1 IES
H 1
infinitesimal voltage. ∆L is the length offset.

12
lI
For voltage dependence modeling (VCR_end and VCR_main), the second order polynomial
based equations are used to avoid the occurrence of negative resistance during the
nf
simulation iteration. Please refer to equation (6-3) for convex shape and equation (6-4) for
concave shape.
or
VCR = ½ * [1 + 1/(1 + Jc1 * (V/L)^2)]

(6-3)
m
VCR = ½ * [3 - 1/(1 + Jc1 * (V/L)^2)]

at
(6-4)
For temperature dependence modeling, the second order polynomial equation used by other resistor
io
models is also employed here. Finally, the median sheet resistance values and their corresponding
IN
variations, Rend0, temperature coefficients, voltage coefficients extracted based on the methodology
described above.
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.14 Interconnect Model

9.14.1 Interconnection line-line capacitance
The interconnection line-line capacitance simulation results, using TMA RAPHAEL (v98.4) with
five parallel lines above one plate and between two plates, are listed in this section.
The simulation structures are :
Struct–re A - Conductors array above the infinite plate :

ÇÊ ÇÊ
TS
M
ÇÉ ÇÈ ÇÉ
C
ËÌÍÍÌÎ ÏÐÑÍÒ
C
VI
on 6 NO /2
Structure B – Conductors array between two infinite plates :

A
ÛÚÝ ÝÞßÛà
fid 65 LO 009
Ó×á ÓáÕÖ Ó×á

TE
ÓØ ÓØ
en 12 G
C /0
tia 1 IES
H 1
Ó×Ô ÓÔÕÖ Ó×Ô

12
ÙÚÛÛÚÜ ÝÞßÛà
lI
nf
or
Note: The figures of structure A and structure B shown before here are schematic. The
dielectric patterns between metals are quite complicated. For detail structures please refer to
m
the cross section scheme in the next page.

at
1) The conduction line is using the min. width of design rule.

io
2) For structure A, the top layer is used as conduction line layer, and the bottom conduction
IN
layer is used as the infinite plate.

For structure B, the middle layer is used as conduction line layer, and the top and bottom
C
conduction layers are used as the infinite plates.

.
3) The dielectric thickness uses the “TYPICAL” dielectric thickness in order to take care of
process variations rather than measurement thickness of previous data. Moreover, the
technology information are listed below:
Document No.
Version
: T-018-LO-DR-001
: 2.8
TECHNOLOGY PARAMETERS FOR TYPICAL CASE:

Conductor layers
Conductor Thickness Min. width Min. space Distance between conductor
layer and substrate under
FOX
PO1 2000 0.18 m(DOM) 0.25 m(DOM) 3500
0.16 m(DOS) 0.27 m(DOS)
M1 5300 0.23 m 0.23 m 11000
M2 5300 0.28 m 0.28 m 24800
M3 5300 0.28 m 0.28 m 38600
M4 5300 0.28 m 0.28 m 52400
M5 5300 0.28 m 0.28 m 66200
TS
CTM 1900 4 m 1.2 m 71690

M6 9900 0.44 m 0.46 m 81500
UTM (20KÅ) 23400
M
1.50 µm 1.50 µm 81500

UTM (40KÅ) 46000 2.60 µm 2.50 µm 81500
C
Dielectric layers
C
VI
Dielectric Thickness %Var Dielectric Comments

on 6 NO /2
constant
A
FOX 3500 ± 17.1% 3.9 See NOTE 4.

fid 65 LO 009
ILD 7500 ± 21.4% 4.0 See NOTE 1.

TE
IMD1a 11800 ± 20% 3.7 See NOTE 1.

en 12 G
IMD1b 2000 ± 3% 4.2

C /0
IMD2a 11800 ± 20% 3.7 See NOTE 1.

tia 1 IES
H 1
IMD2b 2000 ± 3% 4.2

IMD3a 11800 ± 20% 3.7 See NOTE 1.
12
lI
IMD3b 2000 ± 3% 4.2

IMD4a 11800 ± 20% 3.7 See NOTE 1.
nf
IMD4b 2000 ± 3% 4.2

or
IMD5a 11800 ± 20% 3.7 See NOTE 1.

IMD5b 3500 ± 3% 4.2
m
PASS1 10000 ± 10% 4.2 See NOTE 2.

at
PASS1(20KÅ UTM) 25000 ± 10% 4.2 See NOTE 2.

PASS1(40KÅ UTM) 36000 ± 10% 4.2
io
PASS2 1500 ± 10% 4.2

IN
PASS3 6000 ± 10% 7.9 Conformal material.

C
NOTE 1. The dielectric layers of ILD, IMD1b, IMD2b, IMD3b, IMD4b and IMD5b outside the
.
metal are overetched 1000

NOTE 2. The dielectric layer of PASS1 is deposited using HDP approach, which results in facet
formation and stationary fronts. The highest height above top metal with minimum
width is 5000 ; however, the highest height above top metal with width larger than
2 m is 10000 .
NOTE 3. CTM is only used for the MIM capacitors, not allowed for used on interconnection.
NOTE 4. The thickness of FOX under PO1 is 500Å thicker than that under ILD.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Scheme of cross section of interconnection structure:
PASS
3
PASS
2
PASS
M6 M6 M6 M6 1
IMD5b
TS
CTM
Insulator IMD5a
M5 M5 M5
M
M5
IMD4b
C
C
IMD4a
M4 M4 M4 M4
VI
on 6 NO /2
IMD3b
A
fid 65 LO 009
IMD3a
TE
M3 M3 M3 M3
en 12 G
IMD2b
C /0
tia 1 IES
H 1
M2 IMD2a
M2 M2 M2
12
lI
IMD1b
nf
M1 M1 IMD1a
M1
or
M1
m
ILD
at
PO1 PO1 P PO1

io
O1
FOX
IN
Active region
C
Substrate
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
4) The method for calculating the max/min dielectric thickness are listed below :
ã
∑â â ∗
â
â ∗
â
â â
∑â â ∗
â
= ±
äåæ ’s are the variations of interlayer dielectrics among metals, air, and substrate, and
çèéèêë is effective total variation between two layers. Then the min/max value is computed by
Where
çèéèêë from the mean value. The final dielectrics thickness are ìí î .
TS
subtracting or adding
M
5) For structure A,
C
Ctotal : total capacitance of the top center line

Cc : line-to-line coupling capacitance of top center line to neighbor line
C
Cbottom : Ca + 2 * Cf
VI
on 6 NO /2
Ca: area capacitance of top layer to bottom layer

[ ï
( line_width ) * ( εox / dielectric_thickness ) ]
A
Cf : fringe capacitance per side of top center line to infinite bottom plate
fid 65 LO 009
Csum : Ca + 2 * Cf + 2 * Cc
TE
en 12 G
For structure B,
C /0
Ctotal : total capacitance of the middle center line

tia 1 IES
H 1
Cc : line-to-line coupling capacitance of middle center line to neighbor line

Cbottom : Cb_area + 2 * Cfb
12
lI
Cb_area : area capacitance of middle layer to bottom layer

[ ï( line_width ) * (εox / dielectric_thickness ) ]
nf
Cfb : fringe capacitance per side of middle center line to infinite bottom plate
or
Ctop : Ct_area + 2 * Cft

Ct_area : area capacitance of middle layer to top layer
ï
m
[ ( line_width ) * (εox / dielectric_thickness ) ]

Cft: fringe capacitance per side of middle center line to infinite top plate
at
Csum : ( Cb_area + 2 * Cfb ) + ( Ct_area + 2 * Cft ) + 2 * Cc

io
6) The simulation results of the line-to-line capacitance and the fringe capacitance of min. line-
IN
width with various spacing for both structures A & B (TYPICAL, WORST, and BEST cases) are
stored in a 3.5” floppy disk.
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.14.2 TYPICAL INTERCONNECT CAPACITANCE TABLE

9.14.2.1 Normal metal scheme
*** Structure A ***
Structure (as drawn) (after process bias)
width space width space Ctotal Cc Cbottom Ca Cf Csum/Ctotal
(um) (um) (um) (um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um)
PO1-FOX 0.18 0.25 0.16 0.27 1.44E-01 4.66E-02 4.10E-02 1.38E-02 1.36E-02 93.50%
0.18 1.98 0.16 2 9.92E-02 4.32E-03 8.85E-02 1.38E-02 3.73E-02 97.90%
TS
*** Structure A *** (continued)

structure width space Ctotal Cc Cbottom Ca Cf Csum/Ctotal
M
(um) (um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um)

C
M1-FOX 0.23 0.23 2.43E-01 1.05E-01 1.99E-02 7.35E-03 6.26E-03 94.20%

0.23 2 9.10E-02 1.44E-02 5.66E-02 7.35E-03 2.46E-02 93.90%
C
VI
M1-OD 0.23 0.23 2.46E-01 1.04E-01 2.66E-02 1.09E-02 7.89E-03 95.10%

on 6 NO /2
0.23 2 1.02E-01 1.19E-02 7.30E-02 1.09E-02 3.11E-02 95.10%

A
M1-PO1(FOX) 0.23 0.23 2.47E-01 1.01E-01 3.40E-02 1.48E-02 9.57E-03 95.70%

fid 65 LO 009
TE
0.23 2 1.12E-01 1.01E-02 8.69E-02 1.48E-02 3.61E-02 96.00%

M1-PO1(OD) 0.23 0.23 2.49E-01 1.02E-01 3.45E-02 1.50E-02 9.77E-03 95.70%
en 12 G
C /0
0.23 2 1.13E-01 1.01E-02 8.83E-02 1.50E-02 3.67E-02 96.10%

tia 1 IES
M2-FOX 0.28 0.28 2.15E-01 9.28E-02 1.31E-02 3.85E-03 4.63E-03 92.20%

H 1
0.28 2 8.06E-02 2.02E-02 3.19E-02 3.85E-03 1.40E-02 89.80%

12
lI
M2-OD 0.28 0.28 2.18E-01 9.35E-02 1.43E-02 4.47E-03 4.93E-03 92.50%

nf
0.28 2 8.25E-02 1.96E-02 3.58E-02 4.47E-03 1.57E-02 90.80%

M2-PO1(FOX) 0.28 0.28 2.16E-01 9.24E-02 1.51E-02 4.92E-03 5.09E-03 92.60%
or
0.28 2 8.30E-02 1.88E-02 3.82E-02 4.92E-03 1.67E-02 91.30%

m
M2-PO1(OD) 0.28 0.28 2.18E-01 9.33E-02 1.52E-02 4.94E-03 5.12E-03 92.70%

0.28 2 8.37E-02 1.90E-02 3.85E-02 4.94E-03 1.68E-02 91.30%
at
M2-M1 0.28 0.28 2.19E-01 9.00E-02 2.70E-02 1.11E-02 7.96E-03 94.70%

io
0.28 2 9.91E-02 1.33E-02 6.71E-02 1.11E-02 2.80E-02 94.60%

IN
M3-FOX 0.28 0.28 2.15E-01 9.32E-02 1.02E-02 2.45E-03 3.88E-03 91.40%

n
0.28 2 7.77E-02 2.23E-02 2.27E-02 2.45E-03 1.01E-02 86.70%

C
M3-OD 0.28 0.28 2.17E-01 9.40E-02 1.07E-02 2.69E-03 4.00E-03 91.60%

.
0.28 2 7.87E-02 2.22E-02 2.44E-02 2.69E-03 1.08E-02 87.40%

M3-PO1(FOX) 0.28 0.28 2.15E-01 9.31E-02 1.10E-02 2.85E-03 4.08E-03 91.60%
0.28 2 7.84E-02 2.17E-02 2.53E-02 2.85E-03 1.12E-02 87.70%
Document No.
Version
: T-018-LO-DR-001
: 2.8

M3-PO1(OD) 0.28 0.28 2.17E-01 9.40E-02 1.10E-02 2.85E-03 4.09E-03 91.70%
0.28 2 7.90E-02 2.19E-02 2.54E-02 2.85E-03 1.13E-02 87.80%
M3-M1 0.28 0.28 2.15E-01 9.27E-02 1.37E-02 4.20E-03 4.74E-03 92.30%
0.28 2 8.12E-02 1.97E-02 3.37E-02 4.20E-03 1.47E-02 90.10%
M3-M2 0.28 0.28 2.19E-01 9.00E-02 2.69E-02 1.11E-02 7.92E-03 94.70%
0.28 2 9.90E-02 1.34E-02 6.68E-02 1.11E-02 2.78E-02 94.50%
M4-FOX 0.28 0.28 2.15E-01 9.34E-02 8.64E-03 1.80E-03 3.42E-03 90.90%
0.28 2 7.66E-02 2.33E-02 1.79E-02 1.80E-03 8.04E-03 84.30%
TS
M4-OD 0.28 0.28 2.17E-01 9.43E-02 8.94E-03 1.93E-03 3.51E-03 91.10%

0.28 2 7.73E-02 2.34E-02 1.88E-02 1.93E-03 8.42E-03 84.80%
M
M4-PO1(FOX) 0.28 0.28 2.15E-01 9.33E-02 9.08E-03 2.00E-03 3.54E-03 91.10%

C
0.28 2 7.69E-02 2.30E-02 1.93E-02 2.00E-03 8.63E-03 85.00%

C
M4-PO1(OD) 0.28 0.28 2.17E-01 9.43E-02 9.11E-03 2.01E-03 3.55E-03 91.10%

VI
0.28 2 7.74E-02 2.33E-02 1.93E-02 2.01E-03 8.65E-03 85.10%

on 6 NO /2
M4-M1 0.28 0.28 2.15E-01 9.31E-02 1.03E-02 2.59E-03 3.87E-03 91.40%

A
fid 65 LO 009
0.28 2 7.78E-02 2.22E-02 2.32E-02 2.59E-03 1.03E-02 86.80%

TE
M4-M2 0.28 0.28 2.15E-01 9.26E-02 1.35E-02 4.20E-03 4.65E-03 92.30%

en 12 G
0.28 2 8.11E-02 1.98E-02 3.33E-02 4.20E-03 1.45E-02 89.90%

C /0
M4-M3 0.28 0.28 2.19E-01 9.00E-02 2.67E-02 1.11E-02 7.81E-03 94.60%

tia 1 IES
H 1
0.28 2 9.89E-02 1.35E-02 6.64E-02 1.11E-02 2.76E-02 94.40%

M5-FOX 0.28 0.28 2.15E-01 9.35E-02 7.59E-03 1.42E-03 3.08E-03 90.60%
12
lI
0.28 2 7.63E-02 2.41E-02 1.47E-02 1.42E-03 6.63E-03 82.50%

nf
M5-OD 0.28 0.28 2.17E-01 9.44E-02 7.77E-03 1.50E-03 3.13E-03 90.70%

0.28 2 7.69E-02 2.42E-02 1.52E-02 1.50E-03 6.87E-03 82.80%
or
M5-PO1(FOX) 0.28 0.28 2.15E-01 9.35E-02 7.88E-03 1.55E-03 3.17E-03 90.70%

m
0.28 2 7.64E-02 2.39E-02 1.55E-02 1.55E-03 7.00E-03 83.00%

M5-PO1(OD) 0.28 0.28 2.17E-01 9.44E-02 7.88E-03 1.55E-03 3.17E-03 90.70%
at
0.28 2 7.70E-02 2.42E-02 1.56E-02 1.55E-03 7.01E-03 83.00%

io
M5-M1 0.28 0.28 2.15E-01 9.33E-02 8.60E-03 1.87E-03 3.36E-03 90.90%

IN
0.28 2 7.69E-02 2.35E-02 1.78E-02 1.87E-03 7.95E-03 84.20%

M5-M2 0.28 0.28 2.15E-01 9.31E-02 1.01E-02 2.59E-03 3.77E-03 91.30%
C
0.28 2 7.80E-02 2.24E-02 2.25E-02 2.59E-03 9.95E-03 86.30%

.
M5-M3 0.28 0.28 2.15E-01 9.26E-02 1.33E-02 4.20E-03 4.56E-03 92.20%

0.28 2 8.13E-02 2.01E-02 3.26E-02 4.20E-03 1.42E-02 89.50%
Document No.
Version
: T-018-LO-DR-001
: 2.8

M5-M4 0.28 0.28 2.18E-01 9.00E-02 2.66E-02 1.11E-02 7.74E-03 94.50%
0.28 2 9.91E-02 1.37E-02 6.57E-02 1.11E-02 2.73E-02 94.00%
M6-FOX 0.44 0.46 2.58E-01 1.15E-01 6.46E-03 1.82E-03 2.32E-03 92.00%
0.44 2 1.04E-01 4.04E-02 1.21E-02 1.82E-03 5.12E-03 89.00%
M6-OD 0.44 0.46 2.58E-01 1.15E-01 6.62E-03 1.89E-03 2.36E-03 92.10%
0.44 2 1.04E-01 4.03E-02 1.24E-02 1.89E-03 5.27E-03 89.20%
M6-PO1(FOX) 0.44 0.46 2.58E-01 1.15E-01 6.71E-03 1.94E-03 2.39E-03 92.10%
0.44 2 1.04E-01 4.03E-02 1.27E-02 1.94E-03 5.36E-03 89.30%
M6-PO1(OD) 0.44 0.46 2.58E-01 1.15E-01 6.72E-03 1.94E-03 2.39E-03 92.10%
TS
0.44 2 1.04E-01 4.03E-02 1.27E-02 1.94E-03 5.36E-03 89.30%

M6-M1 0.44 0.46 2.58E-01 1.15E-01 7.33E-03 2.26E-03 2.54E-03 92.30%
0.44 2 1.05E-01 4.00E-02 1.41E-02 2.26E-03 5.92E-03 89.90%
M
M6-M2 0.44 0.46 2.58E-01 1.15E-01 8.50E-03 2.87E-03 2.82E-03 92.60%

C
0.44 2 1.05E-01 3.94E-02 1.70E-02 2.87E-03 7.04E-03 91.00%

M6-M3 0.44 0.46 2.58E-01 1.15E-01 1.05E-02 3.93E-03 3.27E-03 93.10%
C
0.44 2 1.07E-01 3.83E-02 2.19E-02 3.93E-03 8.97E-03 92.40%

VI
on 6 NO /2
M6-M4 0.44 0.46 2.59E-01 1.14E-01 1.48E-02 6.23E-03 4.28E-03 93.90%

A
0.44 2 1.10E-01 3.58E-02 3.23E-02 6.23E-03 1.30E-02 94.20%

fid 65 LO 009
M6-M5 0.44 0.46 2.64E-01 1.10E-01 3.18E-02 1.50E-02 8.37E-03 95.60%

TE
0.44 2 1.29E-01 2.89E-02 6.63E-02 1.50E-02 2.56E-02 96.10%

en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
*** Structure B ***

width space width space Ctotal Cc Cbottom Cb_area Cfb Ctop Ct_area Cft Csum/Ctotal
(um) (um) (um) (um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um)
M1-PO1-FOX 0.18 0.25 0.16 0.27 1.48E-01 4.23E-02 3.46E-02 1.38E-02 1.04E-02 2.62E-02 1.03E-02 7.95E-03 98.10%
0.18 1.98 0.16 2 1.16E-01 4.39E-04 6.48E-02 1.38E-02 2.55E-02 5.04E-02 1.03E-02 2.00E-02 100.00%
M2-PO1-FOX 0.18 0.25 0.16 0.27 1.44E-01 4.58E-02 3.64E-02 1.38E-02 1.13E-02 7.89E-03 2.81E-03 2.54E-03 94.70%
0.18 1.98 0.16 2 1.02E-01 2.52E-03 7.81E-02 1.38E-02 3.21E-02 1.82E-02 2.81E-03 7.70E-03 99.80%
M3-PO1-FOX 0.18 0.25 0.16 0.27 1.43E-01 4.61E-02 3.77E-02 1.38E-02 1.19E-02 4.81E-03 1.63E-03 1.59E-03 94.00%
0.18 1.98 0.16 2 1.00E-01 3.45E-03 8.12E-02 1.38E-02 3.37E-02 1.12E-02 1.63E-03 4.76E-03 99.20%
M4-PO1-FOX 0.18 0.25 0.16 0.27 1.43E-01 4.62E-02 3.84E-02 1.38E-02 1.23E-02 3.48E-03 1.15E-03 1.17E-03 93.80%
0.18 1.98 0.16 2 9.96E-02 3.85E-03 8.27E-02 1.38E-02 3.44E-02 8.04E-03 1.15E-03 3.45E-03 98.80%
M5-PO1-FOX 0.18 0.25 0.16 0.27 1.43E-01 4.63E-02 3.90E-02 1.38E-02 1.26E-02 2.74E-03 8.83E-04 9.27E-04 93.70%
TS
0.18 1.98 0.16 2 9.94E-02 4.03E-03 8.35E-02 1.38E-02 3.49E-02 6.29E-03 8.83E-04 2.71E-03 98.50%
M6-PO1-FOX 0.18 0.25 0.16 0.27 1.43E-01 4.63E-02 3.93E-02 1.38E-02 1.28E-02 2.22E-03 7.06E-04 7.56E-04 93.60%
M
0.18 1.98 0.16 2 9.93E-02 4.14E-03 8.42E-02 1.38E-02 3.52E-02 5.08E-03 7.06E-04 2.19E-03 98.20%
C
*** Structure B *** (continued)

Structure width space Ctotal Cc Cbottom Cb_area Cfb Ctop Ct_area Cft Csum/Ctotal
C
(um) (um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um) (fF/um)
VI
on 6 NO /2
M2-M1-FOX 0.23 0.23 2.45E-01 1.02E-01 1.49E-02 7.35E-03 3.78E-03 1.83E-02 9.12E-03 4.61E-03 96.80%
A
0.23 2 1.10E-01 5.93E-03 4.45E-02 7.35E-03 1.86E-02 5.34E-02 9.12E-03 2.22E-02 99.90%
fid 65 LO 009
M2-M1-OD 0.23 0.23 2.47E-01 1.01E-01 2.14E-02 1.09E-02 5.27E-03 1.82E-02 9.12E-03 4.53E-03 97.50%
TE
0.23 2 1.19E-01 4.25E-03 5.89E-02 1.09E-02 2.40E-02 5.12E-02 9.12E-03 2.10E-02 100.00%
M2-M1-PO1(FOX)
en 12 G
0.23 0.23 2.50E-01 9.91E-02 2.87E-02 1.48E-02 6.93E-03 1.81E-02 9.12E-03 4.49E-03 98.10%
0.23 2 1.28E-01 3.23E-03 7.22E-02 1.48E-02 2.87E-02 4.92E-02 9.12E-03 2.00E-02 100.00%
C /0
M2-M1-PO1(OD) 0.23 0.23 2.50E-01 9.90E-02 2.90E-02 1.50E-02 7.01E-03 1.81E-02 9.12E-03 4.49E-03 98.10%
tia 1 IES
H 1
0.23 2 1.28E-01 3.19E-03 7.28E-02 1.50E-02 2.89E-02 4.91E-02 9.12E-03 2.00E-02 100.00%
M3-M1-FOX 0.23 0.23 2.43E-01 1.04E-01 1.58E-02 7.35E-03 4.24E-03 7.77E-03 3.45E-03 2.16E-03 95.10%
12
lI
0.23 2 9.56E-02 1.07E-02 4.85E-02 7.35E-03 2.06E-02 2.47E-02 3.45E-03 1.06E-02 99.00%
M3-M1-OD
nf
0.23 0.23 2.45E-01 1.03E-01 2.24E-02 1.09E-02 5.77E-03 7.58E-03 3.45E-03 2.07E-03 96.00%
0.23 2 1.05E-01 8.47E-03 6.39E-02 1.09E-02 2.65E-02 2.36E-02 3.45E-03 1.00E-02 99.30%
or
M3-M1-PO1(FOX) 0.23 0.23 2.48E-01 1.01E-01 2.98E-02 1.48E-02 7.49E-03 7.51E-03 3.45E-03 2.03E-03 96.60%
0.23 2 1.15E-01 7.02E-03 7.81E-02 1.48E-02 3.16E-02 2.26E-02 3.45E-03 9.55E-03 99.40%
m
M3-M1-PO1(OD) 0.23 0.23 2.48E-01 1.01E-01 3.01E-02 1.50E-02 7.57E-03 7.51E-03 3.45E-03 2.03E-03 96.60%
0.23 2 1.16E-01 6.97E-03 7.87E-02 1.50E-02 3.18E-02 2.25E-02 3.45E-03 9.53E-03 99.40%
at
M3-M2-FOX 0.28 0.28 2.19E-01 8.93E-02 8.28E-03 3.85E-03 2.22E-03 2.28E-02 1.11E-02 5.84E-03 95.80%
io
0.28 2 1.03E-01 9.91E-03 2.31E-02 3.85E-03 9.62E-03 5.93E-02 1.11E-02 2.41E-02 99.10%
M3-M2-OD 0.28 0.28 2.19E-01 8.92E-02 9.45E-03 4.47E-03 2.49E-03 2.26E-02 1.11E-02 5.73E-03 96.00%
IN
0.28 2 1.04E-01 9.26E-03 2.63E-02 4.47E-03 1.09E-02 5.88E-02 1.11E-02 2.38E-02 99.40%
M3-M2-PO1(FOX)
C
0.28 0.28 2.19E-01 8.90E-02 1.03E-02 4.92E-03 2.68E-03 2.24E-02 1.11E-02 5.66E-03 96.20%
0.28 2 1.05E-01 8.85E-03 2.85E-02 4.92E-03 1.18E-02 5.84E-02 1.11E-02 2.36E-02 99.50%
.
M3-M2-PO1(OD) 0.28 0.28 2.19E-01 8.90E-02 1.03E-02 4.94E-03 2.69E-03 2.24E-02 1.11E-02 5.66E-03 96.20%
0.28 2 1.05E-01 8.83E-03 2.86E-02 4.94E-03 1.18E-02 5.83E-02 1.11E-02 2.36E-02 99.50%
M3-M2-M1 0.28 0.28 2.22E-01 8.67E-02 2.18E-02 1.11E-02 5.33E-03 2.18E-02 1.11E-02 5.35E-03 97.80%
0.28 2 1.19E-01 4.96E-03 5.43E-02 1.11E-02 2.16E-02 5.44E-02 1.11E-02 2.17E-02 99.90%
M4-M1-FOX 0.23 0.23 2.43E-01 1.04E-01 1.66E-02 7.35E-03 4.62E-03 5.17E-03 2.13E-03 1.52E-03 94.70%
0.23 2 9.30E-02 1.24E-02 4.99E-02 7.35E-03 2.13E-02 1.62E-02 2.13E-03 7.01E-03 97.70%
Document No.
Version
: T-018-LO-DR-001
: 2.8

M4-M1-OD 0.23 0.23 2.45E-01 1.03E-01 2.33E-02 1.09E-02 6.20E-03 5.01E-03 2.13E-03 1.44E-03 95.60%
0.23 2 1.03E-01 1.00E-02 6.56E-02 1.09E-02 2.74E-02 1.54E-02 2.13E-03 6.61E-03 98.30%
0.23 2 1.13E-01 8.45E-03 8.00E-02 1.48E-02 3.26E-02 1.47E-02 2.13E-03 6.27E-03 98.60%
M4-M1-PO1(OD) 0.23 0.23 2.47E-01 1.01E-01 3.10E-02 1.50E-02 8.01E-03 4.92E-03 2.13E-03 1.40E-03 96.20%
0.23 2 1.14E-01 8.39E-03 8.06E-02 1.50E-02 3.28E-02 1.46E-02 2.13E-03 6.26E-03 98.60%
M4-M2-FOX 0.28 0.28 2.16E-01 9.19E-02 8.93E-03 3.85E-03 2.54E-03 9.72E-03 4.20E-03 2.76E-03 93.80%
0.28 2 8.63E-02 1.57E-02 2.53E-02 3.85E-03 1.07E-02 2.75E-02 4.20E-03 1.17E-02 97.60%
M4-M2-OD 0.28 0.28 2.16E-01 9.17E-02 1.01E-02 4.47E-03 2.82E-03 9.56E-03 4.20E-03 2.68E-03 94.00%
0.28 2 8.76E-02 1.49E-02 2.88E-02 4.47E-03 1.22E-02 2.72E-02 4.20E-03 1.15E-02 98.00%
TS
0.28 2 8.88E-02 1.44E-02 3.13E-02 4.92E-03 1.32E-02 2.71E-02 4.20E-03 1.15E-02 98.20%
M
M4-M2-PO1(OD) 0.28 0.28 2.16E-01 9.15E-02 1.10E-02 4.94E-03 3.02E-03 9.45E-03 4.20E-03 2.63E-03 94.10%
0.28 2 8.88E-02 1.44E-02 3.14E-02 4.94E-03 1.32E-02 2.71E-02 4.20E-03 1.15E-02 98.30%
C
M4-M2-M1 0.28 0.28 2.19E-01 8.92E-02 2.26E-02 1.11E-02 5.74E-03 8.97E-03 4.20E-03 2.38E-03 95.90%
0.28 2 1.04E-01 9.58E-03 5.88E-02 1.11E-02 2.39E-02 2.50E-02 4.20E-03 1.04E-02 99.30%
C
M4-M3-FOX 0.28 0.28 2.19E-01 8.96E-02 5.60E-03 2.45E-03 1.57E-03 2.36E-02 1.11E-02 6.23E-03 95.30%
VI
on 6 NO /2
0.28 2 1.01E-01 1.14E-02 1.54E-02 2.45E-03 6.50E-03 6.07E-02 1.11E-02 2.48E-02 98.00%
A
M4-M3-OD 0.28 0.28 2.19E-01 8.95E-02 6.07E-03 2.69E-03 1.69E-03 2.34E-02 1.11E-02 6.14E-03 95.40%
fid 65 LO 009
0.28 2 1.01E-01 1.11E-02 1.68E-02 2.69E-03 7.06E-03 6.04E-02 1.11E-02 2.47E-02 98.30%
TE
0.28 2 1.01E-01 1.10E-02 1.77E-02 2.85E-03 7.41E-03 6.03E-02 1.11E-02 2.46E-02 98.40%
en 12 G
M4-M3-PO1(OD) 0.28 0.28 2.19E-01 8.95E-02 6.38E-03 2.85E-03 1.76E-03 2.33E-02 1.11E-02 6.09E-03 95.40%
C /0
0.28 2 1.01E-01 1.10E-02 1.77E-02 2.85E-03 7.42E-03 6.02E-02 1.11E-02 2.46E-02 98.40%
tia 1 IES
H 1
M4-M3-M1 0.28 0.28 2.19E-01 8.92E-02 8.94E-03 4.20E-03 2.37E-03 2.26E-02 1.11E-02 5.77E-03 95.90%
0.28 2 1.04E-01 9.54E-03 2.49E-02 4.20E-03 1.04E-02 5.90E-02 1.11E-02 2.39E-02 99.30%
12
lI
M4-M3-M2 0.28 0.28 2.22E-01 8.67E-02 2.18E-02 1.11E-02 5.33E-03 2.18E-02 1.11E-02 5.35E-03 97.80%
nf
0.28 2 1.19E-01 4.96E-03 5.43E-02 1.11E-02 2.16E-02 5.44E-02 1.11E-02 2.17E-02 99.90%
M5-M1-FOX 0.23 0.23 2.43E-01 1.04E-01 1.71E-02 7.35E-03 4.89E-03 3.93E-03 1.54E-03 1.19E-03 94.50%
or
0.23 2 9.21E-02 1.31E-02 5.09E-02 7.35E-03 2.18E-02 1.21E-02 1.54E-03 5.26E-03 96.70%
M5-M1-OD 0.23 0.23 2.45E-01 1.03E-01 2.38E-02 1.09E-02 6.48E-03 3.78E-03 1.54E-03 1.12E-03 95.40%
m
0.23 2 1.02E-01 1.07E-02 6.67E-02 1.09E-02 2.79E-02 1.14E-02 1.54E-03 4.94E-03 97.50%
at
0.23 2 1.12E-01 9.07E-03 8.11E-02 1.48E-02 3.31E-02 1.09E-02 1.54E-03 4.68E-03 97.90%
M5-M1-PO1(OD)
io
0.23 0.23 2.47E-01 1.01E-01 3.16E-02 1.50E-02 8.32E-03 3.70E-03 1.54E-03 1.08E-03 96.10%
0.23 2 1.13E-01 9.01E-03 8.17E-02 1.50E-02 3.34E-02 1.09E-02 1.54E-03 4.67E-03 98.00%
IN
M5-M2-FOX 0.28 0.28 2.16E-01 9.23E-02 9.57E-03 3.85E-03 2.86E-03 6.58E-03 2.59E-03 1.99E-03 93.10%
0.28 2 8.31E-02 1.77E-02 2.62E-02 3.85E-03 1.12E-02 1.80E-02 2.59E-03 7.72E-03 95.80%
C
M5-M2-OD 0.28 0.28 2.16E-01 9.21E-02 1.08E-02 4.47E-03 3.15E-03 6.43E-03 2.59E-03 1.92E-03 93.40%
.
0.28 2 8.45E-02 1.69E-02 2.97E-02 4.47E-03 1.26E-02 1.78E-02 2.59E-03 7.62E-03 96.30%
0.28 2 8.55E-02 1.64E-02 3.22E-02 4.92E-03 1.36E-02 1.77E-02 2.59E-03 7.55E-03 96.60%
M5-M2-PO1(OD) 0.28 0.28 2.16E-01 9.20E-02 1.17E-02 4.94E-03 3.36E-03 6.34E-03 2.59E-03 1.87E-03 93.50%
0.28 2 8.55E-02 1.63E-02 3.23E-02 4.94E-03 1.37E-02 1.77E-02 2.59E-03 7.55E-03 96.60%
M5-M2-M1 0.28 0.28 2.19E-01 8.96E-02 2.34E-02 1.11E-02 6.15E-03 5.88E-03 2.59E-03 1.65E-03 95.30%
0.28 2 1.01E-01 1.13E-02 6.04E-02 1.11E-02 2.47E-02 1.63E-02 2.59E-03 6.83E-03 98.20%
Document No.
Version
: T-018-LO-DR-001
: 2.8

M5-M3-FOX 0.28 0.28 2.16E-01 9.22E-02 6.20E-03 2.45E-03 1.87E-03 1.03E-02 4.20E-03 3.07E-03 93.20%
0.28 2 8.37E-02 1.74E-02 1.71E-02 2.45E-03 7.30E-03 2.83E-02 4.20E-03 1.21E-02 95.90%
M5-M3-OD 0.28 0.28 2.16E-01 9.22E-02 6.68E-03 2.69E-03 2.00E-03 1.02E-02 4.20E-03 3.00E-03 93.30%
0.28 2 8.40E-02 1.71E-02 1.85E-02 2.69E-03 7.91E-03 2.82E-02 4.20E-03 1.20E-02 96.30%
0.28 2 8.43E-02 1.69E-02 1.95E-02 2.85E-03 8.31E-03 2.81E-02 4.20E-03 1.19E-02 96.50%
M5-M3-PO1(OD) 0.28 0.28 2.16E-01 9.21E-02 7.00E-03 2.85E-03 2.07E-03 1.01E-02 4.20E-03 2.96E-03 93.40%
0.28 2 8.43E-02 1.69E-02 1.95E-02 2.85E-03 8.32E-03 2.81E-02 4.20E-03 1.19E-02 96.50%
M5-M3-M1 0.28 0.28 2.16E-01 9.18E-02 9.60E-03 4.20E-03 2.70E-03 9.61E-03 4.20E-03 2.70E-03 93.90%
0.28 2 8.70E-02 1.52E-02 2.73E-02 4.20E-03 1.16E-02 2.74E-02 4.20E-03 1.16E-02 97.90%
TS
M5-M3-M2 0.28 0.28 2.19E-01 8.92E-02 2.26E-02 1.11E-02 5.74E-03 8.97E-03 4.20E-03 2.38E-03 95.90%
0.28 2 1.04E-01 9.58E-03 5.88E-02 1.11E-02 2.39E-02 2.50E-02 4.20E-03 1.04E-02 99.30%
M
M5-M4-FOX 0.28 0.28 2.19E-01 8.97E-02 4.28E-03 1.80E-03 1.24E-03 2.42E-02 1.11E-02 6.53E-03 95.10%
0.28 2 1.00E-01 1.20E-02 1.16E-02 1.80E-03 4.92E-03 6.16E-02 1.11E-02 2.53E-02 97.20%
C
M5-M4-OD 0.28 0.28 2.19E-01 8.97E-02 4.54E-03 1.93E-03 1.31E-03 2.40E-02 1.11E-02 6.47E-03 95.20%
0.28 2 1.00E-01 1.19E-02 1.24E-02 1.93E-03 5.23E-03 6.14E-02 1.11E-02 2.51E-02 97.40%
C
M5-M4-PO1(FOX)
VI
0.28 0.28 2.19E-01 8.97E-02 4.70E-03 2.00E-03 1.35E-03 2.40E-02 1.11E-02 6.43E-03 95.20%
on 6 NO /2
0.28 2 1.00E-01 1.19E-02 1.28E-02 2.00E-03 5.42E-03 6.13E-02 1.11E-02 2.51E-02 97.50%
A
M5-M4-PO1(OD) 0.28 0.28 2.19E-01 8.97E-02 4.70E-03 2.01E-03 1.35E-03 2.40E-02 1.11E-02 6.43E-03 95.20%
fid 65 LO 009
0.28 2 1.00E-01 1.19E-02 1.29E-02 2.01E-03 5.43E-03 6.13E-02 1.11E-02 2.51E-02 97.50%
TE
M5-M4-M1 0.28 0.28 2.19E-01 8.96E-02 5.87E-03 2.59E-03 1.64E-03 2.35E-02 1.11E-02 6.18E-03 95.40%
en 12 G
0.28 2 1.01E-01 1.12E-02 1.62E-02 2.59E-03 6.82E-03 6.05E-02 1.11E-02 2.47E-02 98.20%
M5-M4-M2 0.28 0.28 2.19E-01 8.92E-02 8.94E-03 4.20E-03 2.37E-03 2.26E-02 1.11E-02 5.77E-03 95.90%
C /0
0.28 2 1.04E-01 9.54E-03 2.49E-02 4.20E-03 1.04E-02 5.90E-02 1.11E-02 2.39E-02 99.30%
tia 1 IES
H 1
M5-M4-M3 0.28 0.28 2.22E-01 8.67E-02 2.18E-02 1.11E-02 5.33E-03 2.18E-02 1.11E-02 5.35E-03 97.80%
12
0.28 2 1.19E-01 4.96E-03 5.43E-02 1.11E-02 2.16E-02 5.44E-02 1.11E-02 2.17E-02 99.90%
lI
M6-M1-FOX 0.23 0.23 2.43E-01 1.04E-01 1.76E-02 7.35E-03 5.12E-03 3.13E-03 1.18E-03 9.73E-04 94.40%
nf
0.23 2 9.17E-02 1.35E-02 5.16E-02 7.35E-03 2.21E-02 9.47E-03 1.18E-03 4.14E-03 96.00%
M6-M1-OD 0.23 0.23 2.45E-01 1.03E-01 2.43E-02 1.09E-02 6.71E-03 2.99E-03 1.18E-03 9.05E-04 95.30%
or
0.23 2 1.02E-01 1.11E-02 6.75E-02 1.09E-02 2.83E-02 8.94E-03 1.18E-03 3.88E-03 96.90%
m
0.23 2 1.12E-01 9.39E-03 8.19E-02 1.48E-02 3.36E-02 8.52E-03 1.18E-03 3.67E-03 97.40%
M6-M1-PO1(OD) 0.23 0.23 2.47E-01 1.01E-01 3.21E-02 1.50E-02 8.57E-03 2.92E-03 1.18E-03 8.68E-04 96.00%
at
0.23 2 1.13E-01 9.33E-03 8.26E-02 1.50E-02 3.38E-02 8.50E-03 1.18E-03 3.66E-03 97.50%
io
M6-M2-FOX 0.28 0.28 2.15E-01 9.24E-02 1.01E-02 3.85E-03 3.13E-03 4.97E-03 1.82E-03 1.57E-03 92.80%
0.28 2 8.20E-02 1.86E-02 2.68E-02 3.85E-03 1.15E-02 1.32E-02 1.82E-03 5.69E-03 94.20%
IN
M6-M2-OD 0.28 0.28 2.16E-01 9.22E-02 1.13E-02 4.47E-03 3.43E-03 4.84E-03 1.82E-03 1.51E-03 93.10%
C
0.28 2 8.34E-02 1.78E-02 3.05E-02 4.47E-03 1.30E-02 1.30E-02 1.82E-03 5.61E-03 94.90%
.
0.28 2 8.44E-02 1.73E-02 3.29E-02 4.92E-03 1.40E-02 1.29E-02 1.82E-03 5.54E-03 95.20%
M6-M2-PO1(OD) 0.28 0.28 2.16E-01 9.21E-02 1.22E-02 4.94E-03 3.65E-03 4.76E-03 1.82E-03 1.47E-03 93.30%
0.28 2 8.44E-02 1.72E-02 3.30E-02 4.94E-03 1.40E-02 1.29E-02 1.82E-03 5.54E-03 95.20%
M6-M2-M1 0.28 0.28 2.19E-01 8.97E-02 2.41E-02 1.11E-02 6.49E-03 4.34E-03 1.82E-03 1.26E-03 95.10%
0.28 2 1.00E-01 1.21E-02 6.14E-02 1.11E-02 2.52E-02 1.18E-02 1.82E-03 4.99E-03 97.20%
Document No.
Version
: T-018-LO-DR-001
: 2.8

M6-M3-FOX 0.28 0.28 2.15E-01 9.26E-02 6.81E-03 2.45E-03 2.18E-03 6.94E-03 2.50E-03 2.22E-03 92.50%
0.28 2 8.04E-02 1.97E-02 1.77E-02 2.45E-03 7.64E-03 1.81E-02 2.50E-03 7.78E-03 93.60%
M6-M3-OD 0.28 0.28 2.15E-01 9.26E-02 7.31E-03 2.69E-03 2.31E-03 6.81E-03 2.50E-03 2.16E-03 92.60%
0.28 2 8.07E-02 1.94E-02 1.92E-02 2.69E-03 8.27E-03 1.79E-02 2.50E-03 7.71E-03 94.00%
0.28 2 8.10E-02 1.92E-02 2.02E-02 2.85E-03 8.69E-03 1.79E-02 2.50E-03 7.69E-03 94.40%
M6-M3-PO1(OD) 0.28 0.28 2.15E-01 9.25E-02 7.64E-03 2.85E-03 2.39E-03 6.74E-03 2.50E-03 2.12E-03 92.60%
0.28 2 8.10E-02 1.91E-02 2.03E-02 2.85E-03 8.71E-03 1.79E-02 2.50E-03 7.68E-03 94.40%
M6-M3-M1 0.28 0.28 2.16E-01 9.22E-02 1.03E-02 4.20E-03 3.05E-03 6.30E-03 2.50E-03 1.90E-03 93.20%
0.28 2 8.37E-02 1.74E-02 2.83E-02 4.20E-03 1.20E-02 1.73E-02 2.50E-03 7.42E-03 96.00%
TS
M6-M3-M2 0.28 0.28 2.19E-01 8.96E-02 2.35E-02 1.11E-02 6.19E-03 5.70E-03 2.50E-03 1.60E-03 95.30%
0.28 2 1.01E-01 1.14E-02 6.05E-02 1.11E-02 2.47E-02 1.57E-02 2.50E-03 6.61E-03 98.10%
M
M6-M4-FOX 0.28 0.28 2.15E-01 9.24E-02 4.89E-03 1.80E-03 1.54E-03 1.04E-02 3.96E-03 3.20E-03 92.90%
0.28 2 8.22E-02 1.85E-02 1.30E-02 1.80E-03 5.60E-03 2.75E-02 3.96E-03 1.18E-02 94.30%
C
M6-M4-OD 0.28 0.28 2.15E-01 9.24E-02 5.16E-03 1.93E-03 1.62E-03 1.03E-02 3.96E-03 3.15E-03 92.90%
0.28 2 8.24E-02 1.83E-02 1.38E-02 1.93E-03 5.94E-03 2.74E-02 3.96E-03 1.17E-02 94.60%
C
VI
on 6 NO /2
0.28 2 8.25E-02 1.83E-02 1.43E-02 2.00E-03 6.15E-03 2.73E-02 3.96E-03 1.17E-02 94.80%
A
M6-M4-PO1(OD) 0.28 0.28 2.15E-01 9.24E-02 5.33E-03 2.01E-03 1.66E-03 1.02E-02 3.96E-03 3.11E-03 92.90%
fid 65 LO 009
0.28 2 8.25E-02 1.83E-02 1.43E-02 2.01E-03 6.16E-03 2.73E-02 3.96E-03 1.17E-02 94.80%
TE
M6-M4-M1 0.28 0.28 2.16E-01 9.23E-02 6.54E-03 2.59E-03 1.97E-03 9.80E-03 3.96E-03 2.92E-03 93.20%
0.28 2 8.34E-02 1.76E-02 1.80E-02 2.59E-03 7.70E-03 2.69E-02 3.96E-03 1.14E-02 95.90%
en 12 G
M6-M4-M2 0.28 0.28 2.16E-01 9.19E-02 9.67E-03 4.20E-03 2.73E-03 9.16E-03 3.96E-03 2.60E-03 93.80%
C /0
0.28 2 8.65E-02 1.55E-02 2.74E-02 4.20E-03 1.16E-02 2.60E-02 3.96E-03 1.10E-02 97.70%
tia 1 IES
H 1
M6-M4-M3 0.28 0.28 2.19E-01 8.93E-02 2.27E-02 1.11E-02 5.78E-03 8.52E-03 3.96E-03 2.28E-03 95.80%
0.28 2 1.03E-01 9.83E-03 5.90E-02 1.11E-02 2.40E-02 2.37E-02 3.96E-03 9.88E-03 99.10%
12
lI
M6-M5-FOX 0.28 0.28 2.18E-01 9.04E-02 3.52E-03 1.42E-03 1.05E-03 2.16E-02 9.57E-03 6.03E-03 94.70%
nf
0.28 2 9.58E-02 1.33E-02 9.58E-03 1.42E-03 4.08E-03 5.61E-02 9.57E-03 2.33E-02 96.40%
M6-M5-OD 0.28 0.28 2.18E-01 9.04E-02 3.69E-03 1.50E-03 1.10E-03 2.15E-02 9.57E-03 5.98E-03 94.70%
or
0.28 2 9.59E-02 1.33E-02 1.00E-02 1.50E-03 4.27E-03 5.59E-02 9.57E-03 2.32E-02 96.50%
m
0.28 2 9.60E-02 1.32E-02 1.03E-02 1.55E-03 4.39E-03 5.59E-02 9.57E-03 2.31E-02 96.50%
M6-M5-PO1(OD) 0.28 0.28 2.18E-01 9.04E-02 3.79E-03 1.55E-03 1.12E-03 2.15E-02 9.57E-03 5.95E-03 94.70%
at
0.28 2 9.60E-02 1.32E-02 1.03E-02 1.55E-03 4.39E-03 5.59E-02 9.57E-03 2.31E-02 96.60%
M6-M5-M1
io
0.28 0.28 2.18E-01 9.04E-02 4.48E-03 1.87E-03 1.30E-03 2.11E-02 9.57E-03 5.78E-03 94.80%
0.28 2 9.63E-02 1.29E-02 1.23E-02 1.87E-03 5.22E-03 5.53E-02 9.57E-03 2.29E-02 97.00%
IN
M6-M5-M2 0.28 0.28 2.18E-01 9.02E-02 5.92E-03 2.59E-03 1.66E-03 2.05E-02 9.57E-03 5.48E-03 95.00%
0.28 2 9.72E-02 1.22E-02 1.65E-02 2.59E-03 6.97E-03 5.44E-02 9.57E-03 2.24E-02 98.00%
C
M6-M5-M3 0.28 0.28 2.18E-01 8.99E-02 9.00E-03 4.20E-03 2.40E-03 1.97E-02 9.57E-03 5.09E-03 95.60%
.
0.28 2 9.99E-02 1.04E-02 2.54E-02 4.20E-03 1.06E-02 5.30E-02 9.57E-03 2.17E-02 99.20%
M6-M5-M4 0.28 0.28 2.21E-01 8.74E-02 2.18E-02 1.11E-02 5.34E-03 1.90E-02 9.57E-03 4.71E-03 97.50%
0.28 2 1.15E-01 5.62E-03 5.51E-02 1.11E-02 2.20E-02 4.88E-02 9.57E-03 1.96E-02 99.90%
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.14.2.2 20KÅ UTM

*** Structure A ***
M6-FOX 1.5 1.5 2.07e-01 9.14e-02 1.42e-02 6.29e-03 3.94e-03 95.2%
1.5 10 7.58e-02 1.62e-02 4.06e-02 6.29e-03 1.72e-02 96.1%
M6-OD 1.5 1.5 2.07e-01 9.13e-02 1.46e-02 6.57e-03 4.03e-03 95.3%
1.5 10 7.65e-02 1.58e-02 4.20e-02 6.57e-03 1.77e-02 96.3%
M6-PO1(FOX) 1.5 1.5 2.07e-01 9.13e-02 1.49e-02 6.74e-03 4.09e-03 95.4%
1.5 10 7.70e-02 1.57e-02 4.29e-02 6.74e-03 1.81e-02 96.4%
TS
M6-PO1(OD) 1.5 1.5 2.07e-01 9.12e-02 1.49e-02 6.74e-03 4.09e-03 95.4%

1.5 10 7.70e-02 1.57e-02 4.28e-02 6.74e-03 1.81e-02 96.3%
M
M6-M1 1.5 1.5 2.07e-01 9.08e-02 1.69e-02 7.86e-03 4.52e-03 95.7%

C
1.5 10 8.00e-02 1.46e-02 4.83e-02 7.86e-03 2.02e-02 96.7%

M6-M2 1.5 1.5 2.08e-01 8.99e-02 2.10e-02 1.00e-02 5.47e-03 96.4%
C
VI
1.5 10 8.59e-02 1.28e-02 5.80e-02 1.00e-02 2.40e-02 97.3%

on 6 NO /2
M6-M3 1.5 1.5 2.11e-01 8.83e-02 2.82e-02 1.39e-02 7.15e-03 97.0%

A
1.5 10 9.60e-02 1.06e-02 7.28e-02 1.39e-02 2.94e-02 97.8%

fid 65 LO 009
TE
M6-M4 1.5 1.5 2.18e-01 8.46e-02 4.41e-02 2.25e-02 1.08e-02 97.7%

en 12 G
1.5 10 1.17e-01 7.82e-03 9.95e-02 2.25e-02 3.85e-02 98.4%

C /0
M6-M5 1.5 1.5 2.62e-01 7.54e-02 1.07e-01 5.95e-02 2.36e-02 98.2%

tia 1 IES
H 1
1.5 10 1.87e-01 4.57e-03 1.76e-01 5.95e-02 5.83e-02 99.2%

12
lI

nf

or
M6-PO1-FOX 0.18 0.25 0.16 0.27 1.43E-01 4.63E- 3.93E-02 1.38E-02 1.28E-02 2.22E-03 7.06E-04 7.56E-04 93.60%
m
02
0.18 1.98 0.16 2 9.93E-02 4.14E- 8.42E-02 1.38E-02 3.52E-02 5.08E-03 7.06E-04 2.19E-03 98.20%
at
03
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

M6-M1-FOX 0.23 0.23 2.43e-01 1.04e-01 1.75e-02 7.35e-03 5.10e-03 3.18e-03 1.21e-03 9.88e-04 94.4%
0.23 2 9.18e-02 1.35e-02 5.15e-02 7.35e-03 2.21e-02 9.65e-03 1.21e-03 4.22e-03 96.1%
M6-M1-OD 0.23 0.23 2.45e-01 1.03e-01 2.41e-02 1.08e-02 6.66e-03 3.05e-03 1.21e-03 9.22e-04 95.3%
0.23 2 1.01e-01 1.11e-02 6.69e-02 1.08e-02 2.81e-02 9.13e-03 1.21e-03 3.96e-03 96.9%
M6-M1-PO1(FOX) 0.23 0.23 2.47e-01 1.01e-01 3.17e-02 1.48e-02 8.46e-03 2.97e-03 1.21e-03 8.84e-04 96.0%
0.23 2 1.12e-01 9.37e-03 8.19e-02 1.48e-02 3.35e-02 8.69e-03 1.21e-03 3.74e-03 97.5%
M6-M1-PO1(OD) 0.23 0.23 2.47e-01 1.01e-01 3.17e-02 1.48e-02 8.46e-03 2.97e-03 1.21e-03 8.85e-04 96.0%
0.23 2 1.12e-01 9.37e-03 8.18e-02 1.48e-02 3.35e-02 8.69e-03 1.21e-03 3.74e-03 97.5%
M6-M2-FOX 0.28 0.28 2.15e-01 9.24e-02 1.01e-02 3.85e-03 3.11e-03 5.08e-03 1.87e-03 1.60e-03 92.8%
0.28 2 8.20e-02 1.86e-02 2.68e-02 3.85e-03 1.15e-02 1.35e-02 1.87e-03 5.82e-03 94.3%
M6-M2-OD 0.28 0.28 2.15e-01 9.22e-02 1.13e-02 4.46e-03 3.40e-03 4.95e-03 1.87e-03 1.54e-03 93.1%
0.28 2 8.34e-02 1.78e-02 3.03e-02 4.46e-03 1.29e-02 1.33e-02 1.87e-03 5.73e-03 94.9%
TS
0.28 2 8.45e-02 1.72e-02 3.29e-02 4.92e-03 1.40e-02 1.32e-02 1.87e-03 5.67e-03 95.3%
M6-M2-PO1(OD) 0.28 0.28 2.16e-01 9.20e-02 1.21e-02 4.92e-03 3.61e-03 4.86e-03 1.87e-03 1.49e-03 93.2%
M
0.28 2 8.45e-02 1.72e-02 3.29e-02 4.92e-03 1.40e-02 1.32e-02 1.87e-03 5.67e-03 95.3%
M6-M2-M1 0.28 0.28 2.19e-01 8.97e-02 2.40e-02 1.11e-02 6.47e-03 4.44e-03 1.87e-03 1.28e-03 95.1%
C
0.28 2 1.00e-01 1.20e-02 6.14e-02 1.11e-02 2.51e-02 1.21e-02 1.87e-03 5.11e-03 97.3%
M6-M3-FOX 0.28 0.28 2.15e-01 9.26e-02 6.76e-03 2.45e-03 2.15e-03 7.13e-03 2.59e-03 2.27e-03 92.5%
C
0.28 2 8.05e-02 1.96e-02 1.77e-02 2.45e-03 7.62e-03 1.86e-02 2.59e-03 8.03e-03 93.7%
VI
M6-M3-OD 0.28 0.28 2.15e-01 9.25e-02 7.24e-03 2.69e-03 2.28e-03 7.01e-03 2.59e-03 2.21e-03 92.6%
on 6 NO /2
0.28 2 8.09e-02 1.92e-02 1.92e-02 2.69e-03 8.24e-03 1.85e-02 2.59e-03 7.97e-03 94.3%
A
fid 65 LO 009
0.28 2 8.11e-02 1.90e-02 2.02e-02 2.85e-03 8.66e-03 1.85e-02 2.59e-03 7.93e-03 94.5%
M6-M3-PO1(OD) 0.28 0.28 2.15e-01 9.24e-02 7.57e-03 2.85e-03 2.36e-03 6.93e-03 2.59e-03 2.17e-03 92.7%
TE
0.28 2 8.11e-02 1.90e-02 2.02e-02 2.85e-03 8.66e-03 1.85e-02 2.59e-03 7.93e-03 94.5%
en 12 G
M6-M3-M1 0.28 0.28 2.16e-01 9.22e-02 1.03e-02 4.20e-03 3.02e-03 6.49e-03 2.59e-03 1.95e-03 93.3%
C /0
0.28 2 8.39e-02 1.72e-02 2.82e-02 4.20e-03 1.20e-02 1.79e-02 2.59e-03 7.66e-03 96.1%
M6-M3-M2 0.28 0.28 2.19e-01 8.96e-02 2.34e-02 1.11e-02 6.15e-03 5.88e-03 2.59e-03 1.65e-03 95.3%
tia 1 IES
H 1
0.28 2 1.01e-01 1.13e-02 6.04e-02 1.11e-02 2.47e-02 1.63e-02 2.59e-03 6.83e-03 98.2%
M6-M4-FOX 0.28 0.28 2.16e-01 9.23e-02 4.83e-03 1.80e-03 1.52e-03 1.08e-02 4.20e-03 3.32e-03 93.0%
12
lI
0.28 2 8.28e-02 1.82e-02 1.30e-02 1.80e-03 5.58e-03 2.90e-02 4.20e-03 1.24e-02 94.6%
M6-M4-OD 0.28 0.28 2.15e-01 9.22e-02 5.10e-03 1.92e-03 1.59e-03 1.07e-02 4.20e-03 3.27e-03 93.0%
nf
0.28 2 8.29e-02 1.80e-02 1.37e-02 1.92e-03 5.89e-03 2.88e-02 4.20e-03 1.23e-02 94.8%
or
0.28 2 8.30e-02 1.79e-02 1.42e-02 2.00e-03 6.11e-03 2.87e-02 4.20e-03 1.23e-02 95.0%
M6-M4-PO1(OD) 0.28 0.28 2.15e-01 9.22e-02 5.27e-03 2.00e-03 1.63e-03 1.07e-02 4.20e-03 3.24e-03 93.0%
m
0.28 2 8.30e-02 1.80e-02 1.42e-02 2.00e-03 6.11e-03 2.87e-02 4.20e-03 1.23e-02 95.0%
M6-M4-M1 0.28 0.28 2.16e-01 9.22e-02 6.48e-03 2.59e-03 1.94e-03 1.03e-02 4.20e-03 3.03e-03 93.3%
at
0.28 2 8.39e-02 1.72e-02 1.79e-02 2.59e-03 7.66e-03 2.82e-02 4.20e-03 1.20e-02 96.1%
M6-M4-M2 0.28 0.28 2.16e-01 9.18e-02 9.60e-03 4.20e-03 2.70e-03 9.61e-03 4.20e-03 2.70e-03 93.9%
io
0.28 2 8.70e-02 1.52e-02 2.73e-02 4.20e-03 1.16e-02 2.74e-02 4.20e-03 1.16e-02 97.9%
M6-M4-M3 0.28 0.28 2.19e-01 8.92e-02 2.26e-02 1.11e-02 5.74e-03 8.97e-03 4.20e-03 2.38e-03 95.9%
IN
0.28 2 1.04e-01 9.58e-03 5.88e-02 1.11e-02 2.39e-02 2.50e-02 4.20e-03 1.04e-02 99.3%
M6-M5-FOX 0.28 0.28 2.18e-01 8.98e-02 3.48e-03 1.42e-03 1.03e-03 2.46e-02 1.11e-02 6.74e-03 95.0%
C
0.28 2 9.98e-02 1.24e-02 9.38e-03 1.42e-03 3.98e-03 6.23e-02 1.11e-02 2.56e-02 96.7%
M6-M5-OD 0.28 0.28 2.18e-01 8.97e-02 3.64e-03 1.50e-03 1.07e-03 2.45e-02 1.11e-02 6.71e-03 95.0%
.
0.28 2 9.99e-02 1.23e-02 9.83e-03 1.50e-03 4.16e-03 6.22e-02 1.11e-02 2.55e-02 96.7%
0.28 2 9.99e-02 1.23e-02 1.01e-02 1.55e-03 4.29e-03 6.20e-02 1.11e-02 2.55e-02 96.8%
M6-M5-PO1(OD) 0.28 0.28 2.18e-01 8.97e-02 3.74e-03 1.55e-03 1.10e-03 2.45e-02 1.11e-02 6.68e-03 95.0%
0.28 2 9.99e-02 1.23e-02 1.01e-02 1.55e-03 4.29e-03 6.21e-02 1.11e-02 2.55e-02 96.8%
M6-M5-M1 0.28 0.28 2.19e-01 8.97e-02 4.43e-03 1.87e-03 1.28e-03 2.41e-02 1.11e-02 6.49e-03 95.2%
0.28 2 1.00e-01 1.20e-02 1.21e-02 1.87e-03 5.10e-03 6.15e-02 1.11e-02 2.52e-02 97.3%
M6-M5-M2 0.28 0.28 2.19e-01 8.96e-02 5.87e-03 2.59e-03 1.64e-03 2.35e-02 1.11e-02 6.18e-03 95.4%
0.28 2 1.01e-01 1.12e-02 1.62e-02 2.59e-03 6.82e-03 6.05e-02 1.11e-02 2.47e-02 98.2%
M6-M5-M3 0.28 0.28 2.19e-01 8.92e-02 8.94e-03 4.20e-03 2.37e-03 2.26e-02 1.11e-02 5.77e-03 95.9%
0.28 2 1.04e-01 9.54e-03 2.49e-02 4.20e-03 1.04e-02 5.90e-02 1.11e-02 2.39e-02 99.3%
M6-M5-M4 0.28 0.28 2.22e-01 8.67e-02 2.18e-02 1.11e-02 5.33e-03 2.18e-02 1.11e-02 5.35e-03 97.8%
0.28 2 1.19e-01 4.96e-03 5.43e-02 1.11e-02 2.16e-02 5.44e-02 1.11e-02 2.17e-02 99.9%
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.14.2.3 40KÅ UTM

*** Structure A ***
M6-FOX 2.6 2.5 2.35E-01 1.00E-01 2.24E-02 1.07E-02 5.83E-03 9.49E-01
M6-M1 2.6 2.5 2.37E-01 9.92E-02 2.73E-02 1.33E-02 6.95E-03 9.54E-01
M6-M2 2.6 2.5 2.39E-01 9.76E-02 3.39E-02 1.69E-02 8.49E-03 9.58E-01
M6-M3 2.6 2.5 2.45E-01 9.51E-02 4.53E-02 2.32E-02 1.10E-02 9.62E-01
M6-M4 2.6 2.5 2.59E-01 9.07E-02 6.92E-02 3.68E-02 1.62E-02 9.66E-01
TS
M6-M5 2.6 2.5 3.24E-01 8.26E-02 1.50E-01 8.89E-02 3.06E-02 9.74E-01

M6-MCT 2.6 2.5 3.51E-01 8.09E-02 1.81E-01 1.11E-01 3.50E-02 9.76E-01
M
M6-OD 2.6 2.5 2.35E-01 1.00E-01 2.33E-02 1.12E-02 6.03E-03 9.50E-01

C
M6-PO1(FOX) 2.6 2.5 2.35E-01 1.00E-01 2.39E-02 1.15E-02 6.18E-03 9.51E-01

C
M6-PO1(OD) 2.6 2.5 2.35E-01 1.00E-01 2.38E-02 1.15E-02 6.15E-03 9.51E-01

VI
on 6 NO /2
*** Structure B ***

A
fid 65 LO 009

TE
en 12 G
C /0
M6-PO1-FOX 0.18 0.25 0.16 0.27 1.43E- 4.63E- 3.94E- 1.38E-02 1.28E-02 2.22E-03 7.06E-04 7.58E-04 93.70%
tia 1 IES
H 1
01 02 02
0.18 1.98 0.16 2 9.93E- 4.14E- 8.42E- 1.38E-02 3.52E-02 5.09E-03 7.06E-04 2.19E-03 98.30%
12
lI
02 03 02
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8

M6-M1-FOX 0.23 0.23 2.43E-01 1.04E-01 1.76E-02 7.34E-03 5.15E-03 3.14E-03 1.18E-03 9.80E-04 94.40%
0.23 2 9.17E-02 1.35E-02 5.16E-02 7.34E-03 2.21E-02 9.48E-03 1.18E-03 4.15E-03 96.10%
M6-M1-OD 0.23 0.23 2.45E-01 1.03E-01 2.44E-02 1.09E-02 6.76E-03 3.00E-03 1.18E-03 9.10E-04 95.30%
0.23 2 1.02E-01 1.10E-02 6.75E-02 1.09E-02 2.83E-02 8.95E-03 1.18E-03 3.89E-03 96.90%
0.23 2 1.12E-01 9.38E-03 8.20E-02 1.48E-02 3.36E-02 8.53E-03 1.18E-03 3.68E-03 97.50%
M6-M1-PO1(OD) 0.23 0.23 2.47E-01 1.01E-01 3.18E-02 1.48E-02 8.51E-03 2.93E-03 1.18E-03 8.74E-04 96.00%
0.23 2 1.12E-01 9.38E-03 8.20E-02 1.48E-02 3.36E-02 8.53E-03 1.18E-03 3.68E-03 97.50%
M6-M2-FOX 0.28 0.28 2.15E-01 9.24E-02 1.02E-02 3.85E-03 3.15E-03 5.00E-03 1.82E-03 1.59E-03 92.80%
0.28 2 8.20E-02 1.86E-02 2.69E-02 3.85E-03 1.15E-02 1.32E-02 1.82E-03 5.70E-03 94.30%
M6-M2-M1 0.28 0.28 2.19E-01 8.97E-02 2.42E-02 1.11E-02 6.52E-03 4.36E-03 1.82E-03 1.27E-03 95.10%
0.28 2 1.00E-01 1.21E-02 6.15E-02 1.11E-02 2.52E-02 1.18E-02 1.82E-03 5.00E-03 97.30%
M6-M2-OD 0.28 0.28 2.16E-01 9.22E-02 1.14E-02 4.47E-03 3.45E-03 4.86E-03 1.82E-03 1.52E-03 93.10%
TS
0.28 2 8.34E-02 1.78E-02 3.05E-02 4.47E-03 1.30E-02 1.30E-02 1.82E-03 5.61E-03 94.90%
0.28 2 8.44E-02 1.73E-02 3.31E-02 4.92E-03 1.41E-02 1.30E-02 1.82E-03 5.58E-03 95.40%
M
M6-M2-PO1(OD) 0.28 0.28 2.16E-01 9.21E-02 1.22E-02 4.92E-03 3.66E-03 4.78E-03 1.82E-03 1.48E-03 93.30%
0.28 2 8.44E-02 1.73E-02 3.31E-02 4.92E-03 1.41E-02 1.30E-02 1.82E-03 5.58E-03 95.40%
C
M6-M3-FOX 0.28 0.28 2.15E-01 9.26E-02 6.85E-03 2.45E-03 2.20E-03 6.97E-03 2.50E-03 2.24E-03 92.50%
0.28 2 8.03E-02 1.97E-02 1.78E-02 2.45E-03 7.66E-03 1.81E-02 2.50E-03 7.80E-03 93.60%
C
M6-M3-M1 0.28 0.28 2.16E-01 9.22E-02 1.04E-02 4.20E-03 3.08E-03 6.34E-03 2.50E-03 1.92E-03 93.30%
VI
0.28 2 8.37E-02 1.74E-02 2.83E-02 4.20E-03 1.21E-02 1.74E-02 2.50E-03 7.44E-03 96.10%
on 6 NO /2
M6-M3-M2 0.28 0.28 2.19E-01 8.96E-02 2.36E-02 1.11E-02 6.23E-03 5.73E-03 2.50E-03 1.62E-03 95.40%
0.28 2 1.01E-01 1.14E-02 6.06E-02 1.11E-02 2.47E-02 1.58E-02 2.50E-03 6.63E-03 98.10%
A
M6-M3-OD 0.28 0.28 2.15E-01 9.26E-02 7.35E-03 2.69E-03 2.33E-03 6.85E-03 2.50E-03 2.17E-03 92.60%
fid 65 LO 009
0.28 2 8.07E-02 1.94E-02 1.93E-02 2.69E-03 8.29E-03 1.80E-02 2.50E-03 7.73E-03 94.10%
TE
0.28 2 8.10E-02 1.91E-02 2.03E-02 2.85E-03 8.72E-03 1.79E-02 2.50E-03 7.71E-03 94.50%
en 12 G
M6-M3-PO1(OD) 0.28 0.28 2.15E-01 9.25E-02 7.67E-03 2.85E-03 2.41E-03 6.78E-03 2.50E-03 2.14E-03 92.70%
C /0
0.28 2 8.10E-02 1.91E-02 2.03E-02 2.85E-03 8.72E-03 1.79E-02 2.50E-03 7.71E-03 94.50%
tia 1 IES
M6-M4-FOX 0.28 0.28 2.15E-01 9.24E-02 4.91E-03 1.80E-03 1.55E-03 1.04E-02 3.96E-03 3.23E-03 92.90%
H 1
0.28 2 8.22E-02 1.85E-02 1.30E-02 1.80E-03 5.61E-03 2.76E-02 3.96E-03 1.18E-02 94.40%
M6-M4-M1 0.28 0.28 2.16E-01 9.22E-02 6.58E-03 2.59E-03 2.00E-03 9.86E-03 3.96E-03 2.95E-03 93.20%
12
lI
0.28 2 8.34E-02 1.76E-02 1.80E-02 2.59E-03 7.72E-03 2.69E-02 3.96E-03 1.15E-02 96.00%
M6-M4-M2 0.28 0.28 2.16E-01 9.19E-02 9.76E-03 4.20E-03 2.78E-03 9.24E-03 3.96E-03 2.64E-03 93.90%
nf
0.28 2 8.65E-02 1.55E-02 2.75E-02 4.20E-03 1.16E-02 2.60E-02 3.96E-03 1.10E-02 97.70%
M6-M4-M3 0.28 0.28 2.19E-01 8.93E-02 2.28E-02 1.11E-02 5.85E-03 8.59E-03 3.96E-03 2.31E-03 95.90%
or
0.28 2 1.03E-01 9.83E-03 5.91E-02 1.11E-02 2.40E-02 2.37E-02 3.96E-03 9.89E-03 99.20%
M6-M4-OD 0.28 0.28 2.15E-01 9.24E-02 5.18E-03 1.93E-03 1.63E-03 1.03E-02 3.96E-03 3.17E-03 92.90%
0.28 2 8.24E-02 1.83E-02 1.38E-02 1.93E-03 5.95E-03 2.75E-02 3.96E-03 1.18E-02 94.70%
m
0.28 2 8.25E-02 1.83E-02 1.43E-02 2.00E-03 6.16E-03 2.74E-02 3.96E-03 1.17E-02 94.90%
at
M6-M4-PO1(OD) 0.28 0.28 2.15E-01 9.23E-02 5.35E-03 2.00E-03 1.67E-03 1.02E-02 3.96E-03 3.14E-03 93.00%
0.28 2 8.25E-02 1.83E-02 1.43E-02 2.00E-03 6.16E-03 2.74E-02 3.96E-03 1.17E-02 94.90%
io
M6-M5-FOX 0.28 0.28 2.18E-01 9.04E-02 3.54E-03 1.42E-03 1.06E-03 2.17E-02 9.57E-03 6.06E-03 94.70%
IN
0.28 2 9.59E-02 1.33E-02 9.57E-03 1.42E-03 4.08E-03 5.61E-02 9.57E-03 2.33E-02 96.40%
n
M6-M5-M1 0.28 0.28 2.18E-01 9.04E-02 4.50E-03 1.87E-03 1.31E-03 2.12E-02 9.57E-03 5.81E-03 94.80%
0.28 2 9.63E-02 1.29E-02 1.23E-02 1.87E-03 5.23E-03 5.54E-02 9.57E-03 2.29E-02 97.10%
C
M6-M5-M2 0.28 0.28 2.18E-01 9.02E-02 5.96E-03 2.59E-03 1.68E-03 2.06E-02 9.57E-03 5.54E-03 95.10%
.
0.28 2 9.72E-02 1.21E-02 1.66E-02 2.59E-03 6.99E-03 5.45E-02 9.57E-03 2.25E-02 98.10%
M6-M5-M3 0.28 0.28 2.18E-01 8.99E-02 9.07E-03 4.20E-03 2.43E-03 1.99E-02 9.57E-03 5.15E-03 95.70%
0.28 2 9.99E-02 1.04E-02 2.54E-02 4.20E-03 1.06E-02 5.30E-02 9.57E-03 2.17E-02 99.20%
M6-M5-M4 0.28 0.28 2.21E-01 8.74E-02 2.19E-02 1.11E-02 5.40E-03 1.91E-02 9.57E-03 4.77E-03 97.60%
0.28 2 1.15E-01 5.62E-03 5.51E-02 1.11E-02 2.20E-02 4.88E-02 9.57E-03 1.96E-02 99.90%
M6-M5-OD 0.28 0.28 2.18E-01 9.04E-02 3.70E-03 1.50E-03 1.10E-03 2.16E-02 9.57E-03 6.01E-03 94.70%
0.28 2 9.59E-02 1.32E-02 1.01E-02 1.50E-03 4.28E-03 5.60E-02 9.57E-03 2.32E-02 96.50%
0.28 2 9.60E-02 1.32E-02 1.03E-02 1.55E-03 4.40E-03 5.59E-02 9.57E-03 2.32E-02 96.60%
M6-M5-PO1(OD) 0.28 0.28 2.18E-01 9.04E-02 3.80E-03 1.55E-03 1.13E-03 2.15E-02 9.57E-03 5.98E-03 94.70%
0.28 2 9.60E-02 1.32E-02 1.03E-02 1.55E-03 4.40E-03 5.59E-02 9.57E-03 2.32E-02 96.60%
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.14.3 Comparison of metal routing delay between

measurement and simulation
The verification of those models is through HSPICE simulation for ring oscillator with metal delay. The ring
oscillator contains 17 stages inverter chain with 7 kinds of metal routing load: (a) a reference ring oscillator
with short metal length as routing, (b) 1.3mm metal length of structure A with 3 different spacings, and (c)
1.3mm metal length of structure B with 3 different spacings. Structure A and B are shown in the schematic.
The units for metal delay extracted from measurement are given as delay in ps. Here, the verification data is
from 0.18um 1P6M 1.8V/3.3V LOGIC technology.
TS
Structure A - Signal line with neighboring power lines:

width
GND space signal space GND
M
C
GND
C
Structure B - Signal line with neighboring signal lines:

VI
on 6 NO /2
width
signal space signal space signal
A
fid 65 LO 009
TE
GND
en 12 G
The ring oscillators were measured and simulated with lumped RC at 25°C. The R & C values used in the
C /0
following tables are calibrated with SEM pictures (the C values are Raphael simulation result by using the
tia 1 IES
H 1
dielectric thickness from SEM). The geometry of metal line/space and speed results are listed below :
12
lI
M1 used as metal routing:

nf
Width Space R C measurement simulation

Structure (um) (um) (ohm/sq.) (fF/um) Delay (ps) Delay (ps)
or
A 0.23 0.23 0.078 2.236e-1 159.1 165.9

A 0.23 0.46 0.078 1.470e-1 110.6 116.8
m
A 0.23 0.69 0.078 1.211e-1 91.2 94.9

at
B 0.23 0.69 0.078 3.790e-2 42.9 43.1

B 0.23 1.15 0.078 4.924e-2 49.4 50.2
io
B 0.23 1.61 0.078 5.781e-2 52.9 55.7

IN
M2 used as metal routing:

C
Width Space R C measurement simulation

.
Structure (um) (um) (ohm/sq.) (fF/um) Delay (ps) Delay (ps)

A 0.28 0.28 0.076 1.905e-1 124.1 128.6
A 0.28 0.56 0.076 1.267e-1 86.8 90.1
A 0.28 0.84 0.076 1.042e-1 73.5 76.3
B 0.28 0.84 0.076 2.098e-2 28.2 26.2
B 0.28 1.40 0.076 2.757e-2 30.9 29.5
B 0.28 1.96 0.076 3.352e-2 33.5 33.8
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15 MIM Capacitor Model

9.15.1 CM018G
The MIM capacitors (metal –insulator-metal) use metal Mx-1 as bottom plate and an additional
thin metal layer between metal Mx-1 and Mx as top plate (capacitor top metal: CTM). The dielectric
is made of 38 nm PECVD oxide for typical thickness to evaluate the capacitor characteristics.
The cross-section of the MiM test structures are shown in Fig. 9.15.1.1. The capacitors unit cells
of different sizes were measured and fitted.
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
Fig. 9.15.1.1 MiM capacitor (metal –insulator-metal) cross-section

or
MiM capacitor are modeled by the following following equation:

C_total = [Ca *area + Cf * PJ]* [1 + TC1*dT + TC2*(dT) 2] * [1 + VC1*V12+ VC2*( V12) 2]
m
where Ca: area capacitance (F/m^2)

at
Cf: fringe capacitance (F/m^2)

PJ is the periphery of MiM capacitor in m
io
area is the area of MiM capacitor in m*m

IN
dT = T – Tnominal (25 °C) Valid range : -40 °C ~ 125 °C

V12 :different DC bias condition Valid range : -5V ~ 5 V
C
.
.C_total=(1.025E-3*area+2.425E-10*PJ)* (1-5.225E-5 *dT +1.0E-8*(dT) 2)*

(1+6.16E-5*V12-2.05E-5*(V12) 2)
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2 CR018G
9.15.2.1 Model Usage Guidelines
Metal-insulator-metal (MIM) capacitors with and without metal shield were modeled based on the two-port S-
parameter measurement and Y-parameter fitting. 1.0fF MIM capacitor model with shield covers metal layer from four
to six, while 1.0fF MIM capacitor model without shield is for metal scheme 1P6M only. 2.0fF MIM capacitor model
with shield and without shield is for metal scheme 1P4M only.
Square and rectangular capacitors of different sizes: 30x30, 25x25, 15x15, 10x10, 5x5, 5x10, 5x20, 5x30, 10x30
and 10x20 were measured and fitted. MIM capacitor scalable models were generated with minimum length and
width at 4 um and the maximum length and width at 30 um where length is always higher than or equal to width.
9.15.2.2 Test Structure & Measurement Procedures

TS
Layouts of the MIM structures are shown in Figure 9.15.2.1. It is designed as a two-port network with the substrate
connected to ground for MIM without shield and metal shield connected to ground for MIM with shield. Two-port S
M
parameter was measured with frequency sweep from 50 MHz to 20.05 GHz for 1.0fF MIM capacitor, and from 200
MHz to 20.05 GHz for 2.0fF MIM capacitor. An open test structure measurement is used as RF de-embedding for
C
each MIM.
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
(a) MIM without Shield (b) MIM with Shield

at
Figure 9.15.2.1: Layout of (a) MIM without shield and (b) MIM with shield structures
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.3 MIM Equivalent Circuit Model

The equivalent circuit models for the MIM capacitor with and without shield are shown in Figure 9.15.2.2 and Figure
9.15.2.3. In these two equivalent circuits, the inter-metal dielectric Cmim is the main element of the capacitor. Rtop
and Ltop are the parasitics existing in the electrode connected to port 1 and Rbot and Lbot are the parasitics
existing in the electrode connected to port 2. Cox of MIM without shield represents the capacitance between port 2
bottom plate metal to substrate. Csub and Rsub are the parasitics that represents the substrate capacitance and
resistance. Cox of MIM with shield represents the capacitance between port2 bottom metal plate to metal shield.
Rtop Cmim Rbot

Top Bottom
Ltop Lbot
TS
Cox
M
C
Rsub Csub
C
VI
on 6 NO /2
A
fid 65 LO 009
Figure 9.15.2.2: Equivalent circuit for the MIM without shield structure
TE
en 12 G
C /0
Rtop Cmim Rbot

tia 1 IES
H 1
Top Bottom
Ltop Lbot
12
lI
Cox
nf
or
m
Figure 9.15.2.3: Equivalent circuit for the MIM with shield structure
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.4 Model Scaling Rule:

9.15.2.4.1 Scaling Rule for MIM With and Without Shield
The scaling rules for the various elements R, L and C are empirically determined as follow:
Rtop (m ohm) = (8000/(L*W)+150)
Ltop (pH) = (W*0.11 - L*0.15 + 10.7)
Cmim (fF) = ((L*W) *1.025 + 2*(L+W) *0.2425)
Rbot (m ohm) = (3000/(L*W)+(L/W)*28+268.7+W*11.75)
Lbot (pH) = (W*0.13 + L*0.43+ 10.7)
TS
For MiM capacitor with metal shield

M
Cox (fF) = (((W+0.8)*(L+0.8)+((W+3.4)*4.4))*0.0396+(L+0.8)*0.01+1.0093)

C
For MiM capacitor without metal shield

C
VI
on 6 NO /2
Cox (fF) = (((W+0.8)*(L+0.8)+((W+3.4)*4.4)+((L+0.8+4.4)*1.5))*0.0056+0.2234)

Csub(fF) = ((W+(0.4+7.1)*2)*(L+(0.4+2.2+4)*2))*0.0022
A
Rsub(ohm) = 29545/((W +(0.4+7.1)*2)*(L+(0.4+2.2+4)*2))

fid 65 LO 009
TE
where
en 12 G
L : Length of top plate metal in m

C /0
W : Width of top plate metal in m

tia 1 IES
H 1
Temperature and voltage effects of Cmin are described in Section 9.15.2.7 while temperature effect of
12
Rtop and Rbot is documented in Section 9.15.2.8.

lI
nf
or
9.15.2.4.2 Parameter Table for MIM With and Without shield

m
Table 9.15.2.1: Parameter table of 1.0fF MIM without shield model

at
MIM Cmim Ltop Rtop Lbot Rbot Cox Rsub Csub

2
( m) (fF) (pH) (m ohm) (pH) (m ohm) (fF) (ohm) (fF)
io
30x30 951.6 9.5 158.9 9.5 652.5 6.7 15.2 4.3

IN
25x25 664.9 9.7 162.8 9.7 595.3 4.9 19.3 3.4

n
15x15 245.2 10.1 185.6 10.1 486.3 2.2 34.9 1.9

C
10x10 112.2 10.3 230.0 10.3 444.2 1.3 50.9 1.3

.
5x5 30.5 10.5 470.0 10.5 475.5 0.7 81.2 0.8

5x10 58.5 9.8 310.0 9.8 443.5 0.9 63.7 1.0
5x20 114.6 8.3 230.0 8.3 469.5 1.3 44.5 1.5
5x30 170.7 6.8 203.3 6.8 515.5 1.7 34.2 1.9
10x30 326.9 7.3 176.7 7.3 480.2 2.7 27.4 2.4
10x20 219.6 8.8 190.0 8.8 457.2 2.0 35.6 1.8
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table 9.15.2.2: Parameter table of 1.0fF MIM with shield model

MIM Cmim Ltop Rtop Lbot Rbot Cox
2
( m) (fF) (pH) (m ohm) (pH) (m ohm) (fF)
30x30 951.6 9.5 158.9 9.5 652.5 44.7
25x25 664.9 9.7 162.8 9.7 595.3 32.6
15x15 245.2 10.1 185.6 10.1 486.3 14.3
10x10 112.2 10.3 230.0 10.3 444.2 8.1
5x5 30.5 10.5 470.0 10.5 475.5 3.9
5x10 58.5 9.8 310.0 9.8 443.5 5.1
5x20 114.6 8.3 230.0 8.3 469.5 7.5
5x30 170.7 6.8 203.3 6.8 515.5 9.9
10x30 326.9 7.3 176.7 7.3 480.2 16.8
10x20 219.6 8.8 190.0 8.8 457.2 12.4
TS
Table 9.15.2.3: Parameter table of 2.0fF MIM without shield model

MIM(lt,wt) Cmim Ltop Rtop Lbot Rbot Cox Rsub Csub
M
2
(µm ) (fF) (pH) (m ohm) (pH) (m ohm) (fF) (ohm) (fF)
C
30x30 1791.9 9.5 158.9 27.5 652.5 11.5 15.2 4.3

20x20 803.6 9.9 170 21.9 539.2 5.9 25.4 2.6
C
10x10 206.2 10.3 230.0 16.3 444.2 2.3 50.9 1.3

VI
10x30 608.1 7.3 176.7 24.9 480.2 5.3 27.4 2.4

on 6 NO /2
A
Table 9.15.2.4: Parameter table of 2.0fF MIM with shield model

fid 65 LO 009
MIM(lt,wt) Cmim Ltop Rtop Lbot Rbot Cox

TE
2
( m) (fF) (pH) (m ohm) (pH) (m ohm) (fF)
en 12 G
30x30 1791.9 9.5 158.9 27.5 652.5 44.7

C /0
20x20 803.6 9.9 170 21.9 539.2 22.43

tia 1 IES
10x10 206.2 10.3 230.0 16.3 444.2 8.1

H 1
10x30 608.1 7.3 176.7 24.9 480.2 16.8

12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.5 Model Error Table

MIM capacitor fitting error between measurement and simulation are summarized in Table 9.15.2.5 ~ 9.15.2.10. For
each device four Y-parameter fitting errors are separated with real part and imaginary part.
Table 9.15.2.5: Fitting error (real Y-parameter) table of 1.0fF MIM without shield capacitor Model
Fitting Error (Real Y-parameter)
MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_
Target Parameter 30x30 25X25 15X15 10X10 5X5 5x10 5x20 5x30 10x20 10x30
Y11(%) 13.93 18.24 7.43 9.84 33.55 20.83 12.04 14.45 15.56 23.12
Y21(%) 13.94 18.12 8.34 20.11 31.87 28.47 18.67 18.48 17.21 24.07
Y12(%) 13.54 18.24 6.24 13.67 36.16 22.81 10.94 12.19 12.78 22.03
Y22(%) 13.46 17.81 6.25 16.51 67.96 38.08 14.79 10.19 11.96 21.00
MEAN(%) 13.72 18.10 7.07 15.03 42.39 27.55 14.11 13.83 14.38 22.56
Table 9.15.2.6: Fitting error (imaginary Y-parameter) table of 1.0fF MIM without shield capacitor Model
TS
Fitting Error (Imaginary Y-parameter)

M
Y11(%) 0.78 0.41 0.26 0.11 0.49 0.17 0.16 0.21 0.21 0.32
Y21(%) 0.77 0.39 0.26 0.46 0.97 0.18 0.16 0.21 0.18 0.29
C
Y12(%) 0.77 0.39 0.25 0.46 0.96 0.17 0.17 0.22 0.18 0.29
Y22(%) 0.77 0.35 0.35 0.14 0.55 0.34 0.12 0.24 0.20 0.28
C
MEAN(%) 0.77 0.38 0.28 0.29 0.74 0.21 0.15 0.22 0.19 0.29
VI
on 6 NO /2
Table 9.15.2.7: Fitting error (real Y-parameter) table of 1.0fF MIM with shield capacitor model
A

fid 65 LO 009
TE
Y11(%) 16.45 8.37 5.14 12.21 29.93 25.69 13.94 12.47 9.33 18.92
en 12 G
Y21(%) 15.35 6.96 4.88 14.12 35.07 34.16 12.32 8.98 6.08 17.17
Y12(%) 15.33 6.90 4.76 20.67 29.91 27.57 11.42 10.77 7.07 17.76
C /0
Y22(%) 14.11 5.12 10.11 24.30 33.44 20.39 35.29 10.05 9.95 13.84
tia 1 IES
H 1
MEAN(%) 15.31 6.84 6.22 17.83 32.09 26.95 18.24 10.57 8.10 16.92
Table 9.15.2.8: Fitting error (imaginary Y-parameter) table of 1.0fF MIM with shield Capacitor model
12
lI
Fitting Error (Imaginary Y-parameter)

nf
Y11(%) 1.02 0.69 0.14 0.43 0.15 0.17 0.22 0.33 0.28 0.19
or
Y21(%) 0.79 0.38 0.23 1.48 0.85 0.72 0.61 0.77 0.57 0.26
Y12(%) 0.81 0.40 0.21 1.50 0.79 0.66 0.53 0.70 0.50 0.22
m
Y22(%) 0.85 0.30 0.11 0.89 0.69 0.73 0.46 0.55 0.51 0.19
MEAN(%) 0.87 0.44 0.17 1.08 0.62 0.57 0.45 0.59 0.47 0.22
at
Table 9.15.2.9: Fitting error (real Y-parameter) table of 2.0fF MIM with/without shield capacitor Model
io

With shield Without shield
IN
Target MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_

Parameter 30x30 20X20 10X10 10x30 30x30 20X20 10X10 10x30
C
Y11(%) 5.53 14.62 7.55 5.15 13.38 16.31 7.82 9.23

Y21(%) 5.25 13.35 12.90 4.35 13.69 14.52 14.66 7.60
.
Y12(%) 6.33 16.08 5.21 6.57 13.06 17.42 4.96 10.46

Y22(%) 6.05 14.81 8.02 5.73 13.36 15.60 10.78 8.70
MEAN(%) 5.79 14.71 8.42 5.45 13.37 15.96 9.55 9.00
Table 9.15.2.10: Fitting error (imaginary Y-parameter) of 2.0fF MIM with/without shield capacitor Model
Fitting Error (Imag Y-parameter)
With shield Without shield
Target MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_ MIM_
Parameter 30x30 20X20 10X10 10x30 30x30 20X20 10X10 10x30
Y11(%) 0.43 0.59 1.43 2.45 0.34 0.63 5.74 2.97
Y21(%) 0.72 0.36 1.09 2.83 0.35 0.58 5.62 3.12
Y12(%) 0.69 0.37 1.14 2.81 0.34 0.58 5.67 3.09
Y22(%) 1.82 0.62 0.74 3.64 0.82 0.57 5.56 3.32
MEAN(%) 0.91 0.49 1.10 2.93 0.46 0.59 5.65 3.13
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.6 Fitting Results

Q fitting error at lower frequency is high and it is getting worse when capacitor size getting smaller. The Q values
are relatively high and the model error is not significant to circuit designs.
9.15.2.6.1 1.0fF MIM Without Shield
TS
M
C
C
VI
on 6 NO /2
(a) C (b) Q
A
fid 65 LO 009
Figure 9.15.2.4: MIM without shield 30x30, 25x25, 15x15, 10x10, 5x5 (a) C, (b) Q Plots
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
(a) C (b) Q
io
IN
Figure 9.15.2.5: MIM without shield 10x10, 10x20, 10x30 (a) C, (b) Q Plots
n
C
.
(a) C (b) Q
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.6.2 1.0fF MIM With Shield
TS
M
C
(a) C (b) Q
Figure 9.15.2.7: MIM without shield 30x30, 25x25, 15x15, 10x10, 5x5 (a) C, (b) Q Plots
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
(a) C (b) Q
m
at
io
IN
n
C
.
(a) C (b) Q
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.6.3 2.0fF MIM Without Shield
TS
M
C
(a) C (b) Q
C
VI
on 6 NO /2
Figure 9.15.2.10: 2.0fF MIM without shield 30x30, 25x2520x20, 15x15, 10x10, 5x5 (a) C, (b) Q Plots
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
(a) C (b) Q
IN
Figure 4.11: 2.0fF MIM without shield 10x10, 10x20, 10x30 (a) C, (b) Q Plots
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.6.4 2.0fF MIM With Shield
TS
M
C
C
(a) C (b) Q
VI
Figure 9.15.2.12: 2.0fF MIM without shield 30x30, 25x2520x20, 15x15, 10x10, 5x5 (a) C, (b) Q Plots
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
(a) C (b) Q
Figure 9.15.2.13: 2.0fF MIM without shield 10x10, 10x20, 10x30 (a) C, (b) Q Plots
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.7 Voltage and Temperature Coefficients of Cmin

9.15.2.7.1 1.0fF MIM Capacitor Model
Voltage and temperature characteristics of the capacitor are evaluated with 25x25 m2 MIM capacitor. The
capacitance shows a parabolic dependence of the DC bias (-5V to 5V in steps of 1V) at 25 oC with Vcc1 =
61.6 ppm/V and Vcc2 = -20.5 ppm/V2. At 0 V bias, temperature effect can be modeled with Tcc1 = –52.25
ppm/oC, and Tcc2 = 0.01 ppm/oC2 .
1 .0 0 0 1 1 .0 0 2 0
1 .0 0 0 0 1 .0 0 1 5 T c c 1 = -5 2 .2 5 p p m / o C
0 .9 9 9 9 1 .0 0 1 0 T c c 2 = 0 .0 1 p p m / o C 2
Normalized Cap
Normalized Cap
0 .9 9 9 8 1 .0 0 0 5
TS
0 .9 9 9 7 1 .0 0 0 0
0 .9 9 9 5
0 .9 9 9 6 V c c 1 = 6 1 .6 p p m /V 0 .9 9 9 0
M
0 .9 9 9 5 0 .9 9 8 5
V c c 2 = -2 0 .5 p p m /V 2
0 .9 9 9 4 0 .9 9 8 0
C
0 .9 9 9 3 0 .9 9 7 5
-6 -4 -2 0 2 4 6 -1 00 -5 0 0 50 100 150
C
V o lt D e lt a T e m p
VI
on 6 NO /2
(a) (b)
Figure 9.15.2.14: (a) VCC, (b) TCC Plots
A
fid 65 LO 009
1
Curve fitting of the measured C for VCC is modeled with C(V) = Co[1+Vcc1(V)+Vcc2(V)2 ], where Co is
TE
capacitance at 0V bias.
en 12 G
2
Curve fitting of the measured C for TCC is modeled with C(T) = C(Tnom)[1+Tcc1(T-Tnom)+Tcc2(T-
C /0
Tnom)2 ], where Tnom is at 25 oC and C(Tnom) is capacitance at 25 oC.

tia 1 IES
H 1
12
9.15.2.7.2 2.0fF MIM Capacitor Model

lI
Voltage and temperature characteristics of the capacitor are evaluated with 25x25 m2 MIM capacitor. The
nf
o
capacitance shows a parabolic dependence of the DC bias (-5V to 5V in steps of 1V) at 25 C with Vcc1 =
or
128 ppm/V and Vcc2 = -57 ppm/V2. At 0 V bias, temperature effect can be modeled with Tcc1 = –
29.4 ppm/oC, and Tcc2 = 0 ppm/oC2 .
m
at
1.0004 1.0005
io
1.0002 1.0000
IN
1.0000
n
0.9995
2.0fF/um^2
C/C_0 C (%)
0.9998
C/C_0V (%)
0.9990
C
0.9996
0.9985
o
2.0fF/um^2
0.9994
.
0.9980
0.9992 2
y = -0.000057x + 0.000128x + 1.000004
0.9990 2
0.9975
R = 0.997738 2
0.9970 y = -0.0000000x - 0.0000294x + 1.0000315
0.9988 2
R = 0.9980485
0.9986 0.9965
-5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 -20 10 40 70 100
DC Bias (volts) o
T-25 ( C)
(a) (b)
Figure 9.15.2.15: (a) VCC, (b) TCC Plots
1 2
Curve fitting of the measured C for VCC is modeled with C(V) = Co[1+Vcc1(V)+Vcc2(V) ], where Co is capacitance at 0V bias.
2 2 o
Curve fitting of the measured C for TCC is modeled with C(T) = C(Tnom)[1+Tcc1(T-Tnom)+Tcc2(T-Tnom) ], where Tnom is at 25 C and
o
C(Tnom) is capacitance at 25 C.
3
Measurements have been carried out using the HP 4284 LCR meter @100KHz.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.8 Temperature Effect to Capacitance and Q

Temperature effect to capacitance and Q as a function of operating frequency is studied with a 25x25
m2 MIM capacitor and summarized in Figure 9.15.2.16.
1.0 1.E+05
Q mea 125C
Q sim 125C
1.E+04 Q mea 25C
Q sim 25C
0.8
1.E+03 Q mea -45C
Q sim -45C
C [pf] Q
C mea 125C
C sim 125C
1.E+02
0.6
C mea 25C
TS
C sim 25C 1.E+01

C mea -45C
C sim -45C
M
0.4 1.E+00
0 4 8 12 16 20 0 4 8 12 16 20
C
Freq [E+9] Freq [E+9]

(a) (b)
C
Figure 9.15.2.16: MIM 25x25 at 125oC, 25oC, -45oC (a) C, (b) Q plots
VI
on 6 NO /2
The capacitance is not sensitive to the temperature effect when frequency is swept from low frequency to
A
20 GHz. However, the Q changes with the temperature. The temperature effect can be contributed by the
fid 65 LO 009
resistors Rbot and Rtop of the MIM capacitor. The effect can be modeled with Tcr1 = 5.16 E-3 and Tcr2 =
TE
-1.34 E-5
en 12 G
C /0
2
tia 1 IES
H 1
1.5
12
Normalized R
lI
nf
1
or
0.5 TCR1 = 5.16E-3

m
TCR2 = -1.34E-5
at
0
io
-100 -50 0 50 100 150

Delta Temp
IN
Figure 4.17: MIM TCR Plot

n
C
1
Curve fitting of the measured R for TCR uses R(T) = R(Tnom)[1+Tcr1(T-Tnom)+Tcr2(T-Tnom)2],
where Tnom is at 25 oC and R(Tnom) is resistance at 25 oC.
.
2
Resistance value (Rtop +Rbot) obtained through fitting of S-parameter measurement of MIM at
different temperature.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.15.2.9 Corner Model Table:

The skew parameters are listed below for corner-case simulation.
WORST CASE PATAMETER VALUES
component Parameter SLOW Typical FAST
Rtop rctm_mimfac 1.1727 1 0.8273
Rbot rctm_mimfac 1.1727 1 0.8273
Ltop l_mimfac 1.0235 1 0.9762
Lbot l_mimfac 1.0235 1 0.9762
Cmim cmim_mimfac 1.15 1 0.85
TS
Cox cm5_mimfac 1.052 1 0.9538

Rsub rsub_mimfac 0.8 1 1.2
M
Csub csub_mimfac 1.25 1 0.8333

C
9.15.2.10 Mismatch and Statistical model:

C
VI
on 6 NO /2
The model for this technology has added the capability for mismatch analysis of an identical and closely
A
spaced MIM pair. Random variations in Gaussian distribution of the total capacitance are included in the
fid 65 LO 009
model to account for the mismatch performance. The mismatch models are with subcuit names ”xxx_mis”
TE
with a suffix “mis”. The designers need to include appropriate models for nominal or Monte-Carlo analysis.
en 12 G
The simulation results with the measured data of mimcaps are shown in Fig. 9.15.2.18
C /0
Statistical libraries for process (die to die ) variation are denoted by MC_RFMIM and MC_MIM for RF and
tia 1 IES
H 1
baseband model respectively.

12
lI
0.50
nf
0.45 MIM(Lot-to-Lot)
or
0.40
m
0.35
σ of δ C(%)
at
0.30
y = 2.51 x
io
0.25
IN
0.20
n
0.15 Lot1
C
Lot2
.
0.10
0.05 simulation
0.00
0.00 0.05 0.10 0.15
0.5 -1
1/(Area) (um )
Figure 9.15.2.18: Simulation data of the Monte-Carlo
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16 Inductor Model

9.16.1 Model Usage Guide
Standard and symmetric octagonal spiral inductors using a thick AlCu metal with physical thickness at 2.34 um &
4.6um were fabricated on top of P-substrate and modeled based on the two-port Y-parameter fitting. Three types of
scalable inductor models, which are standard (STD), symmetric (SYM), and symmetric with center tap (SYMCT)
have been included in this release. The detailed ranges of models are listed in Table 9.16.1.
Table 9.16.1: Modeled spiral inductors
Specification Standard Inductor Symmetric Inductor
Inductance(nH) 0.21 ~ 15.75 0.21 ~ 13.49
Fixed width(µµm) 6 9 15 30 9 15 30
TS
0.5 ~ 5.5 0.5 ~ 5.5 0.5 ~ 5.5 1.5 ~ 5.5 1~4 1~5 1~5
Valid Turns(N) Integral turn increments for symmetric without center-tap
1/4 turn increments
Odd turn increments for symmetric with center-tap
M
Valid Radius(R:µµm) 30 ~ 125 30 ~ 120 40 ~ 120 65 ~ 150

C
Variable Metal Layer 1P4M, 1P5M, 1P6M

Valid Temperature -40oC ~ 125oC
C
Valid Frequency min(20GHz, Fsr)

VI
(a) 20KÅ UTM inductor model scope

on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
(b) 40KÅ UTM inductor model scope

or
The symmetric inductors without center-tap can be used both in a single-ended operation and differential mode
m
operation. Under differential mode operation, a DC biased can be applied at the tap. No devices are allowed to be
placed underneath the inductor since performance will be affected by the magnetic flux penetrating into the silicon
at
substrate. Designers can change turns (N) and r®us (R) to tune inductance (L). For information regarding the
inductor design, please refer to the thick metal rule (section 4.6.7).
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.2 Inductor Layout

Top views of different inductor layouts with the key design parameters are shown in Figure 9.16.1.
Port1
M6
N=2.5 2R S P-substrate
W
pick-up
TS
50um
M
Under-
path(M5)
C
Port2
C
Standard inductor
VI
on 6 NO /2
A
Port1 Port2 Port1 Port2

fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
N=3
H 1
N=3
2R
12
lI
nf
or
Under Center
crossing(M5) tap(M4)
m
Symmetric inductor Symmetric inductor with center-tap

at
io
Figure 9.16.1: Top views of inductor layouts.

IN
Key inductor parameters are described below:

C
N: Number of turns
W: Inductor track width
.
S: Spacing between tracks

R: Inner radius of inductor
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.3 Equivalent Circuit Model

A lumped RLC equivalent circuit representation of two-port standard inductor is shown in Figure 9.16.2. The values
of each component are extracted through the fitting of the two-port Y-parameters that are obtained after de-
embedding the dummy open and through accordingly. Figure 9.16.3 shows the equivalent circuit of a symmetric
inductor with and without center-tap (dash-line).
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
Figure 9.16.2: Equivalent circuit of a standard inductor.

en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
Figure 9.16.3: Equivalent circuit of a symmetric inductor with and without center-tap.
.
The definitions of the parameters are,

• L1 (and L2): Inductor self-inductance
• M: Mutual inductance
• R1 (and R2): Metal series resistance
• C12: Coupling capacitance between ports 1 and 2
• Cox1 (Cox2 and Cox3): Oxide capacitance between the spiral and substrate
• Rsub1 (Rsub2 and Rsub3): Silicon substrate resistance
• Csub1 (Csub2 and Csub3): Silicon substrate capacitance
• Ls1 (and Ls2): Inductance to model the skin effect of the metal track
• Rs1 (and Rs2): Resistance to model the skin effect of the metal track
• Lct: Inductance due to the center tap metal
• Rct: Resistance due to the center tap metal
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.4 Scaling Rules and Model Parameters

Inductance as a function of number of turns (N) and r®us (R) is modeled with the empirical equation below.
b c d f
L1=L2=a*N *DA *DO +e*N +g
where a, b, c, d, e, f and g are fitting parameters, DO is outer diameter, DI is inner diameter and DA(average
diameter) = (DO+DI)/2. Quality of the model is show in Figure 9.16.4.
TS
L(nH)
M
100.0
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
Measured
at
Simulated
io
Figure 9.16.4: Inductance (W=15 m) as a function of number of turns and radius @ 0.9GHz
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
The scaling formulae for other parameters with respect to N and DA are,
For standard inductor,
2 2
R1=R2=a*N*DA +b*N+c*DA+d*N +e
2 2
Rs1=Rs2=a*N*DA +b*N+c*DA+d*N +e
2 2
C12=a*N+b*N*DA+c*N +d*DA +e
Cox1=a*N*DA+b
Cox2=Cox1
Cox3=Cox1+Cox2
Rsub1=a/(N*DA)+b/DA+c/N+d
Rsub2=Rsub1
Rsub3=Rsub1*Rsub2/(Rsub1+Rsub2)
TS
Csub1=1.053e-11/Rsub1
Csub2=Csub1
M
Csub3=Csub1+Csub2
C
For symmetric inductor

b c d f
C
K=a*N *DA *DO +e*N +g

VI
on 6 NO /2
For symmetric with center-tap

A
2
fid 65 LO 009
Lct=a*N +b*N+c
TE
Rct=a*N+b
en 12 G
Fr is the resonance frequency of the inductor under single-end operation, Qs (-imagY11/realY11) is the Q-
C /0
factor of the inductor under single-end operation, Qd (imagZd/realZd) is the Q-factor of the inductor under
tia 1 IES
H 1
differential mode operation and Fdr is the resonance frequency of the inductor under differential mode
operation.
12
lI
The differential mode one-port S-parameter Sd and differential mode input impedance Zd are obtained by
nf
using the formulae below,

or
S11 + S 22 − S12 − S 21
Sd = ,
2
m
 1 + Sd 
Z d = 2Z o  
at
 1 − Sd 
io
IN
where 2Zo is the differential system impedance with Zo assumed to be 50Ω. S11, S12, S21 and S22 are the
n
two-port S-parameters of the single-ended mode inductor. All of S11, S12, S21, S22, and Sd were used in
C
the parameter extraction.

.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Table.2: Scaling rules and model parameters of STD, SYM, and SYMCT with W=15 µm
Parameter STD
1.731 2.228 -1.034
L1=L2 4.381E-4*N *DA *DO -19.27*N9.96E-4+19.34
Ls1=Ls2 0.717*N1.063*DA-0.104*DO0.181-0.942*N1.113-0.0492
9.897E-06*N*DA2-0.1242*N+2.602E-05*DA+0.0843*N2+0.717
R1=R2
Rs1=Rs2 3.469E-06*N*DA2+0.87*N+0.00374*DA-0.0366*N2-0.365
C12 14.87*N-1.424E-03*N*DA-1.239*N2+3.621E-4*DA2-9.075
Cox1 0.0471*N*DA+14.27
Cox2 0.0399*N*DA+15.21
Rsub1 62440/(N*DA)+45261.4/DA+1311.3/N-49.659
TS
Rsub2 -11417/(N*DA)+172202/DA+866.29/N+130.12
M
Parameter SYM & SYMCT

1.492 1.866
L1=L2 4.54E-4*N *DA *DO +5.691*N-0.00965-5.656
-0.72
C
Ls1=Ls2 16.77*N0.205*DA0.0685*DO-0.0719-655.2*N0.00502+638.9
C
R1=R2 7.641E-06*N*DA2-0.394*N-0.00145*DA+0.155*N2+1.067
VI
on 6 NO /2
Rs1=Rs2 4.653E-06*N*DA2+0.136*N+0.00279*DA+0.085*N2-0.303
A
C12 3.208*N+0.0833*N*DA+0.434*N2-5.02E-05*DA2-11
fid 65 LO 009
Cox1 0.0391*N*DA+10.45
TE
Rsub1 53011/(N*DA)+45116/DA+1666/N-395.07
en 12 G
K 0.928*N0.366*DA2.44*DO-2.574+0.901*N0.3002-1.2304
C /0
Lct 3.75E-4*N2+0.181625
tia 1 IES
H 1
Rct 0.075*N+0.645
12
lI
Table.3: Extracted parameters of STD, SYM, and SYMCT with W=15 µm.
nf
STD
or
Device L1 L11 R1 R11 C1 Cox1 Cox2 Rsub1 Rsub2

N=0.5 R=34 µm 0.112 0.013 0.712 0.384 0.500 16.2 16.9 4616.7 3656.9
m
N=0.5 R=64 µm 0.135 0.028 0.781 0.632 5.379 17.7 18.1 3760.7 2905.4
N=1.5 R=32.1 µm 0.222 0.125 0.860 1.265 13.591 21.1 21.0 1727.3 2417.7
at
N=1.5 R=62.1 µm 0.372 0.157 1.087 1.569 18.949 25.3 24.6 1380.6 1761.0
io
N=3.5 R=32.1 µm 0.890 0.410 1.906 2.924 33.284 35.8 33.4 809.5 1674.7
IN
N=3.5 R=62.1 µm 1.531 0.448 2.574 3.382 39.949 45.7 41.8 656.7 1265.6
n
N=3.5 R=122.1 µm 3.005 0.529 4.658 4.560 61.098 65.5 58.6 528.4 922.2
C
N=5.5 R=32.1 µm 2.301 0.759 4.057 4.441 43.705 56.9 51.3 533.4 1323.4
N=5.5 R=62.1 µm 3.698 0.792 5.328 5.110 51.676 72.4 64.5 441.2 1046.3
.
N=5.5 R=122.1 µm 6.898 0.882 9.045 6.861 75.438 103.5 90.8 353.2 781.8
SYM & SYMCT

Device L1 L11 R1 R11 C1 Cox Rsub K Lct Rct
N=1 R=40 µm 0.111 0.012 0.759 0.226 0.099 14.2 2304.7 0.017 0.182 0.72
N=1 R=60 µm 0.152 0.041 0.771 0.380 2.969 15.7 1998.6 0.038 0.182 0.72
N=1 R=120 µm 0.286 0.062 0.955 0.933 10.614 20.4 1656.6 0.053 0.182 0.72
N=3 R=40 µm 0.464 0.239 1.474 1.464 33.937 25.6 647.2 0.339 0.185 0.87
N=3 R=60 µm 0.674 0.318 1.689 1.743 43.335 30.3 532.0 0.386 0.185 0.87
N=3 R=120 µm 1.363 0.424 2.775 2.845 70.562 44.4 377.8 0.457 0.185 0.87
N=5 R=40 µm 1.232 0.616 3.751 3.579 82.467 42.3 280.1 0.524 0.191 1.02
N=5 R=60 µm 1.683 0.710 4.252 4.031 98.393 50.1 212.8 0.571 0.191 1.02
N=5 R=120 µm 3.157 0.858 6.490 5.835 145.20 73.6 110.8 0.659 0.191 1.02
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.5 Variable Metal Layer Model

Field oxide capacitance, Coxn, where n is 4, 5 or 6, can be represented with the equation below.
Cox(layer)=Cox(layer=6)*((1/(7.67792+(4.14167)*(layer-2)))/(0.0412463))
The variation of Q with different metal layers (1P4M ~ 1P6M) is caused by the varying capacitance between the
spiral and substrate. High Coxn degrades Q. The effect is shown in Figure 9.16.5.
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
Circle: Measured; Line: Simulated

TE
en 12 G
Figure 9.16.5 20KÅ UTM (a) Standard inductor (b) Symmetric inductor
C /0
tia 1 IES
H 1
9.16.6 Corner Model Table

12
lI
nf
Skew parameters are listed in Table 9.16.4. The worst case is determined on the variation of Q-value.
or
Table 9.16.4: Corner parameters for inductor model.

WORST CASE PATAMETER VALUES
m
component Parameter SLOW Typical FAST

at
L, Ls, K, Lct l_indfac 1.0235 1 0.9762

io
R, Rs rm6_indfac 1.1 1 0.9

IN
C12 c12_indfac 1.2236 1 0.7764

C
Cox cm6_indfac 1.0509 1 0.9551

.
Rsub rsub_indfac 0.8 1 1.2

Rct rm5_indfac 1.1 1 0.90
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.7 Model Error Table

Inductor fitting error between measurement and simulation are summarized in Table 9.16.5 to 9.16.14.
For each device four Y-parameter fitting errors are separated with real part and imaginary part. Definition
of fitting error is documented in section 12.
Target Width = 6um Width = 9um
Parameter N 0.5 0.5 3.5 3.5 3.5 5.5 5.5 5.5 0.5 0.5 1.5 1.5 2.5 2.5 2.5 4.5 4.5 4.5
R 39.0 54.0 31.0 61.0 121.1 31.0 61.0 121.1 42.0 57.0 31.4 61.4 31.4 61.4 121.4 31.4 61.4 121.4
Y11(%) 10.7 18.8 14.2 2.5 0.9 15.6 4.6 1.1 10.8 16.6 16.4 0.7 12.5 1.3 1.6 7.3 4.6 2.9
Y21(%) 10.7 18.7 14.2 2.5 1.1 15.6 4.7 1.7 10.8 16.6 16.4 0.6 12.5 1.3 1.7 7.3 4.7 3.1
TS
Y12(%) 10.7 18.8 14.2 2.5 1.1 15.6 4.7 1.6 10.8 16.6 16.4 0.7 12.5 1.3 1.7 7.3 4.6 3.0
Y22(%) 10.7 18.8 14.2 2.6 1.1 15.6 4.7 1.3 10.8 16.6 16.4 0.7 12.5 1.4 1.7 7.4 4.7 2.9
MEAN(%) 10.7 18.8 14.2 2.5 1.0 15.6 4.7 1.4 10.8 16.6 16.4 0.7 12.5 1.3 1.7 7.3 4.6 3.0
M
Table 9.16.5: Fitting error (real Y-parameter) table for 20KÅ UTM standard inductors (W = 6, 9um).
C

Parameter N
C
0.5 0.5 3.5 3.5 3.5 5.5 5.5 5.5 0.5 0.5 1.5 1.5 2.5 2.5 2.5 4.5 4.5 4.5
VI
R 39.0 54.0 31.0 61.0 121.1 31.0 61.0 121.1 42.0 57.0 31.4 61.4 31.4 61.4 121.4 31.4 61.4 121.4
on 6 NO /2
Y11(%) 9.9 18.2 16.0 3.1 0.7 19.5 7.3 2.7 10.7 16.2 16.8 0.7 13.8 1.3 2.6 9.7 7.2 4.6
A
Y21(%) 10.0 18.2 16.3 5.6 6.7 19.9 9.1 7.9 10.7 16.2 16.8 1.6 13.9 3.2 5.1 10.1 7.9 6.6
fid 65 LO 009
Y12(%) 9.9 18.1 16.2 5.6 6.7 19.8 9.0 7.9 10.6 16.1 16.8 1.6 13.8 3.2 5.1 10.0 7.8 6.6
TE
Y22(%) 9.9 18.2 16.0 3.2 0.8 19.5 7.3 2.7 10.7 16.2 16.8 0.7 13.8 1.3 2.6 9.7 7.2 4.6
MEAN(%) 9.9 18.2 16.1 4.4 3.7 19.7 8.2 5.3 10.7 16.2 16.8 1.2 13.8 2.3 3.8 9.9 7.5 5.6
en 12 G
Table 9.16.6: Fitting error (imaginary Y-parameter) table for 20KÅ UTM standard inductors (W = 6,
C /0
9um).
tia 1 IES
H 1

12
lI
Parameter N 0.5 0.5 1.5 1.5 3.5. 3.5 3.5 5.5 5.5 5.5 1.5 1.5 3.5 3.5 3.5 5.5 5.5 5.5
R 34.0 64.0 32.1 62.1 32.1 62.1 122.1 32.1 62.1 122.1 34.1 64.1 34.1 64.1 124.1 34.1 64.1 124.1
nf
Y11(%) 16.5 19.7 13.8 5.0 7.1 2.8 2.6 6.1 4.8 7.1 7.0 8.5 1.2 2.7 2.5 1.0 1.8 2.0
Y21(%) 16.5 19.7 13.8 5.0 7.1 2.8 2.7 6.1 4.9 7.3 7.1 8.5 1.3 2.5 1.9 0.6 1.7 3.0
or
Y12(%) 16.6 19.7 13.8 5.0 7.1 2.8 2.6 6.1 4.7 7.1 7.1 8.5 1.3 2.6 2.1 0.6 1.5 2.8
Y22(%) 16.5 19.8 13.8 5.1 7.1 2.8 2.5 6.1 4.8 7.1 7.0 8.5 1.1 2.6 2.1 0.6 1.5 1.9
m
MEAN(%) 16.5 19.7 13.8 5.0 7.1 2.8 2.6 6.1 4.8 7.2 7.1 8.5 1.2 2.6 2.1 0.7 1.6 2.4
Table 9.16.7: Fitting error (real Y-parameter) table for 20KÅ UTM standard inductors (W = 15, 30um).
at

io

Parameter N
IN
0.5 0.5 1.5 1.5 3.5. 3.5 3.5 5.5 5.5 5.5 1.5 1.5 3.5 3.5 3.5 5.5 5.5 5.5
n
R 34.0 64.0 32.1 62.1 32.1 62.1 122.1 32.1 62.1 122.1 34.1 64.1 34.1 64.1 124.1 34.1 64.1 124.1
Y11(%)
C
13.4 19.5 14.7 5.1 9.9 5.6 6.1 12.9 7.6 7.2 11.5 15.3 3.9 4.7 2.8 0.8 1.3 2.3
Y21(%) 13.4 19.5 14.7 5.2 10.2 6.0 6.8 12.9 7.7 7.6 11.4 15.2 3.9 4.6 2.8 0.3 1.1 2.0
.
Y12(%) 13.4 19.4 14.7 5.1 10.1 5.9 6.7 12.9 7.7 7.6 11.4 15.2 3.9 4.6 2.9 0.3 1.2 2.1
Y22(%) 13.4 19.5 14.7 5.1 10.0 5.6 6.1 12.9 7.6 7.2 11.4 15.3 3.9 4.7 2.8 0.6 1.3 2.3
MEAN(%) 13.4 19.5 14.7 5.1 10.1 5.8 6.4 12.9 7.6 7.4 11.4 15.3 3.9 4.7 2.8 0.5 1.2 2.2
Table 9.16.8: Fitting error (imaginary Y-parameter) table for 20KÅ UTM standard inductors (W = 15,
30um).
Document No.
Version
: T-018-LO-DR-001
: 2.8

Target Width = 9um Width = 9um with center-tap
Parameter N 1 1 1 3 3 3 5 5 5 1 1 1 3 3 3
R 30 60 120 30 60 120 30 60 120 30 60 120 30 60 120
Y11(%) 20.3 13.4 5.5 6.5 5.2 4.8 7.8 1.3 2.6 6.1 4.1 6.5 6.1 6.8 7.8
Y21(%) 20.3 13.3 5.5 6.5 5.2 4.8 7.9 1.5 2.6 9.6 7.3 12.8 21.9 26.0 21.4
Y12(%) 20.4 13.4 5.4 6.5 5.2 4.8 7.8 1.4 2.5 9.5 7.4 12.7 22.0 26.3 21.7
Y22(%) 20.3 13.4 5.5 6.5 5.2 4.8 7.8 1.3 2.6 5.7 3.4 9.1 2.6 6.3 7.6
MEAN(%) 20.3 13.4 5.5 6.5 5.2 4.8 7.8 1.4 2.6 7.7 5.6 10.3 13.1 16.4 14.6
Table 9.16.9: Fitting error (real Y-parameter) table for 20KÅ UTM symmetric inductors (W = 9um).
TS
Parameter N 1 1 1 3 3 3 5 5 5 1 1 1 3 3 3
R 30 60 120 30 60 120 30 60 120 30 60 120 30 60 120
M
Y11(%) 20.9 14.3 5.4 7.0 7.4 8.0 9.3 2.2 3.9 11.8 6.6 6.3 7.8 6.9 7.0
C
Y21(%) 20.9 14.3 5.6 7.0 7.3 8.0 9.3 2.2 3.8 12.5 6.0 10.0 16.1 24.5 20.2
Y12(%) 20.8 14.2 5.6 6.9 7.5 8.1 9.2 2.3 3.8 12.3 6.0 10.0 16.2 24.5 20.2
C
Y22(%) 20.9 14.3 5.4 7.0 7.4 8.0 9.3 2.2 3.9 11.0 5.6 9.1 5.4 6.7 7.1
VI
on 6 NO /2
MEAN(%) 20.9 14.3 5.5 7.0 7.4 8.0 9.3 2.3 3.9 11.9 6.1 8.9 11.4 15.7 13.6
Table 9.16.10: Fitting error (imaginary Y-parameter) table for 20KÅ UTM symmetric inductors (W =
A
9um).
fid 65 LO 009
TE

en 12 G
Parameter N 1 1 1 3 3 3 5 5 5 1 1 1 3 3 3 5 5 5
C /0
R 40 60 120 40 60 120 40 60 120 40 60 120 40 60 120 40 60 120

tia 1 IES
H 1
Y11(%) 8.4 8.2 5.1 6.6 5.4 1.4 3.9 1.7 4.6 17.1 10.6 9.6 4.7 5.2 6.8 9.1 9.9 10.7
Y21(%) 8.5 8.2 5.2 6.6 5.4 1.5 4.0 1.8 4.7 38.0 28.0 11.0 25.3 22.1 17.5 26.6 24.0 20.7
12
Y12(%)
lI
8.4 8.2 5.1 6.5 5.3 1.5 3.9 1.7 4.5 38.0 27.8 11.1 26.4 22.3 17.9 26.5 24.1 20.8
Y22(%) 8.4 8.2 5.1 6.6 5.4 1.4 3.9 1.7 4.6 24.3 14.0 11.1 6.2 6.2 6.2 7.5 8.9 10.2
nf
MEAN(%) 8.4 8.2 5.1 6.6 5.4 1.4 3.9 1.7 4.6 29.3 20.1 10.7 15.6 14.0 12.1 17.4 16.7 15.6
Table 9.16.11: Fitting error (real Y-parameter) table for 20KÅ UTM symmetric inductors (W =
or
15um).
m

Parameter N
at
1 1 1 3 3 3 5 5 5 1 1 1 3 3 3 5 5 5
R 40 60 120 40 60 120 40 60 120 40 60 120 40 60 120 40 60 120
io
Y11(%) 12.5 10.0 4.5 9.2 9.9 1.8 8.7 3.9 5.7 12.4 8.4 10.2 5.5 5.7 5.5 10.0 8.8 9.6
Y21(%) 12.5 10.1 4.8 9.1 9.7 1.9 8.6 3.8 5.7 27.0 20.3 11.2 21.4 20.4 14.8 21.4 20.0 18.7
IN
Y12(%) 12.4 10.0 4.7 9.2 9.8 2.0 8.5 3.7 5.7 27.0 20.4 10.6 21.6 20.6 14.7 21.4 20.0 18.7
Y22(%) 12.5 10.0 4.5 9.2 9.9 1.8 8.7 3.9 5.7 17.2 7.9 12.3 5.3 6.3 5.3 9.1 9.2 9.4
C
MEAN(%) 12.5 10.0 4.7 9.1 9.8 1.9 8.6 3.8 5.7 20.9 14.3 11.1 13.4 13.2 10.1 15.5 14.5 14.1
.
15um).
Parameter N 1 1 1 3 3 3 5 5 5 1 1 1 3 3 3 5 5 5
R 65 90 150 65 90 150 65 90 150 65 90 150 65 90 150 65 90 150
Y11(%) 8.3 3.8 5.0 3.1 2.8 3.7 2.9 3.9 5.2 16.8 11.4 9.6 8.5 10.1 12.3 17.3 17.9 17.6
Y21(%) 8.4 3.8 5.1 3.2 2.9 3.8 3.2 4.2 5.5 43.3 37.3 17.4 30.1 31.7 28.3 37.2 33.8 26.9
Y12(%) 8.3 3.8 5.0 3.3 3.0 3.9 3.0 4.0 5.4 44.8 39.1 19.7 30.5 32.1 28.4 37.4 33.8 26.9
Y22(%) 8.3 3.8 5.0 3.1 2.8 3.6 2.9 3.9 5.2 28.0 24.6 15.7 7.4 7.6 10.6 16.2 17.2 17.1
MEAN(%) 8.3 3.8 5.0 3.2 2.9 3.8 3.0 4.0 5.3 33.2 28.1 15.6 19.1 20.4 19.9 27.0 25.7 22.1
Table 9.16.13: Fitting error (real Y-parameter) table for 20KÅ UTM symmetric inductors (W =
30um).
Document No.
Version
: T-018-LO-DR-001
: 2.8

Parameter N 1 1 1 3 3 3 5 5 5 1 1 1 3 3 3 5 5 5
R 65 90 150 65 90 150 65 90 150 65 90 150 65 90 150 65 90 150
Y11(%) 13.3 8.2 8.4 4.5 3.6 3.8 3.1 1.4 1.4 8.9 5.8 8.5 6.7 7.4 7.9 13.0 13.0 12.5
Y21(%) 13.3 8.3 8.6 4.4 3.5 3.6 3.0 1.6 2.1 20.1 22.3 11.0 26.1 28.0 28.0 33.7 32.4 26.9
Y12(%) 13.3 8.2 8.5 4.5 3.6 3.7 3.0 1.6 2.1 19.8 21.4 10.7 26.3 27.6 28.0 33.7 32.5 26.9
Y22(%) 13.3 8.2 8.4 4.5 3.7 3.8 3.0 1.4 1.4 12.5 11.5 8.0 7.7 6.5 7.8 12.8 12.8 12.3
MEAN(%) 13.3 8.2 8.5 4.5 3.6 3.7 3.0 1.5 1.7 15.4 15.2 9.5 16.7 17.4 18.0 23.3 22.7 19.6
30um).
TS
M
C
C
Table 9.16.15: Fitting error (real Y-parameter) table for 40KÅ UTM standard inductors.
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
Table 9.16.16: Fitting error (imaginary Y-parameter) table for 40KÅ UTM standard inductors.
lI
nf
or
m
at
io
IN
Table 9.16.17: Fitting error (real Y-parameter) table for 40KÅ UTM symmetric inductors.
C
.
Table 9.16.18: Fitting error (imaginary Y-parameter) table for 40KÅ UTM symmetric inductors.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.8 Device Characteristics

W = 6 um 20KÅ UTM Standard Inductor Fitting Results
Circle : Measured
Line : Simulated
TS
(a) (b) (c)

Figure 9.16.6: Measured and simulated data of Q and L (a) R=31um, (b) R=61um, (c) R=121um
M
W = 9um 20KÅ UTM Standard Inductor Fitting Results

C
C
VI
on 6 NO /2
Circle : Measured
Line : Simulated
A
fid 65 LO 009
TE
en 12 G
C /0
(a) (b) (c)

tia 1 IES
H 1
Figure 9.16.7:Measured and simulated data of Q and L (a) R=31.4um, (b) R=61.4um, (c)
R=121.4um
12
lI

nf
or
Circle : Measured
m
Line : Simulated
at
io
IN
(a) (b) (c)

n
C
R=122.1um
.
Circle : Measured
Line : Simulated
(a) (b) (c)

R=124.1um
Document No.
Version
: T-018-LO-DR-001
: 2.8
W = 9um 20KÅ UTM Symmetric Inductor Fitting Results
Circle : Measured
Line : Simulated
(a) (b) (c)
TS

M
C
Circle : Measured
C
Line : Simulated
VI
on 6 NO /2
A
fid 65 LO 009
TE
(a) (b) (c)

en 12 G
C /0

tia 1 IES
H 1
12
lI
Circle : Measured
nf
Line : Simulated
or
m
at
(a) (b) (c)

io
IN
W = 6um and 9um, 40KÅ UTM Standard Inductor single-ended Fitting Results
C
.
3.5
3.5
(a) (b) (c) (d)

Figure 9.16.13: Measured and simulated data of Q and L (a) W=6um R=60um, (b) W=6um
R=120um, (c) W=9um R=60um, (d) W=9um R=120um
Document No.
Version
: T-018-LO-DR-001
: 2.8
W = 15um and 30um, 40KÅ UTM Standard Inductor single-ended Fitting Results
(a) (b) (c) (d)
TS

M
W = 9um and 15um, 40KÅ UTM Symmetric Inductor Differential Fitting Results
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
(a) (b) (c) (d)

tia 1 IES
H 1
12
lI
W = 30um 40KÅ UTM Symmetric Inductor Differential Fitting Results

nf
or
m
at
io
IN
n
C
(a) (b)
.
R=120um.
Document No.
Version
: T-018-LO-DR-001
: 2.8
9.16.9 Temperature Effect Model

Temperature effect was analyzed through characterization of S-parameters. Two types of inductors (standard and
symmetric inductor) were measured at three different temperatures (-40C, 25C, and 125C). Temperature effect is
handled with the two equations below.
R(T)=R*(0.003286*(temp-25)+1)
Rsub(T)=Rsub*(0.000027*(temp-25)*(temp-25)+0.00644586*(temp-25)+1)
Variation of Q with temperature is attributed to spiral metal resistance and substrate resistance. The spiral metal
has a positive TCR, which increases resistance with the temperature. It decreases the Q-value. Although substrate
resistance also has a positive temperature coefficient, it enhances Q-value at high frequency. Figure 9.16.16 shows
the simulated and measured data at three different temperatures.
TS
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
Standard
at
Symmetric
io
IN
n
C
Circle: Measured; Line: Simulated

.
Figure 9.16.16: (a) 20KÅ UTM Standard inductor (b) 20KÅ UTM Symmetric inductor
(c) 40KÅ UTM Standard inductor (d) 40KÅ UTM Symmetric inductor
Document No.
Version
: T-018-LO-DR-001
: 2.8
Appendix A REVISION HISTORY

A.1 TSMC 0.18UM CMOS LOGIC/MS/RF AND 0.16UM
CMOS LOGIC/MS DESIGN RULE (CL018G/LV/LP,
CM018G, CR018G, CL016G, CM016G)
A.1.1 From Version 2.7 to Version 2.8
From Version 2.7 to Version 2.8
TS
Rule Sec. No. Section Title Revision Description

1.2 Integrated Design Rule Manuals Merge T-018-CR-DR-001
M
2.1.1 Front-End Features Add BJT offering in Table 2.1.1

2.1.3 MS/RF devices Features Add CM016G P-type HRI offering to align SPICE
C
2.3 Cross-Section Add UTM information

2.4.1 Logic Metallization Options Add VIAD and MD options for RDL
C
2.4.2 Mixed Signal & RF Metallization Options remove UTM 3 metal layers' option due to UTM
VI
on 6 NO /2
SPICE doesn't offer

2.5 User Guide 1. move from original sec.1.5
A
2. Add database unit (DBU) description

fid 65 LO 009
2.5.1 Logic Design Recommendations Add "Un-salicided poly resistor guidelines",

TE
move from section 1.5.2

en 12 G
3.1 Mask Information, Key Process Sequence, and Add MD, VIAD & CB/PM for flip chip options to
C /0
CAD Layers Information table3.1.1~3.1.10

tia 1 IES
3.3 Special Recognition CAD Layer Summary correct associated with rules, ESD description
H 1
and add dummy layers: ESD, DPDUMMY,

12
PLDUMMY, SBDDMY, RWDMY(drawing1),

lI
RPDUMMY, RPDUMMY(drawing1),
nf
RPDUMMY(drawing3), CTMDMY(drawing5),
VSSDMY, VDDDMY,
or
3.4 Device Truth Tables 1. correct table3.4.1~3.4.9 P+OD resistor vs.

NW legend
m
2. Add 3T model resistors

3.4.7 CM018G/CR018G 1.8/3.3V Add inductor, varactor, SBD and circuit under
at
MIM into device truth table

3.4.9 CM016G 1.8V/3.3V Add HRI P+ Poly resistor
io
3.5.7 CM018G/CR018G 1.8/3.3V Add inductor, varactor and SBD

IN
3.5.9 CM016G 1.8V/3.3V Add HRI P+ Poly resistor

4.2.1 Derived Geometries Correct definitions for NWROD and NWRSTI
C
4.2.2 Special Definition add sealring definition

.
4.4 Minimum Pitches Add 40K UTM pitch

NWR.R.3 4.5.2 NW resistor within OD Add
NT_N.I.4 4.5.3 Native Device (NT_N) Layout Rules revise wording
OD.S.1 4.5.4 Thin Oxide (OD) Layout Rules (Mask ID: 120) Revise description
4.5.5 Thick Oxide (OD2) Layout Rules (Mask ID: correct OD2.E.4/OD2.C.4 reference figure
132)
RES.2® 4.5.7 Poly Resistor and OD Resistor Guidelines and Add RF resistor Nsq
Rule
RES.9 4.5.7 Poly Resistor and OD Resistor Guidelines and Add
Rule
Rule
Document No.
Version
: T-018-LO-DR-001
: 2.8

Rule
NP.R.3 4.5.8 N+ S/D (NP) Layout Rules (Mask ID: 198) revise wording to except SBDDMY region
PP.O.1 4.5.9 P+ S/D (PP) Layout Rules (Mask ID: 197) revise wording to except SBDDMY region
PP.E.1 4.5.9 P+ S/D (PP) Layout Rules (Mask ID: 197) revise wording to except SBDDMY region
PP.R.3 4.5.9 P+ S/D (PP) Layout Rules (Mask ID: 197) revise wording to except SBDDMY region
RPO.C.3 4.5.10 Resist Protection Oxide (RPO) Layout Rules revise wording to except ESD region
(Mask ID: 155)
CO.W.1 4.5.11 Contact (CO) Layout Rules (Mask ID: 156) revise wording to except sealring region
CO.E.3 4.5.11 Contact (CO) Layout Rules (Mask ID: 156) revise wording to except SBDDMY region
VIAx.W.1 4.5.13 VIA1 to VIA4 (VIAx) Layout Rules (Mask ID: revise wording to except sealring region
178, 179, 173, 174)
TS
VIAx.S.2 4.5.13.1 C018 VIA Array Layout Rules Add

M

C

C

VI

on 6 NO /2
VIAn.W.1 4.5.15 Top VIA (VIAn) Layout Rule (Mask ID: 175) revise wording to except sealring region
A
Mn.E.1 4.5.16 Top Metal (Mn) Layout Rule (Mask ID: 186) Correct typo to align command file
fid 65 LO 009
LOGO.R.2 4.5.17 Product Labels and Logo Layout Rules Add

TE
4.5.18 Passivation (CB), & Polyimide (PM) & AP-MD Add AP-MD in title
en 12 G
Layout Rule (Mask ID: 107, & 009 & 309)

C /0
A.R.2, 3,5, 6 4.5.21 Antenna Effect Prevention (A) Layout Rules 1. revise description wording from "diode" to
"OD"
tia 1 IES
H 1
2. Correct OD area to "larger or equal to" from

12
"larger"
lI
4.5.22.3.1 Chip Corner Power Line and Dummy Pad Add dummy description
nf
4.5.22.3.1 Chip Corner Power Line and Dummy Pad Modify Figure.4.5.22.2~4.5.22.5
DNW.S.2® 4.6.1 Deep N-Well (DNW) Layout Rules (Mask ID: Add
or
119)
U
DNW.R.6 4.6.1 Deep N-Well (DNW) Layout Rules (Mask ID: Add
m
119)
DNW.E.1® 4.6.1 Deep N-Well (DNW) Layout Rules (Mask ID: revise wording to except SBDDMY region
at
119)
VTM_N.R.1 4.6.2 Medium Vt NMOS (VTM_N) Layout Rules Delete due to SPICE offers
io
(Mask ID: 118)

IN
VTM_P.R.1 4.6.3 Medium Vt PMOS (VTM_P) Layout Rules Delete due to SPICE offers
(Mask ID: 117)
C
4.6.5 Schottky Barrier Diode (SBD) Layout Rules Add SBD rules
.
4.6.6.1 Mx Layout Rules for Capacitor Bottom Metal Add CBM definition
CTM.W.4 4.6.6.2 Capacitor Top Metal (CTM) Layout Rules Add dummy CTM
(Mask ID: 182)
U
CTM.R.4® 4.6.6.2 Capacitor Top Metal (CTM) Layout Rules Revise wording for circuit under MIM application
(Mask ID: 182)
U
MIMVIA.R.2® 4.6.6.3 VIA Layout Rules for MIM Capacitor delete due to same as CTM.R.4
MIMVIA.S.1 4.6.6.3 VIA Layout Rules for MIM Capacitor define VIAn check method as on the same CTM
MIMVIA.S.2 4.6.6.3 VIA Layout Rules for MIM Capacitor define VIAn method as on the same MIM
4.6.6.3 VIA Layout Rules for MIM Capacitor remove CTMDMY in MIMVIA.R.3 &
MIMVIA.S.1/2 figures
4.6.6.4 MIM Capacitor PDK Guidelines add
4.6.7 Antenna Effect Prevention Layout Rules for Modify Figure.4.6.7.2 & 4.6.7.3
MIM Capacitor
4.6.7.2 MIM Structure Recognition Methodology Add
A.R.MIM.1 4.6.7.3 Antenna Effect Prevention Layout Rules define check ratio as to cumulative mode
Document No.
Version
: T-018-LO-DR-001
: 2.8

A.R.MIM.2 4.6.7.3 Antenna Effect Prevention Layout Rules define check ratio as to cumulative mode & CTM
node value
A.R.MIM.3 4.6.7.3 Antenna Effect Prevention Layout Rules define check as ratio to cumulative mode & CBM
node value
A.R.MIM.4 4.6.7.3 Antenna Effect Prevention Layout Rules define check ratio as to cumulative mode
A.R.MIM.5 4.6.7.3 Antenna Effect Prevention Layout Rules Add CBM connecting to OD through underneath
VIA is not allowed.
4.6.8.2 40KÅ UTM design rule Correct inductor figure
Chap.5 Layout Guidelines for Latch-Up and I/O ESD Correct typo
5.2.3 DRC methodology for Latch-up rules add
U
AN.R.34mg 6.2.3.2 BJT Add
U
AN.R.35m 6.3.2 Matching Rules and Guidelines Add
TS
U
AN.R.12mg 6.3.2 Matching Rules and Guidelines Revise description
U
AN.R.37mg 6.3.2 Matching Rules and Guidelines Add
U
AN.R.38mg 6.3.2 Matching Rules and Guidelines Add
M
U
AN.R.24mg 6.3.4 Noise Correct refer rule to DNW.R.6 from DRW.R.4
C
7.1 Metal/CO/Via Current Density delete not needed rating factor of Jmax
DNW.C.2 8.2.1 Non-shrinkable Layout Rules Delete
C
DNW.C.3 8.2.1 Non-shrinkable Layout Rules Delete

VI
CB.W.1 8.2.1.4 Non-shrinkable Layout Rules revise wording to except sealring region
on 6 NO /2
8.3 Design flow for Tape-out Add Legacy IP porting

A
Chap.9 Electrical Parameter Add SPICE reference summary table

fid 65 LO 009
TE
Rule No Mapping Table

en 12 G
Section Old rule no New rule no

C /0
U
ADP.1 ADP.1
U
tia 1 IES
ADP.2 ADP.2
H 1
ADP.S.2 ADP.S.2g
12
U
4.5.22.3.1 ADP.S.3 ADP.S.3g
lI
ADP.W.3 ADP.W.3g
nf
ADP.W.4 ADP.W.4g
U
ADP.R.6 ADP.R.6g
or
U
AM.R.1 AM.R.1g
4.5.22.3.2 U
AM.R.2 AM.R.2g
m
UTM20K.C.1 UTM20K.C.1®
4.6.7
UTM40K.C.1 UTM40K.C.1®
at
U U
AN.R.21mg AN.R.22mg
io
U U
AN.R.22mg AN.R.24mg
U U
AN.R.24mg AN.R.25mg
IN
U U
6.3.4.1 AN.R.25mg AN.R.26mg
U U
C
AN.R.26mg AN.R.27mg
U U
AN.R.27mg AN.R.28mg
.
U U
AN.R.28mg AN.R.29mg
U U
AN.R.29mg AN.R.30mg
U U
AN.R.30mg AN.R.31mg
6.3.4.2 U U
AN.R.31mg AN.R.32mg
U U
AN.R.32mg AN.R.33mg
U
4.6.6.2 CTM.R.3 CTM.R.3
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.1.2 From Version 2.6 to Version 2.7

Consolidate 8 0.18um logic, mixed-signal rule and
0.16um design rule documents.
Chap.2 Technology Overview Add chapter 2 “Technology Overview”
Chap.3 General Layout Information Add chapter 3 “General Layout Information”
4.6 Mixed Signal Layout Rules Copy and add section 4.6 “Mixed Signal Layout
and Guidelines Rules and Guidelines” from 0.18um mixed-signal
design rule.
Chap.5 Layout Guidelines for Latch- Separate ESD/LU section as chapter 5 and ESD
TS
Up and I/O ESD expert JHLeea provides the revised ESD

guidelines for all consolidated process.
M
Chap.6 Analog circuit layout rule, Add chapter 6 “Analog circuit layout rule,
recommendation & guideline recommendation & guideline”
C
Chap.7 Current Density (EM) Separate current density section as chapter 7 and
Specifications add UTM EM spec. (DC: Jmax, AC: Jav, Jrms,
C
Jpeak_ac)
VI
on 6 NO /2
Chap.8 0.16um Technology Add chapter 8 0.16um technology

(CL016G/ CM016G)
A
Chap.9 Electrical Parameter Follow advanced technologies to add SPICE data

fid 65 LO 009
into DRM
TE
Remove DNW rule for 1.5/2.5V LV logic process

en 12 G
based on Marketing’s comment.

C /0
NT_N.I.6 Remove native device rule in mixed signal section

due to duplicate with logic section 4.5.3. The extra
tia 1 IES
H 1
rule NT_N.I.6 in mixed signal can be covered by

12
NT_N.I.4 & NT_N.E.1.

lI
3.3 Special Recognition CAD Remove document no. T-018-MM-RP-008 & 009
nf
Layer Summary for varactor due to obsolescence. SPICE model

has cover it.
or
4.1 Layout Rule Convention Add guideline symbol “g”

4.5.7 Poly Resistor and OD Align guideline format with 4.6.4 and add RES.6
m
Resistor Guideline since this rule exist in picture, just no

recommendation description. Refine RES.3 for
at
clear definition of DMN2V & DMP2V.

VIAx.0 4.5.13 VIA1 to VIA4 (VIAx) Layout Change VIAx.0 & VIAx.C.1 to note since these are
io
VIAx.C.1 Rules not rules.

IN
VIAn.C.1 4.5.15 Top VIA (VIAn) Layout Rule Change VIAn.C.1 to note since these are not
rules.
C
4.5.17 Product Labels and Logo Copy CL013 LOGO rule to reduce process defect
.
Layout Rules from LOGO pattern. Reduce LOGO.S.1 from

10um to 3um since uniformity concern in Al
process is smaller than Cu process.
4.5.20 Seal-Ring Rule Add mixed signal layer into seal ring
ADP.C.2 4.5.22.3.1 Chip Corner Power Line and There are 2 ADP.C.2 rules and one is fully the
Dummy Pad same with ADP.C.1. Remove the duplicate one.
Besides, rearrange rule & guideline location.
The value 0.16 is correct for VIA4/VIA5 space due
to 0.16=0.23-(((0.36-0.26)/2)*SQRT(2))
ADP.S.4 4.5.22.3.1 Chip Corner Power Line and ADP.S.4 is same with ADP.S.1. Remove
Dummy Pad ADP.S.4.
AM.W.1 4.5.22.3.2 Metal Stress Relief – Metal Remove AM.W.1 rule per RA PFQR1/BLLina’s
Slot comment. (For EM portion, EM design rule can
cover all metal width. So, it can be removed if this
rule is only relative to EM.)
DNW.I.x 4.6.1 Deep N-Well (DNW) Layout Remove label H from DNW Fig4.6.1 due to no
Document No.
Version
: T-018-LO-DR-001
: 2.8

Rules such rule. Besides, rename DNW.I.5,6,7 to
DNW.R.3,4,5 (align rule no. with other DRM) and
move these rules together in the bottom of table.
VTM_N.I.x 4.6.2 Medium Vt NMOS (VTM_N) Rename VTM_N.I.x to VTM_N.R.x and move
Layout Rules (Mask ID: 118) these rules together in the bottom of table.
VTM_P.I.x 4.6.3 Medium Vt PMOS (VTM_P) Rename VTM_P.I.x to VTM_P.R.x and move
Layout Rules (Mask ID: 117) these rules together in the bottom of table.
4.6.4 HRI Poly Resistor Rule Remove the description, pictures & RES.1 for
non-salicided poly resistor (except HRI) due to
duplicate with section 4.5.7.
PO.W.1_HRI Change rule no. PO.W.1 to PO.W.1_HRI and

TS
RES.HRI.x. RES.x to RES.HRI.x.
RPO.O.1_HRI Change RPO.O.1 to RPO.O.1_HRI for HRI only

M
and revise label “I” to label “F” due to conflicting

with another label “I” in other RPO rules. Then
C
move this rule to section 4.6.4 HRI Poly Resistor

Rule
C
HRI.E.1
VI
on 6 NO /2
Revise “extension” to ”enclosure” for better rule

A
explanation in HRI.E.1.
fid 65 LO 009
RES.8
TE
Remove RES.8 due to duplicate with RES.7.HRI

MIM_Mx.W.1 4.6.5.1 Mx Layout Rules for Remove “For example, 36um x 36um Mx….” Due
en 12 G
Capacitor Bottom Metal to unneeded.

C /0
MIM_Mx.E.3 Move CTM.E.3 from CTM rule to MIM capacitor

tia 1 IES
H 1
(CTM.E.3) bottom metal rule and rename as MIM_Mx.E.3.

Remove CTMDMY & label “K” in figure since the
12
lI
rule of CTMDMY has been removed in previous

revision.
nf
2
A.R.MIM.5 4.6.6 Antenna Effect Prevention Add one antenna rule for new offering 2.0 fF/um
Layout Rules for MIM MIM capacitor.
or
Capacitor
4.6.7 Ultra Thick Metal (UTM) Add rule for new offering 40KÅ UTM.
m
Layout Rules
7.2 Poly Current Density Add poly current density per customer’s request
at
UBM.EN.1 8.2.1.5 Flip Chip Bump Rules Change rule value from 110 to 88 since
io
UBM.EN.1 rule value has been changed from 100

to 80 in T-000-CL-DR-002 V1.4.
IN
8.3 Design flow for Tape-out Refine design flow for easy reading
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Rule No Mapping Table

Section Old rule no New rule no
DNW.I.5 DNW.R.3
4.6.1 DNW.I.6 DNW.R.4
DNW.I.7 DNW.R.5
VTM_N.I.1 VTM_N.R.1
VTM_N.I.2 VTM_N.R.2
4.6.2 VTM_N.I.3 VTM_N.R.3
VTM_N.I.4 VTM_N.R.4
VTM_N.I.5 VTM_N.R.5
VTM_P.I.1 VTM_P.R.1
VTM_P.I.2 VTM_P.R.2
TS
4.6.3 VTM_P.I.3 VTM_P.R.3

VTM_P.I.4 VTM_P.R.4
VTM_P.I.5 VTM_P.R.5
M
PO.W.1 PO.W.1_HRI
C
RPO.O.1 RPO.O.1_HRI
RES.2 RES.HRI.1
C
RES.3 RES.HRI.2
VI
on 6 NO /2
4.6.4 RES.4 RES.HRI.3

RES.5 RES.HRI.4
A
RES.6 RES.HRI.5
fid 65 LO 009
RES.7 RES.HRI.6
TE
RES.8 RES.HRI.7
en 12 G
4.6.5.1 CTM.E.3 MIM_Mx.E.3

C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.2 CL018G 1.8V/3.3V (General Purpose)

Ver Eff Date Author Change Description
0.1 05-13-98 C. C. Tsai Original
0.2 09-15-98 C. C. Tsai Increase manufacturability and make design rule description more clear
1.0 10-09-98 C. C. Tsai Make design rule more compatible with Si data
1.1 11-05-98 C. C. Tsai Modify P5 make process margin safer
1. Make rule more clear and safer
1.2 03-23-99 C. C. Tsai (Change items refer to P.5)
2. Change Document Number from “TA-10A5-4001” to “T-018-LO-DR-001”
1. Guideline for migration to CL018LV and poly resistor, P3V, RPO.C.6, antenna ratio
for top metal, native device rule, metal fuse rule
TS
2.0 05-18-00 J. H. Hsu 2. Recommendation of NW resistor under STI, N2V/N3V/NP/PP.C.4, NP/PP.S.2,

passivatioin rules
M
3. Ph layer, OD.W.3, CO.S.2, CO.C.2, A.R.3, A.R.6, ESD guideline

1. Use guide update
C
2. Delete N2V/N3V/P2V/P3V
2.1 09-29-00 C. P. Yeh
3. Merge via rule/metal rule
C
4. ESD guideline update

VI
on 6 NO /2
1. Add redundancy guideline for embedded SRAM and modify user guide
2. Add description of planar capacitor Emb-SRAM in user guide
A
3. Delete metal fuse rule and alignment mark rule for there’s a separate document
fid 65 LO 009
2.2 05-30-01 S. C. Kuo 4. Modify NP.E.6/PP.E.6

TE

en 12 G

C /0
7. Add layout grid 0.004um at 1X

1. Add planar capacitor Emb-SRAM rules
tia 1 IES
H 1
2.3 11-02-01 S. J. Peng

2. Delete DSER guide Pait I item 17 (P.5), planar capacitor Emb-SRAM guidelines
12
1. Revise NW resistor rule NWR.0.1. NW resistor under STI add “NP to OD extension”
lI
rule.
nf
2. Merge section of “Redundancy Guideline for Embedded SRAM” and “Dummy

2.4 17-04-03 Alex Fahn Layout for Embedded SRAM” to “SRAM Guideline”
or
3. Keep no Polyimide (PM) over seal ring and assembly isolation. Seal ring rule add
some wordings.
m
4. Add the section of “Guidelines for NC (No-Connect) pin during ESD testing:
1. Revise wide metal and metal slot rules.
at
2. Revise NTN.W.1.
2.5 04-23-04 T. M. Fu
3. Move NTN section to the front.
io

IN
1. Add NP.R.3 and PP.R.3

n
2.6 05-16-06 R. G. Wu
2. Refine RPO.C.4, RPO.C.5, OD.W.3 and NT_N.I.3.
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
CHANGES BETWEEN VERSION 2.0 AND VERSION 2.1

Item. V2.0 V2.1 Remark
None 13. ESD implant TSMC should use ESD Dummy layer to
generate additional ESD mask by logic
operation.
User guide part
1 None 14. OD layout guide line Avoid long strip OD with narrow STI
I
polygon inside
None 15. Current density rule related Apply/calculate current density after metal
slots are added
User guide part Rule 4, NW Deleted Allow NW space 0.6 (NW.S.2)
2
IV space 0.86um
NW resistor in None Add descriptions Transfer Fig 1(a) to 7 rule items.
3
OD rule.
TS
0.3 0.22 Minimum clearance from RPO to related

4 NWR.C.2
OD
M
5 OD.W.3 > 0.42 ≥ 0.42 Make DRC consistent with rule

Maximum length Maximum length of salicide Description modification
C
of poly between poly on STI between two

6 PO.R.2 two contacts contacts or between one
C
contact and poly line end when

VI
on 6 NO /2
poly width ≤ 0.24um

A
Existed Deleted N2V/N3V/P2V/P3V masks are generated by

N2V/N3V/P2V/
fid 65 LO 009
7 logical operations as default to simplify the

P3V
TE
tape out process.

Via 1~4, 4 sets of Via x (x=1,2,3,4), 1 set of rule Merge Via 1~4 rule
en 12 G
8 Via rule rule with the

C /0
same dimensions
tia 1 IES
H 1
Metal 2~5, 4 sets Metal x (x=2,3,4,5), 1 set of Merge Metal 2~5 rule
9 Metal rule of rule with the rule
12
lI
same dimensions
Current density None It’s nominal AlCu thickness Description modification
10
nf
specification
Metal fuse rule 20 10 In consistence with CL025
or
11
Item M.
Latch-up A > 20 A > 15 Correct typing error
m
12
prevention Fig1
Dummy layouts None Add dummy layouts rule for Prevent proximity and loading effect. Detail
at
13 for embedded embedded SRAM guidelines and their GDS-II examples are
io
SRAM provided in SRAM cell layout documents

14 AM.S.3 None 35um Maximum slots space
IN
ESD guide line: None ESD3DMY (CAD layer 234) is TSMC should use ESD3DMY layer to
(on 5V High required. generate additional ESD mask by logic
C
15
Voltage operation.
.
Tolerant I/O)
None Poly spacing between inactive Better ESD performance once spacing
ESD poly
16 poly and active poly is 0.25um~0.45um.
spacing
0.25um~0.45um
None The minimum Lg in I/O buffer No approved data in tsmc for Lg > 0.5um.
for ESD implant is 0.4um
17 ESD Rule 9
ESD performance is not
guaranteed once Lg > 0.5 um.
ESD Existed Deleted Use ESD3DMY (CAD layer, 234) to
18 implantation (ESD (110)) generate additional ESD layer.
rule
Document No.
Version
: T-018-LO-DR-001
: 2.8

a. Clearly define wide-metal as being
>35×35um (both width and length).
Wide-metal
b. Add the slot density “AMS.DN.Mx” to
1 & - Refind
replace all slotting rules.
Slotting rules
c. Slotting dimension rules became
guidelines.
a. Add descriptions for SDI-dummy for
ESD rule
DRC purpose.
&
2 - Refind b. Add descriptions for some process-
Guidance
control-related items for DRC,
wording
including ESD.5x, 6 and 11.
TS
3 NT_N rule - Refind Relax NTN.W.1 from 0.86 to 0.74um.

M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
lI
nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.3 CL018G 1.8V/5V (General Purpose)

0.1 09-27-02 S. C. Yen Original
1.0 10-03-03 H. F. Lina Pass process qual thus revision to 1.0 & add title general purpose
2.0 04-28-04 T. M. Fu Refine ESD guidelines wording & correct typo.
2.1 R. G. Wu Refine the OD2 rule.
A.4 CL018LV 1.5V/3.3V (Low Voltage)

TS
0.1 04-09-99 Michael Wu Original

1. Change notice (P.3)
0.2 05-04-99 Michael Wu
2. Modify PO Pitch 0.18/0.25 (core), 0.35/0.25 (I/O)(P.24)
M
1. Add Native device rule

1.0 09-08-99 Jch Lin
C
2. Modify Four well rule into one well rule

1. Add Poly resistor, P3V, RPO.C., antenna ratio for Top metal, native device rule,
C
metal fuse rule.

VI
1.1 07-05-00 J. W. Weng 2. Delete Recommendation of NW resistor under STI. N2V/NP/PP.S.2, passivation
on 6 NO /2
rules.
A
3. Modify PH layer, OD.W.3, CO.S.2, CO.C.2, A.R.3, A.R.6, ESD guideline.

fid 65 LO 009
1. Add dummy layouts for embedded SRAM, ASM.S.3

TE
1.2 11-03-00 J. W. Weng 2. Delete N2V/N3V/ESD (110) rule.

3. Modify OD.2.3, PO.R.3 ESD guideline
en 12 G
1. Add redundancy guideline for embedded SRAM and modify user guide
C /0
2. Add description of planar capacitor Emb-SRAM in user guide.

tia 1 IES
H 1
3. Delete metal fuse rule and alignment mark rule for there’s a separate document.
1.3 05-30-01 S. C. Kuo 4. Modify NP.E.6/PP.E.6.
12
lI
5. Modify Seal-ring rule.

6. Modify figure of NP/PP.
nf
7. Add layout grid 0.005um at 1X.

1. Revise NW resistor rule NWR.O.1. NW resistor under STI add “NP to OD
or
extension” rule.
2. Merge section of “Redundancy Guideline for Embedded SRAM” and “Dummy
m
Layout for Embedded SRAM” to “SRAM Guideline”.

1.4 07-22-03 Alex Fahn
3. Keep on Polyimide(PM) over seal ring and assembly isolation. Seal ring rule add
at
some wordings.
io
4. Add the section of “Guidelines for NC (No-Connect) pin during ESD testing”
5. Remove old doc no ‘TA-10A5-4003’.
IN

1.5 R. G. Wu 2. Refine RPO.C.4, RPO.C.5, OD.W.3 and NT_N.I.2
C
3. Refine metal slot rules to align T-018-LO-DR-001

.
Document No.
Version
: T-018-LO-DR-001
: 2.8

None 13. ESD implant is required for TSMC should use ESD Dummy
5VT layer to generate additional ESD
mask by logic operation.
User guide
1 None 14. OD layout guide line Avoid long strip OD with narrow
part I
STI polygon inside
None 15. Current density rule related Current density calculation after
metal slots are added
User guide Rule 4, NW space 0.86um Delete Allow NW space 0.6 (NW.S.2)
2
part IV
3 NW.S.2 0.86 0.60 Consistent with C018G
NW resistor None Add descriptions Transfer Fig 1(a) to 7 rule items.
TS
4
in OD rule.
0.3 0.22 Minimum clearance from RPO to
5 NWR.C.2
M
related OD
6 OD.W.3 >0.42 >0.42 Make DRC consistent with rule
C
Maximum length of poly Maximum length of salicide poly Description modification

between two contacts on STI between two contacts or
C
7 PO.R.2 between one contact and poly

VI
on 6 NO /2
line end when poly width ≤

0.24um
A
Existed Delete N2V/P2V masks are generated by

fid 65 LO 009
8 N2V/P2V
above logical operations as default.
TE
Via 1~4, 4 sets of rule with Viax (x=1,2,3,4), 1 set of rule Merge Via 1~4 rule
en 12 G
9 Via rule
the same dimensions
C /0
Metal 2~5, 4 sets of rule Metal-x (x=2,3,4,5), 1 set of rule Merge Metal 2~5 rule
10 Metal rule
tia 1 IES
H 1
with the same dimensions

12
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nf
or
m
at
io
IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.5 CL018LV 1.5V/2.5V (Low Voltage)

1.0 07-05-00 J. W. Weng Original
1. Add dummy layouts for embedded SRAM, ASM.S.3
1.1 11-03-00 J. W. Weng 2. Delete N2V/N3V/ESD (110) rules
3. Modify OD.W.3, PO.R.2 ESD guideline
1. Add redundancy guideline for embedded SRAM and modify user
guide
2. Add description of planar capacitor Emb-SRAM in user guide
3. Delete metal fuse rule and alignment mark rule for there’s a separate
1.2 05-30-01 S. C. Kuo document
TS
4. Modify NP.E.6/PP.E.6
M
7. Add layout grid 0.005um at 1x

C
1. Revise NW resistor rule NWR.O.1. NW resistor under STI add “NP to

OD extension” rule.
C
2. Merge section of “Redundancy Guideline for Embedded SRAM” and

VI
“Dummy Layout for Embedded SRAM” to “SRAM Guideline”.

on 6 NO /2
1.3 07-14-03 Alex Fahn

3. Keep no Polyimide (PM) over seal ring and assembly isolation. Seal
A
ring rule add some wordings.

fid 65 LO 009
4. Add the section of “Guidelines for NC (No-Connect) pin during ESD

TE
testing”
en 12 G
1. Revise wide metal and metal slot rules.

2. Revise NTN.W.1.
C /0
2.0 04-23-04 T. M. Fu 3. Move DNW, NTN rule to the front.

tia 1 IES
H 1

5. Remove old doc no ‘TA-10A5-4008’
12
lI

2.1 R. G. Wu
2. Refine RPO.C.4, RPO.C.5, OD.W.3 and NT_N.I.3.
nf
or

m
Metal stress AMS.W.x AMS.1 Clearly define wide-metal as both sides > 35x35um.
relief portion AMS.S.x AMS.DN.Mx ≥1.5% The slotting density rule is to replace all slotting rules.
at
The slotting dimension rules become guidelines.

NTN.W.1 0.86 um 0.74 um Relax NTN.W.1 to align with mix-mode rule.
io
DNW portion; Move DNW, NTN rules to the front.

IN
NTN portion.
ESD portion Rewording for ESD Add descriptions of SDI_dummy for DRC purpose.
C
portion. Add description for some process-control-related items

.
for DRC check, including ESD.5x, ESD.6 and ESD.11.

Correct few typo.
Document No.
Version
: T-018-LO-DR-001
: 2.8

User guide None 13. ESD implant is TSMC should use ESD Dummy layer to generate
part I required for 3.3VT additional ESD mask by logic operation.
None 14. OD layout guide line Avoid long strip OD with narrow STI polygon
inside
None 15. Current density rule Current density calculation after metal slots are added
related
User guide Rule 4, NW Delete Allow NW space 0.6 (NW.S.2)
part IV space 0.86um
NW.S.2 0.86 0.60 Consistent with C018G
NW resistor in None Add descriptions Transfer Fig 1(a) to 7 rule items.
OD rule.
TS
NWR.C.2 0.3 0.22 Minimum clearance from RPO to related OD

OD.W.3 >0.42 >0.42 Make DRC consistent with rule
PO.R.2 Maximum Maximum length of Description modification
M
length of poly salicide poly on STI

C
between two between two contacts or

contacts between one contact and
C
poly line end when poly

VI
width ≤ 0.24um
on 6 NO /2
N2V/P2V Existed Delete N2V/P2V masks are generated by above logical

A
operations as default.
fid 65 LO 009
Via rule Via 1~4, 4 sets Viax (x=1,2,3,4), 1 set of Merge Via 1~4 rule
TE
of rule with the rule

en 12 G
same
dimensions
C /0
Metal rule Metal 2~5, 4 Metal-x (x=2,3,4,5), 1 set Merge Metal 2~5 rule
tia 1 IES
H 1
sets of rule with of rule

the same
12
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dimensions
Current density None It’s nominal AlCu Description modification
nf
specification thickness.
or
Metal fuse rule 20 10 In consistence with CL025

Item M.
m
Latch-up A>20 A>15 Correct typing error

prevention Fig1
at
Dummy layouts None Add dummy layouts rulePrevent proximity and loading effect. Detail guidelines
for embedded for embedded SRAM and their GDS-II examples are provided in SRAM cell
io
SRAM layout documents

IN
NT_N rule None Need 116 mask if 2.5V Description modification

n
NT_N device is used.

C
AM.S.3 None 35um Maximum slots space

ESD guide line: None ESDimp & ESD3 dummy TSMC should use ESD Dummy layer to generate
.
(on 3.3V High (CAD-layer 234) are additional ESD mask by logic operation.
Voltage required.
Tolerant I/O)
ESD poly None Poly spacing between Better ESD performance once spacing 0.25um~
spacing inactive poly and active 0.45um.
poly is 0.25um~0.45um
ESD Rule 9 None ESD performance is not No approved data by tsmc.
guaranteed once Lg > 0.4
um.
ESD Existed Deleted Use Dummy layer (gds layer, 234) to generate
implantation (ESD (110)) additional ESD layer.
rule
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.6 CL018LP 1.8V/3.3V (Low Power)

Original
1.0 11-16-00 J. H. Hsu
Remove old doc no ‘TA-10A5-4009’.
1.1 Refine the OD2 rule.
A.7 CL018G 1.8V/5V (Low Power)

TS
1.0 11-14-03 H. F. Lina Original. Remove old doc no ‘TA-10A5-4014’

1.1 09-28-06 R. G. Wu 1. Add three new rules: OD.C.2.1, OD.C.3.1, and OD.C.4.1.
2. Refine the OD2 rule.
M
C
C
VI
on 6 NO /2
A
fid 65 LO 009
TE
en 12 G
C /0
tia 1 IES
H 1
12
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nf
or
m
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IN
n
C
.
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.8 CL016G & CM016G

Note : The section No. belongs to the old document T-016-CL-DR-001.
Version 0.1 to 1.0
Stagger pad
2.1.3
1. non-shrinkable Pad Rule for Wire Bond Stagger pad non-shrinkable rules
rules
TS
Pad length of 55um pitch Single in-line pad is

2. CB.W.2 2.1.3 Pad Rule for Wire Bond
shrinkable
3. UBM.S.1 2.1.4 Flip Chip Bump Rule Change from 66um to 55um
M
4. ESD.5A Add these two rules for ESD performance

3.1.6 ESD non-shrinkable rule
C
5. ESD.5C improvement
Remove LP from this document due to the
6. “LP” - -
C
CL018LP will be delayed to 2006.

VI
on 6 NO /2
7. CBVIAT.R.1 2.1.3 Pad Rule for Wire Bond Delete this non-shrinkable rule
Version 1.0 to 1.1
A

fid 65 LO 009
TE

1. NT_N.W.2
en 12 G
3.1.2 General Logic Rules Add these two rules for native devices
C /0
2. NT_N.W.3
3. ESD.5A
tia 1 IES
Remove these two rules and use logical

H 1
3.2 ESD Guidelines

4. ESD.5C operation to enlarge this ESD dimension
12
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Key process Chapter Technology Add this chapter for the information of Reserved
5.
sequence 2 Information mask name and ID, and Key process sequence.
nf
Version 1.1 to 1.2

or

m
Title Add “CM016G” in title

1.1 Overview Add “CM016G…”
at
Related Design Rule

Add CM018 design rule document no. for
1.2 Manuals And
io
reference.
Documents
IN
1. Release CM016G
n
Specifications For
Add sec1.3.2 “Mixed-mode Design
1.3 CL016G And CM018
C
Specification”
Technology
.
Reserved mask name

Add Table 2.1.2 for CM016G process
2.1 and ID, and Key
sequence
process sequence
2. DNW.W.1 Add new non-shrinkable rule for CM016G
3. DNW.S.1 Mixed-mode non- Add new non-shrinkable rule for CM016G
3.1.3
4. DNW.C.2 shrinkable rule Add new non-shrinkable rule for CM016G
5. DNW.C.3 Add new non-shrinkable rule for CM016G
Pad Rule for Wire
6. CB.W.1 3.1.4 Align with T-000-CL-DR-002
Bond
Pad Rule for Wire
7. CB.S.1 3.1.4 Align with T-000-CL-DR-002
Bond
Design Flow for Tape-
8. Add Design Flow Chapter 4
out
Document No.
Version
: T-018-LO-DR-001
: 2.8
A.9 CM018G
Note : The section & page No. belong to the old document T-018-MM-DR-001.
Version 0.1 to 1.2
Rule no. Page Purpose Ver 0.1 Ver 0.2 Ver 1.0 Ver 1.1 Ver 1.2
User guide
Item 8 5 Top view of 2VN high resistor Top view Delete
Pitches 10 DNW pitch 8.0µm
10 M6T pitch 4.00µm 3.00µm
DNW.I..3 14 1.5µm Modify Modify
TS
DNW.W.1 5.0µm
DNW.E.1 1.5µm
M
DNW.C.1 3.5µm
DNW.C.2 N+_NW clearance in DNW 0.5um
C
DNW.C.3 N+_NW clearance in DNW 0.5um

DNW.C.4 N+_NW clearance outside DNW NA 3.0um
C
NT_N.PO. 17 Re-name NT_N.E.2 NT_N.PO.1

VI
on 6 NO /2
1 NA 0.26um
NT_N.I.6 0.86um 0.74um
A
NT_N.W.1
fid 65 LO 009
RPO.C.1a 21 0.3µm
TE
RPO.O.1 Modify
en 12 G
CTM.S.4 26 Via rule on CTM for better Q NA 2.00µm

C /0
CTM.S.4a value 1%
tia 1 IES
CTM.S.5 Min. density of Via on CTM NA 4.00µm

H 1
CTM.S.6 Via rule on CBM for better Q NA 0.8um

12
CTM.R.3 value NA 2.00µm

lI
CTM.I.1 Min. space between two CBM NA 30µm

nf
CTM.I.2 Dummy layer rule NA 35µm

CTM.I.3 Maximum width of CTM NA not allowed
or
CTM.I.4 Maximum width of CBM NA not allowed

2
CTM.A.1 ViaN and metal routing under 0.202 um
m
CTM Device under CTM region

Minimum area of CTM
at
M6T.S.1 29 Minimum space between two 2.00µm 1.5µm

M6T.S.2 M6T regions 10µm 15µm Modify
io
M6T.W.1 Minimum width of M6T 2.00µm 1.5µm

IN
2 2
n
M6T.A.1 Minimum area of M6T 4.00µm 2.25µm

M6T.C.1 Min. clearance of inductor to M6T 50µm
C
M6T.E.3 Min. extension of INDDMY/M6T 50µm

.
M6T.I.1
M6T.I.2
VTM_N.I.5 22 NA 0.26um
VTM_P.I.5 23 NA 0.26um
HRI.O.1 24 Deleted
HRI.E.1
HRI.E.2
HRI.C.5
HRI.R.2
Document No.
Version
: T-018-LO-DR-001
: 2.8
Version 1.2 to 1.3

Rule no. Page Purpose Ver 1.2 Ver. 1.3
User guide 4 Added description N/A “TSMC PDK” used in this document should
for “TSMC PDK” refer to document No. “T-018-MM-SP-001-K1”
for layout guideline.
DNW.I..1 13 Clear wording It is necessary that a DNW It is necessary that a DNW surrounded or
surrounded by NW. covered by NW.
DNW.I.2 13 Allowed 3.3V PMOS Delete
in DNW.
DNW.I.3 13 Delete redundant Delete
rule
NT_N rule 16 Error correcting NT_N … Rule (124) NT_N … Rule.
PO.W.1 17 Changed minimum 2.0 1.0
TS
resistor width
130 rule 17 Changed the W>=2.0, Nsq>=5 W>=1.0, Nsq>=2
note-2 recommended width
M
and square number

C
HRI.C.2 23 Clear wording Minimum clearance from an HRI Minimum clearance from an HRI region to a
region to an un related PP PP region.
C
region.
VI
on 6 NO /2
CTM.I.1 25 Clear wording Maximum dimension of a … Maximum dimension (each sides) of a …

CTM.I.2 25 Clear wording Maximum dimension of a … Maximum dimension (both sides) of a …
A
CTM.I.3 25 Allowed metal No ViaN and metal layers under No ViaN under CTM region are allowed.
fid 65 LO 009
routing under CTM CTM region are allowed. Suggestion :

TE
Suggestion : Metal routing under MIM is allowed.

en 12 G
Dummy pattern of metal for… Nonetheless, to place routing metal under

MIM, it is strongly recommended to add a
C /0
high frequency signal isolation metal layer

tia 1 IES
H 1
under CBM. Customer should refer to TSMC

PDK for better model accuracy.
12
lI
M6T.C.1 28 Added wording to Minimum clearance from one Minimum clearance from one M6T used
waive NT_N.I.3 and M6T used as inductor device as inductor device (dummy layer
nf
NT_N.E.2 two rule (dummy layer "INDDMY" is "INDDMY" is needed to define the
inductor region) to other M6T region.
or
violations in needed to define the inductor

INDDMY region. region) to other M6T region. Three types of inductor layout are offered.
When these layouts are implemented, two
m
rule violations: NT_N.I.4 and NT_N.E.1 in

INDDMY region will be waived.
at
M6T.I.1 28 Clear wording No Via and metal layers inside No Via and metal layers inside INDDMY
io
INDDMY region are allowed region are allowed except underpass

except underpass via and metal vias, metal interconnect and the
IN
interconnect of inductor. substrate pick up node of inductor.

M6T note-1 28 Added Note-1 for N/A Note-1: For inductor devices offered in
C
NT_N layer TSMC’s SPICE model, a native substrate

.
description. doping layer is created under the

inductor coil to minimize eddy currents.
This layer is specified by use of an NT_N
(CAD#129) implant blocking layer of the
exact shape as the INDDMY layer. This
NT_N drawn layer adds no process cost
and no extra mask and is included in
TSMC PDK and its associated sample
layout document. For those who prefer to
draw inductors by themselves, designers
have the option to draw a NT_N layer
that exactly matches the INDDMY dummy
marker layer geometry.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Version 1.3 to 1.4

1. 1.1 Overview Refine wording
2 1.2 Reference Documentation Add table
3 1.3.1 Design recommendation Modify the resistor width from 2.0um to 1.0um
to align SPICE offering
3.1 1.3.2 Guideline for Half Technologies Delete old table and add new document
information for C016 mixed mode design
4 2.1 Semiconductor process features Add wording
for MS/RF devices
5 2.2 Metallization Option Refine from old table in ver 1.3 in Chapter 1.
6 3.1 Reserved Mask Names and Ids. Refine from old table in ver 1.3 in Chapter 2 and
Key Process Sequence, and CAD Section 1.1.
TS
layers
7 3.2 Special Layer Summary Refine from old table in ver 1.3 in Section 1.5
M
8 3.3 Device truth table New added table

9 4.1 Layout Rule Conventions Add wording
C
10 4.2.1 Derived Geometries New added table

11 4.2.2 Special Definition Refine from old table in ver 1.3 in Section 1.2.
C
12 DNW.I.1 4.5.1 DNW rules Change the rule to a recommendation rule

VI
on 6 NO /2
13 DNW.C.2 4.5.1 DNW rules Remove the rule

14 DNW.C.3 4.5.1 DNW rules Remove the rule
A
15 DNW.I.5 4.5.1 DNW rules Change the rule to a recommendation rule

fid 65 LO 009
TE
16 DNW.E.1 4.5.1 DNW rules Change the rule to a recommendation rule

17 DNW.E.2 4.5.1 DNW rules Add new rule
en 12 G
18 NT_N.I.4 4.5.2 NT_N rules Modify the rule from P+ region to P+ GATE
C /0
19 NT_N.I.5 4.5.2 NT_N rules Modify the wording from Po1 to PO

tia 1 IES
H 1
NT_N.W.2
NT_N.W.3
12
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NT_N.PO.1
20 4.5.5 Poly Resistor Rule Modify the Nsq to align with the SPICE
nf
21 4.5.5 Poly Resistor Rule Add the recommendation for RLPPDMY

layer
or
22 RPO.C.1.a 4.5.7 RPO Rule Delete the redundant rule as in T-018-LO-DR-

001
m
23 VTM_N.W.2 4.5.3 VTM_N rules Modify the wording from Po1 to PO

at
VTM_N.W.3
24 VTM_N.I.3 4.5.3 VTM_N rules Modify the rule from P+ region to P+ GATE
io
25 VTM_P.W.2 4.5.4 VTM_P rules Modify the wording from Po1 to PO

IN
26 VTM_P.I.3 4.5.4 VTM_N rules Modify the rule from N+ region to N+ GATE
n
27 CTM.I.4 4.5.8 CTM rules Change the rule to a recommendation rule

C
28 4.5.8 CTM rules Add layer definition of CTM…etc.

29 CTM.S.5 4.5.8 CTM rules Modify the rule wording
.
CTM.R.4
Document No.
Version
: T-018-LO-DR-001
: 2.8
Version 1.4 to 1.5

1. 1.1 Overview Refine wording
2 1.2 Reference Documentation Refine table:
a) Add C016 DRM document number.
b) Add bond pad DRC document number
3 1.3.1 Design recommendation Refine wording
4 1.3.2 Guideline for Half Refine wording
Technologies
5 2.1 Semiconductor process 1. Refine wording
features for MS/RF devices 2. Replace “M6T” with “UTM” for the ultra thick metal
6 2.2 Metallization Option Refine wording by replacing VIAtop with VIAn
7 3.1 Reserved Mask Names and Refine wording
TS
Ids. Key Process Sequence,

and CAD layers
8 3.2 Special Layer Summary Refine wording
M
9 4.1 Layout Rule Conventions Add “U” and “®”option for the rule numbers.
C
10 4.2.1 Derived Geometries Add new terms “PW” and “Dummy CTM”
11 4.2.2 Special Definition Add new definitions used for later sections and delete un-
C
used definitions like Cold N_Well …etc.

VI
on 6 NO /2
12 4.2.3 Definition of Layout Add new definitions like CUT, INTERACT,

Geometrical Terminology OUTSIDE …etc.
A
13 DNW.I.4 4.5.1 DNW rules Delete this rule.

fid 65 LO 009
14 DNW.I.6 4.5.1 DNW rules Refine wording.

TE
15 DNW.I.7 4.5.1 DNW rules Refine wording from “NW layer connected to DNW” to
en 12 G
“{NW interact DNW}”

C /0
16 DNW.S.1 4.5.1 DNW rules Refine wording.

tia 1 IES
17 DNW.O.1 4.5.1 DNW rules Refine wording.

H 1
18 DNW.C.4 4.5.1 DNW rules Refine wording.

12
lI
18.1 DNW.E.2 4.5.1 DNW rules Refine wording

19 DNW.I.1 4.5.1 DNW rules Delete this recommendation and merge with DNW.E.1®.
nf
20 DNW.I.5® 4.5.1 DNW rules Refine wording.

21 DNW.E.1® 4.5.1 DNW rules Refine wording and merge from DNW.I.1.
or
22 NT_N.I.1 4.5.2 NT_N rules Refine rule to align DRC definition.

23 NT_N.I.2 4.5.2 NT_N rules Delete this rule and merge to NT_N.C.2.
m
24 NT_N.I.3 4.5.2 NT_N rules Refine wording.

at

io

IN
28 NT_N.S.1 4.5.2 NT_N rules Delete the wording “for same potential”.
n
29 NT_N.C.2 4.5.2 NT_N rules Merge from NT_N.I.2.

C
30 NT_N.PO.1 4.5.2 NT_N rules Refine wording.

.
31 VTM_N.I.1 4.5.3 VTM_N rules Refine rule to align DRC definition.

32 VTM_N.I.2 4.5.3 VTM_N rules Refine rule to align DRC definition.
33 VTM_N.I.3 4.5.3 VTM_N rules Refine wording.
36 VTM_N.W.2 4.5.3 VTM_N rules Refine wording.
37 VTM_N.W.3 4.5.3 VTM_N rules Refine wording.
38 VTM_N.E.1 4.5.3 VTM_N rules Refine wording.
39 VTM_N.C.1 4.5.3 VTM_N rules Refine wording.
40 VTM_N.C.2 4.5.3 VTM_N rules Refine wording and merge the NW part from VTM_N.I.2.
41 VTM_P.I.1 4.5.4 VTM_P rules Refine rule to align DRC definition.
42 VTM_P.I.2 4.5.4 VTM_P rules Refine rule to align DRC definition.
43 VTM_P.I.3 4.5.4 VTM_P rules Refine wording.
Document No.
Version
: T-018-LO-DR-001
: 2.8

46 VTM_P.W.2 4.5.4 VTM_P rules Refine wording.
47 VTM_P.E.1 4.5.4 VTM_P rules Refine wording.
48 VTM_P.C.1 4.5.4 VTM_P rules Refine wording.
49 VTM_P.C.2 4.5.4 VTM_P rules Refine wording and merge the NW part from VTM_P.I.2.
50 4.5.5 PO resistor rule Refine wording on RES.1®, RES.2® and RES.4®
51 HRI.R.1 4.5.5.1 HRI rules Refine wording.
52 HRI.R.2 4.5.5.1 HRI rules Refine wording.
52.1 RES.8® 4.5.5.1 HRI rules Copy rules from Section 4.5.5
53 4.5.7 MIM Capacitor Layout Rules The old rules are split into 3 sub-sections with new rule
numbers.
54 MIM_Mx.W.1 4.5.7.1 Mx Layout Rules for Change rule number from CTM.I.2 and refine wording.
Capacitor Bottom Metal
55 MIM_Mx.S.1 4.5.7.1 Mx Layout Rules for Change rule number from CTM.S.6 and refine wording.
TS

56 MIM_Mx.S.2 4.5.7.1 Mx Layout Rules for Change rule number from CTM.S.3 and refine wording.
M

57 CTM.W.1 4.5.7.2 CTM Layout Rules Refine wording.
C
57.1 CTM.W.2 4.5.7.2 CTM Layout Rules Refine wording.

58 CTM.W.3 4.5.7.2 CTM Layout Rules Delete Rule
C
59 CTM.S.1 4.5.7.2 CTM Layout Rules Refine wording.

VI
on 6 NO /2
60 CTM.S.2 4.5.7.2 CTM Layout Rules Refine wording.

61 CTM.R.2 4.5.7.2 CTM Layout Rules Refine wording.
A
62 CTM.R.3 4.5.7.2 CTM Layout Rules Refine wording and relax rule.
fid 65 LO 009
TE
63 CTM.W.4 4.5.7.2 CTM Layout Rules Change rule number from CTM.I.1 and refine wording.
64 CTM.R.5 4.5.7.2 CTM Layout Rules New rule
en 12 G
65 CTM.R.4® 4.5.7.2 CTM Layout Rules Change rule number from CTM.I.4
C /0
66 CTM.E.3 4.5.7.2 CTM Layout Rules Refine wording.

tia 1 IES
H 1
67 CTM.R.1 4.5.7.2 CTM Layout Rules Refine wording to align with DRC.
68 MIMVIA.E.1 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.E.1
12
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69 MIMVIA.E.2 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.E.2 and refine wording.
70 MIMVIA.C.1 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.C.1
nf
71 MIMVIA.S.1 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.4
or
72 MIMVIA.S.2 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.5
73 MIMVIA.R.1 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.4a and refine wording
m
74 MIMVIA.R.3 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.I.3 and refine wording
75 MIMVIA.S.1® 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.5 and refine wording
at
76 MIMVIA.S.2® 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.5 and refine wording
76.1 MIMVIA.R.1® 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.S.5 and refine wording
io
77 MIMVIA.R.2® 4.5.7.3 VIA Layout Rules for MIM Change rule number from CTM.I.3 and refine wording
IN
78 4.5.8.1 Antenna Effect Prevention Add description for overview.

Layout Rules for MIM
C
Capacitor
.
79 A.R.MIM.1 4.5.8.2 Antenna Effect Prevention New rule

Layout Rules
Layout Rules
Layout Rules
Layout Rules
83 4.5.9 UTM rules 1. Replace “M6T” with “UTM” for the ultra thick metal
2. Replace “VIAn” with “VIA5” for the top VIA connected
to UTM.
84 UTM.S.2 4.5.9 UTM rules Refine wording.
85 UTM.R.1 4.5.9 UTM rules Refine wording.
86 UTM.C.1 4.5.9 UTM rules Refine wording.
87 UTM.I.1 4.5.9 UTM rules Refine wording.
Document No.
Version
: T-018-LO-DR-001
: 2.8
Rule Mapping Table (Version 1.4 to 1.5)

Ver. 1.4 Ver. 1.5
MIM Rules
CTM.I.1 CTM.W.4
CTM.I.4 CTM.R.4®
CTM.S.3 MIM_Mx.S.2
CTM.S.6 MIM_Mx.S.1
CTM.I.2 MIM_Mx.W.1
CTM.E.1 MIMVIA.E.1
TS
CTM.E.2 MIMVIA.E.2
CTM.C.1 MIMVIA.C.1
M
CTM.S.4 MIMVIA.S.1
C
CTM.S.4a MIMVIA.R.1
C
CTM.S.5 MIMVIA.S.2
VI
on 6 NO /2
CTM.S.5 MIMVIA.R.1®
A
CTM.S.5 MIMVIA.S.1®
fid 65 LO 009
CTM.S.5 MIMVIA.S.2®
TE
CTM.I.3 MIMVIA.R.3
en 12 G
C /0
CTM.I.3 MIMVIA.R.2®
tia 1 IES
H 1
UTM Rules
12
M6T.W.1 UTM.W.1
lI
M6T.S.1 UTM.S.1
nf
M6T.E.1 UTM.E.1
or
M6T.E.2 UTM.E.2
m
M6T.S.2 UTM.S.2
at
M6T.A.1 UTM.A.1
M6T.R.1 UTM.R.1
io
M6T.C.1 UTM.C.1
IN
M6T.E.3 UTM.E.3
C
M6T.I.1 UTM.I.1
.
M6T.I.2 UTM.I.2

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SECURITY B

tsmc Taiwan Semiconductor Manufacturing Co., LTD

Ver Eff_Date ECN No. Author Change Description

2.7 05-06-08 E070200817023 Y. M.Chenj See Appendix A

Reviser : S. L. Liu (PDS) Title

Revising Line Manager : Y. C. Harn TSMC 0.18UM CMOS

Ver Eff_Date ECN No. Author Change Description

2.3 11-02-01 F012402 S. J. Peng 1. Add planar capacitor Emb-SRAM rules

2. Delete DSER guide Pait I item 17 (P.5), Planar

2. Merge section of “Redundancy Guideline for

Embedded SRAM” and “Dummy Layout for

3. Keep no Polyimide(PM) over seal ring and

assembly isolation . Seal ring rule add some

4. Add the section of “Guidelines for NC (No-Connect)

pin during ESD testing”

3. Move NTN section to the front.

TSMC 0.18UM CMOS

Ver Eff_Date ECN No. Author Change Description

resistor, P3V, RPO.C.6, antenna ratio for top metal,

2.Recommendation of NW resitor under STI,

N2V/N3V/NP/PP.C.4, NP/PP.S.2, passivatioin rules

2.1 09-29-00 F003714 C. P. Yeh 1.Use guide update

3.Merge via rule/metal rule

4.ESD guideline update

TSMC 0.18UM CMOS

TSMC 0.18UM CMOS LOGIC/MS/RF AND 0.16UM CMOS

LOGIC/MS DESIGN RULE (CL018G/LV/LP, CM018G,

CR018G, CL016G, CM016G)

2.1.2 Back-End Features ............................................................................................................................ 17

2.2 POWER SUPPLY OF DEVICES ...................................................................................................................... 19

2.4 METALLIZATION OPTIONS ........................................................................................................................... 21

2.4.2 Mixed Signal & RF Metallization Options .......................................................................................... 22

2.5 USER GUIDE .............................................................................................................................................. 24

2.5.1 Logic Design Recommendations ....................................................................................................... 24

2.5.2 Mixed Signal Design Recommendations........................................................................................... 26

3. GENERAL LAYOUT INFORMATION ........................................................................................................... 27

3.2 MASK REQUIREMENTS FOR DEVICE OPTIONS.............................................................................................. 38

3.3 SPECIAL RECOGNITION CAD LAYER SUMMARY ........................................................................................... 39

3.4.1 CL018G 1.8V/3.3V............................................................................................................................. 42

3.4.3 CL018LV 1.5V/2.5V ........................................................................................................................... 44

3.4.4 CL018LV 1.5V/3.3V ........................................................................................................................... 45

3.4.6 CL018LP 1.8V/5V .............................................................................................................................. 47

3.4.8 CL016G 1.8V/3.3V............................................................................................................................. 50

3.5 DEVICE LIST & SPEC .................................................................................................................................. 51

3.5.1 CL018G 1.8V/3.3V............................................................................................................................. 51

3.5.3 CL018LV 1.5V/2.5V ........................................................................................................................... 53

3.5.4 CL018LV 1.5V/3.3V ........................................................................................................................... 54

4.5 LOGIC LAYOUT RULES AND GUIDELINES...................................................................................................... 64

4.5.13.2 C016 VIA Array Layout Rules....................................................................................................... 97

4.5.17 Product Labels and Logo Layout Rules......................................................................................... 105

4.5.20 Seal-Ring Rule............................................................................................................................... 107

4.5.21 Antenna Effect Prevention (A) Layout Rules ................................................................................. 109

4.5.23 SRAM Guideline ............................................................................................................................ 121

4.5.24 Planar Capacitor EMB-SRAM Rules ............................................................................................. 122

4.6.4 HRI Poly Resistor Rule .................................................................................................................... 127

4.6.6 MIM Capacitor Layout Rules ........................................................................................................... 135

5. LAYOUT GUIDELINES FOR LATCH-UP AND I/O ESD ............................................................................ 150

5.1.1 General Guideline for ESD Protection ............................................................................................. 151

8.1 SPECIFICATIONS FOR CL016G AND CM016G TECHNOLOGY .................................................................... 189

8.1.1 General Design Specifications......................................................................................................... 189

8.2.1 Non-shrinkable Layout Rules........................................................................................................... 190

8.2.3 Current Density (EM) Specifications................................................................................................ 192

8.2.4 Antenna Effect Prevention Layout Rules ......................................................................................... 192