Timers/Counters in 8051

8051 has two 16-bit counter Timer-0 (T0) and Timer-1 (T1). For read write operation
it is accessed as two 8-bit registers TL0/TL1 (lower byte of the timer) and TH0/TH1
(upper byte of the counter. It may be used as a
• Timer : an interval timer
o measure time between two events or generate a delay
o Count the internal clock
• Counter : as an event counter
o Count number of external events
Counts external clock in T0 (P3.4) or T1 (P3.5) that are derived from the
events.

𝐷15 𝐷14 𝐷13 𝐷12 𝐷11 𝐷10 𝐷9 𝐷8 𝐷7 𝐷6 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0

TH0 TL0
T0

𝐷15 𝐷14 𝐷13 𝐷12 𝐷11 𝐷10 𝐷9 𝐷8 𝐷7 𝐷6 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0

TH1 TL1
T1

A delay is generated by counting clock pulse of known time period. As

the internal clock frequency is most accurate and stable, timers count internal
clock. In 8051, a timer counts the machine cycle consists of 12 internal clock
cycles. The event counting is basically external. An external event is converted
to clock pulse and fed to processor. So, a counter counts external clock pulse
generated by events. So, a timer always counts whether it is used to generate
delay, as interval timer or event counter. The only difference is the clock source.
Timers in 8051 are up Counter.

Timers in 8051
• 8051 has two programmable 16-bit timers: T1 and T0.
o 8052 has three 16-bit timers: T2, T1 and T0.
• The upper byte of T1 is called TH1 and Lower byte is called TL1.
• Similarly, T0 consists of TH0 and TL0.
• In general the upper byte and lower byte of timers are denoted as THx and
TLx respectively Where x=0 or 1.
• A 16-bit timer is always accessed as two 8-bit special function register.
o Write or read to THx or TLx.
• Operates in four different mode: Mode0, Mode-1, Mode-2 and Mode-3,
• The timers can be programmed independently in any mode and may operate
as a timer or a counter.
Special Function Register, Timers
• Timer0 (T0)
o TL0 ➔ Address 8AH
o TH0 ➔ Address 8CH

• Timer 1 (T1)
o TL1 ➔ Address 8BH
o TH1 ➔ Address 8DH
Other Special Function Registers associated
Other special function registers associated with timers are
1. Timer Mode register (TMOD)
2. Timer Control register (TCON)
Pin associated with Timers
• P 3.4 (pin 14) ➔ T0, External clock input to event counter, Timer 0
• P 3.5 (pin 15) ➔ T1, External clock input to event counter, Timer 1
• P 3.2 (pin 12) ➔ ̅̅̅̅̅̅̅
𝐼𝑁𝑇0, Control (RUN/STOP) Timer0 when GATE=1
• P 3.3 (pin 13) ➔ ̅̅̅̅̅̅̅
𝐼𝑁𝑇1, Control (RUN/STOP) Timer1 when GATE=1

TMOD: Timer Mode SFR

• An 8-bit register.
• Only Byte addressable.
• Used to
a. Configure as a counter or timer.
b. Set Mode of operation: Mode-0, Mode-1, Mode-2 or Mode-3
c. Enable or disable hardware control of timer
MSB TMOD Register LSB
𝐷7 𝐷6 𝐷5 𝐷4 𝐷3 𝐷2 𝐷1 𝐷0

GATE1 ̅̅̅̅
C/T1 M1 M0 GATE0 ̅̅̅̅
C/T0 M1 M0

TIMER1 TIMER0

Name Explanation of Function

1: Enable hardware control to run or stop timer-x.
GATEx
0: Hardware control disabled.

̅̅̅ 1: Timer-x operates as a counter.

C/Tx
0: Timer-x operates as interval a timer.

M1, M0 Select Mode of operation

Where, x= ‘0’ or ‘1’
M0 & M1: Timer Modes
M1 M0 Timer Mode
0 0 MODE-0

0 1 MODE-1

1 0 MODE-2

1 1 MODE-3

TCON: Timer Control SFR

• TCON is a bit-addressable 8-bit register.
• It is both Byte addressable and bit addressable
• High order 4-bit is used for timer and low order 4-bit is used for external
interrupts.
Format
TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Timer 1 Timer 0 Interrupt

‘Timer1’ overflow flag.

TF1
TF1=1; when Timer-1 overflows.
‘Timer1’ RUN control bit.
TR1 1 : RUN timer-1
0: Stop timer-1
‘Timer0’ overflow flag.
TF0
TF0=1 when Timer-0 overflows.
‘Timer0’ RUN control bit.
TR0 1 : RUN timer-0
0: Stop timer-0
‘External Interrupt 1’ edge flag.
IE1
When edge sensitivity is selected, it stores the edge information
‘External Interrupt 1’ triggering signal type.
IT1 0: LEVEL Triggering (LOW level).
1: Edge triggering (falling edge).

‘External Interrupt 0’ edge flag

IE0
When edge sensitivity is selected, it stores the edge information
‘External Interrupt 0’ triggering signal type
IT0 0: LEVEL Triggering (LOW level)
1: Edge triggering (falling edge)
Operations as Timer
• Always operates as up counter.
• Counts the M/C consist of 12 clock cycle. So, internal clock is divided by
12 and fed to the counter.
• The timer is triggered by –ve edge (falling edge) of the clock.
• When the count goes from FFH to 00H, count overflows and output goes
high, TFx=1.
• The high output set the timer flag (𝑇𝐹𝑥 = 1).
• 𝑇𝐹𝑥 = 1, generates the timer interrupt if timer interrupt is enabled.
𝑓𝑜𝑠𝑐⁄
Clock 12
÷12 TIMER 𝑇𝐹𝑥
Oscillator
(Counts UP)

One time period is “O/P=1” on overflow

equal to the duration of (Count rolls from
one Machine Cycle. maximum count to
zero.)

To use as timer:
1. Configure interrupt and mode of operation.
2. The timer flag bit is cleared TFx=0.
3. Load THx and TLx with initial count/preset value.
4. Timer RUN bit is set i.e.;TRx=1 to run the timer.
5. If interrupt is disabled, monitor TFx.
6. RUN the service routine when TFx=1.
7. If timer interrupt has been enabled, service routine will run on interrupt
service.
8. In the service routine:
a. Clear TR0 to stop timer
b. To the task if any
c. Clear Timer Flag, TFx
d. Set timer run bit, TRx
e. Go to step 5 to repeat.
Operations as Counter
• Counts the External Pulses at pin Tx (T1 or T0).
o The pulses represent events. For example
o Counts the number of external events occurred
▪ No of people entering a hall
▪ No of pills filled in to a bottle
▪ Counts number of rotations => Speedo meter etc.
• External events are converted to electrical pulses and fed as external
clock through a pin.
 o P3.4 (Pin14) ➔ T0 (external clock input for Counter0)
o P3.5 (Pin15) ➔ T1 (external clock input for Counter1)
• ISR can read the count value in a predetermined interval, that can be used
by software.
Modes of Operations
Timers/Counters operates in 4 different modes. The mode is selected by
programming TMOD register.
Timers are programmed independently to operate in any mode.
MODE0
• Both timers can operate in this mode as a 13-bit timer or counter.
• MODE0 is not generally used in 8051. Instead Mode1 is preferred that has
similar operations with a higher maximum count. MODE0 is provided for
backward compatibility with previous Micro-controller 8048.
o That means software written for timers in 8048 will also run on 8051.
• Maximum counting is 213=8192 i.e. FF20H (counts from 0000H to FF1FH).
• Count is maximum when Pre-set Value (Initial Count) loaded is 0000H.
• C/Tx
̅̅̅ bit is used to select the operation as counter or Timer.
• 5 LSB-bits of TLx and all 8 bits of THx is used as 13-bit counter.
C13 C12 C11 C10 C9 C7 C6 C5 X X X C4 C3 C2 C1 C0
THx TLx
• C0, C1…… C13 are counting bits of timer. THx is incremented when TLx
is incremented to 00H.
• Timer overflows when THx goes from FFH to 00H and TFx is set (TFx=1).
• Assuming GATE=0, timer starts running when TRx=1.
• TFx is monitored to detect end of counting if interrupt has not been
enabled.
• Once the timer overflows, the Pre-set Value has to be loaded again to
timer.
• The operation is easily understood from the diagram given below.

Fig: Operation of Timer0 in Mode0. Operation of Timer1 is similar.

Explanation of the circuit

 • The clock source is connected to the timer through a 2 × 1 MUX (shown as
switch in figure) and a tristate buffer.
• 𝐶⁄ selects the input of MUX that select the clock source.
𝑇̅
• The clock input triggers the timer/counter and it counts up. When it overflows
(goes to zero from maximum count) Timer Flag bit (TF0) is set, that generates
the Timer0 interrupt if enabled.
• When 𝐶⁄ ̅ =0, the internal clock input is selected. The clock source is
𝑇
connected through a divide-by-12 circuit, as 8051 counts the Machine cycle.
So, it operates as a timer.
• When 𝐶⁄ ̅ =1, the external clock is selected. So, it operates as counter.
𝑇
• The clock is available to counter when the control signal enables the buffer.
• The control signal will be high and timer will run only if
o For GATE = 0: TR0=1 (𝐼𝑁𝑇0 ̅̅̅̅̅̅̅= 0 or 1: don’t care condition)
o For GATE =1: Both TR0=1 and ̅̅̅̅̅̅̅ 𝐼𝑁𝑇0= 1
• TR0 is the timer run bit. When GATE = 0, the bit controls the operation (RUN
or STOP) of timer.
o TR0=1 runs the timer
o TR0=0 stops the counter as control will be 0 in this case.
• GATE flag is available in TMOD register.
o GATE=0: Only TR0 flag control the timer as control signal connected to
buffer will be 1.
o GATE=1: Both 𝐼𝑁𝑇0 ̅̅̅̅̅̅̅ and TR0 together control the timer.
▪ Timer runs only if both 𝐼𝑁𝑇0 ̅̅̅̅̅̅̅ =1 and TR0=1. When any one is 0,
control input to buffer goes low and the clock is inhibited. So,
timer stops.
▪ ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 is the external signal that RUN or STOP the counter. This
is the hardware control of timer.
• T0 is the external clock input generated from an event.
MODE1
• Both T1 and T0 operate as 16-bit timer/counter.
• Maximum count is 216 = 65536 (10000H=FFFFH+1: counts from 0000H to
FFFFH).
• The maximum count is obtained when initial count is 0000H.
• C/Tx
̅̅̅ bit is used to select the operation as counter or timer.
• TFx is set when Tx overflows i.e. goes from FFFFH to 0000H.
• TRx is the timer run bit. So, TRx=1 start the timer when GATEx=0,
• TFx is monitored to detect end of counting if interrupt is disabled.
• Once the timer overflows, the Pre-set Value has to be loaded again to
timer.
• The operation is easily understood from the diagram given below.
 Clock Source

Timer Run
Fig: Operation of timer T0 in Mode1. Operation of Timer1 is
similar. Only the flags and signal input pins are different.

Explanation of the circuit

• The clock source is connected to timer through a 2 × 1 MUX (shown as switch
in figure) and a tristate buffer.
• The clock input triggers the counter and the counter counts up. When it
overflows (goes to zero from maximum count) Timer Flag bit (TF0) is set, that
generates the Timer0 interrupt if enabled.
o 𝐶⁄ ̅ =0 selects the internal clock source and get connected through a
𝑇
divide-by-12 circuit. So, it operates as timer.
o 𝐶⁄ ̅ =1 selects the external clock source and it operates as counter.
𝑇
• The clock is available to counter when control signal enables the buffer.
• The control signal will be high and timer will run only if
o For GATE = 0: TR0=1 (𝐼𝑁𝑇0 ̅̅̅̅̅̅̅= 0 or 1: don’t care condition)
o For GATE =1: Both TR0=1 and ̅̅̅̅̅̅̅ 𝐼𝑁𝑇0= 1

• TR0 is the timer run bit. When GATE = 0, the bit controls the operation (RUN
or STOP) of timer.
o TR0=1 runs the timer
o TR0=0 stops the counter as control will be 0 in this case.
• GATE flag is available in TMOD Register.
o GATE=0: Only TR0 flag control the timer as control signal connected to
buffer will be 1.
o GATE=1: Both ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 and TR0 together control the timer.
▪ Timer runs only if both ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 =1 and TR0=1. When any one is 0,
control input to MUX goes low and the clock is inhibited. So,
timer stops.
• ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 is the external signal to RUN or STOP the counter. This is the hardware
control of timer.
• T0 is the external clock input for counter mode.
Mode-2: Auto Reload Mode
• The lower byte of timers TL1 and TL0 operates as 8-bit timer.
• TH1 and TH0 holds the Pre-set Value for TL1 & TL0.
• Maximum count is 28 =256 (100H=FF H +1).
• Pre-set Value is loaded to TH0 or TH1 during Initialisation process.
• The Pre-Set value in TH0 /TH1 is loaded to TL0/TL1 by hardware
automatically.
• When count rolls from FFH to 00H.
o TF0 or TF1 flag is set that generate interrupt if enabled.
o Pre-set Value in TH0 or TH1 is reloaded to TL0 or TL1 by hardware.
o Counting process restarts automatically.
• Timer1 overflow (in any mode) is used to generate Baud rate for serial
communication. But the Mode-2 is most preferable as it avoids the reloading
the Pre-set Value and restart the timer. So easy to generate Baud rate.
• The operation is easily understood from the diagram given below

Explanation of the circuit

• The parallel output of
TH0 is connected to
parallel input of TL0 Clock Source
through an 8-bit
tristate buffer.
• The timer output is
connected to both
enable input of tristate
buffer and TF0 flag.
• When the timer TL0
overflows
o TF0 will be set Timer Run
o Buffer will be
enabled. So, Fig: Operation of Timer0 in Mode-2.
the buffer loads
the Pre-set
Value.
• The clock source is connected to TL0 through a 2 × 1 MUX (shown as switch
in figure) and a tristate buffer.
• The clock input triggers the counter and the counter counts up. Counter
overflow (rolls over to zero from maximum count) sets the Timer Flag bit of
Timer0 (TF0) if the interrupt is enabled.
• 𝐶⁄ ̅ selects the input of MUS that select the clock source.
𝑇
o 𝐶⁄ ̅ =0 selects the internal clock source and get connected through a
𝑇
divide-by-12 circuit. So, it operates as Timer.
o 𝐶⁄ ̅ =1 selects the external clock source and it operates as counter.
𝑇
• The clock is available to counter when control signal enables the buffer.
 • The control signal will be high and timer will run only if
o For GATE = 0: TR0=1 (𝐼𝑁𝑇0 ̅̅̅̅̅̅̅= 0 or 1: don’t care condition)
o For GATE =1: Both TR0=1 and 𝐼𝑁𝑇0 ̅̅̅̅̅̅̅= 1
• TR0 is the timer run bit. When GATE = 0, the bit controls the operation (RUN
or STOP) of timer.
o TR0=1 runs the timer
o TR0=0 stops the counter as control will be 0
• GATE flag is available in TMOD Register.
o GATE=0: Only TR0 flag control the timer as control signal connected to
buffer will be 1.
o GATE=1: Both ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 and TR0 together control the timer.
▪ Timer runs only if both ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 =1 and TR0=1. When any one is 0,
control input to MUX goes low and the clock is inhibited. So,
timer stops.
• ̅̅̅̅̅̅̅
𝐼𝑁𝑇0 is the external signal to RUN or STOP the counter. This is the hardware
control of timer.
• T0 is the external clock input generated from an event.
Mode-3: Split Timer Mode
• Timer0 operates as two 8-bit timer and Timer1 operates as 16-bit timer.
o TL0 operates as an 8-bit timer or a counter
o TH0 operates as another 8-bit timer and can’t be operated as counter.
• TL0 uses the resources of T0 where TH0 uses the resources of T1.
o TR0 acts as the run bit for TL0 and TR1 acts as the run bit for TH0
o TF0 is set when TL0 overflows and TF1 is set when TH0 overflows
o T0 is external clock input for TL0. TH0 can’t operate as counter. So
external clock input is not required for TH0.
̅̅̅̅̅̅̅ is external control for TL0 when GATE=1 for Timer0.
o 𝐼𝑁𝑇0
o Timer1 has no external hardware control facility.
• Timer1 has no timer run bit. It starts to count as soon as it enters to Mode3
and stop counting when it goes out of Mode3.
• The operation is easily understood from the figure shown below.
Explanation of the circuit
• The connection of T0 as two 8-bit
split timer is shown in the figure.
• The operation of TL0 is similar to
operation of T0 in Mode1. Here,
TL0 is the timer instead of T0. So,
the maximum count is 28= (256).
• TH0 operates as simple an 8-bit
timer with TR1 as timer run bit and
TF1 is the timer flag. Fig: Operation of Timer0 in
Mode3.
NOTE: Important Flags: 𝑇𝑅0 , 𝑇𝑅1, 𝑇𝐹0 , 𝑇𝐹1 , 𝐶⁄ ̅
𝑇

Additional study
Determination of Pre-set Count
The Pre-set count can be determined as follows. Please note that the maximum
count for:
8-bit timer 28=256 (FF+1=100H)
13-bit timer 213=8192 (1FFF+1=2000H)
16-bit timer 216=65536 (FFFF+1=10000H)
The number of times the timer counts is known as Count.
The number loaded to timer during initialisation is known as Pre-set Count Value.
So, 𝐶𝑜𝑢𝑛𝑡 = 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝐶𝑜𝑢𝑛𝑡 – 𝑃𝑟𝑒𝑠𝑒𝑡 𝑉𝑎𝑙𝑢𝑒
1 1 12
Also, Pulse width = 𝐼𝑛𝑝𝑢𝑡 𝑐𝑙𝑜𝑐𝑘 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 = 𝑓 =𝑓
( 𝑜𝑠𝑐⁄12) 𝑜𝑠𝑐

But, 𝐷𝑒𝑙𝑎𝑦 = 𝑃𝑢𝑙𝑠𝑒 𝑤𝑖𝑑𝑡ℎ 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡 𝐶𝑙𝑜𝑐𝑘 × 𝐶𝑜𝑢𝑛𝑡

𝑓𝑜𝑠𝑐
➔ 𝐷𝑒𝑙𝑎𝑦 = × (𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝐶𝑜𝑢𝑛𝑡 – 𝑃𝑟𝑒𝑠𝑒𝑡 𝑉𝑎𝑙𝑢𝑒)
12

12 × 𝐷𝑒𝑙𝑎𝑦
➔ 𝑃𝑟𝑒𝑠𝑒𝑡 𝑉𝑎𝑙𝑢𝑒 = 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝐶𝑜𝑢𝑛𝑡 −
𝑓𝑜𝑠𝑐

Programming Timers
Steps
1. Configuring timer/counter using TMOD.
a. Select as counter or timer using 𝐶⁄ ̅ .
𝑇
b. Set Mode of operation with M0 and M1.
c. GATE=0, normally.
2. Load initial count as pre-set value
a. For Mode0, Mode1 and Mode3
i. Timer0
MOV TH0, #MSB_Value
MOV TL0, #LSB_Value
ii. Timer1
MOV TH1, #MSB_Value
MOV TL1, #LSB_Value
b. For Mode2 (Auto-reload Mode)
MOV TH0, #MSB_Value
MOV TH1, #MSB_Value
 3. Initialise interrupt system (Enable or Disable as desired)
a. SETB EA ; Enable Interrupt system
b. SETB ET0 ; Enable Timer0 interrupt
c. SETB ET1 ; Enable Timer1 interrupt
d. CLR ET0 ; Disable Timer0 interrupt
e. SETB ET1 ; Disable Timer1 interrupt
4. Start timer/counter through TR0, TR1
a. SETB TR0 , RUN Timer0
b. SETB TR1 ; RUN Timer1
5. if interrupt is disabled poll Timer Flag TFx
a. JNB TF0, $ ; Repeatedly execute till TF0=1
b. Wait: JNB TF0, Wait ; Repeatedly execute till TF0=1
c. JNB TF1, $ ; Repeatedly execute till TF1=1
6. When timer overflows, following task is performed
a. If interrupt is disabled (Polling)
i. Stop Timer
1. CLR TR0
2. CLR TR1
b. Load Pre-set value to Timer (Except in Mode2)
c. Clear interrupt flag (TF0 orTF1) (Except Mode2)
i. CLR TF0
ii. CLR TF1

Example:
Write the necessary instructions that will load timers with Pre-set Value as
follows.
Timer 0 = 2BCDH and ad Timer 1 = 103FH
Solution:
• Not possible to write 16-bit data directly.
• The Timers is loaded by loading to THx & TLx separately.
Instructions that load the desired Pre-set Value
MOV TL0, #CDH
MOV TH0, #2BH
MOV TL1, #3FH
MOV TH1, #10H