Professional Documents
Culture Documents
Introduction: Flat and thin are the current trends in the display industry.
An LCD with cold cathode fluorescent lamps (CCFLs) satisfies the
demands regarding display performance, size and efficiency [1]. In
recent years, there has been increasing interest in large size LCD displays, Fig. 2 Equivalent circuit of parallel configuration
as required in LCD TV sets and computer monitors, which require higher
brightness for proper backlighting. Therefore, a backlight inverter is
required to drive multiple CCFLs in parallel. The terminal voltage (VT1) of Fig. 2 can be obtained as
There are several possible ways of configuring CCFLs in parallel
C
[2, 3]. One method is the direct parallel connection of the CCFLs. This VT 1 ¼ VLp1 1 þ u1 1 o2s Llk1 Ctotal1
Cb1
configuration has the well-known problem that the CCFL currents may
not be balanced owing to the lamp voltage variation and the constant Cp1
þ j ILp1 os Llk1 1 þ
voltage load characteristic of the CCFL [3]. The imbalance of the lamp Cb1
( )
currents causes a reduced lifetime and non-uniformity of brightness. 1
One feasible method of parallel configuration is to make the parallel 1 2 ð1Þ
os Llk1 ðCb1 þ Cp1 Þ
connection at the transformer primary side, as shown in Fig. 1, which
can minimise the effect of the lamp voltage variation on the common
where os is the switching angular frequency. VLp1 and ILp1 are the
node voltage. In this Letter, detailed analysis is performed to derive
amplitudes of the lamp voltage and current, respectively. The total
design equations, which provide balanced current to each lamp with
capacitance (Ctotal1) is
respect to the variations in the lamp voltage and the resonant compo-
nents. The analysis results are verified from experiments with two Cb1 Cu1
720 mm=4 mm CCFLs for 32-inch LCD TVs. Experimental results Ctotal1 ¼ Cp1 þ ð2Þ
Cb1 þ Cu1
with eight CCFLs in parallel are also presented.
From (1), the coefficient of VLp can be reduced to zero, which
eliminates the effect of lamp voltage variation. The condition is
1
os ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð3Þ
Llk1 Ctotal1
ILp7 ILp8
0V
ILp5 ILp6
0V
1 V/div.
ILp3 ILp4
0V
ILp1 ILp 2
0V
time, 5 ms/div.