(d)

Fig.1. The circuit configuration of proposed inverter

The switch S1 is a unidirectional type switch, a

conventional switch with a series-connected ultra-fast diode.
Also, the S5 switch is a bidirectional switch, which can be
created by using two conventional switches that are placed in (e)
the common-source connection.The proposed inverter has a Fig. 2. Different operating modes of the proposed inverter during a cycle
(a) vON = Vin, (b) vON = 2Vin, (c) vON = 0, (d) vON = -Vin, (e) vON = -2Vin
voltage gain of two and can statically increase the internal
voltage by using internal capacitors. Each of the SCs is
charged up to the input source voltage level in a positive half Table I. Active switches and output voltage of
cycle. proposed inverter in different stages. (charging: ▲),
(discharging: ▼)
A. Operational modes of proposed inverter SC’s
Stage Active Switches vON
The proposed inverter circuit consists of five different C1 C2
operation modes (I~V) as shown in Table. I and Fig. 2. The I S1, S2, S5, S6 ▲ -- +Vin
paths of the output current are shown with red lines, the II S2, S6, S8 ▼ ▼ +2Vin
charging paths of switched capacitors are shown in green, and III S1, S4, S7, S8 -- ▲ 0
the inactive power switches are demonstrates in black in IV S5, S7 -- ▼ -Vin
V S3, S7 -- ▼ -2Vin
different modes. Mode. I generates the output voltage equal to
Vin along with charging the capacitor C1 up to the voltage level Also, the capacitor C2 is charged up to the level of the input
Vin by turning on the relative switches. According to the states source voltage by activating the corresponding switches in the
of the switches that are ON, as shown in Fig. 2(b), the sum of output voltage of zero mode, according to Fig. 2(c). According
the voltages of SCs are discharged with their series placement to Fig. 2(d) and 2(e), the generation of voltage levels -Vin and
in the output stage to produce a voltage level of 2Vin. -2Vin are through the discharge of capacitors C2 and the sum
of two SCs, respectively. According to Fig. 2, the current flow
path for resistive-inductive load in different operation modes
can be seen.
B. SPWM control method
The SPWM method is widely used in SC inverters
according to Fig. 3 to generate switch gate signals of power
switches. As seen in Fig. 3(a), in this control method, a
reference signal (vref) and two carrier signals (C1, C2) are used
to produce a five-level output voltage. These two carrier
(a) signals are phase-shifted relative to each other. According to
Fig. 3(b), based on the position of the reference signal in the
positive half-cycle (0 < ωt < π) or the negative half-cycle (π
< ωt < 2π), comparing it with the carrier signals, and using
logical OR gates, the gate signals of the proposed inverter
switches are generated.

(b)

(c) (a)
 Table II. Comparison of proposed inverter with recent five level inverters.
No. of
Min/max

Boosting

AB-SCV
Devices Reported

Vmax on
No. of

SCs
Topology CGT Efficiency
ON-
Sw. D C So. (%)
Switches
96 @
C-H5 [10] 10 0 2 2 No No Yes Vin/2 4/5
0.5 kW
5L HB 95.8 @
12 0 3 1 No No No Vin 4/5
based [11] 0.5 kW
5L-ANPC 90 @
12 0 5 1 No No No Vin/2 6/6
[12] 1.5 kW
97.2 @
[13] 12 0 4 1 Yes No Yes Vin 4/4
300W
CG-SC- 98.5 @
9 1 3 1 Yes Yes Yes Vin 3/5
(b) based [14] 1 kW
Fig. 3. SPWM method, (a) references, carrier signals and output voltage, SCMLI 97.91 @
(b) logic function diagram 9 1 1 1 Yes No Yes Vin 4/4
[15] 2 kW
SBD2T5L- 98.2 @
10 0 3 1 Yes Yes No 2Vin 4/5
TL [16] 1 kW
III. COMPARISON OF THE PROPOSED INVERTER TOPOLOGY Proposed 98 @
WITH EXISTING SIMILAR STRUCTURES 9 0 2 1 Yes Yes Yes Vin 2/4
Inverter 0.5 kW
A comparison summary of the proposed inverter with
similar five-level inverters presented in recent studies is given IV. SIMULATION AND EXPERIMENTAL RESULTS
in Table. II. According to Table. II, a comparison based on the The performance of the proposed inverter is evaluated
number of power switches (Sw.), ultra-fast diodes (D), through simulation in MATLAB/Simulink software and the
switched capacitors (C), and DC voltage sources (So.) is simulation parameters are given in Table. III. Fig. 4 to Fig. 6
provided. Also, the topologies of the proposed inverter and show the simulated waveforms of the proposed inverter under
similar topologies are compared with each other in terms of different loading conditions. According to Fig. 4(a), the five-
the ability to increase the input voltage, the type of common level voltage waveform is produced without any spike in the
ground (CG), the self-balancing capability of the SCs (AB- output voltage levels considering that the load is inductive and
SCV), the minimum and the maximum number of control has a phase shift of 58°. Moreover, the voltage of the switched
switches in the operating modes (Min/max No. of capacitors C1 and C2 in this case is charged up to the input
simultaneously ON-switches), and the corresponding voltage level of 200V and has a ripple around 4V. It can be
efficiency. Charging the capacitor with high voltages will lead seen that the maximum value of the output voltage has
to the use of capacitors with high voltage variation, and as a increased to 400V per input voltage of 200V. Also, according
result, the volume and weight of the inverter circuit will to Fig. 4(b) and Fig. (5), despite the sudden changes under
increase. According to Table. II, although the maximum different loads, the output voltage levels are constant and
voltage of the capacitors used in the topologies presented in stable, which shows the stable voltage ripple of the capacitors.
5L-ANPC [10] and C-H5 [8] is low in comparison with the This stability in the capacitors was obtained without any
proposed inverter topology, the proposed inverter has fewer complicated controller and without additional circuits, and
semiconductor components. Moreover, the presence of two only by using the typical charging and discharging modes of
SCs in the proposed inverter structure reduces capacitor ripple the capacitors in a complete cycle. According to Fig. 6(a), with
losses. the modulation index changes from 0.48 to 0.98, the output
voltage changes from a three-level state to a five-level state as
The inverters proposed in [10] and [5] cannot increase the
expected. The changes of the output load in the presence of
input voltage and have leakage current due to their lack of
the output filter from an resistive load to a resistive-inductive
common-ground features, which makes them inappropriate
load with 27.6° phase shift are exhibited in Fig. 6(b).
for PV applications. Although the SCMLI topology [13] has
fewer capacitors compared to other topologies, its structure is Table. III. The simulation parameters
not common mode, and therefore, there will be leakage Variable Description
current. Thus, due to a large number of ON switches in Input Voltages (Vdc) 200 [V]
different modes, the efficiency of the inverter topology in [13] Max. Output Voltage 400 [V]
is lower than the proposed inverter. The inverters presented in Switched Capacitors (C1 & C2) 1200 [µF]
Switching Frequency (fsw) 20 [kHz]
[11], SBD2T5L-TL [14], and 5L HB based [9] have a higher
Reference Frequency (fref) 50 [Hz]
quantity of power switches than the proposed inverter. Using
Output Filters (‫)݂ܥ( & )݂ܮ‬ 1.6 mH & 2.2 µF
a large number of power switches increases switching and
conduction losses, as well as increasing the number of
heatsinks. The proposed inverters of CG-SC-based [12] and
SCMLI [13] have the same number of power switches as the
proposed topology. However, these inverters have ultra fast
diodes, which can increase switching losses in addition to
increasing conduction losses. Thus, based on the analysis
above, the proposed inverter has fewer number of components
compared to other similar inverters in Table. II. Additionally,
it can increase the input voltage due to the common ground
capability, and it can be used in PV applications according to
the full transfer capability of reactive power.
(a)
 R = 300 Ω Z = 300 Ω + 500mH
φ = 0° φ = 27.6°
(b)
Fig. 4. Simulation results, (a) output voltage, output current and voltage
of capacitors waveforms with R-L load (100Ω + 500mH), (b) a sudden (a)
MI = 0.98 MI = 0.48
step changes in the load from R load to R-L load.

Z = 100 Ω + 500 mH Z = 300 Ω + 500 mH

(a)
Z = 300 Ω + 500 mH Z = 300 Ω + 500 mH
(b)
Fig. 6. Simulation results, (a) sudden step change from R load (φ=0°) to
°
R-L load (φ=27.6 ), (b) index modulation change from 0.98 to 0.48.

The voltage value equality of the capacitors in the

proposed inverter and their voltage ripple per resistive-
inductive load of 90Ω + 560mH are shown in Fig. 8(d). The
stability of the voltage in the switched-capacitors without
using any controller and additional circuit is one of the
capabilities of the proposed inverter.
R = 250 Ω R = 150 Ω
SCs
(b) Power
Fig. 5. Simulation results with sudden load step change (a) for R-L load, Switches Power
(b) for R load. R Load
Diode
Moreover, the proposed inverter prototype model was
constructed as seen in Fig. 7 to validate the analyzes and L Load
simulation results. The input voltage source is 50V and the Current
switching frequency of the proposed inverter switches is 20 Probe
kHz. The switches used are IRF740, and TLP250 is used as an
optocoupler in the control circuit. According to the Fig. 7, the Isolated Sources
of Gate Drivers
switch S1 is made of the combination of conventional switch
DC Source
and ultra-fast diode. Arduino Uno
The capacitance of the SCs is 470µF, and the Arduino Uno
processor as shown in Fig. 7 is used to generate switch gate Fig. 7. Experimental Setup
pulses signals. The simulation results of the inverter output
voltage and current for an resistive load of 80 Ω and changes
vAN [50 V/div]
in the resistive-inductive load from 45Ω + 280mH to 90Ω +
560mH are shown in Fig. 8(a) and Fig. 8(b), respectively. For
both of the studied loads, the maximum output voltage of
100V can be seen in the five-level voltage for the input voltage
of 50V. Fig. 8(b) shows the reactive power transfer capability
of the proposed inverter in the laboratory environment with
sudden load changes. The dynamic response of the inverter to
sudden load changes from resistive load to resistive-inductive io [1 A/div]
load is shown in Fig. 8(c). According to this figure, the load
has suddenly changed from the value of 45Ω to the value of
90Ω + 560mH. (a)

vAN [50 V/div]
Step change
io [1 A/div]
(b)
vAN [50 V/div]
Step change
io [1 A/div]
(c)
vc1 [50 V/div]
vc2 [50 V/div]
(d)
Fig. 8. Experimental results, (a) vAN and iO waveforms with R load, (b)
vAN and iO waveforms with R-L load, (c) vAN and iO waveforms with step
change in the load from R to R-L, (d) capacitors voltage variation in the
R-L load.
V. CONCLUSION
This paper has presented a novel topology of five-level
switched-capacitor inverter which has static voltage boost,
automatic voltage balance of switched capacitors, reduced
number of components, ability to transfer full reactive power
in the common-ground type, and no leakage current. The
operation of different operation modes was shown using a
simple SPWM control method to generate five-level output
voltage. The superiority of proposed inverter topology is
proved in comparison with other similar topologies using
important evaluation parameters such as leakage current, and
power electronics components quantity. Finally, the
simulation results and experimental analysis confirmed the
effectiveness and enhanced performance of the proposed
inverter topology for 1-φ grid-tied PV system application.
REFERENCES
[1] J. F. Ardashir and H. V. Ghadim, "A PV Based Multilevel Inverter with
Ultra-Capacitor Bank for Microgrid Applications," 2021 11th Smart
Grid Conference (SGC), 2021, pp. 1-5, doi:
10.1109/SGC54087.2021.9664106.
[2] J. Hu, Y. Shan, K. W. Cheng and S. Islam, "Overview of Power
Converter Control in Microgrids—Challenges, Advances, and Future
Trends," in IEEE Transactions on Power Electronics, vol. 37, no. 8, pp.
9907-9922, Aug. 2022, doi: 10.1109/TPEL.2022.3159828.
[3] M. Shahabadini and H. Iman-Eini, "Leakage Current Suppression in
Multilevel Cascaded H-Bridge Based Photovoltaic Inverters," in IEEE
Transactions on Power Electronics, vol. 36, no. 12, pp. 13754-13762,
Dec. 2021, doi: 10.1109/TPEL.2021.3084699.
[4] J. F. Ardashir, H. V. Ghadim and A. M. Ogly, "A Novel Step-up
Common Ground Five-Level Inverter with Inherent Balance of
Capacitors Voltage," 2022 IEEE Kansas Power and Energy Conference
(KPEC), 2022, pp. 1-5, doi: 10.1109/KPEC54747.2022.9814729.
[5] Y. C. Fong, K. W. E. Cheng, S. R. Raman and J. Hu, "A Single Source
Cascaded Multilevel Inverter Based on Switched-capacitor with Series
and Parallel Connectivity," 2018 IEEE Energy Conversion Congress
and Exposition (ECCE), 2018, pp. 2601-2606, doi:
10.1109/ECCE.2018.8558017.
[6] Fallah Ardashir, J., Gasemi, M., Rozmeh, B. A New 13-Level Flying
Capacitor-based 1-φ Inverter with Full Reactive Power Support. AUT
Journal of Electrical Engineering, 2022; 54(1): 15-28. doi:
10.22060/eej.2021.20090.5418
[7] M. Karimi, P. Kargar, K. Varesi and S. S. Lee, "A 21-Level Boost
Inverter with Limited Inrush-Current of Capacitors Suitable for AC
Microgrids," 2021 11th Smart Grid Conference (SGC), 2021, pp. 1-5,
doi: 10.1109/SGC54087.2021.9664192.
[8] J. F. Ardashir, B. Rozmeh, M. Gasemi, A. M. Shotorbani and A. A.
Ghavifekr, "A Novel Boost Fifteen-Level Asymmetrical Flying-
Capacitor Inverter with Natural Balancing of Capacitor Voltages," 2021
12th Power Electronics, Drive Systems, and Technologies Conference
(PEDSTC), 2021, pp. 1-5, doi: 10.1109/PEDSTC52094.2021.9405887.
[9] K. Varesi, F. Esmaeili, S. Deliri and H. Tarzamni, "Single-Input
Quadruple-Boosting Switched-Capacitor Nine-Level Inverter With
Self-Balanced Capacitors," in IEEE Access, vol. 10, pp. 70350-70361,
2022, doi: 10.1109/ACCESS.2022.3187005.
[10] X. Guo and X. Jia, "Hardware-Based Cascaded Topology and
Modulation Strategy With Leakage Current Reduction for
Transformerless PV Systems," IEEE Transactions on Industrial
Electronics, vol. 63, no. 12, pp. 7823-7832, 2016, doi:
10.1109/TIE.2016.2607163.
[11] X. Zhu, H. Wang, W. Zhang, H. Wang, X. Deng, and X. Yue, "A Single-
Phase Five-Level Transformer-Less PV Inverter for Leakage Current
Reduction," IEEE Transactions on Industrial Electronics, vol. 69, no. 4,
pp. 3546-3555, 2022, doi: 10.1109/TIE.2021.3075874.
[12] E. Burguete, J. López, and M. Zabaleta, "A New Five-Level Active
Neutral-Point-Clamped Converter With Reduced Overvoltages," IEEE
Transactions on Industrial Electronics, vol. 63, no. 11, pp. 7175-7183,
2016, doi: 10.1109/TIE.2016.2557308.
[13] L. He and C. Cheng, "A Flying-Capacitor-Clamped Five-Level Inverter
Based on Bridge Modular Switched-Capacitor Topology," IEEE
Transactions on Industrial Electronics, vol. 63, no. 12, pp. 7814-7822,
2016, doi: 10.1109/TIE.2016.2607155.
[14] M. N. H. Khan et al., "A Common Grounded Type Dual-Mode Five-
Level Transformerless Inverter for Photovoltaic Applications," IEEE
Transactions on Industrial Electronics, vol. 68, no. 10, pp. 9742-9754,
2021, doi: 10.1109/TIE.2020.3028810.
[15] A. Taghvaie, J. Adabi, and M. Rezanejad, "A Self-Balanced Step-Up
Multilevel Inverter Based on Switched-Capacitor Structure," IEEE
Transactions on Power Electronics, vol. 33, no. 1, pp. 199-209, 2018,
doi: 10.1109/TPEL.2017.2669377.
[16] R. Barzegarkhoo, S. S. Lee, Y. P. Siwakoti, S. A. Khan, and F.
Blaabjerg, "Design, Control, and Analysis of a Novel Grid-Interfaced
Switched-Boost Dual T-Type Five-Level Inverter With Common-
Ground Concept," IEEE Transactions on Industrial Electronics, vol. 68,
no. 9, pp. 8193-8206, 2021, doi: 10.1109/TIE.2020.3018073.