COLLEGE OF

ENGINEERING AND
PETROLEUM

Intro to Logic Design

with Verilog
Slides Set#4

CpE-477
Fall 2020

Dr. Abbas A. Fairouz

Computer Engineering Department
Topics
1. Structural Models of Combinational Logic
2. Logic System, Design Verification, and Test Methodology
3. Propagation Delay
4. Truth Table Models of Combinational andSequential Logic with
Verilog

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Structural Models of Combinational Logic
• A Verilog model of a circuit encapsulates a description of its
functionality as a structural or behavioral view of its input–output
(I/O) relationship.
• Structural design is similar to creating a schematic.

Figure 4.1 Schematic and Verilog description of a half adder.

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Verilog Primitives and Design Encapsulation
• Verilog includes a set of 26 predefined functional models of common
combinational logic gates, called primitives.
• Primitives are the most basic functional objects that can be used to
compose a design.
• There are no pre-defined
sequential primitives in Verilog.

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Verilog Primitives and Design Encapsulation
• Each primitive has ports (corresponding to hardware pins/terminals) that
connect to its environment.
• The output port(s) of a primitive must be first in the list of ports, followed
by the primitive’s input port(s).
• Figure 4-3 shows a list of instantiated primitives that are connected by
wires to have the functionality of a five-input and-or-invert (AOI) circuit.

Figure 4.3 A list of declarations of wire-connected Figure 4.2 A three-input nand gate and an
primitives having the functionality of a five-input AOI gate. example of its instantiation as a Verilog primitive.

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Verilog Primitives and Design Encapsulation
• Verilog modules using the 1995 syntax have the text format shown in
Figure 4-4.
• The keywords module and endmodule encapsulate the text that
describes the module having type-name my_design.
• The ANSI-style syntax approved by IEEE in 2001 has the form shown
below and eliminates redundant text.
module my_design (Declarations of port mode and name go here);
// Functional details go here
endmodule
Figure 4.4 (1995 syntax) The format of a
Figure 4.4-x (2001 ANSI-style syntax). Verilog module, with module … endmodule
keyword encapsulation.

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Verilog Primitives and Design Encapsulation

Figure 4.5 An AOI circuit and its Verilog model: (a) IEEE
1364-1995 syntax and (b) IEEE 1364-2002, 2005 syntax.

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Module Ports
• The ports of a module define its interface to the environment in
which it is used.
• The mode of a port determines the direction that information (signal
values) may flow through the port.
• A port’s mode may be unidirectional (input, output) or bidirectional
(inout).

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Some Language Rules
• Verilog is a case-sensitive language, so it matters whether you refer to a
signal as C_out_bar or C_OUT_BAR.
• An identifier (name) in Verilog is composed of a case-sensitive, space-free
sequence of upper- and lower-case letters from the alphabet, the digits (0,
1, 9), the underscore (_), and the ($) symbol.
• The name of a variable may not begin with a digit or ‘$’, and may be up to
1024 characters long.
• Usually, each line of text in a Verilog description must terminate with a
semicolon (;), except for endmodule keyword.
• For comments:
ØA pair of slashes ‘//’: single line comment.
ØA symbol pair ‘/*’ to start a multi-line comment, and ‘*/’ to terminate it.
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Top-Down Design and Nested Modules
• Top-down design refers to the practice of systematically and repeatedly
partitioning a complex system into simpler functional units whose design
can be managed and executed successfully.
• The divide-and-conquer strategy of top-down design makes possible the
design of circuits with several million gates.
• Top-down design is used in the most modern and sophisticated design
methodologies that integrate entire systems on a chip (SoC).
• The instantiation of a module within the declaration of a different module
is referred to as a nested module.
• Nested modules are the Verilog mechanism supporting top-down design
because nesting automatically creates a partition of the design.
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Top-Down Design and Nested Modules
• A binary full adder circuit can
be formed by combining two
half adders and an OR gate as
shown in the schematic in
Figure 4-6(a).
• Modules may be nested
within other modules, but
not in a recursive manner.
• The referencing module is
called a parent module; the
referenced module is called a
child module. Figure 4.6 Hierarchical decomposition of a full adder:
(a) gate-level schematic and (b) Verilog model.

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Top-Down Design and Nested Modules

Figure 4.7 Hierarchical decomposition of a 16-bit, ripple-carry adder into a chain of four 4-bit-
slice adders, each formed by a chain of full adders:
(a) top-level schematic symbol, (b) decomposition into four 4-bit adders,
(c) interior detail of a 4-bit adder, (d) a full adder, and (e) gate level schematic of a half adder.

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Design Hierarchy and Source-Code Organization

Figure 4.8 Design hierarchy of a 16-bit ripple-carry adder.

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Vectors in Verilog
• A vector in Verilog is denoted by square brackets, enclosing a
contiguous range of bits, e.g., sum[3:0] represents four bits from sum.
• The language specifies that, for the purpose of calculating the decimal
equivalent value of a vector, the leftmost index in the bit range is the
most significant bit, and the rightmost is the least significant bit.
• For example, if an 8-bit word vect_word[7:0] has a stored value of
decimal 4, then vect_word[2] has a value of 1; vect_word[3:0] has a
value of 4; and vect_word[5:1] has a value of 2.

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Structural Connectivity
• Wires in Verilog establish connectivity between design objects.
• They connect primitives to other primitives and/or modules, and
connect modules to other modules and/or primitives.
• By themselves, wires have no logic.
• The logic value of a wire (net) is determined dynamically during
simulation by what is connected to the wire.
• The ports of an instantiated module must be
connected in a manner that is consistent with
the declaration of the module, but the names
of the connecting signals need not be the same.
Figure 4.9 Formal and actual names for port
association by name in module Add_full.

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Structural Connectivity
module Comp_2_str (
output A_gt_B, A_lt_B, A_eq_B,
input A, A, B, B
);
nor (A_gt_B, A_lt_B, A_eq_B);
or (A_lt_B, w1, w2, w3);
and (A_eq_B, w4, w5);
and (w1, w6, B1);
and (w2, w6, w7, B0);
and (w3, w7, B0, B1);
not (w6, A1);
not (w7, A0);
xnor (w4, A1, B1);
xnor (w5, A0, B0);
endmodule Figure 4.10 Schematic of a 2-bit binary comparator.

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Structural Connectivity
module Comp_4_str (
output A_gt_B, A_lt_B, A_eq_B,
input A3, A2, A1, A0, B3, B2, B1, B0
);
wire w1, w0;
Comp_2_str M1 (A_gt_B_M1, A_lt_B_M1, A_eq_B_M1, A3, A2, B3, B2);
Comp_2_str M0 (A_gt_B_M0, A_lt_B_M0, A_eq_B_M0, A1, A0, B1, B0); Figure 4.11 Block diagram symbol of a 4-bit comparator.
or (A_gt_B, A_gt_B_M1, w1);
and (w1, A_eq_B_M1, A_gt_B_M0);
and (A_eq_B, A_eq_B_M1, A_eq_B_M0);
or (A_lt_B, A_lt_B_M1, w0);
and (w0, A_eq_B_M1, A_lt_B_M0);
endmodule

Figure 4.12 Hierarchical structure of a 4-bit binary

Figure 4.13 Simulation results for a 4-bit binary comparator. comparator composed of 2-bit comparators and glue logic.

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Logic System, Design Verification, and Test Methodology

• Language-based models of a circuit must be verified to assure that their

functionality conforms to the specification for the design.
• Two methods of verification are used:
1. Logic simulation: applies stimulus patterns to a circuit and monitors its simulated behavior
to determine whether it is correct.
2. Formal verification: uses elaborate mathematical proofs to verify a circuit’s functionality
without having to apply stimulus patterns.
• We will consider only logic simulation.

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Four-Value Logic and Signal Resolution in Verilog
• Verilog uses a four-valued logic system having the symbols: 0, 1, x,
and z.
• 0: de-assertion (False).
• 1: assertion (True).
• x: unknown (ambiguous value).
• z: high impedance.
• A logic simulator creates symbolic input waveforms in this four-value
logic system and generates the internal and symbolic output signals
for a circuit.

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Four-Value Logic and Signal Resolution in Verilog

Figure 4.14 Four-value logic waveforms for the and primitive.

Figure 4.15 Resolution of multiple drivers on a net.

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Test Methodology
• A large circuit must be tested and verified systematically to ensure
that all of its logic has been exercised and found to be functionally
correct.
• In practice, design teams write an elaborate test plan that specifies
the features that will be tested and the process by which they will be
tested.
• The plan must also identify features that will not be tested.
• Systematic verification proceeds in the opposite direction of modeling
(top-down), beginning with the simpler units and moving to the more
complex units above them in the design hierarchy.
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Test Methodology
• A basic methodology for verifying the functionality of a digital circuit
ØBuilding a testbench that applies stimulus patterns to the circuit and displays
the waveforms that result.
• The testbench is a separate Verilog module
that has the basic organization shown
in Figure 4-16.
• It resides at the top of a new design hierarchy
that contains a stimulus generator,
a response monitor, and an instantiation of
the unit under test (UUT).
Figure 4.16 Organization of a testbench for
verifying a unit under test.

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Signal Generators for Testbenches
• A Verilog behavior is a group of statements that execute during simulation to assign value
to simulation variables as though they were driven by hardware.
• The keyword initial declares a single-pass behavior that begins executing when the
simulator is activated, at 𝑡!"# = 0 (we use 𝑡!"# to denote the time base of the
simulator).
• The statements that are associated with the behavior are listed within the begin…end
block keywords, and are called procedural statements.
• The statements execute sequentially from top to bottom and from left to right across
lines of text that may contain multiple statements.
• A delay control operator (#) preceding a procedural assignment statement suspends its
execution and, consequently, suspends the execution of the subsequent statements in
the behavior until the specified time interval has elapsed during simulation.
• Example: #10 => a delay of 10 time units.

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TestBench Example
The module below, t_Add_half, has the basic structure of a testbench for verifying
Add_half in a simulator having a graphical user interface.

module t_Add_half();
wire sum, c_out; reg a, b;
Add_half M1 (c_out, sum, a, b); // UUT
initial begin // Time Out
#100 $finish;
end
initial begin // Stimulus patterns
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0; Figure 4.17 Waveforms produced by a simulation of Add_half,
a 0-delay binary half adder.
end
endmodule

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TestBench Template

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Propagation Delay
• Physical logic gates have a propagation delay between the time that
an input changes and the time that the output responds to the
change.
• The primitives in Verilog have a default delay of 0, meaning that the
output responds to the input immediately, but a nonzero delay can
also be associated with a primitive.
• Timing verification ultimately depends on realistic values of the
propagation delays in a circuit.
• Simulations are either done using a 0-delay or a unit delay.

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Propagation Delay

Figure 4.18 Results of unit-delay simulation of a 1-bit full adder.

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Propagation Delay

Figure 4.19 Results of simulating a 1-bit full adder implemented

with ASIC cells having technology-dependent propagation delays.

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Inertial and Transport Delays
• Logic transitions in a digital circuit correspond to transitions in voltage
levels caused by the accumulation or dissipation of charge at a physical
node/net.
• The physical behavior of a signal transition is said to have inertia.
• The amount of time that the input pulse must be constant in order for the
gate to make a transition is the inertial delay of the gate.
• Verilog uses the propagation delay of a gate as the minimum width of an
input pulse that could affect the output;
Øthat is the value of propagation delay is also used as the value of the inertial delay.
• The width of a pulse must be at least as long as the propagation delay of
the gate.
• The time-of-flight of a signal traveling a wire of a circuit is modeled as a
transport delay.
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Truth Table Models in Verilog
• Verilog supports truth-table models of combinational and sequential
logic.
• The Verilog has a mechanism for building user-defined primitives
(UDPs), which use truth tables to describe sequential behavior and/or
more complex combinational complex logic.
• UDPs are widely used in ASIC cell libraries because they simulate
faster and require less storage than modules.
• The output of a UDP must be a scalar.
• UDPs are declared in a source file in the same way that a module is
declared, but with the encapsulating keyword pair
primitive…endprimitive.

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 Truth Table Models in Verilog
Example: The Verilog UDP mux_prim, shown
in Figure 4-21 describes a two-input
multiplexer and includes comments citing
some basic rules for UDP models.

• A simulator will automatically

assign the (default) value x to the
output of a UDP if its inputs have
values that do not match a row of
the table.
• An input value of z is treated as x by
the simulator.
• The last two rows of the table
describing the behavior of the
multiplexer in Figure 4-21 reduce
the pessimism that might result
during simulation.
Figure 4.21 UDP for a two-input multiplexer.

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Truth Table Models in Verilog
• The entries for the inputs in a truth table can be reduced by using a
shorthand notation.
• The ‘?’ symbol allows an input to take on any of the three values, 0, 1,
and x. This allows one table row to effectively replace three rows.

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Truth Table Models in Verilog
• A truth table that describes sequential behavior has:
Ø input columns followed by a colon (:) and
Øa column for the present state of the device,
Øand another colon and a column for its next state, that is, the state that will
be caused by the present inputs.
• In addition, the output of the UDP must be declared to have type reg
because the value of the output is produced abstractly, by a table,
and must be held in memory during simulation.

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Truth Table Models in Verilog
Example: A truth-table description of a transparent latch is given below by latch_rp. It describes transparent
behavior and latching behavior, and also deals with the possibility that, under simulation, the input enable
might acquire an x value.

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Truth Table Models in Verilog
• UDPs can describe behavior that is sensitive to either the positive or
negative edge (transition) of a clock signal, with built-in semantics for
signal transitions:
• positive edge (posedge)
• negative edge (negedge).
• A falling edge (negedge) transition is denoted by the following signal
value pairs: (10), (1x), and (x0);
• Rising edges (posedge) are denoted by (01), (0x), and (x1).

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 Truth Table Models in Verilog
Example: The UDP d_prim1 in Figure 4-22
describes the behavior of an edge-
sensitive D-type flip-flop. The input signal
clock synchronizes the transfer of data to
q_out.

Figure 4.22 Truth-table model of a D-type flip-flop.

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Truth Table Models in Verilog

Example: A J-K flip-flop having asynchronous

preset and clear with edge-sensitive sequential
behavior is described in Figure 4-23.
• The preset and clear inputs are active-low,
and the output is sensitive to the rising edge
of the clock.
• The signal clock synchronizes the changes of
q_out.
• Depending on the values of the preset and
clear signals when the clock edge occurs:
Ø q_out does not change (𝑗 = 0, 𝑘 = 0),
Ø q_out gets a value of 0, (𝑗 = 0, 𝑘 = 1),
Ø q_out gets a value of 1, (𝑗 = 1, 𝑘 = 0),
Ø q_out is toggled (𝑗 = 1, 𝑘 = 1).

Figure 4.23 UDP for a J-K flip-flop.

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