05 Behavioral Verilog

COLLEGE OF
ENGINEERING AND
PETROLEUM
Logic Design with

Behaioral Models in Verilog
Slides Set#5
CpE-477
Fall 2020
Dr. Abbas A. Fairouz

Computer Engineering Department
Topics
1. Behavioral Modeling
2. Data Types for Behavioral Modeling
3. Boolean Equation-Based Behavioral Modeling
4. Propagation Delay and Continuous Assignments
5. Level-Sensitive Circuits in Verilog
6. Comparison of Styles for Behavioral Modeling
7. Behavioral Models of Multiplexers, Encoders, and Decoders
8. Dataflow Models of a Linear-Feedback Shift Register
9. Modeling Digital Machines with Repititve Algorithms
10. Functions and Tasks
11. Behavioral Models of Counters, Shift Register, and Register File
12. Switch Debiunce, Metastability, and Synchronizers for Asynchronous Signals
CpE-477: HDL-based Design Dr. A. Fairouz 2

Behavioral Modeling
• Verilog supports structural and behavioral modeling.
• Structural modeling connects primitive gates and/or functional units to
create a specified functionality (for example, an adder) just as parts are
connected on a chip or a circuit board.
• Behavioral modeling is the predominant descriptive style used by the
industry, enabling the design of massive chips.
• Behavioral models specify the input–output model of a logic circuit and
suppress details about its low-level internal structure (architecture) and
physical implementation.
• Propagation delays are not included in the behavioral model of the circuit,
Øbut the propagation delays of the cells in the target technology are considered by the
synthesis tool when it imposes timing constraints on the physical realization of the
logic.

Data Types
• All variables in Verilog have a predefined type, and there are only two
families of data types: nets and registers.
• Net variables act like wires in a physical circuit and establish
connectivity between design objects that represent hardware units.
• Register variables act like variables in ordinary procedural
languages—they store information while the program executes.
• Not all data types are useful in a synthesis methodology, and we will
use mainly the net type wire and the register types reg and integer.
• A wire and a reg have a default size of 1 bit.
• The size of an integer is automatically fixed at the word length
supported by the host computer, at least 32 bits.

Boolean Equation-Based Behavioral Modeling
• A Boolean equation describes combinational logic by an expression
of operations on variables.
ØIts counterpart in Verilog is the continuous assignment statement.
• The keyword assign declares a continuous assignment and associates
the Boolean expression on the right-hand side (RHS) of the statement
with the variable on the lefthand side (LHS).
• Verilog has several built-in operators for arithmetic, logical, and
machine-oriented operations (e.g., concatenation, reduction, and
shifting operators) that can be used in expressions.

• The five-input and-or-invert (AOI) circuit that was shown in Figure 4-7
can be described by a single continuous assignment statement that
forms the output of the circuit from operations on its inputs, as
shown in AOI_5_CA0 below.
• Logical operators: AND à &&, OR à ||, inversion à !

• A continuous assignment statement with a conditional operator
provides a convenient way to model the multiplexer circuit.
Figure 5.2 A two-channel mux with 32-bit datapaths.

Propagation Delay and Continuous Assignments
• Propagation (inertial) delay can be associated with a continuous
assignment so that its implicit logic has the same functionality and
timing characteristics as its gate-level counterpart.
• As an alternative to the structural model of a 2-bit comparator that
was presented in CH4, the model Comp_2_CA0 given below.

Propagation Delay and Continuous Assignments
• A synthesis tool will create the
actual hardware realization of
the continuous assignment.
Figure 5.3 Verilog counterparts of three

common descriptions of combinational logic.

Level-Sensitive Circuits in Verilog
• Below, Latch_CA uses a continuous assignment statement with
feedback to model this functionality, as implemented in CH4 but
using a truth table instead.
Figure 5.4 Simulation results for a transparent latch modeled

by a continuous assignment statement with feedback.

• The latch model Latch_Rbar_CA below uses a nested conditional
operator to add the functionality of an active-low reset to a
transparent latch.
Figure 5.5 Simulation results for a transparent

latch with active-low reset and active-high enable.
• Continuous assignments are convenient for modeling small Boolean
expressions, three-state behavior, and transparent latches.
• But designers writing large Boolean equation models (continuous
assignments) are prone to making mistakes when there are several
variables and large expressions.
• Also, the Boolean expressions might obscure the functionality of the
design, even if they are written correctly.
• So, it is worthwhile to consider other language constructs that offer
simpler, but more readable alternatives that describe edge-sensitive
as well as level-sensitive behavior.

Cyclic Behavioral Models of Flip-Flops and Latches
• Continuous assignment statements are limited to modeling level-
sensitive behavior combinational logic and transparent latches.
• They cannot model an element that has edge-sensitive behavior, such
as a flip-flop.
• Verilog uses a cyclic behavior to model edge-sensitive functionality.
• Cyclic behaviors are abstract—they execute procedural statements to
generate the values of variables, just as the statements of an ordinary
procedural language (e.g., C) execute to extract, manipulate, and
store variables in memory.
• They are called cyclic behaviors because they re-executed
continuously.

• The keyword always in df_behav declares a cyclic behavior
corresponding to an edge-triggered flip-flop.
• At every rising edge of clk the behavior’s procedural statements
execute, computing the value of q and storing it in memory.
• A continuous assignment statement forms q_bar from q immediately
after q has changed.

• The assignment operator (<=) represents the nonblocking, or
concurrent assignment.
• A variable that is assigned value by a nonblocking assignment
operator in a single-pass or cyclic behavior must be a declared register-
type variable (i.e., not a net).
• All register variables store information during simulation, but they do
not necessarily synthesize a hardware register.

Cyclic Behavior and Edge Detection
• A cyclic behavior is activated at the beginning of simulation.
• Edge semantics for rising (posedge) and falling (negedge) edges are
built into Verilog.
ØQualifies an event-control expression to execute the cyclic behavior procedural
statements.
• A simulator automatically monitors the variables in an event-control
expression, and when the expression changes value, the associated
procedural statements execute if the enabling change took place.

• The reset action of a flip-flop can be asynchronous.
• The functionality modeled below by asynch_df_behav is sensitive to
the rising edge of the clock, but also to the falling edge of rst_b and
set_b, with priority given to rst_b.

• A transparent latch is modeled in tr_latch by a cyclic behavior whose
level-sensitive event-control expression is sensitive to a change in
enable or a change in data.

Comparison of Styles for Behavioral Modeling
• We have already seen how the 2-bit comparator can be described by a
gate-level structure (CH4) and by a Boolean equation-based behavioral
model (earlier in CH5).
• Next, we compare simpler and more readable alternatives that also
use continuous assignments, and then we contrast modeling styles
based on
1. Continuous assignments
2. Register transfer level (RTL) logic
3. Behavioral algorithms.

Comparison of Styles for Behavioral Modeling:
Continuous Assignments
• The functionality in Comp_2_CA1 is evident from the expressions in
the continuous assignment statements.
• The Verilog concatenation {} operator concatenates two or more bits
of the datapaths to form n-bit vectors.

• The functionality in Comp_2_CA1 is evident from the expressions in
the continuous assignment statements.
• The Verilog concatenation {} operator concatenates two or more bits
of the datapaths to form n-bit vectors.

• Suppose now that we want to extend this model to compare two 32-
bit words
ØWe use the model from the previous example by declaring a parameter to size
the word length of the datapath.
Figure 5.6 Block diagram symbol for a 32-bit comparator.

Dataflow/RTL Models
• Dataflow models for synchronous machines are also referred to as RTL
(register transfer level) models because they describe register activity
in a synchronous machine.
• The level-sensitive cyclic behavior in Comp_2_RTL executes and
updates the outputs whenever a bit of either datapath changes.

Dataflow/RTL Models
• The assignment operator (=) in this example is the ordinary procedural
assignment, blocking assignment.
• The statements are executed in the listed order, with the storage of
value occurring immediately after any statement executes and before
the next statement can execute.

Dataflow/RTL Models
• The shift register shown in Figure 5-7 is described below by a
synchronous cyclic behavior with a list of procedural assignments using
the blocking assignment operator (=).
Figure 5.7 A 4-bit serial shift register.
Figure 5.8 Circuit synthesized as a result of expression

substitution in an incorrect model of a 4-bit serial shift register.
Dataflow/RTL Models
• An equivalent model of the 4-bit serial shift register shown in Figure 5-
7 is described below with nonblocking assignment operators (<=).
Figure 5.7 A 4-bit serial shift register.

Algorithm-Based Models
• The algorithm prescribes a sequence of procedural assignments within
a cyclic behavior.
• The outcome of executing the statements determines the values of
storage variables and, ultimately, the output of the machine.
• This style is most challenging for a synthesis tool because it must
perform what is referred to as architectural synthesis, which extracts
the resources (e.g., determines actual requirements for processors,
datapaths, and hardware memory) and scheduling requirements that
support the algorithm and then maps the description into an RTL
model whose logic can be synthesized.
• Not all algorithms can be implemented in hardware.

Algorithm-Based Models
• By initializing all variables to 0, the
algorithm in Comp_2_ algo need
assign only by exception to the
original value, resulting in
simplified code.
• Then the algorithm traverses a
decision tree to determine which
of the three outputs to assert.
• The non-asserted outputs will
retain the value that was assigned
to them at the beginning of the
sequence. Figure 5.9 Synthesis results derived from CompComp_2_algo.

Naming Conventions
• Design teams in industry follow elaborate enterprise-specific rules that
govern the style of their Verilog models.
• Other rules govern the use of upper- and lower-case text, and naming
conventions for signals, modules, functions, tasks, and ports, with the
aim of increasing the readability and the re-usability of the code
• Signals should be given names that describe their use (e.g., clock), and
modules, functions and tasks should be given names that describe the
encapsulated functionality (e.g., comparator).

Simulation with Behavioral Models
• An event at the input of a primitive causes the simulator to schedule
an updating event for its output.
ØAn event in the RHS expression of a continuous assignment statement –
causesà scheduling of an event for LHS variable
• Simulators in a cyclic behavior, their statements execute sequentially,
in the same time step, until the simulator encounters either:
1. A delay-control operator (#).
2. An event-control operator (@).
3. A wait construct.
4. The last statement of the behavior.

Behavioral Models of Multiplexers, Encoders and
Decoders
• Mux_4_32_case is a behavioral model of the four-channel, 32-bit,
multiplexer shown in Figure 5-10 with a three-state output.
Figure 5.10 A four-channel, 32-bit

multiplexer.

Decoders
• An alternative model uses nested conditional statements (if) to model
a multiplexer. The model Mux_4_32_if also includes a continuous
assignment that forms a three-state output.
Figure 5.10 A four-channel, 32-bit

multiplexer.

Decoders
• Two implementations of an 8:3 encoder are shown below.
Figure 5.11 Result of synthesizing an encoder described by

iƒ statements or a case statement, as shown in Example 5.22.

Decoders
• Alternative behaviors describing an 8:3 priority encoder are shown below.
Figure 5.12 Block diagram and circuit synthesized

for the 8:3 priority encoder described in Example 5.23.

Decoders
• A 3:8 decoder is described by the alternative behaviors shown below.
Figure 5.13 Block diagram and circuit synthesized

from a behavioral model of a 3:8 decoder.

Decoders
• The seven-segment light-emitting diode (LED) display depicted in Figure 5-14 is a
useful circuit in many applications using prototyping boards.
Figure 5.14 A
seven-segment
LED display.

Dataflow Models of a Linear-Feedback Shift Register
• RTL models are popular in industry because they are easily synthesized by modern
tools for electronic design automation (EDA).
• Let’s have an example illustrates an RTL model of a synchronous circuit, an
autonomous linear-feedback shift register (LFSR) that executes concurrent
transformations on a datapath under the synchronizing control of its only input, a
clock signal.

• Linear-feedback shift registers (LFSRs) are commonly used in data-compression
circuits implementing a signature analysis technique called cyclic-redundancy
check (CRC).
• Autonomous LFSRs are used in applications requiring pseudo-random binary
numbers.
• For example,
Ø An autonomous LFSR can be a random pattern generator providing stimulus patterns to a
circuit.
Ø The response to these patterns can be compared to the circuit’s expected response and
thereby reveal the presence of an internal fault.

• The Verilog code below describes an eight-cell autonomous LFSR with a
synchronous (edge-sensitive) cyclic behavior using an RTL style of design.
Figure 5.15 LFSR with modulo-2 (exclusive-or) addition.
CpE-477: HDL-based Design Dr. A. Fairouz Figure 5.16 Data movement in an LFSR 39
with modulo-2 (exclusive-or) addition.
Modeling Digital Machines with Repetitive Algorithms
• Mode again the LFSR here by Auto_LFSR_ALGO, an algorithm-based behavioral
model that uses a for loop to sequence through the concurrent(nonblocking)
register assignments one at a time, beginning with the cell to the right of the most
significant bit (MSB).
Figure 5.15 LFSR with modulo-2 (exclusive-or) addition.
Figure 5.17 Register contents

after execution of the ƒor loop.
• Verilog has three additional loop constructs for describing repetitive algorithms:
repeat, while, and forever.
Ø Repeat: executes an associated statement or block of statements a specified number of times.
Ø While: executes while the condition is true.
Ø Forever: unconditional repetitive execution of statements.
Figure 5.19 Clock waveform

implemented with a forever loop.
Machines with Multicycle Operations
• Some digital machines have repetitive operations distributed over
multiple clock cycles.
• This activity can be modeled in Verilog by a synchronous cyclic
behavior that has as many nested edge-sensitive event-control
expressions as are needed to complete the operations.

• The implicit state machine add_4cycle adds four successive samples on
a data bus.
• The disable statement is used to prematurely terminate a named block
of procedural statements.

Figure 5.20 Circuit synthesized for a four-sample adder.

Functions and Tasks in Verilog
• Tasks are declared within a module, and they may be referenced only from within a cyclic
or single-pass behavior.
• Tasks have the following features:
Øtasks are defined in the module in which they are used. It is possible to define a task
in a separate file and use the compile directive 'include to include the task in the file
which instantiates the task.
Øtasks can include timing delays, like posedge, negedge, # delay and wait.
Øtasks can have any number of inputs and outputs.
ØThe variables declared within the task are local to that task. The order of declaration
within the task defines how the variables passed to the task by the caller are used.
Øtasks can take, drive and source global variables, when no local variables are used.
When local variables are used, basically output is assigned only at the end of task
execution.
Øtasks can call another task or function.
Øtasks can be used for modeling both combinational and sequential logic.
ØA task must be specifically called with a statement, it cannot be used within an
expression as a function can.

• The module adder_task contains a user-defined task that adds two 4-bit words
and a carry bit.
Figure 5.21 Circuit synthesized from

adder_task.

• Functions are declared within a parent module and can be referenced in any valid
expression.
Øfunctions are defined in the module in which they are used. It is possible to define
functions in separate files and use compile directive 'include to include the function in
the file which instantiates the task.
Øfunctions can not include timing delays, like posedge, negedge, # delay, which means
that functions should be executed in "zero" time delay.
Øfunctions can have any number of inputs but only one output.
ØThe variables declared within the function are local to that function. The order of
declaration within the function defines how the variables passed to the function by
the caller are used.
Øfunctions can take, drive, and source global variables, when no local variables are
used. When local variables are used, basically output is assigned only at the end of
function execution.
Øfunctions can be used for modeling combinational logic.
Øfunctions can call other functions, but can not call tasks.
• The Verilog model arithmetic_unit uses functions with descriptive names to make
the source code more readable.
Figure 5.22 Circuit synthesized from arithmetic_unit.

Behavioral Models of Counters, Shift Registers and
Register Files
• Counters, shift registers, and register files are important datapath units and are
used in many digital machines.
• The storage elements of counters and registers usually have the same
synchronizing and control signals.
• A counter generates a sequence of related binary words; a register stores data that
can be retrieved and/or overwritten under the control of a host processor.
• The cells of a shift register exchange contents in a systematic and synchronous
manner.
• Register files are a collection of registers that share the same synchronizing and
control signals.

Counters
• A ring counter asserts a single bit that circulates through the
counter in a synchronous manner (8-bit counter in this example).
Figure 5.27 Data movement in an

Figure 5.28 Ring counter synthesized from a Verilog
behavioral description (asynchronous reset).
CpE-477: HDL-based Design 8-bit ring counter. Dr. A. Fairouz 56
Shift Registers
• A register with reset and parallel load is synthesized from the Verilog description of
Par_load_reg4.
Figure 5.31 4-bit register with parallel load, synthesized

from a Verilog behavior.

Register Files
• Usually implemented by D-type flip-flops, register files are not used for mass
storage because they occupy significantly more silicon area than compiled memory.
• A common application combines a register file in tandem with an ALU.
• The single-input, dual-output register file modeled below.
Figure 5.34 A 32-word register file in tandem with

an ALU with a 32-bit datapath.

Metastability and Synchronizers
• Flip-flops and latches are subject to a condition called metastability.
• A hardware latch can enter the metastable state if a pulse at one of its inputs is too
short, or if both inputs are asserted either simultaneously or within a sufficiently
small interval of each other.
• If a mechanical switch generates an input that drives a flip-flop of a circuit, the
input signal could oscillate during the setup interval of the flip-flop and cause it to
enter a metastable state.
• There are various ways to deal with switch
bounce, depending on the application.
Ø For example, the push-button switches on a
typical student prototyping board for an
FPGA have a resistor-capacitor (RC) lowpass
filter and a buffer placed between the switch
and the chip
Figure 5.35 A push-button input device with closure
CpE-477: HDL-based Design Dr. A. Fairouz bounce. 63
• As an alternative remedy, the circuit shown in Figure 5-36 uses a single pole-double
throw switch to eliminate the effect of the bounce.
• A flip-flop may enter a metastable state if the data input changes within a finite
interval before or after the clock transition. The output of the device has an output
between a 0 and 1, and cannot be decoded with certainty.
• If inputs are allowed to be asynchronous,
metastability cannot be prevented, but its
effect can be reduced.
Figure 5.37 An illustration of how metastability can Figure 5.36 A NAND latch configuration for eliminating the
happen in a physical system. effects of switch closure bounce.
• There are two basic types of synchronizer circuits:
1. Asynchronous input pulse > clock period à (Fig. 5.38 a)
• The maximum latency is n+1, where n is the number of stages in the synchronizer chain.
2. Asynchronous input pulse < clock period à (Fig. 5.38 b)
• The maximum latency is n, where n is the number of stages in the synchronizer chain.
Figure 5.38 Synchronizer circuits for asynchronous input signals: (a) circuit for use when the width of the asynchronous input pulse is greater than the period of the
clock, (b) circuit for use when the width of the asynchronous input pulse is less than the period of the clock, (c) waveforms in the circuit of (b) when the asynchronous
pulse does not cause a metastable condition, and (d) waveforms of the circuit in (b) when the asynchronous input signal causes a metastable condition.

• There are two basic types of synchronizer circuits:
1. Asynchronous input pulse > clock period à (Fig. 5.38 a)
2. Asynchronous input pulse < clock period à (Fig. 5.38 b)
Figure 5.38 Synchronizer circuits for asynchronous input signals: (a) circuit for use when the width of the asynchronous input pulse is greater than the period of the
clock, (b) circuit for use when the width of the asynchronous input pulse is less than the period of the clock, (c) waveforms in the circuit of (b) when the asynchronous
pulse does not cause a metastable condition, and (d) waveforms of the circuit in (b) when the asynchronous input signal causes a metastable condition.

• Synchronizers are also used when a signal must cross a boundary between two
clock domains. If clock_1 in Figure 5-39 is slower than clock_2, the synchronizer in
Figure 5-38(a) should be used to synchronize the interface signals controlling data
transfer between the domains,
• Otherwise the synchronizer in Figure 5-38(b) should be used. Care must be taken
to anticipate that more than one active edge of clock_2 will occur while
asynch_in is asserted if asynch_in is synchronized to clock_1, that is, it has
duration.
Figure 5.39 A situation requiring synchronization

across clock domains.

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COLLEGE OF

Logic Design with

Dr. Abbas A. Fairouz

CpE-477: HDL-based Design Dr. A. Fairouz 2

CpE-477: HDL-based Design Dr. A. Fairouz 3

CpE-477: HDL-based Design Dr. A. Fairouz 4

CpE-477: HDL-based Design Dr. A. Fairouz 5

CpE-477: HDL-based Design Dr. A. Fairouz 6

Figure 5.2 A two-channel mux with 32-bit datapaths.

CpE-477: HDL-based Design Dr. A. Fairouz 7

CpE-477: HDL-based Design Dr. A. Fairouz 8

Figure 5.3 Verilog counterparts of three

CpE-477: HDL-based Design Dr. A. Fairouz 9

Figure 5.4 Simulation results for a transparent latch modeled

CpE-477: HDL-based Design Dr. A. Fairouz 10

Figure 5.5 Simulation results for a transparent

CpE-477: HDL-based Design Dr. A. Fairouz 12

CpE-477: HDL-based Design Dr. A. Fairouz 13

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CpE-477: HDL-based Design Dr. A. Fairouz 15

CpE-477: HDL-based Design Dr. A. Fairouz 16

CpE-477: HDL-based Design Dr. A. Fairouz 17

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Figure 5.6 Block diagram symbol for a 32-bit comparator.

CpE-477: HDL-based Design Dr. A. Fairouz 22

CpE-477: HDL-based Design Dr. A. Fairouz 23

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Figure 5.7 A 4-bit serial shift register.

Figure 5.8 Circuit synthesized as a result of expression

Figure 5.7 A 4-bit serial shift register.

CpE-477: HDL-based Design Dr. A. Fairouz 26

CpE-477: HDL-based Design Dr. A. Fairouz 27

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Figure 5.10 A four-channel, 32-bit

CpE-477: HDL-based Design Dr. A. Fairouz 31

Figure 5.10 A four-channel, 32-bit

CpE-477: HDL-based Design Dr. A. Fairouz 32

Figure 5.11 Result of synthesizing an encoder described by

CpE-477: HDL-based Design Dr. A. Fairouz 33

Figure 5.12 Block diagram and circuit synthesized

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Figure 5.13 Block diagram and circuit synthesized

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Figure 5.15 LFSR with modulo-2 (exclusive-or) addition.

Figure 5.15 LFSR with modulo-2 (exclusive-or) addition.

Figure 5.17 Register contents

Figure 5.19 Clock waveform

CpE-477: HDL-based Design Dr. A. Fairouz 43

CpE-477: HDL-based Design Dr. A. Fairouz 44

Figure 5.20 Circuit synthesized for a four-sample adder.

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Figure 5.21 Circuit synthesized from

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Figure 5.22 Circuit synthesized from arithmetic_unit.