CHAPTER 4

MOS CAPACITOR
 MOS (metal-oxide-semiconductor) capacitor is the
most useful device to study semiconductor surface
properties, it is also a key building block for
MOSFET and related devices.

 In this chapter we consider

 The ideal and practical metal−SiO2−Si (MOS)
capacitors.
 The inversion condition and the threshold voltage
of an MOS capacitor.
 C-V and I-V characteristics of MOS capacitors.

1
 MOS CAPACITOR
 Figure 1 shows (a) perspective view and (b) cross-section of an
metal-oxide-semiconductor (MOS) capacitor.

 Fabrication steps of a silicon MOS capacitor

 Thermal oxidation of a 𝐒𝐒𝐒𝐒 wafer to form a SiO2 layer on Si surface.
 Deposit a metal layer on SiO2 and define the metal plate.
 An ohmic contact is made on the bottom of the Si wafer.
 V is the applied voltage on the metal plate (positive or negative
with respect to the ohmic contact).
 d is the thickness of the oxide. 2
 IDEAL MOS CAPACITOR
 An ideal MOS capacitor is defined as:
 Flat band at 𝑽𝑽 = 𝟎𝟎

 Charges at metal surface and in semiconductor only

 Oxide resistivity is infinity

 Figure 2 shows energy band diagram of an ideal MOS capacitor

at 𝑽𝑽 = 𝟎𝟎.

3
 IDEAL MOS CAPACITOR (Cont.)
 For the flat-band condition
𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 𝒒𝒒𝝓𝝓𝒎𝒎 − 𝒒𝒒𝝓𝝓𝒔𝒔 = 𝒒𝒒𝝓𝝓𝒎𝒎 − (𝒒𝒒𝛘𝛘 + 𝑬𝑬𝒈𝒈/𝟐𝟐 + 𝒒𝒒𝝍𝝍𝑩𝑩 ) = 𝟎𝟎
where 𝝓𝝓𝒎𝒎 , 𝝓𝝓𝒔𝒔 ∶ work function of metal and semiconductor.
(from Fermi level to vacuum level)
𝝌𝝌: electron affinity
(from bottom of conduction band to
vacuum level)
𝒒𝒒𝝍𝝍𝑩𝑩 : 𝑬𝑬𝒊𝒊 – 𝑬𝑬𝑭𝑭

 Appendix D for Greek Alphabet:

𝝓𝝓(phi), 𝛘𝛘(ki), 𝛙𝛙(psi)

4
THREE CASES AT SEMICONDUCTOR SURFACE
 When I = 0 , dEF /dx = 𝟎𝟎, i.e., Fermi level is flat. (Eq.6 p. 84 of Ch.3).
But the 𝑬𝑬𝑪𝑪 and 𝑬𝑬𝑽𝑽 can bend upward and downward.
 V < 𝟎𝟎
𝒑𝒑𝒑𝒑 = 𝒏𝒏𝒊𝒊 𝒆𝒆(𝑬𝑬𝒊𝒊 −𝑬𝑬𝑭𝑭)⁄𝒌𝒌𝒌𝒌 (Eq. 26 p. 37)
∵ (𝑬𝑬𝒊𝒊 − 𝑬𝑬𝑭𝑭 ) ↑
∴ 𝒑𝒑𝒑𝒑 > 𝒑𝒑𝒑𝒑𝒑𝒑 (more majority carriers)
Accumulation case
 V > 𝟎𝟎
𝑸𝑸𝑺𝑺 = −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾
(no 𝒏𝒏𝒑𝒑 , 𝒑𝒑𝒑𝒑 in the depletion region)
Depletion case
 V ≫ 𝟎𝟎
𝒏𝒏𝒑𝒑 = 𝒏𝒏𝒊𝒊 𝒆𝒆(𝑬𝑬𝑭𝑭−𝑬𝑬𝒊𝒊 )⁄𝒌𝒌𝒌𝒌 (Eq. 25 p. 36)
∵ (𝑬𝑬𝑭𝑭 − 𝑬𝑬𝒊𝒊 ) > 𝟎𝟎
∴ 𝒏𝒏𝒑𝒑 > 𝒏𝒏𝒊𝒊 (minority carrier density
𝒑𝒑𝒑𝒑 < 𝒏𝒏𝒊𝒊 is larger then the
majority carrier density)
Inversion case 5
 SURFACE DEPLETION REGION

 𝝍𝝍 electrostatic potential = 𝟎𝟎 in the bulk

= 𝝍𝝍𝑺𝑺 at the surface
(𝝍𝝍𝒔𝒔 𝐢𝐢𝐢𝐢 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜 𝐭𝐭𝐭𝐭𝐭𝐭 surface potential)

𝒏𝒏𝒑𝒑 𝒙𝒙 = 𝒏𝒏𝒊𝒊 𝒆𝒆 𝑬𝑬𝑭𝑭 −𝑬𝑬𝒊𝒊 ⁄𝒌𝒌𝒌𝒌 = 𝒏𝒏𝒊𝒊 𝒆𝒆𝒒𝒒 𝝍𝝍−𝝍𝝍𝑩𝑩 ⁄𝒌𝒌𝒌𝒌 = 𝒏𝒏𝒑𝒑𝒑𝒑 𝒆𝒆𝒒𝒒𝝍𝝍⁄𝒌𝒌𝒌𝒌 (5a) 𝑬𝑬𝑭𝑭 ≡ −𝒒𝒒𝝍𝝍𝑩𝑩

𝑬𝑬𝒊𝒊 −𝑬𝑬𝑭𝑭 ⁄𝒌𝒌𝒌𝒌 𝝍𝝍𝑩𝑩 −𝝍𝝍 ⁄𝒌𝒌𝒌𝒌 𝑬𝑬𝒊𝒊 ≡ −𝒒𝒒𝝍𝝍

𝒑𝒑𝒑𝒑 𝒙𝒙 = 𝒏𝒏𝒊𝒊 𝒆𝒆 = 𝒏𝒏𝒊𝒊 𝒆𝒆𝒒𝒒 = 𝒑𝒑𝒑𝒑𝒐𝒐 𝒆𝒆−𝒒𝒒𝝍𝝍⁄𝒌𝒌𝒌𝒌 (5b)

At the surface
𝝍𝝍𝒔𝒔 −𝝍𝝍𝑩𝑩 ⁄𝒌𝒌𝒌𝒌
𝒏𝒏𝒔𝒔 = 𝒏𝒏𝒊𝒊 𝒆𝒆𝒒𝒒 = 𝒏𝒏𝒑𝒑𝒐𝒐 𝒆𝒆𝒒𝒒𝝍𝝍𝒔𝒔 ⁄𝒌𝒌𝒌𝒌 (6a)

𝒑𝒑𝒔𝒔 = 𝒏𝒏𝒊𝒊 𝒆𝒆𝒒𝒒 𝝍𝝍𝑩𝑩 −𝝍𝝍𝒔𝒔 ⁄𝒌𝒌𝒌𝒌 = 𝒑𝒑𝒑𝒑𝒐𝒐 𝒆𝒆−𝒒𝒒𝝍𝝍𝒔𝒔⁄𝒌𝒌𝒌𝒌 (6b)

6
 SURFACE DEPLETION REGION (Cont.)
 Figure 4 shows the energy band diagram at surface of
a p-type semiconductor.

𝝍𝝍𝒔𝒔 < 𝟎𝟎 Accumulation of holes

𝝍𝝍𝒔𝒔 = 𝟎𝟎 Flat band
𝝍𝝍𝑩𝑩 > 𝝍𝝍𝒔𝒔 > 𝟎𝟎 Depletion of holes
𝝍𝝍𝒔𝒔 = 𝝍𝝍𝑩𝑩 𝒏𝒏𝒔𝒔 = 𝒑𝒑𝒔𝒔 = 𝒏𝒏𝒊𝒊 intrinsic
𝝍𝝍𝒔𝒔 > 𝝍𝝍𝑩𝑩 Inversion (as shown) 7
 ELECTROSTATIC POTENTIAL
 The electrostatic potential 𝝍𝝍 as a function of distance can be
obtained from the Poisson equation
𝒅𝒅𝟐𝟐 𝝍𝝍 𝝆𝝆(𝒙𝒙)
𝟐𝟐
=−
𝒅𝒅𝒙𝒙 𝝐𝝐𝒔𝒔
𝝆𝝆 𝒙𝒙 = 𝒒𝒒 𝑵𝑵+ −
𝑫𝑫 − 𝑵𝑵𝑨𝑨 + 𝒑𝒑𝒑𝒑 − 𝒏𝒏𝒑𝒑 = total space-charge density

At 𝒙𝒙 = ∞, 𝝍𝝍 ∞ = 𝟎𝟎 and 𝝆𝝆 ∞ = 𝟎𝟎
𝑵𝑵+ −
𝑫𝑫 − 𝑵𝑵𝑨𝑨 = 𝒏𝒏𝒑𝒑𝒐𝒐 − 𝒑𝒑𝒑𝒑𝒐𝒐

Eq. 5b Eq. 5a
𝒅𝒅𝟐𝟐 𝝍𝝍 𝒒𝒒
∴ 𝟐𝟐
=− 𝒏𝒏𝒑𝒑𝒑𝒑 − 𝒑𝒑𝒑𝒑𝒑𝒑 + 𝒑𝒑𝒑𝒑 − 𝒏𝒏𝒑𝒑
𝒅𝒅𝒙𝒙 𝝐𝝐𝒔𝒔
𝒒𝒒 𝒒𝒒
=− 𝒑𝒑𝒑𝒑𝒑𝒑 (𝒆𝒆−𝜷𝜷𝜷𝜷 − 𝟏𝟏) − 𝒏𝒏𝒑𝒑𝒑𝒑 (𝒆𝒆𝜷𝜷𝜷𝜷 − 𝟏𝟏) where 𝜷𝜷 ≡
𝝐𝝐𝒔𝒔 𝒌𝒌𝒌𝒌
8
 ELECTROSTATIC POTENTIAL (Cont.)
 By solving the above Poisson equation, we obtain the relation
between the surface electric field (𝓔𝓔𝒔𝒔 ≡ − 𝒅𝒅𝝍𝝍𝒔𝒔⁄𝒅𝒅𝒅𝒅) and the surface
potential 𝝍𝝍𝒔𝒔 . Once 𝓔𝓔𝒔𝒔 is known, the charge in the semiconductor
per unit area is given by:
𝟐𝟐𝝐𝝐𝒔𝒔 𝒌𝒌𝒌𝒌 𝒏𝒏𝒑𝒑𝒑𝒑
𝑸𝑸𝒔𝒔 = 𝝐𝝐𝒔𝒔 𝓔𝓔𝒔𝒔 = 𝑭𝑭 𝜷𝜷𝝍𝝍𝒔𝒔 ,
𝒒𝒒𝑳𝑳𝑫𝑫 𝒑𝒑𝒑𝒑𝒑𝒑

where 𝑳𝑳𝑫𝑫 = Debye length ≡ 𝒌𝒌𝒌𝒌𝝐𝝐𝒔𝒔

𝒑𝒑𝒑𝒑𝒐𝒐 𝒒𝒒𝟐𝟐

𝒏𝒏𝒑𝒑𝒐𝒐 𝒏𝒏𝒑𝒑𝒐𝒐
𝑭𝑭 𝜷𝜷𝝍𝝍𝒔𝒔 , ≡ exp −𝜷𝜷𝝍𝝍𝒔𝒔 + 𝜷𝜷𝝍𝝍𝒔𝒔 − 𝟏𝟏 + exp 𝜷𝜷𝝍𝝍𝒔𝒔 − 𝜷𝜷𝝍𝝍𝒔𝒔 − 𝟏𝟏
𝒑𝒑𝒏𝒏𝒐𝒐 𝒑𝒑𝒏𝒏𝒐𝒐

Accumulation Depletion Inversion

(see Reference Book #2 pp.200-203)

9
CHARGE IN THE SEMICONDUCTOR
VERSUS APPLIED VOLTAGE
When 𝝍𝝍𝒔𝒔 = 𝟐𝟐𝝍𝝍𝑩𝑩
Strong inversion starts,
𝑸𝑸𝒔𝒔 increases rapidly.
A very small increase in 𝝍𝝍𝒔𝒔
(corresponding to a very
small increase in depletion
width W) results in a large
increase in 𝑸𝑸𝒔𝒔 . Thus
W → W𝒎𝒎𝒎𝒎𝒎𝒎 (maximum width)
𝑸𝑸𝒔𝒔 = 𝑸𝑸𝒏𝒏 + 𝑸𝑸𝒔𝒔𝒔𝒔
𝑸𝑸𝒏𝒏 = charge in the
inversion region
𝑸𝑸𝒔𝒔𝒔𝒔 = −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾 (ionized
acceptors per unit
area in the depletion
region)
𝑸𝑸𝒔𝒔𝒔𝒔 ≅ −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝒎𝒎 (at and
beyond strong
inversion) 10
 MAXIMUM DEPLETION WIDTH
 In the depletion case, there are no electrons and holes in the
depletion region. For p-type Si, 𝑵𝑵𝑫𝑫 = 𝟎𝟎. Therefore

𝝆𝝆𝒔𝒔 = 𝒒𝒒 𝑵𝑵
�𝑫𝑫 − 𝑵𝑵𝑨𝑨 + 𝒑𝒑
�𝒑𝒑 + 𝒏𝒏
�𝒑𝒑 = −𝒒𝒒𝑵𝑵𝑨𝑨
0 0 0
𝒅𝒅𝟐𝟐 𝝍𝝍 +𝒒𝒒𝑵𝑵𝑨𝑨
∴ =
𝒅𝒅𝒙𝒙𝟐𝟐 𝝐𝝐𝒔𝒔

The integration of the Poisson equation will yield a potential

distribution identical to that for a one-sided n+ p junction:

𝒙𝒙 𝟐𝟐
𝝍𝝍 = 𝝍𝝍𝒔𝒔 𝟏𝟏 − (8)
𝑾𝑾

𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝟐𝟐 (9)

𝝍𝝍𝒔𝒔 =
𝟐𝟐𝝐𝝐𝒔𝒔
11
 MAXIMUM DEPLETION WIDTH (Cont.)

 At the onset of strong inversion

∵ 𝒑𝒑𝒑𝒑𝒑𝒑 = 𝑵𝑵𝑨𝑨 = 𝒏𝒏𝒊𝒊 exp 𝒒𝒒𝝍𝝍𝑩𝑩 ⁄𝒌𝒌𝒌𝒌

𝟐𝟐𝟐𝟐𝟐𝟐 𝑵𝑵𝑨𝑨
∴ 𝝍𝝍𝒔𝒔 𝒊𝒊𝒊𝒊𝒊𝒊 = 𝟐𝟐𝝍𝝍𝑩𝑩 = 𝐥𝐥𝐥𝐥 (10)
𝒒𝒒 𝒏𝒏𝒊𝒊

The maximum depletion width 𝑾𝑾𝒎𝒎 can be obtained from Eqs. 9 & 10

𝟐𝟐𝝐𝝐𝒔𝒔 𝝍𝝍𝒔𝒔 inv 𝝐𝝐𝒔𝒔 𝒌𝒌𝒌𝒌 ln 𝑵𝑵𝑨𝑨 ⁄𝒏𝒏𝒊𝒊 (11)

𝑾𝑾𝒎𝒎 = = 𝟐𝟐
𝒒𝒒𝑵𝑵𝑨𝑨 𝒒𝒒𝟐𝟐 𝑵𝑵𝑨𝑨

𝑸𝑸𝒔𝒔𝒔𝒔 = −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾 = − 𝟐𝟐𝟐𝟐𝝐𝝐𝒔𝒔 𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 ) (12)

12
 MAXIMUM DEPLETION WIDTH (Cont.)
 Figure 5 shows the maximum depletion-layer width
versus impurity concentration of Si and GaAs under
strong-inversion condition.

13
 EXAMPLE 1
 For an ideal metal−SiO2−Si capacitor having 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 ,
calculate the maximum width of the surface depletion region.

SOLUTION
At room temperature, 𝒌𝒌𝒌𝒌⁄𝒒𝒒 = 0.026 V and 𝒏𝒏𝒊𝒊 = 9.65 × 10𝟗𝟗 cm-3,
the dielectric permittivity of Si is 11.9 × 8.85 × 10−𝟏𝟏𝟏𝟏 F⁄cm.
From Eq. 11

𝟏𝟏𝟏𝟏. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎 𝐥𝐥𝐥𝐥 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 ⁄𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗
𝑾𝑾𝒎𝒎 = 𝟐𝟐
𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏

= 𝟏𝟏𝟏𝟏−𝟓𝟓 cm= 0.1 μm

14
 IDEAL MOS CURVES

 Fig.6

(a) Band diagram of an ideal MOS

capacitor.

 (b) Charge distribution under

inversion condition.

𝝆𝝆𝒔𝒔 𝒙𝒙 𝐯𝐯𝐯𝐯. 𝒙𝒙

15
 IDEAL MOS CURVES (cont.)

 (c) Electric field distribution

𝝆𝝆𝒔𝒔 𝑽𝑽𝟎𝟎
𝓔𝓔 = � 𝒅𝒅𝒅𝒅
𝝐𝝐𝒔𝒔 𝝍𝝍𝒔𝒔

Total area= 𝑽𝑽 = 𝑽𝑽𝟎𝟎 + 𝝍𝝍𝒔𝒔

 (d) Potential distribution

𝝍𝝍 = − � 𝓔𝓔𝒅𝒅𝒅𝒅

16
 IDEAL MOS CURVES (Cont.)
 From Fig. 6a 𝑽𝑽 (applied voltage) = 𝑽𝑽𝟎𝟎 + 𝝍𝝍𝒔𝒔
𝑽𝑽𝟎𝟎 (voltage across the oxide) = 𝓔𝓔𝟎𝟎 𝒅𝒅
𝟎𝟎
𝝆𝝆𝒔𝒔 𝑸𝑸𝒎𝒎 𝑸𝑸𝒔𝒔
𝓔𝓔𝟎𝟎 = � 𝒅𝒅𝒅𝒅 = = (13)
−𝒅𝒅 𝝐𝝐𝒐𝒐𝒐𝒐 𝝐𝝐𝒐𝒐𝒐𝒐 𝝐𝝐𝒐𝒐𝒐𝒐
𝑸𝑸𝒔𝒔 𝑸𝑸𝒔𝒔 𝝐𝝐𝒐𝒐𝒐𝒐
∴ 𝑽𝑽𝟎𝟎 = 𝒅𝒅 = where 𝑪𝑪𝒐𝒐 ≡ (14)
𝝐𝝐𝒐𝒐𝒐𝒐 𝑪𝑪𝒐𝒐 𝒅𝒅
The total capacitance is a series combination of 𝑪𝑪𝒐𝒐
𝝐𝝐𝒔𝒔
and 𝑪𝑪𝒋𝒋 ≡
𝑾𝑾 𝑪𝑪𝒐𝒐 𝑪𝑪𝒋𝒋 (15)
∴ 𝑪𝑪 =
𝑪𝑪𝒐𝒐 + 𝑪𝑪𝒋𝒋
 From Eqs. 9, 13, 14, and 15
𝑪𝑪 𝟏𝟏 (16)
=
𝑪𝑪𝒐𝒐
𝟐𝟐𝝐𝝐𝟐𝟐𝒐𝒐𝒐𝒐 𝑽𝑽
𝟏𝟏 +
𝒒𝒒𝑵𝑵𝑨𝑨 𝝐𝝐𝒔𝒔 𝒅𝒅𝟐𝟐 17
 IDEAL MOS CURVES (Cont.)
 The Threshold Voltage 𝑽𝑽𝑻𝑻
𝑽𝑽𝑻𝑻 is defined as the voltage at the onset of strong inversion
when 𝝍𝝍𝒔𝒔 → 𝝍𝝍𝒔𝒔 (inv), and 𝑾𝑾 → 𝑾𝑾𝒎𝒎 or 𝑸𝑸𝒔𝒔 = 𝑸𝑸𝒏𝒏 + 𝑸𝑸𝒔𝒔𝒔𝒔
𝑸𝑸𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝒎𝒎
∴ 𝑽𝑽𝑻𝑻 = + 𝝍𝝍𝒔𝒔 inv = + 𝝍𝝍𝒔𝒔 (inv) small 𝒒𝒒𝑵𝑵𝑨𝑨 W𝒎𝒎
𝑪𝑪𝒐𝒐 𝑪𝑪𝒐𝒐
𝟐𝟐𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑨𝑨 (𝟐𝟐𝝍𝝍𝑩𝑩 )
= + 𝟐𝟐𝝍𝝍𝑩𝑩 (17)
𝑪𝑪𝒐𝒐

 The Minimum Capacitance

At strong inversion, 𝑾𝑾 → 𝑾𝑾𝒎𝒎 , the total capacitance will reach a
minimum value.
𝝐𝝐𝒐𝒐𝒐𝒐 𝝐𝝐𝒔𝒔
𝑪𝑪𝒐𝒐 𝑪𝑪𝒋𝒋,𝒎𝒎𝒎𝒎𝒎𝒎 𝒅𝒅 𝑾𝑾𝒎𝒎 𝝐𝝐𝒐𝒐𝒐𝒐
𝑪𝑪𝒎𝒎𝒎𝒎𝒎𝒎 = = = (18)
𝑪𝑪𝒐𝒐 + 𝑪𝑪𝒋𝒋,𝒎𝒎𝒎𝒎𝒎𝒎 𝝐𝝐𝒐𝒐𝒐𝒐 𝝐𝝐𝒔𝒔 𝝐𝝐
+ 𝒅𝒅 + 𝒐𝒐𝒐𝒐 𝑾𝑾𝒎𝒎
𝒅𝒅 𝑾𝑾𝒎𝒎 𝝐𝝐𝒔𝒔
18
 IDEAL MOS CURVES (Cont. )
 In the accumulation region (𝑽𝑽 < 𝟎𝟎), no depletion region, accumulation
of holes at semiconductor surface.
𝑪𝑪 = 𝝐𝝐𝒐𝒐𝒐𝒐 ⁄𝒅𝒅 = 𝑪𝑪𝟎𝟎 (F⁄cm𝟐𝟐 )

 In the depletion region (𝟎𝟎 < 𝑽𝑽 < 𝑽𝑽𝑻𝑻 ), 𝑪𝑪 decreases as 𝑽𝑽 increases,

Eq.16.

 In the inversion region (𝑽𝑽 > 𝑽𝑽𝑻𝑻 ), the depletion region reaches the
maximum 𝑾𝑾𝒎𝒎 , and 𝑪𝑪𝒋𝒋 → 𝝐𝝐𝒔𝒔 ⁄𝑾𝑾𝒎𝒎 , total capacitance is given by Eq.18.

𝝐𝝐𝒐𝒐𝒐𝒐 ⁄𝒅𝒅 =
↙ Eq.16

↙ (Depletion)

p-type substrate (Inversion) n-type substrate

(Accumulation) , Eq. 18

Eq.17 19
 EXAMPLE 2
 For an ideal metal−SiO2−Si capacitor having 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 and
𝒅𝒅 = 𝟓𝟓 nm , calculate the minimum capacitance of the C−V curve.
The dielectric constant of SiO2 is 3.9 .

SOLUTION

𝜺𝜺𝒐𝒐𝒐𝒐 𝟑𝟑. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 −𝟕𝟕 F⁄cm𝟐𝟐

𝑪𝑪𝒐𝒐 = = = 𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏
𝒅𝒅 𝟓𝟓 × 𝟏𝟏𝟏𝟏−𝟕𝟕

𝑸𝑸𝒔𝒔𝒔𝒔 = −𝒒𝒒𝑵𝑵𝑨𝑨 𝑾𝑾𝒎𝒎 = −𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟏𝟏 × 𝟏𝟏𝟏𝟏−𝟓𝟓

= −𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏−𝟕𝟕 C⁄cm𝟐𝟐

𝑾𝑾𝒎𝒎 is obtained in Example 1.

20
 EXAMPLE 2 (Cont.)

𝟐𝟐𝟐𝟐𝟐𝟐 𝑵𝑵𝑨𝑨 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏

𝝍𝝍𝒔𝒔 inv ≈ 𝟐𝟐𝝍𝝍𝑩𝑩 = 𝐥𝐥𝐥𝐥 =2 × 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎 × 𝐥𝐥𝐥𝐥 = 𝟎𝟎. 𝟖𝟖𝟖𝟖 V
𝒒𝒒 𝒏𝒏𝒊𝒊 𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗

The minimum capacitance 𝑪𝑪𝒎𝒎𝒎𝒎𝒎𝒎 at 𝑽𝑽𝑻𝑻 is

𝝐𝝐𝒐𝒐𝒐𝒐 𝟑𝟑. 𝟗𝟗 × 𝟖𝟖. 𝟖𝟖𝟖𝟖 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏

𝑪𝑪𝒎𝒎𝒎𝒎𝒎𝒎 = =
𝝐𝝐𝒐𝒐𝒐𝒐 𝟑𝟑. 𝟗𝟗
𝒅𝒅 + 𝑾𝑾𝒎𝒎 𝟓𝟓 × 𝟏𝟏𝟏𝟏−𝟕𝟕 + 𝟏𝟏 × 𝟏𝟏𝟏𝟏−𝟓𝟓
𝝐𝝐𝒔𝒔 𝟏𝟏𝟏𝟏. 𝟗𝟗
= 𝟗𝟗. 𝟏𝟏 × 𝟏𝟏𝟏𝟏−𝟖𝟖 F⁄cm𝟐𝟐

Therefore, 𝑪𝑪𝒎𝒎𝒎𝒎𝒎𝒎 is about 13% of 𝑪𝑪𝒐𝒐 .

21
 FREQUENCY EFFECT ON MOS C-V CURVE

 Figure 7b shows the effect of frequency on the C-V curve

DC voltage

AC voltage

22
 FREQUENCY EFFECT ON MOS C-V CURVE
(Cont.)
 If the measurement frequency is low, generation-recombination
rates in the surface depletion region are equal to or greater than
the voltage variation, then the electron concentration (minority
carriers) can follow the alternating current signal and lead to
charge exchange with the inversion layer in step with the
measurement signal. Then the capacitance in strong inversion
will be 𝑪𝑪𝒐𝒐 . The onset of low- frequency curves occurs at
𝒇𝒇 ≤ 𝟏𝟏𝟏𝟏𝟏𝟏 Hz.
C

Low-frequency

High-frequency

𝑽𝑽𝑮𝑮
0 23
 SiO2 – Si MOS CAPACITOR

 Work function difference for p-type semiconductor

𝑬𝑬𝒈𝒈
𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 𝒒𝒒𝝓𝝓𝒎𝒎 − 𝒒𝒒𝝓𝝓𝒔𝒔 = 𝒒𝒒𝝓𝝓𝒎𝒎 − (𝒒𝒒𝝌𝝌 + + 𝒒𝒒𝝍𝝍𝑩𝑩 )
𝟐𝟐
For example, 𝒒𝒒𝝓𝝓𝒎𝒎 for Al is 4.1 eV, 𝒒𝒒𝝌𝝌 for Si is 4.05 eV

𝑵𝑵𝑨𝑨
∴ 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 4.1 − 4.05 + 0.56 + 0.0259 ln
𝒏𝒏𝒊𝒊

𝑵𝑵𝑨𝑨
= −0.51 − 0.0259 ln
𝒏𝒏𝒊𝒊

∴ 𝑵𝑵𝑨𝑨 ↑ and 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 ↓

24
 SiO2 – Si MOS CAPACITOR (Cont.)
 Figure 8 shows the work function difference as a function of
background impurity concentration for Al, n+ −, and p+ −
polysilicon gate materials.

25
 p+ POLYSILICON ON n-TYPE SI
 𝒒𝒒𝝌𝝌 = 4.05 eV, it is not a strong function of doping concentration.
𝑬𝑬𝒈𝒈 for heavily doped silicon is ~ 1.0 eV.
𝑞𝑞𝜙𝜙𝑚𝑚𝑚𝑚

4.05 4.05
= 5.05
4.05

1.0 𝑞𝑞𝑉𝑉𝑛𝑛

 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 5.05 − 4.05 + 𝒒𝒒𝑽𝑽𝒏𝒏 = 1.0 − 𝒒𝒒𝑽𝑽𝒏𝒏

At 𝑵𝑵𝑫𝑫 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 , 𝒒𝒒𝑽𝑽𝒏𝒏 = 0.382 eV, 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 0.618 eV
At 𝑵𝑵𝑫𝑫 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟖𝟖 cm−𝟑𝟑 , 𝒒𝒒𝑽𝑽𝒏𝒏 = 0.11 eV, 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 = 0.89 eV
26
 FLAT-BAND VOLTAGE
 In thermal equilibrium, we require

 The Fermi level must be a constant. i.e., 𝒅𝒅𝑬𝑬𝑭𝑭 ⁄𝒅𝒅𝒅𝒅 = 𝟎𝟎

(no current flows).

 The vacuum level must be continuous.

Figure 9b shows that the metal is positively charged,
and the semiconductor negatively charged.
To achieve flat-band condition, we have to apply a
voltage equal to 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 .
𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎
∴ 𝑽𝑽𝑭𝑭𝑭𝑭 = = 𝝓𝝓𝒎𝒎 − 𝝓𝝓𝒔𝒔 = flat−band voltage
𝒒𝒒

27
 FLAT-BAND VOLTAGE (Cont.)
 Figure 9 (a) Energy band diagram of an isolated metal and an
isolated semiconductor with an oxide layer between them. (b)
Energy band diagram of an MOS capacitor in thermal
equilibrium.

28
INTERFACE TRAPS AND OXIDE CHARGES
 Figure 10 shows terminology for the charges associated with
thermally oxidized silicon.

 Interface-trapped charge (𝑸𝑸𝒊𝒊𝒊𝒊 ) due to interruption of periodic

lattice structure.
 Fixed oxide charge (𝑸𝑸𝒇𝒇 ) located within 3nm of SiO2−Si interface.
 Oxide trapped charges (𝑸𝑸𝒐𝒐𝒐𝒐 ) due to defects in SiO2
 Mobile ionic charges (𝑸𝑸𝒎𝒎 ) mobile within the oxide under high
temperature, high-field operation, e.g., sodium ions. 29
 INTERFACE TRAPS
 Figure 11 shows that any interface-trap system consisting of both
acceptor states and donor states can be interpreted by an
equivalent distribution with a neutral level 𝑬𝑬𝟎𝟎 above which the
states are of the acceptor type and below which of the donor type.
When 𝑬𝑬𝑭𝑭 is above (below) 𝑬𝑬𝟎𝟎 , the net charge is − (+).

𝑬𝑬𝑭𝑭
𝑸𝑸𝒊𝒊𝒊𝒊 = −𝒒𝒒 � 𝑫𝑫𝒊𝒊𝒊𝒊 𝒅𝒅𝒅𝒅
𝑬𝑬𝟎𝟎

𝑬𝑬𝟎𝟎
𝑸𝑸𝒊𝒊𝒊𝒊 = +𝒒𝒒 � 𝑫𝑫𝒊𝒊𝒊𝒊 𝒅𝒅𝒅𝒅
𝑬𝑬𝑭𝑭

𝟏𝟏 𝒅𝒅𝑸𝑸𝒊𝒊𝒊𝒊
𝑫𝑫𝒊𝒊𝒊𝒊 = number of traps⁄ cm𝟐𝟐 −eV (20)
𝒒𝒒 𝒅𝒅𝒅𝒅
 When a voltage is applied, 𝑬𝑬𝑭𝑭 moves up or down, change of
charge in the interface traps occurs, → affect MOS C−V curves. 30
 INTERFACE TRAPS (Cont.)
 For thermally grown 𝐒𝐒𝐒𝐒𝐎𝐎𝟐𝟐 on 𝐒𝐒𝐒𝐒, the interface−trapped charges
can be passivated by low temperature (450℃) hydrogen
annealing:
𝑸𝑸𝒊𝒊𝒊𝒊 ⁄𝒒𝒒 ≈ 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟐𝟐 for 𝟏𝟏𝟏𝟏𝟏𝟏 − oriented Si
𝑸𝑸𝒊𝒊𝒊𝒊 ⁄𝒒𝒒 ≈ 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟐𝟐 for 𝟏𝟏𝟏𝟏𝟏𝟏 − oriented Si

 Therefore, for MOSFET integrated circuits, 𝟏𝟏𝟏𝟏𝟏𝟏 – oriented Si

wafers are used.

31
 FIXED OXIDE CHARGES 𝑸𝑸𝒇𝒇
 𝑸𝑸𝒇𝒇 is fixed, not a function of 𝝍𝝍𝒔𝒔 . When we terminate the
oxidation, some uncompleted silicon bonds (e.g., Si − Si or Si −
O bonds) at the surface may result in 𝑸𝑸𝒇𝒇 . Generally 𝑸𝑸𝒇𝒇 is
positive.

 W (for 𝑸𝑸𝒇𝒇 > 𝟎𝟎) is smaller than W (for 𝑸𝑸𝒇𝒇 = 𝟎𝟎), because some field
lines are terminated on 𝑸𝑸𝒇𝒇 . Thus C (for 𝑸𝑸𝒇𝒇 > 𝟎𝟎 ) increases,
causing the C−V curve to shift left (if 𝑸𝑸𝒇𝒇 < 𝟎𝟎, C−V will shift right)

32
 OXIDE CHARGES
 Figure 12 shows the effect of a sheet charge within the oxide.
(a) Condition for 𝑽𝑽𝑮𝑮 = 𝟎𝟎. (b) Flat-band condition.

𝝆𝝆𝒔𝒔
𝓔𝓔 = � 𝒅𝒅𝒅𝒅
𝝐𝝐𝒔𝒔

33
 OXIDE CHARGES (Cont.)

 The positive sheet charge will induce negative charges partly in

the metal and partly in the semiconductor. The field distribution
is from Poisson’s equation.

 To reach flat-band condition (no induced charge in the

semiconductor), we must apply a negative charge to the metal.

𝑸𝑸𝒐𝒐 𝑸𝑸𝒐𝒐 𝒙𝒙𝒐𝒐

𝑽𝑽𝑭𝑭𝑭𝑭 = −𝓔𝓔𝟎𝟎 𝒙𝒙𝒐𝒐 = − 𝒙𝒙 = − (20)
𝝐𝝐𝒐𝒐𝒐𝒐 𝒐𝒐 𝑪𝑪𝒐𝒐 𝒅𝒅

𝑪𝑪𝒐𝒐 ≡ 𝝐𝝐𝒐𝒐𝒐𝒐 ⁄𝒅𝒅

34
 OXIDE CHARGES (Cont.)
 For a more general case of an arbitrary charge distribution in the oxide.
𝟏𝟏 𝟏𝟏 𝒅𝒅
𝑽𝑽𝑭𝑭𝑭𝑭 = − � 𝒙𝒙𝝆𝝆 𝒙𝒙 𝒅𝒅𝒅𝒅
𝑪𝑪𝒐𝒐 𝒅𝒅 𝟎𝟎
 Fixed oxide charge: 𝝆𝝆 = 𝝆𝝆𝒇𝒇 at 𝒙𝒙 = 𝟎𝟎 𝑄𝑄𝑜𝑜
(right at the oxide semiconductor interface)
𝑸𝑸𝒇𝒇 𝒅𝒅 𝑸𝑸𝒇𝒇
∴ 𝑽𝑽𝑭𝑭𝑭𝑭 = − =−
𝑪𝑪𝒐𝒐 𝒅𝒅 𝑪𝑪𝒐𝒐
 Oxide trapped charge: 𝝆𝝆𝒐𝒐𝒐𝒐
𝟏𝟏 𝟏𝟏 𝒅𝒅 𝑸𝑸𝒐𝒐𝒐𝒐
𝑽𝑽𝑭𝑭𝑭𝑭 = − � 𝒙𝒙𝝆𝝆𝒐𝒐𝒐𝒐 𝒅𝒅𝒅𝒅 = −
𝑪𝑪𝒐𝒐 𝒅𝒅 𝟎𝟎 𝑪𝑪𝒐𝒐
𝑸𝑸𝟎𝟎𝒕𝒕
 Mobile ionic charge: 𝝆𝝆𝒎𝒎
𝟏𝟏 𝟏𝟏 𝒅𝒅 𝑸𝑸𝒎𝒎
𝑽𝑽𝑭𝑭𝑭𝑭 = − � 𝒙𝒙𝝆𝝆𝒎𝒎 𝒅𝒅𝒅𝒅 = −
𝑪𝑪𝒐𝒐 𝒅𝒅 𝟎𝟎 𝑪𝑪𝒐𝒐
𝑸𝑸𝒎𝒎

𝑸𝑸𝒇𝒇 + 𝑸𝑸𝒐𝒐𝒐𝒐 + 𝑸𝑸𝒎𝒎

 If 𝒒𝒒𝝓𝝓𝒎𝒎𝒎𝒎 ≠ 𝟎𝟎, 𝑸𝑸𝒊𝒊𝒊𝒊 → 𝟎𝟎 ∴ 𝑽𝑽𝑭𝑭𝑭𝑭 = 𝝓𝝓𝒎𝒎𝒔𝒔 − (25)
𝑪𝑪𝒐𝒐 35
 EXAMPLE 3
 Calculate the flat-band voltage for an 𝒏𝒏+ − 𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩𝐩 − 𝐒𝐒𝐒𝐒𝐎𝐎𝟐𝟐 −
𝐒𝐒𝐒𝐒 capacitor having 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 and 𝒅𝒅 = 𝟓𝟓 nm . Assume that
𝑸𝑸𝒊𝒊𝒊𝒊 and 𝑸𝑸𝒎𝒎 are negligible in the oxide, and 𝑸𝑸𝒇𝒇 ⁄𝒒𝒒 is 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟐𝟐 .
SOLUTION
From Fig. 8, 𝝓𝝓𝒎𝒎𝒎𝒎 is −0.98 V for n+ polysilicon (p-Si) system
with 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑. 𝑪𝑪𝒐𝒐 is obtained from Ex. 2.
𝑸𝑸𝒇𝒇 + 𝑸𝑸𝒎𝒎 + 𝑸𝑸𝒐𝒐𝒐𝒐
𝑽𝑽𝑭𝑭𝑭𝑭 = 𝝓𝝓𝒎𝒎𝒎𝒎 −
𝑪𝑪𝒐𝒐
𝟏𝟏. 𝟔𝟔 × 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏 × 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
= −𝟎𝟎. 𝟗𝟗𝟗𝟗 − = −𝟏𝟏. 𝟏𝟏𝟏𝟏 𝐕𝐕
𝟔𝟔. 𝟗𝟗 × 𝟏𝟏𝟏𝟏−𝟕𝟕

36
CARRIER TRANSPORT IN MOS CAPACITORS
 Basic Conduction Processes in Insulators
 Direct tunneling – tunneling through the complete width of the
insulator.
Tunneling current ~ exp −𝟐𝟐𝟐𝟐 𝟐𝟐𝒎𝒎𝒏𝒏 (𝒒𝒒𝑽𝑽𝟎𝟎 − 𝑬𝑬)⁄ℏ𝟐𝟐 Eq. 81, Ch. 2

= exp −𝟐𝟐𝟐𝟐 𝟐𝟐𝒎𝒎𝒏𝒏 𝑬𝑬𝟏𝟏 + 𝑬𝑬𝟐𝟐 − 𝒒𝒒𝒒𝒒 ⁄𝟐𝟐ℏ𝟐𝟐 Fig. 14a

as 𝑽𝑽 ↑, tunneling current ↑
 Fowler-Nordheim tunneling – tunneling through partial width of
the barrier. Both the average barrier height and the tunneling
distance , J𝒕𝒕𝒕𝒕𝒕𝒕𝒕𝒕𝒕𝒕𝒕𝒕 .
 Thermionic emission
J ~ exp(− 𝒒𝒒𝝓𝝓𝑩𝑩 ⁄𝒌𝒌𝒌𝒌) J as 𝝓𝝓𝑩𝑩 or 𝑻𝑻
 Frenkel-Poole emission – emission from trapped electrons,
similar to thermionic emission. The barrier height is the depth
of the trap potential well.
37
CARRIER TRANSPORT IN MOS CAPACITORS
(Cont.)
 Figure 14 shows the energy – band diagrams with various
conduction mechanisms of (a) direct tunneling, (b) Fowler-
Nordheim tunneling, (c) thermionic emission, and (d) Frenkel-
Poole emission.

38
 CARRIER TRANSPORT IN MOS CAPACITORS
(Cont.)
 J (in Si3N4) = J𝟏𝟏 + J𝟐𝟐 + J𝟑𝟑
J𝟏𝟏 =Frenkel-Poole emission at high temperatures.
J𝟐𝟐 =Tunneling current at low temperatures.
J𝟑𝟑 =Ohmic in nature at intermediate temperatures.

 J (SiO2) is mainly tunneling current

which is 1000 times lower than that
of Si𝟑𝟑 N𝟒𝟒 .
∵ Si3N4 (𝑬𝑬𝒈𝒈 = 4.7 eV) < SiO2 ( 9 eV)

39
 DIELECTRIC BREAKDOWN

 Percolation theory: carriers transport through

insulator will create defects, when a defect chain is
formed, catastrophic breakdown occurs.

 Time to breakdown : 𝒕𝒕𝑩𝑩𝑩𝑩 = total stress time until

breakdown occurs.

40
 DIELECTRIC BREAKDOWN (Cont.)
 Figure 16 shows the percolation theory: breakdown occurs when
random defects form a chain between the gate and the
semiconductor.

 Figure 17 shows the time to breakdown 𝒕𝒕𝑩𝑩𝑩𝑩 vs. oxide field, for
different oxide thicknesses.

41
 SUMMARY OF CHAPTER 4
 At the SiO𝟐𝟐 −Si interface, there are three possible charge
distributions: accumulation, depletion, and inversion. The
inversion is the most important distribution, because it
relates to the conducting channel for MOSFET operation.
 We have considered the characteristics of an ideal MOS
capacitor. For a practical silicon MOS capacitor, the work
function difference is generally not zero and there are
various charges in the oxide or at the SiO𝟐𝟐 −Si interface
that will affect the ideal MOS characteristics.
 Tunneling is the most important conduction process in
SiO𝟐𝟐 . Tunneling current will generate defects in SiO𝟐𝟐 .
When defects become dense enough to form a continuous
chain connecting the gate to the channel, catastrophic
breakdown will occur.
42