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HP ZBook 17 Compal LA-9371P Rev 0.2 Schematics
HP ZBook 17 Compal LA-9371P Rev 0.2 Schematics
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1 1
2
Compal Confidential 2
2012-09-28
REV : 0.2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 1 of 53
A B C D E
A B C D E
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Compal Confidential
Model Name : Afterburn
File Name : LA-9371P
1 1
DDR3-SO-DIMM2, 3
Ch B BANK 0, 1, 2, 3 Page 12
eDP MUX
eDP Panel Conn. PS8321 eDP
Page 22
Page 36 Intel DDR3-SO-DIMM0, 1
Ch A BANK 0, 1, 2, 3 Page 11
DPC eDPF Haswell DDR3L 1333MHz 1.35V
DP Switch
PI3VDP124 rPGA Processor
Page 36 MXM3.0 Conn
PEGx16 rPGA947
Dock Conn DPD NVidia: Port 1
Page 33 37.5mm*37.5mm Docking x 1
DPE Page 4,5,6,7,8,9,10 Page 33
Page 35
SPI
GEN3 6Gb/S)
daughter board SPK conn Port 8 FPR
LPC BUS
SATA HDD Page 27 Validity VFM471Page
Card Reader GLAN Intel WLAN ODD mSATA SATA HDD BIOS SPI ROM x1, 28
Realtek RTS5237 Clarkville Expresscard (MINI card) Conn. Conn. Conn. Conn. 16 MB
Page 16 Port 10
LS-9373P Page 4 Page 23 Page 23 (Secondary) (primary) Webcam
Page 29 sub/B Page 7 Page 25 Page 23 Page 23 Page 22
33MHz
3 Port 6 Port 13 Port 12
3
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( O MEANS ON X MEANS OFF )
Voltage Rails Symbol Note :
+RTCVCC B+ +5VDS +1.35V +5VS
+3VDS +0.675VS +3VS
D
+1.5VS : means Digital Ground D
power
plane +VCC_CORE
+1.05VS
+1.05VM : means Analog Ground
L Layout Notes
07/24 update
S0
O O O O O : Question Area Mark.(Wait check)
S1
C
O O O O O C
S3
O O O O X Install below 45 level BOM structure for ver. 0.1
S5 S4/AC 45@ : means just put it in the BOM of 45 level.
O O O X X
S5 S4/ Battery only
O O X X X
S5 S4/AC & Battery
don't exist
O X X X X Install below 43 level BOM structure for ver. 0.1
DEBUG@ : means just build when PCIE port 80 CARD function enable.Remove before MP
2nd
SOURCE BATT XDP SODIMM G-SENSOR TP NIC NFC EC MXM
BATT
B I2C_MAIN_CLK
I2C_MAIN_DAT
SMSC1126
V X X X X X X X X X B
I2C_BAY_CLK
I2C_BAY_DAT
SMSC1126
X V X X X X X X X X
MEM_SMBCLK
MEM_SMBDATA
Haswell
X X V V V V X X X X
LAN_SMBCLK
LAN_SMBDATA
Haswell
X X X X X X V V X X
SML1_SMBCLK
SML1_SMBDATA Haswell
X X X X X X X X V V
0 1 RSVD
1 0 SPI
1 1 LPC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 3 of 53
5 4 3 2 1
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+VCCIOA_OUT
PEG_COMP 2 1
D 24.9_0402_1% RC1 D
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PEG_CRX_GTX_P[0..15]
Haswell rPGA EDS PEG_CRX_GTX_P[0..15] <35>
JCPU1A CONN@
PEG_CRX_GTX_N[0..15]
PEG_CRX_GTX_N[0..15] <35>
E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N0 PEG_CTX_GRX_P[0..15]
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1 PEG_CTX_GRX_P[0..15] <35>
<14> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
DMI_CRX_PTX_N1 C21 M31 PEG_CRX_GTX_N2 PEG_CTX_GRX_N[0..15]
<14> DMI_CRX_PTX_N1 DMI_RXN_1 PEG_RXN_2 PEG_CTX_GRX_N[0..15] <35>
DMI_CRX_PTX_N2 B21 L30 PEG_CRX_GTX_N3
<14> DMI_CRX_PTX_N2 DMI_RXN_2 PEG_RXN_3
DMI_CRX_PTX_N3 A21 M33 PEG_CRX_GTX_N4
<14> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6
<14> DMI_CRX_PTX_P0
PEG
DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_CRX_GTX_N7
<14> DMI_CRX_PTX_P1 DMI_RXP_1 PEG_RXN_7
DMI_CRX_PTX_P2 B20 E29 PEG_CRX_GTX_N8
<14> DMI_CRX_PTX_P2 DMI_RXP_2 PEG_RXN_8
DMI_CRX_PTX_P3 A20 D28 PEG_CRX_GTX_N9
<14> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31 PEG_CRX_GTX_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_CRX_GTX_N11
<14> DMI_CTX_PRX_N0 C17 DMI_TXN_0 PEG_RXN_11 E35 2 1 0.22U_0402_6.3V6K
DMI_CTX_PRX_N1 PEG_CRX_GTX_N12 PEG_CTX_GRX_C_P0 CC1 PEG_CTX_GRX_P0
<14> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_CRX_GTX_N13 PEG_CTX_GRX_C_N0 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N0
CC2
<14> DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33 PEG_CRX_GTX_N14
<14> DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32 PEG_CRX_GTX_N15 PEG_CTX_GRX_C_P1 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P1
CC3
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PEG_CRX_GTX_P0 PEG_CTX_GRX_C_N1 CC4 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N1
<14> DMI_CTX_PRX_P0 C18 DMI_TXP_0 PEG_RXP_0 L28
DMI_CTX_PRX_P1 PEG_CRX_GTX_P1
<14> DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_CRX_GTX_P2 PEG_CTX_GRX_C_P2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P2
CC5
C <14> DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_N2 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N2 C
CC6
<14> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4
PEG_RXP_4 K32 PEG_CRX_GTX_P5 PEG_CTX_GRX_C_P3 CC7 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P3
PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_N3 CC8 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N3
PEG_RXP_6 K34 PEG_CRX_GTX_P7
PEG_RXP_7 F29 PEG_CRX_GTX_P8 PEG_CTX_GRX_C_P4 CC9 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P4
FDI_CSYNC H29 PEG_RXP_8 E28 PEG_CRX_GTX_P9 PEG_CTX_GRX_C_N4 CC10 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N4
<14> FDI_CSYNC
FDI
FDI_INT J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CRX_GTX_P10
<14> FDI_INT DISP_INT PEG_RXP_10 E30 PEG_CRX_GTX_P11 PEG_CTX_GRX_C_P5 CC11 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P5
PEG_RXP_11 F35 PEG_CRX_GTX_P12 PEG_CTX_GRX_C_N5 CC12 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N5
PEG_RXP_12 E34 PEG_CRX_GTX_P13
PEG_RXP_13 F33 PEG_CRX_GTX_P14 PEG_CTX_GRX_C_P6 CC13 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P6
PEG_RXP_14 D32 PEG_CRX_GTX_P15 PEG_CTX_GRX_C_N6 CC14 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N6
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P7 CC15 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P7
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N7 CC16 2 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N7
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P8 CC17 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P8
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N8 CC18 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N8
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P9 CC19 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P9
PEG_TXN_7 B31 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 CC20 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N9
PEG_TXN_8 A30 PEG_CTX_GRX_C_N9
PEG_TXN_9 B29 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P10 CC21 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P10
PEG_TXN_10 A28 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N10 CC22 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N10
PEG_TXN_11 B27 PEG_CTX_GRX_C_N12
PEG_TXN_12 A26 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P11 CC23 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P11
PEG_TXN_13 B25 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N11 CC24 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N11
PEG_TXN_14 A24 PEG_CTX_GRX_C_N15
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P12 CC25 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P12
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N12 CC26 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N12
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2
B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P13 CC27 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P13 B
PEG_TXP_3 H31 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N13 CC28 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N13
PEG_TXP_4 H30 PEG_CTX_GRX_C_P5
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P14 CC29 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P14
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N14 CC30 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N14
PEG_TXP_7 C31 PEG_CTX_GRX_C_P8
PEG_TXP_8 B30 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P15 CC31 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P15
PEG_TXP_9 C29 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N15 CC32 1 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N15
PEG_TXP_10 B28 PEG_CTX_GRX_C_P11
PEG_TXP_11 C27 PEG_CTX_GRX_C_P12
PEG_TXP_12 B26 PEG_CTX_GRX_C_P13
PEG_TXP_13 C25 PEG_CTX_GRX_C_P14
PEG_TXP_14 B24 PEG_CTX_GRX_C_P15
PEG_TXP_15
1 OF 9
INTEL_HASWELL_HASWELL
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DMI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 4 of 53
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SM_DRAMPWROK with DDR Power Gating Topology
+VCCIO_OUT
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
+VCCIO_OUT +VCCIO_OUT
CC33
CC34
+1.35VS
+5VDS 2 2 JXDP1
1 2
GND0 GND1
1
CC35 XDP_PREQ# 3 4 CFG17
1 2 XDP_PRDY# 5 OBSFN_A0 OBSFN_C0 6 CFG16 CFG17 <8>
RC5
7 OBSFN_A1 OBSFN_C1 8 CFG16 <8>
1.8K_0402_1% GND2 GND3
0.1U_0402_10V6K Place near JXDP1 CFG0 9 10 CFG8
<8> CFG0 11 OBSDATA_A0 OBSDATA_C0 12 CFG8 <8>
20120923 HP's request UC1 CFG1 CFG9
2
<8> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <8>
5
20120810 HP's request 13 14
1 CFG2 15 GND4 GND5 16 CFG10
P
<30,31,46> PWR_GD B 4 <8> CFG2 17 OBSDATA_A2 OBSDATA_C2 18 CFG10 <8>
PM_DRAM_PWRGD_CPU CFG3 CFG11
D
2 O <8> CFG3 19 OBSDATA_A3 OBSDATA_C3 20 CFG11 <8> D
<14> PM_DRAM_PWRGD A GND6 GND7
G
XDP_OBS0 21 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 <8>
1
1 2 74AHC1G09GW_TSSOP5 XDP_OBS1 23 24 CFG18
+3VS
3
OBSFN_B1 OBSFN_D1 CFG18 <8>
39_0402_5%
RC9 100K_0402_1% Part Number = SA00003Y000 @ RC10 25 26
GND8 GND9
2
3.3K_0402_1% CFG4 27 28 CFG12
<8> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <8>
RC12
CFG5 29 30 CFG13
<8> CFG5 31 OBSDATA_B1 OBSDATA_D1 32 CFG13 <8>
2
CFG6 33 GND10 GND11 34 CFG14
<8> CFG6 CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15 CFG14 <8>
1
<8> CFG7 37 OBSDATA_B3 OBSDATA_D3 38 CFG15 <8>
RC5 need to close to JCPU1 GND12 GND13
H_CPUPWRGD RC13 1 2 1K_0402_1% H_CPUPWRGD_XDP 39 40
PWRGOOD/HOOK0 ITPCLK/HOOK4
1
41 42
<13,14,30> ON/OFFBTN# HOOK1 ITPCLK#/HOOK5
D QC1 43 44
2 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R 2 1 PLT_RST#
<9> RUN_ON_CPU1.5VS3# <9> CPU_PWR_DEBUG HOOK2 RESET#/HOOK6 PLT_RST# <13,14,25,28,29,30,35,37,39>
G RC1071 2 0_0402_5% PM_PWROK_XDP 47 48 XDP_DBRESET# RC16 1K_0402_1%
2N7002K_SOT23-3 <14,30> PM_PWROK 49 HOOK3 DBR#/HOOK7 50
S 20120925 HP's request
51 GND14 GND15 52 XDP_TDO
3
<11,12,13,16,28,38> DDR_XDP_WAN_SMBDAT 53 SDA TD0 54 XDP_TRST#
<11,12,13,16,28,38> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56 XDP_TDI
XDP_TCLK 57 TCK1 TDI 58 XDP_TMS
59 TCK0 TMS 60 2 1 CFG3
GND16 GND17 RC105 1K_0402_1%
SAMTE_BSH-030-01-L-D-A CONN@
KBC_PROC_HOT_R
<24,46> KBC_PROC_HOT_R
+VCCIO_OUT
#4/16 change by HP requirement
DDR3
THERMAL
PAD T118 @ H_CATERR# AN32 AP2 SM_RCOMP2 QC2
CATERR SM_RCOMP_2
D
<30> H_PECI H_PECI AR27 AN3 DDR3_DRAMRST#_CPU DDR3_DRAMRST#_CPU 3 1
AK31 PECI SM_DRAMRST CPU_DRAM_RST# <11>
PAD T1 @
KBC_PROC_HOT RC26 1 2 56_0402_5% KBC_PROC_HOT_R AM30 FC_AK31 AR29 XDP_PRDY#
PROCHOT PRDY
4.99K_0402_1%
RC27 1 2 390_0402_1% H_THERMTRIP# AM35 AT29 XDP_PREQ#
G
<18,35> PCH_THERMTRIP#_R
2
C
THERMTRIP PREQ AM34 XDP_TCLK C
TCK
1
1
D AN33 XDP_TMS
20120911 Delete RC30 as HP's request TMS
RC28
2 AM33 XDP_TRST#
JTAG
24,30> KBC_PROC_HOT# TRST
G Q59 H_PM_SYNC AT28 AM31 XDP_TDI 20120725 for S3 resume as HP's request
<14> H_PM_SYNC
PWR
H_CPUPWRGD AL34 PM_SYNC TDI AL33 XDP_TDO
S <18> H_CPUPWRGD
3
2
2N7002KW_SOT323-3 AT26 SM_DRAMPWROK DBR XDP_DBRESET# <13,14> DDR_RST_EN <16>
<18> CPU_PLTRST# CPU_PLTRST#
PLTRSTIN AR30 XDP_OBS0
BPM_N_0 AN31 XDP_OBS1
G28 BPM_N_1 AN29 XDP_OBS2_R RC36 1 @ 2 0_0402_5%
<15> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2
CLOCK
H28 AP31 XDP_OBS3_R RC38 1 @ 2 0_0402_5%
<15> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3
1
F27 AP30 XDP_OBS4_R RC40 1 @ 2 0_0402_5%
<15> CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM_N_4
E27 AN28 XDP_OBS5_R RC43 1 @ 2 0_0402_5% D QC3
<15> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5
<15> CLK_CPU_DMI#
D26 AP29 XDP_OBS6_R RC45 1 @ 2 0_0402_5% <25,29,30,44,9> KBC_DS3_EN
2
E26 BCLKN BPM_N_6 AP28 XDP_OBS7_R RC47 1 @ 2 0_0402_5% G
<15> CLK_CPU_DMI BCLKP BPM_N_7
S 2N7002K_SOT23-3
For ESD concern, please place close to CPU
3
2 OF 9
INTEL_HASWELL_HASWELL
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21 XDP_DBRESET# RC52 2 1 1K_0402_1%
+1.05VS
H_CPUPWRGD
1
CRB Rev 0.7 no pull up
RC55
B B
10K_0402_1%
XDP_TDO RC57 2 1 51_0402_1%
DDR3 COMPENSATION SIGNALS
2
CRB Rev 0.7 is depop
SM_RCOMP0 RC59 1 2 100_0402_1% XDP_TCLK RC60 2 1 51_0402_1%
CAD Note: SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%
Avoid stub in the PWRGD path
SM_RCOMP2 RC65 1 2 100_0402_1%
20120911 Delete RC66 as HP's request
while placing resistors RC25 & RC130
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 5 of 53
5 4 3 2 1
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D D
1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CC85
CC84
CC86
2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 6 of 53
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D D
EDP_COMP 2 1
24.9_0402_1% RC77
P31 DDID_TXDP_1
R31 DDID_TXDN_2
N30 DDID_TXDP_2
P30 DDID_TXDN_3
DDID_TXDP_3
8 OF 9
+VCCIO_OUT
INTEL_HASWELL_HASWELL
1
RC78
HPD INVERSION FOR EDP 10K_0402_5%
B B
2
20120807 Change RC78 to 10K as HP's request
EDP_HPD
1
D
2 QH1
<36> CPU_EDP_HPD#
G BSS138W-7-F_SOT323-3
S SB000002X00
3
100K_0402_5%
1
RC79
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU-FDI,eDP,DDI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 7 of 53
5 4 3 2 1
5 4 3 2 1
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CFG STRAPS for CPU
CFG2
1K_0402_1%
1
RC80
D D
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
Haswell rPGA EDS
JCPU1I
CFG4
AT1
RSVD_TP
1K_0402_1%
AT2 C23
RSVD_TP RSVD_TP
1
AD10 B23
RSVD RSVD_TP
RC81
D24
A34 RSVD_TP D23
A35 RSVD_TP RSVD_TP
RSVD_TP
2
@ T15 PAD~D W29
@ T12 PAD~D W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16
TESTLO_G26 CFG_16 CFG16 <5>
W33 AR23 CFG18
RSVD CFG_18 CFG18 <5>
@ T16 PAD~D AL30 AP21 CFG17
RSVD CFG_17 CFG17 <5>
@ T17 PAD~D AL29 AP23 CFG19
C
+VCC_CORE
F25 RSVD CFG_19 CFG19 <5> Display Port Presence Strap C
VCC
C35 AR33
B35 RSVD_TP RSVD G6 1 : Disabled; No Physical Display Port
RSVD_TP FC_G6 AM27
AL25 RSVD AM26 CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5
@ T26 PAD~D W30 RSVD AM2 0 : Enabled; An external Display Port device is
@ T28 PAD~D W31 RSVD_TP RSVD K6
H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port
TESTLO E18
CFG0 AT20 RSVD
<5> CFG0 CFG_0
CFG1 AR20 U10 CFG6
<5> CFG1 CFG_1 RSVD
CFG2 AP20 P10
<5> CFG2 CFG_2 RSVD
CFG3 AP22 CFG5
<5> CFG3 CFG_3
1K_0402_1%
CFG4 AT22 B1
<5> CFG4 CFG_4 NC
1
1K_0402_1%
CFG5 AN22 A2
<5> CFG5 CFG_5 RSVD
@ RC82
@ RC83
CFG6 AT25 AR1
<5> CFG6 CFG_6 RSVD_TP
CFG7 AN23
<5> CFG7 CFG_7
CFG8 AR24 E21
<5> CFG8 CFG_8 RSVD_TP
CFG9 AT23 E20
<5> CFG9
2
CFG10 AN20 CFG_9 RSVD_TP
<5> CFG10 CFG_10
CFG11 AP24 AP27
<5> CFG11 CFG_11 RSVD
CFG12 AP26 AR26
<5> CFG12 CFG_12 RSVD
CFG13 AN25
<5> CFG13 CFG_13
CFG14 AN26 AL31
<5> CFG14 CFG_14 VSS
CFG15 AP25 AL32
<5> CFG15 CFG_15 VSS
20120710 Delete RC106/RC107 PCIE Port Bifurcation Straps
9 OF 9
2 1 H_CPU_TESTLO 11: (Default) x16 - Device 1 functions 1 and 2 disabled
INTEL_HASWELL_HASWELL
RC84 49.9_0402_1%
B 2 1 CFG_RCOMP 10: x8, x8 - Device 1 function 1 enabled ; function 2 B
RC85 49.9_0402_1% CONN@
2 1 H_CPU_RSVD CFG[6:5] disabled
RC86 49.9_0402_1% 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG9
CFG7
1
1K_0402_1%
@ RC106
1
1K_0402_1%
@ RC87
2
2
2012/09/21 For a Intel Sighting
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU-RSVD,CFG
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 8 of 53
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+1.35VS Source
B+ B+ QC4 +1.35VS Haswell rPGA EDS
+VCC_CORE
+1.35V SI7326DN-T1-GE3_PAK1212-8-5 JCPU1E CONN@
1
4/20 change by HP 2 AA26
VCC
1
requirement 3 AA28
VCC
2
R461 5 K27 AA34
@ RC88 RC89 L27 RSVD VCC AA30
20K_0402_5% RSVD VCC
1
20K_0402_5%
100K_0402_5% 470_0603_5% T27 AA32
4
R6 V27 RSVD VCC AB26
2
D
RSVD VCC AB29 D
1
RC90 1 2 4.7K_0402_5% RUN_ON_CPU1.5VS3 @ +1.35VS VCC AB25
<25,29,30,44,5> KBC_DS3_EN VCC
6
AB27
2
VCC AB28
VCC
1
1 CC38 2 1 0.1U_0402_10V6K AB11 AB30
DMN66D0LDW-7_SOT363-6 VDDQ VCC
1
RUN_ON_CPU1.5VS3# 2 AB2 AB31
QC5A D CC40 2 1 0.1U_0402_10V6K AB5 VDDQ VCC AB33
VDDQ VCC
3
RC92 CC39 2 RUN_ON_CPU1.5VS3# AB8 AB34
1
330K_0402_5% 2 0.1U_0402_25V6 G AE11 VDDQ VCC AB32
2
Q2 AE2 VDDQ VCC AC26
S
5 DMN66D0LDW-7_SOT363-6 2N7002K_SOT23-3 AE5 VDDQ VCC AB35
<14,30,31,34,39,44> SLP_S3#
3
QC5B AE8 VDDQ VCC AC28
20120911 Delete RC93 AH11 VDDQ VCC AD25
4
as HP's request K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
RUN_ON_CPU1.5VS3 <11,12> VDDQ VCC
N8 AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
RUN_ON_CPU1.5VS3# <5> VDDQ VCC
T5 AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
AK27 RSVD VCC AE28
RSVD VCC AE30
VCC AG28
VCC AG34
VCC AE34
VCC AF25
VCC AF26
C
SVID ALERT VCCSENSE AL35
E17 VCC_SENSE
RSVD
VCC
VCC
VCC
AF27
AF28
C
1
AT35 AH28
RC63 close to CPU 300 - 1500mils RC98 @ T50 PAD~D AR35 RSVD_TP VCC AH30
@ T51 PAD~D AR32 RSVD_TP VCC AH31
150_0402_1% RSVD_TP VCC
@ T52 PAD~D AL26 AH33
@ T53 PAD~D AT34 RSVD_TP VCC AH34
2
AL22 VSS VCC AJ25
AT33 VSS VCC AJ26
CPU_PWR_DEBUG AM21 VSS VCC AJ27
AM25 VSS VCC AJ28
AM22 VSS VCC AJ29
AM20 VSS VCC AJ30
AM24 VSS VCC AJ31
AL19 VSS VCC AJ32
+VCC_CORE AM23 VSS VCC AJ33
AT32 VSS VCC AJ34
VCC_SENSE VSS VCC
VCC
AJ35
100_0402_1%
B G25 B
VCC
1
H25
VCC
RC101
J25
VCC K25
+VCC_CORE VCC L25
VCC M25
CAD Note: RC102 SHOULD BE PLACED CLOSE TO CPU
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D2_2V_Y
20120911 Delete RC102, RC103 as HP's request Y30 U25
330U_D2_2V_Y
1 1 VCC VCC
1 1 1 1 1 1 1 1 1 1 Y31 U26
+ + Y32 VCC VCC V25
CC41
VCC VCC
CC87
CC42
CC43
CC44
CC45
CC46
CC47
CC48
CC49
CC50
CC51
<10,46> VSSSENSE VSSSENSE Y33 V26
Y34 VCC VCC
2 2 2 2 2 2 2 2 2 2 2 2 Y35 VCC W26
@ VCC VCC
1
100_0402_1%
W27
CAD Note: RC103 SHOULD BE PLACED CLOSE TO CPU 5 OF 9 VCC
20120806 Add CC87 as Intel's reply
RC104
INTEL_HASWELL_HASWELL
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
2 2 2 2 2 2 2 2 2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU- PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 9 of 53
5 4 3 2 1
5 4 3 2 1
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D D
Haswell rPGA EDS JCPU1F CONN@ Haswell rPGA EDS JCPU1G CONN@
6 OF 9 7 OF 9
INTEL_HASWELL_HASWELL INTEL_HASWELL_HASWELL
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU-VSS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 10 of 53
5 4 3 2 1
5 4 3 2 1
2
G
QD1 JDIMM3
1
+DIMM_A_DQ
1K_0402_5%
2N7002KW _SOT323-3 1 2
3 1 +1.35V +1.35V 3 VREF_DQ VSS1 4 DDR_A_D4
+DIMM01_VREF_DQ VSS2 DQ4
RD2
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
JDIMM1 DDR_A_D0 5 6 DDR_A_D5
D
1 2 1 2 DDR_A_D1 7 DQ0 DQ5 8
D +1.35V VREF_DQ VSS 1 1 DQ1 VSS3 D
RD24 1K_0402_1% 3 4 DDR_A_D4 9 10 DDR_A_DQS#0
2
VSS DQ4 VSS4 DQS#0
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
CD1
CD2
DDR_A_D0 5 6 DDR_A_D5 11 12 DDR_A_DQS0
DDR_A_D1 7 DQ0 DQ5 8
All VREF traces should 13 DM0 DQS0 14
1 1 DQ1 VSS VSS5 VSS6
1
have 10 mil trace width 2 2
1K_0402_1%
9 10 DDR_A_DQS#0 <12> DDR3_DRAMRST#_R 1 2 DDR_A_D2 15 16 DDR_A_D6
VSS DQS0# CPU_DRAM_RST# <5> DQ2 DQ6
CD3
CD4
11 12 DDR_A_DQS0 DDR_A_D3 17 18 DDR_A_D7
All VREF traces should DM0 DQS0 RD6 33_0402_5% DQ3 DQ7
RD23
13 14 19 20
2 2 VSS VSS VSS7 VSS8
have 10 mil trace width DDR_A_D2 15
DQ2 DQ6
16 DDR_A_D6 DDR_A_D8 21
DQ8 DQ12
22 DDR_A_D12
DDR_A_D3 17 18 DDR_A_D7 DDR_A_D9 23 24 DDR_A_D13
2
19 DQ3 DQ7 20 20120802 Change RD6 to 33Ohm as HP's request 25 DQ9 DQ13 26
DDR_A_D8 21 VSS VSS 22 DDR_A_D12 DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13 DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
25 DQ9 DQ13 26 31 DQS1 RESET# 32
DDR_A_DQS#1 27 VSS VSS 28 DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
<6> DDR_A_D[0..63] DQS1# DM1 DQ10 DQ14
DDR_A_DQS1 29 30 DDR3_DRAMRST#_R DDR_A_D11 35 36 DDR_A_D15
31 DQS1 RESET# 32 37 DQ11 DQ15 38
<6> DDR_A_DQS[0..7] 33 VSS VSS 34 39 VSS13 VSS14 40
DDR_A_D10 DDR_A_D14 DDR_A_D16 DDR_A_D20
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15 DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
<6> DDR_A_DQS#[0..7] 37 DQ11 DQ15 38 43 DQ17 DQ21 44
DDR_A_D16 39 VSS VSS 40 DDR_A_D20 DDR_A_DQS#2 45 VSS15 VSS16 46
<6> DDR_A_MA[0..15] 41 DQ16 DQ20 42 47 DQS#2 DM2 48
DDR_A_D17 DDR_A_D21 DDR_A_DQS2
43 DQ17 DQ21 44 49 DQS2 VSS17 50 DDR_A_D22
DDR_A_DQS#2 45 VSS VSS 46 DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_DQS2 47 DQS2# DM2 48 DDR_A_D19 53 DQ18 DQ23 54
49 DQS2 VSS 50 DDR_A_D22 55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23 DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
Layout Note: DDR_A_D19 53 DQ18 DQ23 54 DDR_A_D25 59 DQ24 DQ29 60
DQ19 VSS DQ25 VSS21
Place near JDIMM1 55
VSS DQ28
56 DDR_A_D28 61
VSS22 DQS#3
62 DDR_A_DQS#3
DDR_A_D24 57 58 DDR_A_D29 63 64 DDR_A_DQS3
DDR_A_D25 59 DQ24 DQ29 60 65 DM3 DQS3 66
61 DQ25 VSS 62 DDR_A_DQS#3 DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
63 VSS DQS3# 64 DDR_A_DQS3 DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
65 DM3 DQS3 66 71 DQ27 DQ31 72
+1.35V DDR_A_D26 67 VSS VSS 68 DDR_A_D30 VSS25 VSS26
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS VSS DDR_CKE2_DIMMA 73 74 DDR_CKE3_DIMMA
<6> DDR_CKE2_DIMMA CKE0 CKE1 DDR_CKE3_DIMMA <6>
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C 75 76 C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA 77 VDD1 VDD2 78 DDR_A_MA15
1 1 1 1 <6> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6> NC1 A15
75 76 DDR_A_BS2 79 80 DDR_A_MA14
VDD VDD BA2 A14
CD5
CD6
CD7
CD8
77 78 DDR_A_MA15 81 82
DDR_A_BS2 79 NC A15 80 DDR_A_MA14 DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
2 2 2 2 <6> DDR_A_BS2 BA2 A14 A12/BC# A11
81 82 DDR_A_MA9 85 86 DDR_A_MA7
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 87 A9 A7 88
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
87 A9 A7 88 DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6 93 A5 A4 94
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
93 A5 A4 94 DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2 99 A1 A0 100
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 M_CLK_A_DDR2 101 VDD9 VDD10 102 M_CLK_A_DDR3
+1.35V A1 A0 <6> M_CLK_A_DDR2 CK0 CK1 M_CLK_A_DDR3 <6>
99 100 M_CLK_A_DDR#2 103 104 M_CLK_A_DDR#3
VDD VDD <6> M_CLK_A_DDR#2 CK0# CK1# M_CLK_A_DDR#3 <6>
M_CLK_A_DDR0 101 102 M_CLK_A_DDR1 105 106
<6> M_CLK_A_DDR0 CK0 CK1 M_CLK_A_DDR1 <6> VDD11 VDD12
M_CLK_A_DDR#0 103 104 M_CLK_A_DDR#1 DDR_A_MA10 107 108 DDR_A_BS1
<6> M_CLK_A_DDR#0 CK0# CK1# M_CLK_A_DDR#1 <6> A10/AP BA1
105 106 DDR_A_BS0 109 110 DDR_A_RAS#
VDD VDD BA0 RAS#
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD10
CD11
CD12
CD13
CD14
CD15
+ CD16 DDR_A_CAS# 115 116 M_A_ODT0 DDR_A_MA13 119 120 M_A_ODT3 +DIMM_VREF_CA
<6> DDR_A_CAS# CAS# ODT0 M_A_ODT0 <6> A13 ODT1 M_A_ODT3 <6>
330U_B2_2.5VM_R15M 117 118 DDR_CS3_DIMMA# 121 122
119 VDD VDD 120 +DIMM_VREF_CA <6> DDR_CS3_DIMMA# 123 S1# NC2 124
DDR_A_MA13 M_A_ODT1 M_A_ODT1 <6>
2 2 2 2 2 2 2 2 DDR_CS1_DIMMA# 121 A13 ODT1 122 125 VDD17 VDD18 126
<6> DDR_CS1_DIMMA# 123 S1# NC 124 127 NCTEST VREF_CA 128
VDD VDD VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
125 126 1 2 DDR_A_D32 129 130 DDR_A_D36
TEST VREF_CA +1.35V DQ32 DQ36
127 128 RD26 1K_0402_1% DDR_A_D33 131 132 DDR_A_D37
VSS VSS DQ33 DQ37
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
SGA00004400 DDR_A_D32 129 130 DDR_A_D36 133 134 1 1
DQ32 DQ36 VSS29 VSS30
CD17
CD18
DDR_A_D33 131 132 DDR_A_D37 DDR_A_DQS#4 135 136
1
DQ33 DQ37 DQS#4 DM4
1K_0402_1%
133 134 1 3 DDR_A_DQS4 137 138
S
VSS VSS 1 1 +SM_VREF_CA DQS4 VSS31
CD19
CD20
DDR_A_DQS#4 135 136 139 140 DDR_A_D38
DQS4# DM4 VSS32 DQ38 2 2
RD25
DDR_A_DQS4 137 138 QD2 DDR_A_D34 141 142 DDR_A_D39
139 DQS4 VSS 140 DDR_A_D38 DDR_A_D35 143 DQ34 DQ39 144
2N7002KW_SOT323-3
G
2
DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 2 2 145 DQ35 VSS33 146 DDR_A_D44
2
DDR_A_D35 143 DQ34 DQ39 144 RUN_ON_CPU1.5VS3 DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
145 DQ35 VSS 146 DDR_A_D44 DDR_A_D41 149 DQ40 DQ45 150
B VSS DQ44 DQ41 VSS35 B
DDR_A_D40 147 148 DDR_A_D45 151 152 DDR_A_DQS#5
DDR_A_D41 149 DQ40 DQ45 150 153 VSS36 DQS#5 154 DDR_A_DQS5
Layout Note: 151 DQ41 VSS 152 DDR_A_DQS#5 155 DM5 DQS5 156
Place near JDIMM1.203,204 153 VSS DQS5# 154 DDR_A_DQS5 DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
155 DM5 DQS5 156 DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DDR_A_D42 157 VSS VSS 158 DDR_A_D46 161 DQ43 DQ47 162
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
161 DQ43 DQ47 162 DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
DDR_A_D48 163 VSS VSS 164 DDR_A_D52 167 DQ49 DQ53 168
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 DDR_A_DQS#6 169 VSS41 VSS42 170
167 DQ49 DQ53 168 DDR_A_DQS6 171 DQS#6 DM6 172
DDR_A_DQS#6 169 VSS VSS 170 173 DQS6 VSS43 174 DDR_A_D54
+0.675VS DDR_A_DQS6 171 DQS6# DM6 172 DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
173 DQS6 VSS 174 DDR_A_D54 DDR_A_D51 177 DQ50 DQ55 178
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55 179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D51 177 DQ50 DQ55 178 DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DQ51 VSS DQ56 DQ61
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD22
CD23
CD24
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
199 200 1 203 204
VDDSPD SDA DDR_XDP_W AN_SMBDAT <12,13,16,28,38,5> +0.675VS VTT1 VTT2 +0.675VS
201 202 1
SA1 SCL DDR_XDP_W AN_SMBCLK <12,13,16,28,38,5>
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
CD26
1 203 204 205 206
+0.675VS VTT VTT +0.675VS GND1 GND2
CD25
1 2
CD28
A
CONN@
Standard A
Reverse
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMM1&2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 11 of 53
5 4 3 2 1
5 4 3 2 1
2
G
QD3
2N7002KW_SOT323-3 +DIMM_B_DQ
3 1 +1.35V JDIMM4 +1.35V
+DIMM23_VREF_DQ
D
+DIMM_B_DQ 1 2 1 2
+1.35V VREF DQ Vss
+1.35V +1.35V RD27 1K_0402_1% 3 4 DDR_B_D4
Vss DQ4
2.2U_0402_6.3V6M
JDIMM2 DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5
0.1U_0402_16V4Z
1 2 DDR_B_D1 7 8
1
VREF_DQ VSS1 DQ1 Vss
1K_0402_1%
3 4 DDR_B_D4 1 1 9 10 DDR_B_DQS#0
D VSS2 DQ4 Vss DQS0# D
CD29
2.2U_0402_6.3V6M
DDR_B_D0 5 6 DDR_B_D5 11 12 DDR_B_DQS0
DQ0 DQ5 DM0 DQS0
RD28
CD30
13 14
0.1U_0402_16V4Z
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_D2 15 Vss Vss 16 DDR_B_D6
1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0 2 2 DQ2 DQ6
CD31
11 12 DDR_B_DQS0 DDR_B_D3 17 18 DDR_B_D7
2
DM0 DQS0 DQ3 DQ7
All VREF traces should
CD32
13 14 19 20
VSS5 VSS6 DDR_B_D8 21 Vss Vss 22 DDR_B_D12
DDR_B_D2 15 16 DDR_B_D6
All VREF traces should 2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7 have 10 mil trace width DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ3 DQ7 DQ9 DQ13
have 10 mil trace width 19
VSS7 VSS8
20 25
Vss Vss
26
DDR_B_D8 21 22 DDR_B_D12 20120710 Change by HP's request DDR_B_DQS#1 27 28
23 DQ8 DQ12 24 DDR_B_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#_R
DDR_B_D9 DDR_B_D13
DQ9 DQ13 31 DQS1 RESET# 32
25 26
<6> DDR_B_D[0..63] VSS9 VSS10 DDR_B_D10 33 Vss Vss 34 DDR_B_D14
DDR_B_DQS#1 27 28
DQS#1 DM1 DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
DDR_B_DQS1 29 30 DDR3_DRAMRST#_R
<6> DDR_B_DQS[0..7] DQS1 RESET# DDR3_DRAMRST#_R <11> DQ11 DQ15
31 32 37 38
33 VSS11 VSS12 34 DDR_B_D16 39 Vss Vss 40 DDR_B_D20
DDR_B_D10 DDR_B_D14
<6> DDR_B_DQS#[0..7] DQ10 DQ14 DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
DDR_B_D11 35 36 DDR_B_D15
DQ11 DQ15 43 DQ17 DQ21 44
37 38
<6> DDR_B_MA[0..15] VSS13 VSS14 DDR_B_DQS#2 45 Vss Vss 46
DDR_B_D16 39 40 DDR_B_D20
DQ16 DQ20 DDR_B_DQS2 47 DQS2# DM2 48
DDR_B_D17 41 42 DDR_B_D21
43 DQ17 DQ21 44 49 DQS2 Vss 50 DDR_B_D22
VSS15 VSS16 DDR_B_D18 51 Vss DQ22 52 DDR_B_D23
DDR_B_DQS#2 45 46
DQS#2 DM2 DDR_B_D19 53 DQ18 DQ23 54
DDR_B_DQS2 47 48
DQS2 VSS17 55 DQ19 Vss 56 DDR_B_D28
49 50 DDR_B_D22
VSS18 DQ22 DDR_B_D24 57 Vss DQ28 58 DDR_B_D29
DDR_B_D18 51 52 DDR_B_D23
Layout Note: DDR_B_D19 53 DQ18 DQ23 54 DDR_B_D25 59 DQ24 DQ29 60
DQ19 VSS19 DQ25 Vss
Place near JDIMM2 55
VSS20 DQ28
56 DDR_B_D28 61
Vss DQS3#
62 DDR_B_DQS#3
DDR_B_D24 57 58 DDR_B_D29 63 64 DDR_B_DQS3
DQ24 DQ29 65 DM3 DQS3 66
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_D26 67 Vss Vss 68 DDR_B_D30
61 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
DDR_B_DQS3
DM3 DQS3 71 DQ27 DQ31 72
65 66
VSS23 VSS24 Vss Vss
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
+1.35V 71 DQ27 DQ31 72
VSS25 VSS26 DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<6> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <6>
75 76
77 VDD VDD 78 DDR_B_MA15
C NC A15 C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD34
CD35
CD36
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD38
CD39
CD40
CD41
CD42
CD43
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
123 124 DDR_B_D32 129 130 DDR_B_D36
VDD17 VDD18 DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
125 126
127 NCTEST VREF_CA 128 133 DQ33 DQ37 134
VSS27 VSS28 Vss Vss 1 1
CD45
CD46
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36 DDR_B_DQS#4 135 136
DQ32 DQ36 DDR_B_DQS4 137 DQS4# DM4 138
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 139 DQS4 Vss 140 DDR_B_D38
133 134 1 1
VSS29 VSS30 Vss DQ38 2 2
CD47
CD48
DDR_B_DQS#4 135 136 DDR_B_D34 141 142 DDR_B_D39
137 DQS#4 DM4 138 DDR_B_D35 143 DQ34 DQ39 144
DDR_B_DQS4
DQS4 VSS31 145 DQ35 Vss 146 DDR_B_D44
139 140 DDR_B_D38
VSS32 DQ38 2 2 DDR_B_D40 147 Vss DQ44 148 DDR_B_D45
DDR_B_D34 141 142 DDR_B_D39
DQ34 DQ39 DDR_B_D41 149 DQ40 DQ45 150
DDR_B_D35 143 144
Layout Note: 145 DQ35 VSS33 146 DDR_B_D44 151 DQ41 Vss 152 DDR_B_DQS#5
B VSS34 DQ44 Vss DQS5# B
Place near JDIMM2.203,204 DDR_B_D40 147
DQ40 DQ45
148 DDR_B_D45 153
DM5 DQS5
154 DDR_B_DQS5
DDR_B_D41 149 150 155 156
DQ41 VSS35 DDR_B_D42 157 Vss Vss 158 DDR_B_D46
151 152 DDR_B_DQS#5
VSS36 DQS#5 DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
153 154 DDR_B_DQS5
DM5 DQS5 161 DQ43 DQ47 162
155 156
157 VSS37 VSS38 158 DDR_B_D48 163 Vss Vss 164 DDR_B_D52
DDR_B_D42 DDR_B_D46
DQ42 DQ46 DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47 167 DQ49 DQ53 168
161 162
VSS39 VSS40 DDR_B_DQS#6 169 Vss Vss 170
+0.675VS DDR_B_D48 163 164 DDR_B_D52
DQ48 DQ52 DDR_B_DQS6 171 DQS6# DM6 172
DDR_B_D49 165 166 DDR_B_D53
167 DQ49 DQ53 168 173 DQS6 Vss 174 DDR_B_D54
VSS41 VSS42 DDR_B_D50 175 Vss DQ54 176 DDR_B_D55
DDR_B_DQS#6 169 170
DQS#6 DM6 DDR_B_D51 177 DQ50 DQ55 178
DDR_B_DQS6 171 172
DQS6 VSS43 DQ51 Vss
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD50
CD51
CD52
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
197 198 203 204
SA0 EVENT# +0.675VS Vtt Vtt +0.675VS
199 200 1 1
VDDSPD SDA DDR_XDP_W AN_SMBDAT <11,13,16,28,38,5>
CD54
201 202 205 206
SA1 SCL DDR_XDP_W AN_SMBCLK <11,13,16,28,38,5> GND GND
CD53
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
203 204
+0.675VS VTT1 VTT2 +0.675VS
1 1 2 2
CD56
CONN@
LCN_DAN06-K4806-0103
2 2 CONN@
A
Reverse A
Reverse
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMM3&4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 12 of 53
5 4 3 2 1
5 4 3 2 1
330K_0402_5%
USB_OC3# PXDP@ RH8 1 2 33_0402_5% XDP_FN3
1 2
1
<17> USB_OC3#
USB_OC4#_R PXDP@ RH3 1 2 33_0402_5% XDP_FN4 +3V_PCH GND0 GND1
<17> USB_OC4#_R 3 4 XDP_FN16
RH6
dGPU_HPD_INTR PXDP@ RH9 1 2 33_0402_5% XDP_FN5 OBSFN_A0 OBSFN_C0
<17,35> dGPU_HPD_INTR 5 6 XDP_FN17
LED_LINK_LAN#_R PXDP@ RH10 1 2 33_0402_5% XDP_FN6 OBSFN_A1 OBSFN_C1
0.1U_0402_16V4Z
<17,29> LED_LINK_LAN#_R 7 8
USB_OC7# PXDP@ RH11 1 2 33_0402_5% XDP_FN7 GND2 GND3
<17> USB_OC7# 1 XDP_FN0 9 10 XDP_FN8
2 SG_IN PXDP@ RH12 1 2 33_0402_5% XDP_FN8 OBSDATA_A0 OBSDATA_C0
XDP_FN1 11 12 XDP_FN9
FN9 PXDP@ RH13 1 2 33_0402_5% XDP_FN9 OBSDATA_A1 OBSDATA_C1
PXDP@
CH12
13 14
mSATA_DET# PXDP@ RH14 1 2 33_0402_5% XDP_FN10 GND4 GND5
PCH_INTVRMEN <18,23> mSATA_DET# XDP_FN2 15 16 XDP_FN10
PCH_GPIO37 PXDP@ RH15 1 2 33_0402_5% XDP_FN11 2 OBSDATA_A2 OBSDATA_C2
<18> PCH_GPIO37 XDP_FN3 17 18 XDP_FN11
KBL_DET# PXDP@ RH17 1 2 33_0402_5% XDP_FN12 OBSDATA_A3 OBSDATA_C3
<18,38> KBL_DET# 19 20
DGPU_PRSNT# PXDP@ RH18 1 2 33_0402_5% XDP_FN13 GND6 GND7
<18,35> DGPU_PRSNT# 21 22
FN14 PXDP@ RH19 1 2 33_0402_5% XDP_FN14 OBSFN_B0 OBSFN_D0
D <15> FN14 23 24 D
INTVRMEN - INTEGRATED SUS 1.05V VRM <15> FN15
FN15 PXDP@ RH20 1 2 33_0402_5% XDP_FN15
25 OBSFN_B1 OBSFN_D1 26
PCH_GPIO8 PXDP@ RH21 1 2 33_0402_5% XDP_FN16 GND8 GND9
ENABLE <18> PCH_GPIO8 XDP_FN4 27 28 XDP_FN12
Sec_HDD_DET PXDP@ RH22 1 2 33_0402_5% XDP_FN17 OBSDATA_B0 OBSDATA_D0
<18> Sec_HDD_DET XDP_FN5 29 30 XDP_FN13
High - Enable Internal VRs <14,30> PM_RSMRST#
PM_RSMRST# PXDP@ RH23 1 2 1K_0402_1% RSMRST#_XDP
31 OBSDATA_B1 OBSDATA_D1 32
PLT_RST# PXDP@ RH25 1 2 1K_0402_1% RESET_OUT#_R GND10 GND11
Low - Enable External VRs XDP_FN6 33 34 XDP_FN14
XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
37 OBSDATA_B3 OBSDATA_D3 38
#4/18 change by HP requirement RSMRST#_XDP 39 GND12 GND13 40
PWRGOOD/HOOK0 ITPCLK/HOOK4 +1.05VS
1 PXDP@ 2 ON/OFFBTN#_XDP 41 42
<14,30,5> ON/OFFBTN# 43 HOOK1 ITPCLK#/HOOK5 44
RH24 0_0402_5% +3V_PCH
+3VS 45 VCC_OBS_AB VCC_OBS_CD 46 RESET_OUT#_R
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <14,5>
RH26 0_0402_5%
1 2 HDA_SPKR 1 PXDP@ 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
@ RH29 10K_0402_5% <11,12,16,28,38,5> DDR_XDP_WAN_SMBDAT SDA TD0
0.1U_0402_16V4Z
1 PXDP@ 2 DDR_XDP_WAN_SMBCLK_R2 53 54
<11,12,16,28,38,5> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56
RH27 0_0402_5% PCH_JTAG_TDI 1
PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
TCK0 TMS
PXDP@
NO REBOOT STRAP
CH103
59 60
GND16 GND17
2
DISABLED WHEN LOW (DEFAULT) PCH_RTCX1 RH37 RH38 SAMTE_BSH-030-01-L-D-A CONN@ 2
10K_0402_5% 10K_0402_5%
ENABLED WHEN HIGH <14,25,28,29,30,35,37,39,5> PLT_RST# BAT_GRNLED# <30,39> 1 2 PCH_RTCX2
RH28 10M_0402_5%
1
2
5
+3V_PCH
QH11B
G
G
QH11A
D
RH30 2.2K_0402_5%
4
1 2 HDD_HALTLED
18P_0402_50V8J
+3VS
RH33 100K_0402_5% MESS84DW-G_SC88-6 MESS84DW-G_SC88-6
1 1
OSC
OSC
20120709 Change by HP request
CH13 CH14
20120919 Change QH11 to PMOS 18P_0402_50V8J
FLASH DESCRIPTOR SECURITY OVERRIDE
C 20120802 HP's request 2 2 C
YH1
NC
NC
LOW = DESABLED (DEFAULT)
LPT_PCH_M_EDS
HIGH = ENABLED UH1A REV = 5
3
BC8 SATA_PRX_DTX_N0
B5 SATA_RXN_0 BE8 SATA_PRX_DTX_N0 <23>
PCH_RTCX1 SATA_PRX_DTX_P0
RTCX1 SATA_RXP_0 SATA_PRX_DTX_P0 <23>
PCH_RTCX2 B4 AW8 SATA_PTX_DRX_N0
HDD_Primary
RTCX2 SATA_TXN_0 AY8 SATA_PTX_DRX_N0 <23>
SATA_PTX_DRX_P0
RTC
SATA_TXP_0 SATA_PTX_DRX_P0 <23>
+RTCVCC RH34 1 2 20K_0402_5% SRTCRST# B9
SRTCRST# BC10 SATA_PRX_DTX_N1
SATA_RXN_1 SATA_PRX_DTX_N1 <23>
RH35 1 2 1M_0402_5% INTRUDER# A8 BE10 SATA_PRX_DTX_P1
INTRUDER# SATA_RXP_1 SATA_PRX_DTX_P1 <23>
1 2 PCH_INTVRMEN G10 AV10 SATA_PTX_DRX_N1
ODD
<25> WWAN_DET# INTVRMEN SATA_TXN_1 AW10 SATA_PTX_DRX_N1 <23>
RH230 0_0402_5% SATA_PTX_DRX_P1
SATA_TXP_1 SATA_PTX_DRX_P1 <23>
RH36 1 2 20K_0402_5% PCH_RTCRST# D9
RTCRST#
SATA
CMOS_CLR1 CMOS setting SATA_RXN_2
BB9 SATA_PRX_DTX_N2
SATA_PRX_DTX_N2 <33>
BD9 SATA_PRX_DTX_P2
SATA_RXP_2 SATA_PRX_DTX_P2 <33>
Shunt Clear CMOS <14> PCH_RTCRST# HDA_BIT_CLK B25
HDA_BCLK DOCK_SATA2
AY13 SATA_PTX_DRX_N2
SATA_TXN_2 SATA_PTX_DRX_N2 <33>
Open Keep CMOS 1
1 2
2 1
1 2
2 HDA_SYNC A22
HDA_SYNC SATA_TXP_2
AW13 SATA_PTX_DRX_P2
SATA_PTX_DRX_P2 <33>
HDA_SPKR AL10 BC12 SATA_PRX_DTX_N3
<26> HDA_SPKR SPKR SATA_RXN_3 SATA_PRX_DTX_N3 <33>
ME_CLR1 TPM setting SATA_RXP_3
BE12 SATA_PRX_DTX_P3
SATA_PRX_DTX_P3 <33>
@ @ HDA_RST# C24
Shunt Clear ME RTC Registers ME1 SHORT PADS CMOS1 SHORT PADS HDA_RST# AR13 SATA_PTX_DRX_N3
DOCK_SATA3
1 2 1 2 L22 SATA_TXN_3 AT13 SATA_PTX_DRX_N3 <33>
AZALIA
HDA_SDI0 SATA_PTX_DRX_P3
<26> HDA_SDI0 HDA_SDI0 SATA_TXP_3 SATA_PTX_DRX_P3 <33>
Open Keep ME RTC Registers CH15 1U_0402_6.3V6K CH16 1U_0402_6.3V6K
K22
CMOS place near DIMM HDA_SDI1 BD13 SATA_PRX_DTX_N4
G22 SATA_RXN4/PERN1 BB13 SATA_PRX_DTX_N4 <23>
SATA_PRX_DTX_P4
HDA_SDI2 SATA_RXP4/PERP1 SATA_PRX_DTX_P4 <23> HDD_Secondary
F22 AV15 SATA_PTX_DRX_N4
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_PTX_DRX_N4 <23>
SATA_PTX_DRX_P4
A24 SATA_TXP4/PETP1 SATA_PTX_DRX_P4 <23>
B HDA_SDOUT B
HDA_SDO BC14 SATA_PRX_DTX_N5
B17 SATA_RXN5/PERN2 BE14 SATA_PRX_DTX_N5 <23>
20120703 HDD_HALTLED SATA_PRX_DTX_P5
<39> HDD_HALTLED DOCKEN#/GPIO33 SATA_RXP5/PERP2 SATA_PRX_DTX_P5 <23>
+3V_PCH ISO_PREP# C22 AP15 SATA_PTX_DRX_N5 mSATA +3VS
HDA_SYNC Isolation Circuit +5VS
<33,36> ISO_PREP# HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2
SATA_TXP5/PETP2
AR15 SATA_PTX_DRX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5
<23>
<23>
1
AY5 SATA_COMP R463 1 2 10K_0402_5% 10K_0402_5%
SATA_RCOMP +3VS
2
R7
G
#4/18 change by
QH2 HP requirement AP3 SATA_ACT#
SATA_ACT# <33,39>
2
HDA_SYNC_R 3 1 HDA_SYNC SATALED#
SG_IN <22>
RH39 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 SG_IN
S
@ JTAG_TCK SATA0GP/GPIO21
SB000002X00
1
BSS138W-7-F_SOT323-3 RH40 1 2 PCH_JTAG_TMS AD1 AU2 FN9
@ JTAG_TMS SATA1GP/GPIO19
200_0402_5% PAD~D T72 @
10K_0402_5%
2
JTAG
@ JTAG_TDI SATA_IREF +1.5VS R8
RH43 200_0402_5% RH42 0_0402_5%
1M_0402_5% RH44 1 @ 2 PCH_JTAG_TDO AD3 BA2
2
200_0402_5% JTAG_TDO TP9
1 2 PCH_TP25 F8 BB2
RH237
1
TP25 TP8
100_0402_1%
100_0402_1%
100_0402_1%
RH45 0_0402_5%
1
C26 +3VS
1 2
TP22
RH46
RH47
RH48
AB6 10K_0402_5%
TP20
1
D Q70
2
3
RTC Circuit +1.5VS
1 2 HDA_SDOUT SATA_COMP 1 2
+RTCVCC +3VDS +BATT1.1 <26> HDA_SDOUT_AUDIO
RH50 33_0402_5% 7.5K_0402_1% RH49
A A
1 2 HDA_SYNC_R
<26> HDA_SYNC_AUDIO
RH51 33_0402_5% CAD note:
D40 1 2 HDA_RST#
2 <26> HDA_RST_AUDIO#
RH52 33_0402_5%
Place the resistor within 500 mils of the PCH. Avoid
1 RH233 JBATT1 1 2 HDA_BIT_CLK routing next to clock pins.
W=20mils 3 +BATT_D 1 2 1 <26> HDA_BITCLK_AUDIO
1 RH53 33_0402_5%
W=20mils W=20mils W=20mils 2
27P_0402_50V8J
1 G1 1
4
1U_0603_10V4Z G2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 Place near PCH ACES_50273-0020N-001
2 Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-RTC,HDA,SATA,XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 13 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +3V_PCH
+RTCVCC
1 2 SUS_PWR_ACK
+3VS
330K_0402_5%
RH63 10K_0402_5%
2
1 2 PCH_PCIE_WAKE# +3VDS
RH55
RH64 10K_0402_5% PCI_PIRQA# 2 1
1 2 PCH_RI# 8.2K_0402_5% RH56
JME1 DSWODVREN - ON DIE DSW VR ENABLE PCI_PIRQB# 2 1
RH72 10K_0402_5% 1
1 8.2K_0402_5% RH57
1 2 BT_OFF 2 HIGH = ENABLED (DEFAULT)
1
SLP_S3# PCI_PIRQC# 2 1
RH75 10K_0402_5% 3 2
+3VS SLP_S5# 4 3 LOW = DISABLED 8.2K_0402_5% RH59
4 PCI_PIRQD# 2 1
SLP_S4# 5 DSWODVREN 8.2K_0402_5% RH60
1 2 SIO_SLP_A# 6 5
D PM_CLKRUN# PWRSV_SEL# 2 1 D
7 6 16
RH78 8.2K_0402_5% 10K_0402_5% RH62
8 7 G2 15
1 2 SLP_LAN# 8 G1 DGPU_HOLD_RST# 2 1
RH70 10K_0402_5% <13> PCH_RTCRST# PCH_RTCRST# 9 10K_0402_5% RH66
10 9
10 DGPU_PWR_EN 2 1
ON/OFFBTN# 11
11
A16 SWAP OVERRIDE STRAP 10K_0402_5% RH69
12 ODD_DA# 2 1
SYS_RESET# 13 12
1 2 SYS_RESET# 13 10K_0402_5% RH71
<13,5> XDP_DBRESET#
RH54 0_0402_5%
14
14
STP_A16OVR LOW = A16 SWAP OVERRIDE NMI_SMI_DBG# 2 1
FCI_10051922-1410ELF HIGH = DEFAULT 100K_0402_5% RH74
PCH_DPWROK 1 2 PM_RSMRST# PCH_CRT_DDC_CLK 2 1
20120920 HP's request
CONN@ 2.2K_0402_5% RH76
RH67 0_0402_5%
@ RH246 PCH_CRT_DDC_DAT 2 1
1 2 2.2K_0402_5% RH77
<30> VCC1_PWRGD DGPU_SELECT# 2 1
0_0402_5% 20120920 Add ME debug circuit for HP's request 1 2 PCH_CRT_BLU 10K_0402_5% RH80
RH98 150_0402_1% Camera_ON 2 1
20120810 HP's request 1 2 PCH_CRT_GRN 10K_0402_5% RH82
RH99 150_0402_1% ACCEL_INT_R# 2 1
1 2 PCH_CRT_RED 8.2K_0402_5% RH83
RH100 150_0402_1% CR_SX_WARN# 2 1
1 2 ENVDD_PCH 10K_0402_5% RH245
LPT_PCH_M_EDS RH101 100K_0402_5%
UH1B REV = 5
20120723 HP's request
CRT
AV45 <36> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK
DMI_CRX_PTX_N2 BD17 TP15
<4> DMI_CRX_PTX_N2 DMI_TXN_2 1 2 HSYNC N42 N38
DMI_CRX_PTX_N3 BE18 AW44 <36> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA
<4> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 RH84 20_0402_1%
1 2 VSYNC N44
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC <36> PCH_CRT_VSYNC VGA_VSYNC
<4> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <4> RH85 20_0402_1% H45
DMI_CRX_PTX_P1 BC20 1 2 CRT_IREF U40 DDPB_AUXN
<4> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 FDI_INT RH87 649_0402_1% DAC_IREF K43
FDI_INT FDI_INT <4>
DMI_CRX_PTX_P2 BB17 U39 DDPC_AUXN
<4> DMI_CRX_PTX_P2 BC18 DMI_TXP_2 AT45 1 2
DISPLAY
DMI_CRX_PTX_P3 FDI_IREF +1.5VS VGA_IRTN J42
<4> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF RH86 0_0402_5% DDPD_AUXN
+1.5VS
1 2 DMI_IREF BE16 AU42 BKL_PWM_PCH N36 H43
RH88 0_0402_5% DMI_IREF TP17 <35> BKL_PWM_PCH EDP_BKLTCTL DDPB_AUXP
LVDS
AW17 AU44 K36 K45
TP12 TP13 <35> PANEL_BKEN_PCH EDP_BKLTEN DDPC_AUXP
AV17 AR44 FDI_RCOMP 2 1 +1.5VS ENVDD_PCH G36 J44
TP7 FDI_RCOMP 7.5K_0402_1% RH89 <35> ENVDD_PCH EDP_VDDEN DDPD_AUXP
+1.5VS
1 2 DMI_RCOMP AY17 K40
RH90 7.5K_0402_1% DMI_RCOMP DDPB_HPD
20120911 HP's request PCI_PIRQA# H20
<30> SUSACK# PIRQA# K38
PCI_PIRQB# L20 DDPC_HPD
SIO_SLP_SUS# 1 @ 2 SUSACK# R6 C8 DSWODVREN PIRQB# H39
R230 0_0402_5% SUSACK# DSWVRMEN DDPD_HPD
System Power PCI_PIRQC# K17
SYS_RESET# AM1 L13 PCH_DPWROK PIRQC#
SYS_RESET# Management DPWROK 20120705 Correct net name to follow GPIO table
PCI_PIRQD# M20
<30,5> PM_PWROK RH92 1 2 0_0402_5% SYS_PWROK_R AD7 K3 PCH_PCIE_WAKE# PCH_PCIE_WAKE# <25,39> PIRQD# PCI G17 PWRSV_SEL#
SYS_PWROK WAKE# PIRQE#/GPIO2 PWRSV_SEL# <37>
DGPU_HOLD_RST# A12
RH93 1 2 0_0402_5% PCH_PWROK F10 AN7 PM_CLKRUN# <35> DGPU_HOLD_RST# GPIO50
1> PCH_PWROK_R PWROK CLKRUN# PM_CLKRUN# <28,30,32> F17 ODD_DA# ODD_DA# <23>
DGPU_SELECT# B13 PIRQF#/GPIO3
RH221 1 2 0_0402_5% PM_APWROK_R AB7 U7 BT_OFF <35,36> DGPU_SELECT# GPIO52
<30,31> PM_APWROK APWROK SUS_STAT#/GPIO61 BT_OFF <25> L15 NMI_SMI_DBG# NMI_SMI_DBG# <30>
20120911 HP request DGPU_PWR_EN C12 PIRQG#/GPIO4
RH94 1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK_KBC <15,35> DGPU_PWR_EN GPIO54
<5> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK_KBC <30> M15 ACCEL_INT_R# 2 1
B 0_0402_5% PIRQH#/GPIO5 ACCEL_INT# <28> B
+3VS
1 2 PCH_GPIO51 C10 0_0402_5% RH96
<13,30> PM_RSMRST# 1 2 PCH_RSMRST#_R J2 Y7 SLP_S5# T85 PAD~D@ RH147 100K_0402_5% GPIO51 AD10 @ T87 PAD~D
RH95 0_0402_5% RSMRST# SLP_S5#/GPIO63 PME#
T86 PAD~D @ Camera_ON 20120920 A10
1 2 ME_SUS_PWR_ACK_R J4 C6 SLP_S4# <22> Camera_ON GPIO53
<30> SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# SLP_S4# <44> Y11 PLTRST#
RH97 0_0402_5% CR_SX_WARN# AL6 PLTRST#
ON/OFFBTN# K1 H1 SLP_S3# <39> CR_SX_WARN# GPIO55
<13,30,5> ON/OFFBTN# PWRBTN# SLP_S3# SLP_S3# <30,31,34,39,44,9> 5 OF 11
<30,35> AC_PRES_OUT AC_PRES_OUT E6 F3 SIO_SLP_A#
ACPRESENT/GPIO31 SLP_A# SIO_SLP_A# <30,31,45> LYNXPOINT_BGA695
T88 PAD~D @ 20120723
@ T150 PAD~D GPIO72 K7 F1 SIO_SLP_SUS#
BATLOW#/GPIO72 SLP_SUS# SIO_SLP_SUS# <34>
T89 PAD~D @ +3V_PCH
20120911 Change BT_OFF to GPIO61 PCH_RI# N4 AY3 H_PM_SYNC
RI# PMSYNCH H_PM_SYNC <5> CH20
20120810 HP's request
1 2
@ T90 PAD~D AB10 G5 SLP_LAN#
TP21 SLP_LAN# SLP_LAN# <29,30>
0.1U_0402_16V4Z
SLP_WLAN# D2
<25,44> SLP_WLAN# SLP_WLAN#/GPIO29
2 OF 11
5
UH3
LYNXPOINT_BGA695
VCC
PLTRST# 1
IN1 4PLT_RST#
OUT PLT_RST# <13,25,28,29,30,35,37,39,5>
2
GND
IN2
1
@ CH107
Boot BIOS Strap MC74VHC1G08DFT2G_SC70-5
3
22P_0402_50V8J
2
PCH_GPIO51 SATA1GP/
GPIO19 Boot BIOS Location 20120713 Add for ESD's request
1 0 PCI
1 1 SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH -DMI,FDI,PM,DP,CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 14 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
+3V_PCH
2
10K_0402_5%
RH106
1
GFX_CLK_REQ#
D D
FN14
<13> FN14
FN15
<13> FN15
LPT_PCH_M_EDS
UH1C REV = 5
2
Y45 AB36 CLK_PCIE_VGA
G
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <35>
2N7002KW_SOT323-3
RH104 2 1 10K_0402_5% AB1 AF6 GFX_CLK_REQ# 1 3
+3V_PCH PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 PEG_CLK_REQ# <35>
S
20120911 HP's request 20120703 Follow HP's GPIO table
CLK_PCIE_CR# AA44 Y39
<39> CLK_PCIE_CR# CLKOUT_PCIE_N_1 CLKOUT_PEG_B
CLK_PCIE_CR AA42 RH109
<39> CLK_PCIE_CR CLKOUT_PCIE_P_1 Q55
RH105 2 1 10K_0402_5% Y38 2 1
+3VS CLKOUT_PEG_B_P +3V_PCH
RH203 2 1 0_0402_5% FN14 AF1
<39> CR_CLK_REQ# PCIECLKRQ1#/GPIO18 10K_0402_5%
U4 WLAN_TRAMSIT_OFF#
20120911 HP's request PEGB_CLKRQ#/GPIO56 WLAN_TRAMSIT_OFF# <25>
<39> CLK_TB_REFCLK# CLK_TB_REFCLK#AB43
CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
CLKOUT_DMI CLK_CPU_DMI# <5>
CLK_TB_REFCLK AB45
<39> CLK_TB_REFCLK CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI
CLKOUT_DMI_P CLK_CPU_DMI <5>
RH113 2 1 10K_0402_5% FN15 AF3
+3VS PCIECLKRQ2#/GPIO20/SMI#
RH205 2 1 0_0402_5% AJ40 CLK_CPU_SSC_DPLL#
<39> TB_CLKREQ# CLKOUT_DP CLK_CPU_SSC_DPLL# <5>
AD43 AJ39 CLK_CPU_SSC_DPLL
C CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <5> C
AD45
RH118 2 1 10K_0402_5% T3 CLKOUT_PCIE_P_3 AF35 CLK_CPU_DPLL#
+3V_PCH PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLK_CPU_DPLL# <5>
AF36 CLK_CPU_DPLL
CLKOUT_DPNS_P CLK_CPU_DPLL <5>
AF43
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI#
RH121 2 1 10K_0402_5% V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
+3V_PCH PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
20120911 HP's request CLK_PCIE_EXP# AE44 AR24 CLK_BUF_BCLK#
<39> CLK_PCIE_EXP# CLKOUT_PCIE_N5 CLKIN_GND
<39> CLK_PCIE_EXP CLK_PCIE_EXP AE42 AT24 CLK_BUF_BCLK
CLKREQ_EXP# AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
<39> CLKREQ_EXP# 2 1 10K_0402_5% PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
+3V_PCH RH125
CLK_PCIE_LAN# AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
<29> CLK_PCIE_LAN# CLKOUT_PCIE_N_6 CLKIN_DOT96P
CLK_PCIE_LAN AB39
<29> CLK_PCIE_LAN 20120911 HP's request CLK_PCIE_LAN_REQ1# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
<29> CLK_PCIE_LAN_REQ1# 2 1 10K_0402_5% PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
+3V_PCH RH128
CLK_PCIE_MINI1# AJ44 CLKIN_SATA_P
<25> CLK_PCIE_MINI1# CLKOUT_PCIE_N_7
20120911 HP's request F45 CLK_PCH_14M
CLK_PCIE_MINI1 AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
<25> CLK_PCIE_MINI1 CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
RH131 2 1 10K_0402_5%
+3V_PCH
MINI1_CLKREQ# Y3 AM43 XTAL25_IN
<25> MINI1_CLKREQ# PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT 1 2
AH43 XTAL25_OUT RH132 1M_0402_5%
CLKOUT_ITPXDP C40 20120807 Corret pin name as Intel's specification
AH45 CLKOUTFLEX0/GPIO64 PAD~D T91 @
RH135 2 1 10_0402_5% CLKOUT_ITPXDP_P F38 SIO_14M RH136 2 1 22_0402_5%
<30> CLK_PCI_KBC CLK_SIO_14M <32> YH2
RH137 2 1 10_0402_5% CLK_PCI0 D44 CLKOUTFLEX1/GPIO65 2 1
<32> CLK_PCI_SIO CLKOUT_33MHZ0 F36
CLK_PCI_LOOPBACK RH138 2 1 22_0402_5% PCI_LOOPBACKOUT E44 CLKOUTFLEX2/GPIO66 PAD~D T92 @
CLKOUT_33MHZ1 F39
CLKOUTFLEX3/GPIO67 25MHZ_20PF_7A25000012
18P_0402_50V8J
RH139 2 1 22_0402_5% CLK_PCI2 B42
<28> CLK_PCI_TPM CLKOUT_33MHZ2
18P_0402_50V8J
AM45 ICLK_IREF 1 2 1
ICLK_IREF +1.5VS
F41 0_0402_5% RH140 1
B CLKOUT_33MHZ3 AD39 CH21 CH22 B
RH141 2 1 22_0402_5% CLK_PCI4 A40 TP19 AD38
<25> CLK_PCI_DEBUG CLKOUT_33MHZ4 TP18 2
RH234 2 1 22_0402_5% AN44 PCH_CLK_BIASREF 1 2 2
<30> CLK_PCI_DEBUG_KBC DIFFCLK_BIASREF +1.5VS
CLOCK SIGNAL 7.5K_0402_1% RH142
LYNXPOINT_BGA695 2 OF 11
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH- CLK
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 15 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com +3V_PCH
FPR_OFF 2 1
10K_0402_5% RH143
MEM_SMBCLK 2 1
2.2K_0402_5% RH144
MEM_SMBDATA 2 1
2.2K_0402_5% RH146
DDR_RST_EN 2 1
2.2K_0402_5% RH148 20120807 Change RH148 to 2.2K as HP's request
NFC_RST# 2 1
10K_0402_5% RH149
SML1_SMBCLK 1 2
20120703 Add RH149 for NFC
D D
2.2K_0402_5% RH150
SML1_SMBDATA 1 2
2.2K_0402_5% RH151
+3VM_LAN
+3VS LAN_SMBCLK 2 1
2.2K_0402_5% RH152
LAN_SMBDATA 2 1
1 2 SIRQ 2.2K_0402_5% RH153
RH145 10K_0402_5%
+3VS
LPT_PCH_M_EDS
UH1D REV = 5
2
N7 FPR_OFF
SMBALERT#/GPIO11 FPR_OFF <28>
LPC_LAD0 A20
<25,28,30,32> LPC_LAD0 LAD_0
SMBus R10 MEM_SMBCLK MEM_SMBCLK 6 1
SMBCLK DDR_XDP_WAN_SMBCLK <11,12,13,28,38,5>
LPC_LAD1 C20
<25,28,30,32> LPC_LAD1 LAD_1 DMN66D0LDW-7_SOT363-6
U11 MEM_SMBDATA QH3A
SMBDATA
5
LPC_LAD2 A18
LPC
<25,28,30,32> LPC_LAD2 LAD_2 N8 DDR_RST_EN
SML0ALERT#/GPIO60 DDR_RST_EN <5>
LPC_LAD3 C18 MEM_SMBDATA 3 4
<25,28,30,32> LPC_LAD3 LAD_3 DDR_XDP_WAN_SMBDAT <11,12,13,28,38,5>
U8 LAN_SMBCLK
SML0CLK LAN_SMBCLK <29> DMN66D0LDW-7_SOT363-6
LPC_LFRAME# B21 QH3B
<25,28,30,32> LPC_LFRAME# LFRAME# R7 LAN_SMBDATA
SML0DATA LAN_SMBDATA <29>
D21
<32> LPC_LDRQ0# LDRQ0# +3VS
H6 NFC_RST#
SML1ALERT#/PCHHOT#/GPIO74 NFC_RST# <39>
G20
C LDRQ1#/GPIO23 K6 SML1_SMBCLK
C
5
QH10B 2 1
@ +3VS
AF11 CL_CLK1 2.2K_0402_5%
CL_CLK CL_CLK1 <25> LAN_SMBCLK 3 4
PCH_SPI_CLK 1 2 PCH_SPI_CLK_R AJ11 NFC_3S_SMBCLK <39>
SPI
<30> PCH_SPI_CLK SPI_CLK
RH154 4.99_0402_1% AF10 CL_DATA1 DMN66D0LDW-7_SOT363-6
C-Link CL_DATA CL_DATA1 <25> @ RH239
PCH_SPI_CS0# 1 2 PCH_SPI_CS0#_R AJ7
2
<30> PCH_SPI_CS0# SPI_CS0# 2 1
RH155 4.99_0402_1% AF7 CL_RST1# +3VS
CL_RST# CL_RST1# <25>
AL7 2.2K_0402_5%
SPI_CS1# LAN_SMBDATA 6 1
NFC_3S_SMBDAT <39>
AJ10 QH10A DMN66D0LDW-7_SOT363-6
SPI_CS2# BA45
TP1 @
<30> PCH_SPI_SI PCH_SPI_SI 2 1 PCH_SPI_SI_R AH1
RH156 4.99_0402_1% SPI_MOSI BC45
PCH_SPI_SO 2 1 PCH_SPI_SO_R AH3 Thermal TP2 20120703 Add for NFC
<30> PCH_SPI_SO SPI_MISO
RH157 4.99_0402_1% BE43 20120920 Uninstall QH10, RH238, RH239
PCH_SPI_WP# 2 1 PCH_SPI_WP#_R AJ4 TP4
<30> PCH_SPI_WP# 15_0402_5% SPI_IO2 DMN66D0LDW-7_SOT363-6
RH243 BE44
PCH_SPI_HOLD# 2 1 PCH_SPI_HOLD#_R AJ2 TP3 QH9A
<30> PCH_SPI_HOLD# RH244 SPI_IO3 SML1_SMBCLK 1 6
15_0402_5% AY43 PCH_TD_IREF 1 2 PCH_KBC_I2CLK <30,35>
TD_IREF RH158 8.2K_0402_1%
20120719 HP's request
20120726 HP's request +3V_PCH
2
4 OF 11 QH9B
LYNXPOINT_BGA695 SML1_SMBDATA 4 3
PCH_KBC_I2CDAT <30,35>
DMN66D0LDW-7_SOT363-6
+3V_PCH
5
B B
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
1
1
1
1
1
1
1
1
H27 H24 H28 H38 H1 H4 H6 H8 H7 H37 H41 H46 H36
H_3P0 H_3P0 H_3P0 H_3P0 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_2P1N H_3P3N H_2P6X2P1N H_3P6X2P1N
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
1
1
1
FD1 FD2
FIDUCIAL_C40M80 FIDUCIAL_C40M80 H44 H45
H42 H43 H34 H15 H30 H39 H_3P0N H_3P0N
H_3P0 H_3P0 H_6P0X7P0 H_3P8 H_3P8 H_3P8
ZZZ1 ZZZ2
@ @ HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
A FD3 FD4 A
@ @
1
1
@ @ @ @ @ @ FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
1
1
1
1
PCB DCIN 45@
MB @ @
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH - SPI, SMBUS,LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 16 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
D D
LPT_PCH_M_EDS
UH1I REV = 5
PCIe
PCIE_PRX_EXPTX_N5 AW36 USB2N12 F26 USBP12+ ----->WWAN
<39> PCIE_PRX_EXPTX_N5
USB
PCIE_PRX_EXPTX_P5 AV36 PERN_5 USB2P12 F24 USBP13- USBP12+ <25>
<39> PCIE_PRX_EXPTX_P5 PERP_5 USB2N13 USBP13- <25>
Express card slot USB2P13
G24 USBP13+
USBP13+ <25> ----->BT/WLAN Combo
CH1001 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_N5_CBD37
<39> PCIE_PTX_EXPRX_N5 PETN_5
CH99 1 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_P5_C BB37
<39> PCIE_PTX_EXPRX_P5 PETP_5 AR26 USB3RN1 USBRBIAS
USB3RN1 USB3RN1 <33>
<29> PCIE_PRX_DTX_N6
PCIE_PRX_DTX_N6 AY38
PERN_6 USB3RP1
AP26 USB3RP1
USB3RP1
----->Docking USB 3.0
<33>
22.6_0402_1%
PCIE_PRX_DTX_P6 AW38 BE24 USB3TN1
<29> PCIE_PRX_DTX_P6 PERP_6 USB3TN1 USB3TN1 <33>
1
BD23 USB3TP1
GIGA LAN USB3TP1 USB3TP1 <33>
RH159
<29> PCIE_PTX_C_DRX_N6 CH31 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N6 BC38 AW26 USB3RN2
PETN_6 USB3RN2 USB3RN2 <39>
<29> PCIE_PTX_C_DRX_P6 CH32 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P6 BE38
PETP_6 USB3RP2
AV26 USB3RP2
USB3RP2
----->USB 3.0 Walkup port 2
<39>
BD25 USB3TN2
PCIE_PRX_DTX_N7 AT40 USB3TN2 BC24 USB3TP2 USB3TN2 <39>
<25> PCIE_PRX_DTX_N7 USB3TP2 <39>
2
PCIE_PRX_DTX_P7 AT39 PERN_7 USB3TP2 AW29 USB3RN5
<25> PCIE_PRX_DTX_P7 PERP_7 USB3RN5 USB3RN5 <39>
WLAN USB3RP5
AV29 USB3RP5
USB3RP5
----->USB 3.0 Walkup port 5
<39>
CH33 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N7 BE40 BE26 USB3TN5
<25> PCIE_PTX_C_DRX_N7 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P7 BC40 PETN_7 USB3TN5 BC26 USB3TP5 USB3TN5 <39>
CH34
<25> PCIE_PTX_C_DRX_P7 PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 <39>
AN38 USB3RN6 AP29 USB3RN6 <39>
PCIE_PRX_DTX_N8 USB3RP6 CAD NOTE:
<39> PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8 AN39 PERN_8 USB3RP6 BD27 USB3TN6
USB3RP6 ----->USB 3.0 Walkup port 6
<39>
<39> PCIE_PRX_DTX_P8 PERP_8 USB3TN6 BE28 USB3TP6 USB3TN6 <39> Route single-end 50-ohms and max 500-mils length.
Card Reader CH35 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N8 BD42 USB3TP6 USB3TP6 <39> Avoid routing next to clock pins or under stitching capacitors.
<39> PCIE_PTX_C_DRX_N8 PETN_8
<39> PCIE_PTX_C_DRX_P8 CH36 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P8 BD41 K24 USBRBIAS Recommended minimum spacing to other signal traces is 15 mils.
PETP_8 USBRBIAS# K26
USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33
+1.5VS PCIE_IREF TP24 +3V_PCH
RH160 0_0402_5% L33
TP23
BC30 P3 USB_OC0#_R RPH1
B TP11 OC0#/GPIO59 USB_OC0#_R <13> USB_OC0#_R 4 5 B
V1 USB_OC1#_R
OC1#/GPIO40 USB_OC1#_R <13> dGPU_HPD_INTR 3 6
U2 USB_OC2#
OC2#/GPIO41 USB_OC2# <13> USB_OC2# 2 7
BB29 P1 USB_OC3#
TP6 OC3#/GPIO42 USB_OC3# <13> USB_OC1#_R 1 8
M3 USB_OC4#_R
OC4#/GPIO43 USB_OC4#_R <13>
T1 dGPU_HPD_INTR 20120911 For DB1-R
OC5#/GPIO9 dGPU_HPD_INTR <13,35> 10K_1206_8P4R_5%
1 2 PCH_PCIE_RCOMP BD29 N2 platform ID
+1.5VS PCIE_RCOMP OC6#/GPIO10 LED_LINK_LAN#_R <13,29>
RH164 7.5K_0402_1% M1 USB_OC7#_R RH1651 @ 2 0_0402_5%
OC7#/GPIO14 USB_OC7# <13> RPH2
9 OF 11 RH2421 2 0_0402_5% USB_OC4#_R 4 5
TB_HOT_PLUG# <39>
LYNXPOINT_BGA695 USB_OC7#_R 3 6
20120718 HP's request LED_LINK_LAN#_R 2 7
USB_OC3# 1 8
10K_1206_8P4R_5%
20120702 Swap for layout routing
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-PCIE,USB
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 17 of 53
5 4 3 2 1
5 4 3 2 1
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+3VS 2N7002KW_SOT323-3 Q58
1
D +3VS
2 1 PCH_GPIO0 2
RH167 10K_0402_5% <30> OCP_PWM_OUT
G A20GATE 2 1
2 1 OCP_OC# S UH1F LPT_PCH_M_EDS REV = 5 10K_0402_5% RH166
3
RH169 100K_0402_5% RCIN# 2 1
2 1 THERM_SCI# PCH_GPIO0 AT8 10K_0402_5% RH168
RH240 10K_0402_5% BMBUSY#/GPIO0
2 1 ODD_EN 20120705 Add PU resistor
OCP_OC# F13
RH171 10K_0402_5% TACH1/GPIO1
1 2 DGPU_PWROK EC_SCI# A14
RH175 8.2K_0402_5% <30> EC_SCI# TACH2/GPIO6
2 1 FPR_LOCK# THERM_SCI# G15 CPU/Misc
@ RH176 10K_0402_5% TACH3/GPIO7
1 2 DOCK_ID0 PCH_GPIO8 Y1
RH177 10K_0402_5% <13> PCH_GPIO8 GPIO8
D D
1 2 DOCK_ID1 LAN_DIS# K13
RH172 10K_0402_5% <29> LAN_DIS# LAN_PHY_PWR_CTRL/GPIO12 AN10 A20GATE
1 2 KBC_SIO_RST# TP14 A20GATE <30>
PCH_GPIO15 AB11
RH173 10K_0402_5% GPIO15 AY1 PAD~D T104 @
1 2 EC_SCI# KBL_DET# AN2 PECI
RH178 10K_0402_5% <13,38> KBL_DET# SATA4GP/GPIO16 AT6 RCIN#
2 1 WWAN_TRANSMIT_OFF# DGPU_PWROK C14 GPIO RCIN#
<35> DGPU_PWROK TACH0/GPIO17
RH241 10K_0402_5% 20120705 Add PU resistor AV3 H_CPUPWRGD +1.05VS
PROCPWRGD H_CPUPWRGD <5>
WWAN_TRANSMIT_OFF# BB4
+3V_PCH <25> WWAN_TRANSMIT_OFF# SCLOCK/GPIO22 AV1 PCH_THERMTRIP#_R 2 1
PCH_GPIO24 Y10 THRMTRIP# RH179 56_0402_5%
GPIO24
0.1U_0402_16V4Z
AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <5>
LANWAKE# R11 1
<29> LANWAKE# GPIO27
2 1 PCH_GPIO24 N10
VSS
CH37
RH182 10K_0402_5% PCH_GPIO28 AD11 PCH_THERMTRIP#_R PCH_THERMTRIP#_R <35,5>
2 1 GPIO28
PCH_GPIO8
RH183 10K_0402_5% PCH_GPIO34 AN6 2
20120801 HP's request GPIO34
2 1 LAN_DIS#
RH184 10K_0402_5% <13,23> mSATA_DET# mSATA_DET# AP1
2 1 GPIO35/NMI#
@ NFC_INT
RH185 10K_0402_5% <13> Sec_HDD_DET Sec_HDD_DET AT3
SATA2GP/GPIO36
20120703 Change for NFC PCH_GPIO37 AK1
<13> PCH_GPIO37 SATA3GP/GPIO37
+3V_PCH
DOCK_ID0 AT7
SLOAD/GPIO38
DOCK_ID1 AM3 A2
2
4.7K_0402_5%
2 1 Sec_HDD_DET
RH198 10K_0402_5%
2 1 PCH_GPIO37 20120801 HP's request
RH200 10K_0402_5%
+3VS
1 2 KBL_DET#
Config GPIO16,49 RH197 10K_0402_5%
2 1 DGPU_PRSNT#
RH199 10K_0402_5% 1 2 PCH_GPIO15 GPIO15
USB X4,PCIEX8,SATAX6 11 RH181 1K_0402_1%
1 2 PCH_GPIO34 GPIO34
RH170 100K_0402_5%
USB X6,PCIEX8,SATAX4 01 +3VS 1 2 mSATA_DET# GPIO35
RH180 10K_0402_5%
20120801 HP's request
20120911 HP's request
DB2 0 0 1 0
SI1 0 1 0 0
SI1B 0 1 0 1
A SI2 0 1 1 0 A
PV1 1 0 0 0
MV 1 1 0 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH -GPIO,MISC,NTFC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 18 of 53
5 4 3 2 1
5 4 3 2 1
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D D
LH1
+VCCADAC 2 1
+1.5VS
BLM18PG181SN1D_2P
0.01U_0402_16V7K
0.1U_0402_16V4Z
10U_0603_6.3V6M
1 1 1
CH40
CH41
CH42
2 2 2
LPT_PCH_M_EDS
UH1G REV = 5
+1.5VS
+1.05VS P45
VCCADAC1_5
AA24 P43
VCC CRT DAC VSS +1.05VS
10U_0603_6.3V6M
AA26
VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 AD20 M31 1
VCC VCCADACBG3_3 +3VS
1U_0402_6.3V6K
AD22 @
VCC
CH38
CH39
CH43
CH44
CH45
C AD24 C
VCC 1
AD26 BB44
2 2 2 2 VCC VCCVRM +3VS 2
CH46
AD28
AE18 VCC FDI
AN34
AE20 VCC VCCIO 2
AE22 VCC AN35
VCC VCCIO +3V_PCH
0.1U_0402_16V4Z
AE24
AE26 VCC R30
VCC HVCMOS VCC3_3_R30 1
AG18 R32
VCC VCC3_3_R32
0.1U_0402_16V4Z
CH47
AG20
AG22 VCC Y12 +PCH_USB_DCPSUS1
VCC DCPSUS1 T142 1 2
AG24
VCC
CH48
Y26 AJ30
VCC VCCSUS3_3
Core
AJ32
VCCSUS3_3 2
+1.05VM AJ26 +PCH_USB_DCPSUS3 +1.5VS
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 T143
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05VS
U18 AK26
VCCASW VCCVRM +1.5VS
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
U20 AK28 1
U22 VCCASW VCCVRM @
1 1 1 VCCASW
CH52
U24 BE22
VCCASW VCCVRM
CH49
CH50
CH51
V18 PCIe/DMI
VCCASW +1.5VS 2
10U_0603_6.3V6M
V20 AK18 1
2 2 2 VCCASW VCCIO +1.05VS
V22 @
VCCASW
CH53
V24 AN11
Y18 VCCASW VCCVRM
VCCASW SATA 2
10U_0603_6.3V6M
Y20 AK22 1
Y22 VCCASW VCCIO +1.05VS @
VCCASW
CH54
AM18
VCCIO AM20
VCCIO AM22 2
B VCCMPHY VCCIO AP22 B
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1
VCCIO AT22
VCCIO
CH55
CH56
CH57
CH58
CH59
7 OF 11
LYNXPOINT_BGA695 2 2 2 2 2
1 2 +PCH_VCCDSW
RH204 5.11_0402_1%~D
+PCH_VCCDSW_R
1U_0402_6.3V6K
1
CH61
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH- Power
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 19 of 53
5 4 3 2 1
5 4 3 2 1
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D D
+3V_PCH
2 1
UH1H LPT_PCH_M_EDS REV = 5 0_0402_5% RH208
0.1U_0402_10V6K
2 1 +3VDS
+3V_PCH +3V_PCH 0_0402_5% @ RH209
1
CH64
R24 R20 CH104
R26 VCCSUS3_3 VCCSUS3_3 R22 1 2
VCCSUS3_3 VCCSUS3_3
0.1U_0402_10V6K
R28
+1.05VS U26 VCCSUS3_3 GPIO/LPC 0.1U_0402_10V6K 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3
CH65
M24
VSS AA14 +PCH_VCCSST 1 2 +3VS
2 +3VS DCPSST
0.1U_0402_10V6K
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH67
0.01U_0402_16V7K_X7R
AG14
VCC3_3 +3V_PCH
0.1U_0402_10V6K
U30 1
2 VCCIO
CH69
1 +1.05VS V28
VCCIO
CH68
0.1U_0402_10V7K~D
+1.5VS T144 S2 Y35 Azalia
DCPSUS2 A26
1 VCCSUSHDA 1
AF34
VCCVRM
CH70
CH71
+RTCVCC
10U_0603_6.3V6M
1U_0402_6.3V6K
1 +1.05VS_VCC AP45 K8 1
2 VCC VCCSUS3_3 2
CH72
CH73
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
C 2 RTC 2 C
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
+PCH_VCCCLK3_3 M29 P14
+PCH_DCPRTC
VCCCLK3_3 DCPRTC P16 CH74 1 2 0.1U_0402_10V7K~D
DCPRTC 1 1 1
L29 +1.05VS
VCCCLK3_3
CH75
CH76
CH77
CH105 1 2 0.1U_0402_10V6K
L26 AJ12 CH83 1 2 0.1U_0402_10V6K
M26 VCCCLK3_3 V_PROC_IO AJ14 CH84 1 2 1U_0402_6.3V6K 2 2 2
CPU
VCCCLK3_3 V_PROC_IO
20120725 HP's request
U32
V32 VCCCLK3_3 AD12
ICC
VCCCLK3_3 SPI VCCSPI +3V_PCH
+PCH_VCCCLK AD34
VCCCLK 20120911 Delete RH226 HP's request
1U_0402_6.3V6K
P18 +3VS
AA30 VCC P20
VCCCLK VCC
1U_0402_6.3V6K
AA32 1
VCCCLK L17
Fuse VCCASW +1.05VM 1
CH79
AD35
+1.05VS +1.05VS_VCC VCCCLK
CH92
R18
LH2 AG30 VCCASW 2
1 2 +1.05VS_VCC AG32 VCCCLK 2
4.7UH_LQM18FN4R7M00D_20% VCCCLK AW40
VCCVRM +1.5VS
AD36
VCCCLK AK30 +3VS
VCC3_3
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 AE30 Thermal
AE32 VCCCLK AK32
VCCCLK VCC3_3
CH80
CH81
0.1U_0402_10V6K
2 2 8 OF 11 1
CH85
LYNXPOINT_BGA695
2
B B
+1.05VS +PCH_VCCCLK
1 2
RH213 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 1 1
CH87
CH88
CH89
CH90
CH91
@
CH86
2 2 2 2 2 2
Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32
+3VS +PCH_VCCCLK3_3
1 2
RH216 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CH93
CH94
CH95
CH96
2 2 2 2
A A
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH - Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 20 of 53
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5 4 3 2 1
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D D
REV = 5
AL34 K39 AA16 REV = 5 B19
AL38 VSS VSS L2 AA20 VSS VSS B23
AL8 VSS VSS L44 AA22 VSS VSS B27
AM14 VSS VSS M17 AA28 VSS VSS B31
AM24 VSS VSS M22 AA4 VSS VSS B35
AM26 VSS VSS N12 AB12 VSS VSS B39
AM28 VSS VSS N35 AB34 VSS VSS B7
AM30 VSS VSS N39 AB38 VSS VSS BA40
AM32 VSS VSS N6 AB8 VSS VSS BD11
AM16 VSS VSS P22 AC2 VSS VSS BD15
AN36 VSS VSS P24 AC44 VSS VSS BD19
AN40 VSS VSS P26 AD14 VSS VSS AY36
AN42 VSS VSS P28 AD16 VSS VSS AT43
AN8 VSS VSS P30 AD18 VSS VSS BD31
AP13 VSS VSS P32 AD30 VSS VSS BD35
AP24 VSS VSS R12 AD32 VSS VSS BD39
AP31 VSS VSS R14 AD40 VSS VSS BD7
AP43 VSS VSS R16 AD6 VSS VSS D25
C AR2 VSS VSS R2 AD8 VSS VSS AV7 C
AK16 VSS VSS R34 AE16 VSS VSS F15
AT10 VSS VSS R38 AE28 VSS VSS F20
AT15 VSS VSS R44 AF38 VSS VSS F29
AT17 VSS VSS R8 AF8 VSS VSS F33
AT20 VSS VSS T43 AG16 VSS VSS BC16
AT26 VSS VSS U10 AG2 VSS VSS D4
AT29 VSS VSS U16 AG26 VSS VSS G2
AT36 VSS VSS U28 AG28 VSS VSS G38
AT38 VSS VSS U34 AG44 VSS VSS G44
D42 VSS VSS U38 AJ16 VSS VSS G8
AV13 VSS VSS U42 AJ18 VSS VSS H10
AV22 VSS VSS U6 AJ20 VSS VSS H13
AV24 VSS VSS V14 AJ22 VSS VSS H17
AV31 VSS VSS V16 AJ24 VSS VSS H22
AV33 VSS VSS V26 AJ34 VSS VSS H24
BB25 VSS VSS V43 AJ38 VSS VSS H26
AV40 VSS VSS W2 AJ6 VSS VSS H31
AV6 VSS VSS W44 AJ8 VSS VSS H36
AW2 VSS VSS Y14 AK14 VSS VSS H40
F43 VSS VSS Y16 AK24 VSS VSS H7
AY10 VSS VSS Y24 AK43 VSS VSS K10
AY15 VSS VSS Y28 AK45 VSS VSS K15
AY20 VSS VSS Y34 AL12 VSS VSS K20
AY26 VSS VSS Y36 AL2 VSS VSS K29
AY29 VSS VSS Y40 BC22 VSS VSS K33
AY7 VSS VSS Y8 BB42 VSS VSS BC28
B11 VSS VSS VSS VSS
B15 VSS
VSS 11 OF 11
10 OF 11 LYNXPOINT_BGA695
B LYNXPOINT_BGA695 B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH - GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 21 of 53
5 4 3 2 1
5 4 3 2 1
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D
LCD POWER CIRCUIT D
+LCDVDD INVPWR_B+ L1 B+
W=60mils FBMA-L11-201209-221LMA30T_0805
Place closed to JLVDS1 2 1
1
+5VS +3VS +LCDVDD L2
W=60mils FBMA-L11-201209-221LMA30T_0805
R9 2 1
100_0603_5%
1
1 1 1 1 1 1
2
2 2 2 2 2 2
2
R11
3
200K_0402_5% S Q20
2 2 1 2 AO3413L_SOT23-3
Q12A
DMN66D0LDW-7_SOT363-6 1
G
D
eDP PANEL Conn.
1
1
C6 @ +LCDVDD
W=60mils W=60mils
0.047U_0402_16V7K W=60mils
3
2
Q12B 1 1 1
DMN66D0LDW-7_SOT363-6 C8
5 C368 @
ENAVDD 0.1U_0402_16V4Z
<35> ENAVDD 18P_0402_50V8J
C7
2 2 2
+3VS
4
1
4.7U_0603_6.3V6K
R490 20120719 RF's request
100K_0402_5% 20120711 Change to +3VS as HP's request
07/06 Change for eDP MUX JEDP1
1
2
C 2 1 C
<36> EDP_SW_D3N 2
3
<36> EDP_SW_D3P 3
4
5 4
<36> EDP_SW_D2N 5
6
<36> EDP_SW_D2P 6
7
8 7
<36> EDP_SW_D1N 8
9
<36> EDP_SW_D1P 9
10
11 10
ENABLT R12 1 2 <36> EDP_SW_D0N 11
<35> ENABLT 12
2K_0402_5% <36> EDP_SW_D0P 12
13
14 13
1
<36> EDC_SW_AUX 15 14
R13 <36> EDC_SW_AUX# 16 15
100K_0402_5% +LCDVDD 16
2
1 2 17 +5VS
R179 R178 18 17
100K_0402_5% 100K_0402_5% 19 18
2
20 19
21 20
+3VS
1
22 21
4.7U_0603_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_25V7K
47P_0402_50V8J
<13> SG_IN 23 22
EDP_SW_HPD
D3 <36> EDP_SW_HPD 24 23
ENABLT_R
RB751V-40_SOD323-2 24 1 1 1 1 1 1
INV_PWM 25
C84
C81
C82
C23
C80
C111
<35> INV_PWM +3VS 25
26
1 2 ENABLT_R 26
<30,39> LID_SW# D_MIC_CLK 27
<26> D_MIC_CLK D_MIC_DATA 28 27 2 2 2 2 2 2
<26> D_MIC_DATA 28
1
1 29
R491 C83 30 29
31 30
20120731 Delete KB LOGO circuit 100K_0402_5% 0.1U_0402_16V4Z <14> Camera_ON 31
32
2 +5VS 32
33
2
B USB20_P10_R 34 33 B
@ USB20_N10_R 35 34
R15 1 2 0_0402_5% 35
36 41
37 36 G1 42
L3 38 37 G2 43
1 2 USB20_P10_R INVPWR_B+ 38 G3
<17> USBP10+ 1 2 39 44
40 39 G4 45
40 G5
4 3 USB20_N10_R C22 2 1 680P_0402_50V7K INV_PWM
<17> USBP10- 4 3 ACES_50398-04071-001
CONN@
WCM-2012-900T_4P
1 R16 2 0_0402_5%
20120911 Change JEDP1's footprint
@
20120913 Modify pin assignment
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/LVDS CONN & Camera
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9371P
Date: Friday, September 28, 2012 Sheet 22 of 53
5 4 3 2 1
5 4 3 2 1
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10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
GND 13 V5 15
GND V5
10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
14 16 1 1 1 1
+5VS
C135
C119
C132
C112
V5 15 V5 17
1 1 1 1
V5 GND
C45
C46
C47
C48
16 18
V5 +5VS Reserved
17 19
GND GND 2 2 2 2
18 20
23 Reserved 19 2 2 2 2 23 V12 21
24 GND GND 20 24 GND V12 22
GND V12 21 25 GND V12
V12 22 26 NPTH
Placea caps. near
V12
Placea caps. near NPTH
HDD CONN.
SANTA_199201-1 HDD CONN. ALLTO_C166J7-12205-L
4.7U_0603_6.3V6K
SATA_PRX_DTX_P1 <13>
0.1U_0402_16V4Z
9 10 B+ 7
11 9 10 12 2 2 GND
13 11 12 14
13 14 +5V_ODD
15 16 8 R56 1 2 @ 0_0402_5%
15 16 DP 9
14 V5 10
10U_0805_10V4K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
17 18 GND V5 +5V_ODD 1
17 18 15 11 C53
19 20 GND MD ODD_DA# <14>
16 12
C55
C56
C57
C58
21 19 20 22 NPTH GND 1 1 1 1
B 21 22 17 13 @ 0.1U_0402_10V6K B
C61 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P5 23 24 NPTH GND 2
<13> SATA_PRX_DTX_P5 1 2 0.01U_0402_16V7K 25 23 24 26
C62 SATA_PRX_C_DTX_N5
<13> SATA_PRX_DTX_N5 27 25 26 28 SANTA_204102-1 2 2 2 2
29 27 28 30
C63 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N5 31 29 30 32
<13> SATA_PTX_DRX_N5 31 32
C64 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P5 33 34
<13> SATA_PTX_DRX_P5 33 34
35 36
37 35
37
36
38
38
20120730 Correct JODD1's footprint +5VS +5V_ODD
Placea caps. near
20120801 Change to Port 5 as HP's request +3VS
39
41 39 40
40
42 1 2 ODD CONN.
43 41 42 44 @ R55 0_0805_5%
45 43 44 46
47 45 46 48
49 47 48 50
R1353
49 50 3 1
S
mSATA_DET# 1 2 51 52
D
<13,18> mSATA_DET# 53 51 52 54
500_0402_1% G1 G2 +5VS
1U_0402_6.3V6K
CC52
1 2 1 Q24
+3VS
G
2
R1316 10K_0402_5% SI2305CDS-T1-GE3_SOT23-3
BELLW_80003-2021
1
2
R57
20120705 Change R1316 to 10K
100K_0402_5%
20120801 Delete Q48 as HP's request
2
R1336
ODD_EN# 1 2
100K_0402_5%
0.1U_0402_10V6K
1
1
C54
D
ODD_EN 2 Q25
A <18> ODD_EN A
G 2N7002K_SOT23-3 @
S 2
20120705 Correct net name to follow GPIO table
3
20120711 Change to +5VS and add R58 as HP's request
+5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 23 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
PWM Fan Control circuit +5VS
5
U3 1
1 22_0402_5% 2 1
P
<30> FAN_PWM B 4 1 2 3 2
D4
2 1 2 Y R60 C65 4 3
<30,5> KBC_PROC_HOT# A 4
G
D 2 1 5 D
G5
1
RB751V-40_SOD323-2 TC7SET00FU_SSOP5 6
3
@ 0.1U_0402_10V6K G6
+VCCIO_OUT R133
ACES_50273-0040N-001
4.7K_0402_5%
CONN@
20120711 HP's request
1 2
C R166
R17 1 2 2 Q65 1 2
+5VS
2K_0402_5% B MMBT3904_SOT23-3 20120709 Correct pin assignment
E 47K_0402_5%
3
<46,5> KBC_PROC_HOT_R Notes:
Place Q65 close CPU side
C C
28K_0402_1%
+3VS
U38 R1315
R61
1 1 2
1 2 +3VS_TH 5 SET
VCC 2
4 GND
150_0402_1% HYST 3 R492 1 2 0_0402_5%
@ KBC_PWR_ON <30,34>
OT#
2
0.1U_0402_16V4Z C66
GMT G708T1U 20120801
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Sandy(2/7) PM,XDP,Thermal
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 24 of 53
5 4 3 2 1
A B C D E
WWW.AliSaler.Com
+3V_WWAN
WWAN 1
JMINI3 CONN@
+3V_WWAN
WLAN
<13> WWAN_DET# GND (Presence) +3V_AOAC
3 2
0.01U_0402_16V7K
0.1U_0402_10V6K
4.7U_0805_10V4Z
5 GND 3P3VAUX 4 R1374
C72
C73
C74
7 GND 3P3VAUX 6 WWAN_FULL_PWR 2 1 1 1 1
<17> USBP12+ USB_D+ FULL_CARD_PWR_OFF# +3V_WWAN
9 8 M_WXMIT_OFF#
<17> USBP12- USB_D- W_DISABLE1# 10K_0402_5%
11 10 WW_LED#
2
GND LED1#
20120908 Add PU as HP's request 2 2 2
R64
20120807 HP's request
12 10K_0402_5% R65 +3V_AOAC
10K_0402_5% WLAN +3V_AOAC
WWAN_SSD_IND 13 AUDIO0 14 2 1 +3VS
PAD @
@T125
T125 +3VS
1
WLAN_WAKE# R1354 1 2 0_0402_5% WWAN_WAKE# 15 GND_WWAN AUDIO1 16
1 @ 1
R1375 1 2 10K_0402_5% WWAN_RSVD2 17 RSV (WAKE# /OD)) AUDIO2 18 JMINI2 CONN@
+3V_WWAN RSV(DPR) AUDIO3 (W_DISABLE#2) GPS_XMIT_OFF# <18>
19 20 R671 @ 2 0_0402_5% WLAN_WAKE# 1 2
20120908 Add PU as HP's request <14,39> PCH_PCIE_WAKE# 1 2
2
21 GND IUM_RFU 22 +3V_WWAN 1 2 3 4
G
UIM_RST <29,30,44,5,9> KBC_DS3_EN @
23 USB3_TX- UIM_RESET 24 UIM_CLK R1355 0_0402_5% 5 3 4 6
25 USB3_TX+ UIM_CLK 26 UIM_DATA 1 3 20120807 HP's request 7 5 6 8 LPC_LFRAME#
GND UIM_DATA <15> MINI1_CLKREQ# 7 8 LPC_LFRAME# <16,28,30,32>
27 28 UIM_PWR 9 10 LPC_LAD3
@ 39P_0402_50V8J
@ 39P_0402_50V8J
@ 39P_0402_50V8J
S
USB3RX- UIM_PWR 9 10 LPC_LAD3 <16,28,30,32>
29 30 11 12 LPC_LAD2
C69
C70
C71
USB3RX+ DEVSLP <15> CLK_PCIE_MINI1# 11 12 LPC_LAD2 <16,28,30,32>
31 32 Q69 13 14 LPC_LAD1
GND GNSS0 1 1 1 <15> CLK_PCIE_MINI1 13 14 LPC_LAD1 <16,28,30,32>
33 34 2N7002KW_SOT323-3 15 16 LPC_LAD0
PETn0/SATA_B+ GNSS1 15 16 LPC_LAD0 <16,28,30,32>
35 36
37 PETn0/SATA_B- GNSS2 38
39 GND GNSS3 40 2 2 2 PLT_RST# 17 18 D10 RB751V-40_SOD323-2
41 PERn0/SATA_A- GNSS4 42 CLK_PCI_DEBUG 19 17 18 20 2 1
PERn0/SATA_A+ PERST# <15> CLK_PCI_DEBUG 19 20 WLAN_TRAMSIT_OFF# <15>
43 44 21 22 PLT_RST# <13,14,28,29,30,35,37,39,5>
45 GND CLKREQ# 46 23 21 22 24
REFCLKN PEWake# <17> PCIE_PRX_DTX_N7 23 24
47 48 <17> PCIE_PRX_DTX_P7 25 26
REFCLKP Config_0 T146 @ PAD 27 25 26 28
49 50
GND Config_1 T147 @ PAD 29 27 28 30
PAD @
@T148
T148 51 52 20120807 Add test point as HP's request
53 ANTCTL0 COEX3 54 31 29 30 32
PAD @
@T149
T149 ANTCTL1 COEX2 <17> PCIE_PTX_C_DRX_N7 31 32
55 56 @ R1352 33 34
ANTCTL2 COEX1 <17> PCIE_PTX_C_DRX_P7 33 34
57 58 SIM_DET 2 1 35 36
20120807 Add test point as HP's request ANTCTL3 SIM_DET +3V_WWAN 35 36 USBP13- <17>
PLT_RST# 59 60 37 38
RESET# SUSCLK 10K_0402_5% 37 38 USBP13+ <17>
NGFF_WWAN_PEDET 61 62 39 40
PAD @
@T134
T134 PEDET 3P3VAUX 39 40
63 64 41 42
GND 3P3VAUX 20120730 41 42
65 66 43 44 WL_LED# WLAN_TRAMSIT_OFF#
67 GND 3P3VAUX 45 43 44 46
PAD @
@T135
T135 NGFF_WWAN_USB3_OC <16> CL_CLK1
OC_USB3 47 45 46 48
<16> CL_DATA1 47 48
69 68 49 50 1
GND2 GND1 <16> CL_RST1# 49 50
51 52 @ C364
53 51 52 54
LOTES_APCI0018-P002A 22P_0402_50V8J
+3V_AOAC G1 G2
2
2 2
BELLW_80003-1023
1
20120713 Add for ESD's request
R85
D8 10K_0402_5%
U5 <18> WWAN_TRANSMIT_OFF# 1 2 M_WXMIT_OFF#
2
1 6 BT_ON
CH1 CH4 RB751V-40_SOD323-2
2 5 +3V_WWAN
Vn Vp +3VDS
1
3 4 D
CH2 CH3
2 Q28
@ S DIO(BR) NUP4301MR6T1 TSOP-6 +3V_WWAN <14> BT_OFF
G 2N7002K_SOT23-3
2
R81 S
D9
3
@ DAN217T146_SC59-3
JSIM1 CONN@ 3 10K_0402_5% WLAN&BT Combo module circuits
5 1 UIM_PWR 1
UIM_VPP 6 GND VCC 2 UIM_RST 2 BT BT
<39> UIM_VPP
1
UIM_DATA 7 VPP RST 3 UIM_CLK on module on module
SIM_DET 4 I/O CLK
NC 1 04/23 HP Enable Disable
18P_0402_50V8J
C76
3
S
R84 G
1 2 2 Q27
4.7U_0805_10V4Z
0.1U_0402_10V6K
<30> WWAN_DISABLE
2 BT_CRTL HI LO
C77
C78
9 SI2305CDS-T1-GE3_SOT23-3
1 1
0.1U_0402_10V6K
GND 8 220K_0402_1%
+3V_WWAN
C79
GND
1
02/13 HP 1
R83
D
BT_ON# LO HI
1
@ 47K_0402_5% @ 2 2
+3VDS @
2 7W
2
HB_5680629-SICR11
3 3
+3VDS
UIM_PWR 20120719 HP's request
R457 200K_0402_5% R458
Mini Card Power Rating 1 2 1 2
WLAN_DISABLE <30>
Power Primary Power (mA) Auxiliary Power (mA) 4.7K_0402_5%
1
+3VS 1000 750 R90
1K_0402_5% +3VDS Q68 @
1
1
47K_0402_5% +1.5VS 500 375 5 (Not wake enable) 1 2 D
+3V_AOAC 2
SLP_WLAN# <14,44>
2
@C85
@ C85 0.047U_0402_16V7K G
2
+3VS
1
G
WL/BT_LED# S
3
WL/BT_LED# <39> 20120719 HP's request
1 3 +3VDS R459 @
S
0.1U_0402_16V4Z 100K_0402_5%
6
1
3
47K C86
Q4A Q30
2
Q29 20120801 Change to uninstall as HP's request
DTA114YKAGZT146_SOT23-3 BT_ON 2 DMN66D0LDW-7_SOT363-6 AO3413L_SOT23-3
WL_LED# 2 10K 2
1
Q4B
WL_LED 5
DMN66D0LDW-7_SOT363-6
4 4
4
1
WW_LED# 2 10K
WL_LED R94 1 2 100K_0402_5% Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
2012/06/11 2013/06/11
47K
Q31 Issued Date Deciphered Date
3
DTA114YKAGZT146_SOT23-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WWAN/NAND mini
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+3VS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 25 of 53
A B C D E
5 4 3 2 1
WWW.AliSaler.Com Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
0.1U_0402_25V6
0.1U_0402_25V6 2 1 1 1 SENSE_A CA1 1 2 1000P_0402_50V7K
0.1U_0402_25V6
1U_0402_6.3V6K
1U_0402_6.3V6K
CA9,CA21 near UA5 PIN39
CA4
1 1
CA3
CA6
CA7
CA2 CA5
10U_0603_6.3V UA1
1 2 2 2 SENSE_B RA4 1 2 2.49K_0402_1%
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
2 2 +AVDD_CODEC
1 27 1 1 1 1
DVDD_CORE AVDD1 38
CA9
CA10
AVDD2 1 2 1000P_0402_50V7K
CA11
CA12
CA13 If Sense_B is un-used, then pull high
3 45
DVDD_IO PVDD1 39 2 2 2 2
PLACE CLOSE TO U1 PIN 14 @ Sense_B to AVDD by 10Kohm resistor
PVDD2
CA8 9 13 SENSE_A
DVDD SENSE_A SENSE_A <27>
22P_0402_50V8J 14 SENSE_B
SENSE_B SENSE_B <27>
HDA_BITCLK_AUDIO 1 RA9 2 1 2
28
HP0_PORTA_L DOCK_HP_L_CODEC <27>
@ 33_0402_5% @ 29 External MIC
HP0_PORTA_R DOCK_HP_R_CODEC <27>
23
HDA_BITCLK_AUDIO 6 VREFOUT_A
<13> HDA_BITCLK_AUDIO HDA_BITCLK 31 HP_OUT_L
Combo Jack
HP1_PORTB_L HP_OUT_L <39>
<13> HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5 32 HP_OUT_R Headphone
HDA_SDO HP1_PORTB_R HP_OUT_R <39>
1 CA14 0.1U_0402_25V6
RA16 CA15
4.7U_0603_6.3V6K 21
10K_0402_5% VREFFILT 22
2 35 CAP2 34
1
CAP- V- 37
VREG(+2.5V)
7
10U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+3VS DVSS
1 1 1 1
1U_0402_6.3V6K
42 26
CA16
CA21
PVSS AVSS1 30
CA18
AVSS2 20120702 Delete MUTE circuit
49 33
CA19
PAD AVSS3 2 2 2 2
1
RA13 @ 92HD91B2X5NLGXWCX8_QFN48_7X7
4.7K_0402_5%
B B
Place C209,C210,CA87,CA89 close to Codec
2
HDA_RST_AUDIO#
1
RA17 +AVDD_CODEC
10K_0402_5%
+5VS UA2
REC_MUTE_CTRL_KB <38> 5
RA18 W=40Mil
2
CA22 1 VOUT
1 2 1 2 MONO_IN VIN
4
CA23 @1 2 0.1U_0402_25V6 0.1U_0402_25V6 100K_0402_5% 1 2 3 BYPASS
2N7002KW_SOT323-3
0.1U_0402_25V6
EN
1
D RA20 1
6
CA24 @1 2 0.1U_0402_25V6 2
CA28
2 2
680P_0603_50V7K
REC_MUTE_LED_CTRL 10K_0402_5% GND
1
G C87
1
CA25 @1 2 0.1U_0402_25V6 1 HPA01085DBVR SOT23 5P CA29
S 1
1
HDA_SPKR 2 RA19 2
3
2
CA27 @1 2 0.1U_0402_25V6 CA26 1
2
CA31
QA1A 10K_0402_5%
SB Beep 0.01U_0402_16V7K 680P_0603_50V7K 0.1U_0402_25V6
1
2
CA30 @1 2 0.1U_0402_25V6 RA28 DMN66D0LDW-7_SOT363-6 2
2
10K_0402_5%
A RA21 1 2 0_0805_5% A
1
GND GNDA Security Classification Compal Secret Data Compal Electronics, Inc.
20120719 HP's request
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
RA53 need under or near UA1 Audio IDT 92HD91
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-XXXXP
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 26 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
Speaker Connector <26> VREFOUT_MIC_JACK
RA22
JSPKR1
6 2.2K_0402_5%
5 G6 LA3
SPKR+ 4 G5 2 1 EXT_MIC_L2
<26> EXT_MIC_JACK
1U_0402_6.3V6K
<26> SPKR+ 3 4 EXT_MIC_L2 <39>
SPKR-
<26> SPKR- 3
SPKL+ 2 1 BLM18AG601SN1D_2P
<26> SPKL+ 1 2
SPKL-
<26> SPKL- 1 C89
ACES_50273-0040N-001 1
2
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
CONN@
1 1 1 1 CA36
220P_0402_50V7K
2
CA32
CA33
CA34
CA35
D D
2 2 2 2
2
3
2
1
1
DA2 @
@ DA3
3.3_0402_5%
3.3_0402_5%
3.3_0402_5%
3.3_0402_5%
RA25
RA23
RA26
RA24
YSDA0502C C/A SOT-23
1
1
1
20120713 Change P/N for ESD's request
2
2
YSDA0502C C/A SOT-23
8
U6A
C90
3
P
+VREF_EQ + 1 MIC_OUT 2 1
OUT EXT_MIC_L <26>
2 2
20120702 Change C91/C94 to 2.2uF as specified. -
G
1U_0603_16V7
C92 TLV2462CDR_SO8
C91
4
LA6 0.01U_0402_16V7K
1 2 1 2 2 1 1
<26> DOCK_HP_L_CODEC DLINE_OUT_L <33>
R97 IN-
2.2U_0603_10V7K 30_0402_5% BLM18AG601SN1D_2P +AVDD_CODEC
C94 LA7
1 2 1 2 2 1 R96
<26> DOCK_HP_R_CODEC DLINE_OUT_R <33>
1
R98 1 2
2.2U_0603_10V7K 30_0402_5% BLM18AG601SN1D_2P +AVDD_CODEC
C93 100K_0402_5%
1 1 1100K_0402_5%
2 R103
2
1
CA39 CA40
15P_0402_50V8J
8
220P_0402_50V7K 220P_0402_50V7K U6B
20K_0402_1% 20K_0402_1% 2 2 5
P
R100 R101 + 7
OUT +VREF_EQ
6
2
G
2 1 0.1U_0402_16V7K
TLV2462CDR_SO8
4
100K_0402_5% CC55 C97
R105
2.2U_0402_6.3V6M
1 2
C95
2
LA8
CC53 6.2K_0402_5% EXT_MIC_JACK 1 2 2 1 1 2 IN-
<26> DOCK_LI_L_CODEC 1 2 1 2 DOCK_LINE_IN_L R99 10K_0402_5%
DOCK_LINE_IN_L <33>
470P_0603_50V8J BLM18AG601SN1D_2P
2.2U_0402_6.3V6M R102
B CC54 6.2K_0402_5% B
1
<26> DOCK_LI_R_CODEC 1 2 1 2 DOCK_LINE_IN_R C96
DOCK_LINE_IN_R <33>
68P_0402_50V8J
2.2U_0402_6.3V6M R104
1
R106 R107
2K_0402_5% 2K_0402_5%
2
+AVDD_CODEC
R167
SENSE_B <26>
2
1 2
SENSE_A <26>
R174
3
30K_0402_1% 20K_0402_1%
1
R108
1
6 2
3 2
DMN66D0LDW-7_SOT363-6
Q6A Q6B
2 DMN66D0LDW-7_SOT363-6 5
<33> DOCK_HPS# <33> LINE_IN_SENSE DMN66D0LDW-7_SOT363-6
1
1
1
100K_0402_5% 100K_0402_5%
R110 R111
2
A A
WWW.AliSaler.Com
TPM1.2
1
1
1
0.1U_0402_16V4Z
9656@
R1357
9656@
R112
R113
0_0402_5%
9656@
R114
0_0402_5%
9635@
ACCELEROMETER +3VS
0_0402_5% 0_0402_5%
1 1 1
2
C98 C99 C100
2
2
1
20120810 1 Base I/O Address
0.1U_0402_16V4Z HP's request C101 0 = 02Eh +3VS RH219
2 2 2 for * 1 = 04Eh 10K_0402_5%
0.1U_0402_16V4Z ST33TPM12 0.1U_0402_16V4Z
24
19
10
1
U8 2
2
R115
VDD
VDD
VDD
VDD
D 9635@ D
4.7K_0402_5% ACCEL_INT#
LPC_LAD0 26 28 LPC_PD#_TPM +3VS ACCEL_INT# <14>
<16,25,30,32> LPC_LAD0
2
LPC_LAD1 23 LAD0 NC 9 BADD
<16,25,30,32> LPC_LAD1 LPC_LAD2 20 LAD1 TESTB1/LRESET# 8
<16,25,30,32> LPC_LAD2 LAD2 TEST1 U9
1
LPC_LAD3 17 R116
<16,25,30,32> LPC_LAD3 LAD3 1 9 +3VS
@ 4.7K_0402_5%
Vdd_IO INT2
1
14 TPM_XTALO R117 11
NC 13 TPM_XTALI 4 INT1 14
SLB9656TT1.2 NC 9635@
<11,12,13,16,38,5>
<11,12,13,16,38,5>
DDR_XDP_WAN_SMBCLK
DDR_XDP_WAN_SMBDAT
6 SCL/SPC VDD
2
21 4.7K_0402_5% 7 SDA/SDI/SDO 5
<15> CLK_PCI_TPM 22 LCLK 2 2 1 8 SDO/SA0 GND 12
<16,25,30,32> LPC_LFRAME# T108 PAD @ +3VS
2
PLT_RST# 16 LFRAME# NC 6 R118 10K_0402_5% CS GND 10
<13,14,25,29,30,35,37,39,5> PLT_RST# 27 LRESET# GPIO T109 PAD @ RES 13
<16,30,32> SIRQ SERIRQ RES 1 1
1
PM_CLKRUN#_TPM 15 1 C102 2 15 C103
1 2 7 TEST NC 3 22P_0402_50V8J R121 3 NC RES 16 C104
+3VS PP NC NC RES
R119 12 CLK_PCI_TPM 1 R120 2 1 2 0_0402_5% 0.1U_0402_16V7K 10U_0603_6.3V6M
GND
GND
GND
GND
NC
1
@ 4.7K_0402_5% 2 2
HP3DC2
1
R122 @ 33_0402_5% @
2
@ R123 SLB9656TT1.2_TSSOP28
4
11
18
25
0_0402_5%
1
0_0402_5%
2
1
2
20120706 0_0402_5%
R1358 9635@ 18P_0402_50V8J
+3VS TPM_XTALI C105 1 2 @
2
0_0402_5%
1
9656@
2
1
2
@ R127
R126 9635@ Y1 9635@
4.7K_0402_5% 32.768KHZ_12.5PF_FC-135
1
C C
2
9656@
PLT_RST# R129 2 1 0_0402_5% BADD
20120703 Delete LED1
R177
Finger printer
1 2 PM_CLKRUN#_TPM +3VS
<14,30,32> PM_CLKRUN#
0_0402_5%
1
9635@ C107
0.1U_0402_16V4Z
2
JFP1
1 2
R131 20_0402_5%1
0_0402_5% USB20_N8_R 3 1 2 4
<17> USBP8- 3 4
<17> USBP8+ R130 20_0402_5%1
0_0402_5% USB20_P8_R 5 6
7 5 6 8
FPR_LOCK# 9 7 8 10
<18> FPR_LOCK# FPR_OFF 11 9 10 12
TPM BOM Option (Not Install) <16> FPR_OFF 11 12
3
B ACES_85203-0602N-10 B
SLB9635 R112, R113, R129
D11 CONN@
SLB9656 R114, R115, R117, R126, R177, C105, C106, Y1 20120907 Change JFP1's footprint
SCA00000U10
R113, R129,R114, R115, R117, R126, R177, R1357,
ST33TPM12 R1358,R127,R122,R116,R120, C102, C101, C105, C106, Y1 YSLC05CH_SOT23-3
1
20120713 Change P/N for ESD's request
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TPM/Gsensor
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 28 of 53
5 4 3 2 1
1 2 3 4 5
WWW.AliSaler.Com W=60mils
+3VM_LAN
Q34
+5VDS
+3VM_LAN
1
2N7002K_SOT23-3
R376
10U_0805_10V4Z
R157
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V6K
R128 100K_0402_5%
C110
LED_LINK_LAN#_R 1 2 1 3 LED_LINK_LAN#
S
1 1 1 1 1 2 1 LANWAKE#
C109
C108
0_0402_5%
C370
C369
4.7K_0402_5%
2
+3VM_LAN
G
2 2 2 2 2 SLP_LAN
<34> SLP_LAN
2
20120719 Change R128 to 4.7K as HP's request
0.1U_0402_16V4Z
0.1U_0402_16V4Z
6
AMT@ 1 1
C426
20120719 HP's request LAN_DIS#
C425
A Q7A A
<14,30> SLP_LAN# 2 DMN66D0LDW-7_SOT363-6 +3VM_LAN 2 2
1
4/6 U10 footprint need check
20120720 HP's request
56
50
38
27
18
10
4
U43
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
U10
48 DOCK_MDO0-
0B1 DOCK_MDO0- <33>
47 DOCK_MDO0+
48 13 LAN_MDIP0 1B1 DOCK_MDO0+ <33>
<15> CLK_PCIE_LAN_REQ1# MDO0- 2
36 CLK_REQ_N MDI_PLUS0 14 LAN_MDIN0 A0
<13,14,25,28,30,35,37,39,5> PLT_RST# 43 DOCK_MDO1-
PE_RST_N MDI_MINUS0 2B1 DOCK_MDO1- <33>
20120711 HP's request MDO0+ 3 42 DOCK_MDO1+
44 17 LAN_MDIP1 A1 3B1 DOCK_MDO1+ <33>
<15> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
<15> CLK_PCIE_LAN# 45 18 LAN_MDIN1 37 DOCK_MDO2-
PCIE
PE_CLKN MDI_MINUS1 4B1 DOCK_MDO2- <33>
MDO1- 7 36 DOCK_MDO2+
A2 5B1 DOCK_MDO2+ <33>
MDI
C115 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P6_C 38 20 LAN_MDIP2
<17> PCIE_PRX_DTX_P6 PETp MDI_PLUS2
C116 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_N6_C 39 21 LAN_MDIN2 MDO1+ 8 32 DOCK_MDO3-
<17> PCIE_PRX_DTX_N6 PETn MDI_MINUS2 A3 6B1 DOCK_MDO3- <33>
31 DOCK_MDO3+
41 23 LAN_MDIP3 7B1 DOCK_MDO3+ <33>
<17> PCIE_PTX_C_DRX_P6 PERp MDI_PLUS3
<17> PCIE_PTX_C_DRX_N6 42 24 LAN_MDIN3 MDO2- 11 22 DOCK_LAN_ACT# DOCK_LAN_ACT# <33>
PERn MDI_MINUS3 A4 0LED1
20120711 HP's request 23 DOCK_LED_LINK_LAN# DOCK_LED_LINK_LAN# <33>
6 MDO2+ 12 1LED1 52
SVR_EN_N A5 2LED1
1 1 2 +3VM_LAN 46 MB_MDO0-
RSVD1_VCC3P3 0B2
SMBUS
LAN_SMBCLK 28 47K_0402_5% MDO3- 14 45 MB_MDO0+
<16> LAN_SMBCLK SMB_CLK A6 1B2
LAN_SMBDATA 31 5 R145
<16> LAN_SMBDATA SMB_DATA VDD3P3_IN
MDO3+ 15 41 MB_MDO1-
R1356 1 @ 2 0_0402_5% 20120807 HP's request 4 A7 2B2 40
<25,30,44,5,9> KBC_DS3_EN MB_MDO1+
LANWAKE# 2 VDD3P3_4 15 3B2
<18> LANWAKE# LANWAKE_N VDD3P3_15 C117
19 DOCK_ID 17 35 MB_MDO2-
VDD3P3_19 <33,36> DOCK_ID SEL 4B2
<18> LAN_DIS# LAN_DIS# 3 29 1 2 34 MB_MDO2+
LAN_DISABLE_N VDD3P3_29 5B2
20120711 HP's request
B LAN_ACT# 19 30 MB_MDO3- B
R153 1 @ 2 0_0402_5% LED_LINK_LAN# 26 8 1000P_0402_50V7K LED0 6B2
<13,17> LED_LINK_LAN#_R LED_LINK_LAN# 20 29 MB_MDO3+
LAN_ACT# 27 LED0 VDD0P9_8 11 LED1 7B2
54
LED
25 LED1 VDD0P9_11 16 LED2 25 MB_LAN_ACT#
LED2 VDD0P9_16 +1.05VM_LAN 0LED2
5 26 MB_LED_LINK_LAN#
22 NOTE: L : A-->B1 (DOCK) NC 1LED2 51
32 VDD0P9_22 2LED2
57
T110
34 JTAG_TDI 37
H: A-->B2 (M/B) PAD_GND
GND10
GND11
GND12
GND13
T111
JTAG
JTAG_TDO VDD0P9_37
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
+3VM_LAN R154 1 @ 2 10K_0402_5% LAN_JTAG_TMS 33
R155 1 @ 2 10K_0402_5% LAN_JTAG_TCK 35 JTAG_TMS 40
JTAG_TCK VDD0P9_40 43
VDD0P9_43 46
VDD0P9_46 PI3L500-AZFEX_TQFN56_11X5
1
6
9
13
16
21
24
28
33
39
44
49
53
55
XTAL2 9 47
XTAL1 10 XTAL_OUT VDD0P9_47
XTAL_IN
L15
R158 1 2 1K_0402_5% 30 7 1 2
TEST_EN CTRL_0P9 4.7UH +-5% NLC252018T-4R7J-N
1 1
R159 1 2 3.01K_0402_1% 12 49 C350 C351
RBIAS CTRL_0P9
XTAL1
0.1U_0402_16V4Z 22U_0805_6.3V6M
2 2
XTAL2 CLARKVILLE
C124 1 1 +3VM_LAN
C125
NC OUT
IN
33P_0402_50V8J 33P_0402_50V8J
2
Y2
2
RJ-45 CONN.
NC
1
10K_0402_5%
R136
C C
25MHZ 18PF_CRG3202518
2
JRJ45 CONN@
20120927
+3VM_LAN 10
2
Orange LED+
MB_LAN_ACT# R138 1 2 300_0603_5% MB_LAN_ACT#_R 9
Orange LED- 13
TS1 MB_MDO3- 8 SHLD1
LAN_MDIP0 1 24 MDO0+ 1 2 PR4-
TD1+ TX1+
@ 680P_0402_50V7K C114 MB_MDO3+ 7
LAN_MDIN0 2 23 MDO0- PR4+
TD1- TX1-
MB_MDO1- 6
+V_DAC 3 22 R160 1 2 75_0402_5% PR2-
TDCT1 TXCT1 R161 1 2 75_0402_5% MB_MDO2- 5
+V_DAC 4 21 R162 1 2 75_0402_5% PR3-
TDCT2 TXCT2 R163 1 2 75_0402_5%
C371 1 2 0.1U_0402_16V4Z MB_MDO2+ 4
LAN_MDIP1 5 20 MDO1+ PR3+
TD2+ TX2+
C120 1 2 0.01U_0402_16V7K MB_MDO1+ 3
LAN_MDIN1 6 19 MDO1- 20120719 HP's request PR2+
TD2- TX2- 2
C121 MB_MDO0- 2
C372 1 2 0.1U_0402_16V4Z LAN_MDIP2 7 18 MDO2+ SE120102K90 PR1-
TD3+ TX3+ 1000P_1808_3KV MB_MDO0+ 1
C373 1 2 0.1U_0402_16V4Z LAN_MDIN2 8 17 MDO2- 1 R144 1 2 10K_0402_5% PR1+ 14
TD3- TX3- +3VM_LAN SHLD2
12
3
2
LAN_MDIP3 11 14 MDO3+ @ 680P_0402_50V7K C118
TD4+ TX4+
YSLC05CH_SOT23-3
LAN_MDIN3 12 13 MDO3- D12 @
TD4- TX4- 100UH_SSC0301101MCF_0.18A_20%
2
SCA00000U10
1
MHPC_NS692417 YSLC05CH_SOT23-3
D 20120713 Change P/N for ESD's request D
1
20120713 Change P/N for ESD's request
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Intel 82566 Nineveh
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 29 of 53
1 2 3 4 5
1 2 3 4 5
20120713 Change by HP request +3VDS
+3VDS
20120912 Change RP1 and RP2 to 100K ohms. +RTCVCC
LPC Debug Port
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C179
C180
C181
C182
C183
C184
C185
7 2 KSI0 1 1 1 1 1 1 1 20120925 Delete R537, Q73, D21 as HP's request
6 3 KSI3 JTAG_RST# 1 2
+3VDS
5 4 KSI2 R215 100K_0402_5%
100K_0804_8P4R_5% 2 2 2 2 2 2 2
JP6
RP2 20120713 Change by HP request 1
1 8 KSI7 1 2 2 Ground
<15> CLK_PCI_DEBUG_KBC 3 LPC_PCI_CLK
2 7 KSI6 C186 1U_0402_6.3V6K
3 6 KSI5 +RTCVCC 4
LPC_LFRAME# Ground
4 5 KSI4 SIRQ 5 LPC_FRAME#
6 +V3S
<13,14,25,28,29,35,37,39,5> PLT_RST# LPC_RESET#
A 100K_0804_8P4R_5% PVT_MOSI R218 1 2 0_0402_5% NMI_SMI_DBG# 7 A
+V3S
106
119
20120912 Delete R543 Layout note: 2vias to GND LPC_LAD0 8
68
58
84
14
37
49
U17 LPC_LAD1 9 LPC_AD0
20120718 Install R218/Uninstall R219 PCH_SPI_SI 128 15 C187 1 2 4.7U_0805_10V4Z LPC_LAD2 10 LPC_AD1
+3VDS
*VBAT
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
*JTAG_RST#
<16> PCH_SPI_SI 127 FLDATAOUT CAP 11 LPC_AD2
20120908 Delete R219 PVT_MOSI_R LPC_LAD3
PCH_SPI_CS0# 97 *PVT_MOSI/GPIO54 93 SIO_SLP_A# 20120725 HP's request 12 LPC_AD3
R496 1 2 10K_0402_5% KSO0 <16> PCH_SPI_CS0# FLCS0# *GPIO145 SIO_SLP_A# <14,31,45> VCC_3VA
PVT_CS# 96 100mA 2mA 98 R222 1 2 0_0402_5% TX_STBY_LED# 13
R497 1 2 10K_0402_5% KSO1 *PVT_CS0#/GPIO146 *GPIO157/BC_CLK SUS_PWR_ACK <14> PWR_LED#
PCH_SPI_SO 95 99 AC_PRES_OUT 8051RX_CAPLED# 14
R498 1 2 10K_0402_5% KSO2 <16> PCH_SPI_SO FLDATAIN *GPIO160/BC_DAT AC_PRES_OUT <14,35> CAPS_LED#
PVT_MISO 94 100 KBC_PWR_ON 8051_RECOVER#/_NUM_LOCK_LED# 15
R499 1 2 10K_0402_5% KSO3 *PVT_MISO/GPIO164 *GPIO161/BC_INT# KBC_PWR_ON <24,34> 20120925 HP's request NUM_LED#
126 CHARGER_CLK VCC1_PWRGD 16
PAD T121 @ KSO4 20120713 Change by HP request *GPIO24/I2C3_CLK0 CHARGER_CLK <42> VCC1_PWRGD
KSO5
125 CHARGER_DAT KSO0 R237 1 2 15_0402_5% 17
PAD T122 @ <38> KSO[0..13] *GPIO25/I2C3_DAT0 CHARGER_DAT <42> SPI_CLK
KSO0 21 KSO1 R235 1 2 15_0402_5% 18
KSO1 20 KSO0 124 R227 1 2 0_0402_5% KSO3 R234 1 2 15_0402_5% 19 SPI_CS#
19 KSO1 *GPIO66 NMI_SMI_DBG# <14> 1 2 15_0402_5% 20 SPI_SI
KSO2 20120926 HP's request KSO2 R233
KSO3 18 KSO2 123 FET_A JTAG_RST# R231 1 2 15_0402_5% 21 SPI_SO
+3VS D44 KSO3 *GPIO44 FET_A <51> SPI_HOLD#
KSO4 17 122 KBRST# R1381 1 2 0_0402_5% 22
+3VS 3 KSO4 *GPIO135/KBRST PM_APWROK <14,31> +3VDS Reserved
Keyboard/Mouse Interface
PS2_CLK KSO5 16 121 FAN_PWM 23
4.7K_0804_8P4R_5% 13 KSO5 *GPIO34/TACH2PWM_OUT 120 FAN_PWM <24> 24 Reserved
KSO6 BAT_GRNLED#
1 8 TP_CLK 1 KSO6 *GPIO133/PWM0 BAT_GRNLED# <13,39> Reserved
SMSC_1322-NU_TQFP-128P
TP_DATA KSO8 10
3 6 SP_CLK 2 PS2_DATA KSO9 9 KSO8 107 CPPWR_EN
20120713 Delete R236
ACES_87216-2404_24P
4 5 SP_DATA KSO10 8 KSO9 *GPIO30 79 CPPWR_EN <39>
+1.05VS CONN@
KSO11 7 KSO10 VREF_PCEI 80 H_PECI_R R238 1 2 43_0402_1%
RP3 BAT54CW_SOT323-3 KSO11 *GPIO131/PECI_DATA H_PECI <5>
KSO12 6 81 SLP_S3#
5 *KSO12/GPIO5 *GPIO7/KSO14 83 SLP_S3# <14,31,34,39,44,9>
D45 KSO13 8051_RECOVER#/_NUM_LOCK_LED#
4.7K_0804_8P4R_5% *KSO13/GPIO6 *GPIO10/KSO15 8051_RECOVER#/_NUM_LOCK_LED# <38>
1 8 PS2_CLK 3 KBD_DATA PM_RSMRST# <13,14> 20120719 Install R541 and R542 for NFC function PLT_SEL R252 1 2 10K_0402_5%
85 PM_RSMRST# R1348 1 @ 2 0_0402_5%
2 7 PS2_DATA <38> KSI[0..7] OUT1/RSMRST# PCH_SPI_WP# <16> 20120725 add R1348 & R1349 for Quad I/O SPI support
KSI0 29 86 NFC_UART_RX_R R541 1 2 0_0402_5%
3 6 KBD_DATA 1 KSI0 *GPIO162/RXD NFC_UART_RX <39> 20120818 Delete R1348 & R1349 and Add R541 and R542
KSI1 28 87 PLT_SEL R542 1 2 0_0402_5%
4 5 KBD_CLK KSI1 *GPIO165/TXD/HSD_CS1# NFC_UART_TX <39>
KSI2 27 R1349 1 @ 2 0_0402_5%
2 KBD_CLK KSI2 PCH_SPI_HOLD# <16>
KSI3 26 88 AB2A_DATA R239 1 2 0_0402_5% PCH_KBC_I2CDAT
RP4 25 KSI3 *GPIO23/I2C1_DAT0 89 PCH_KBC_I2CDAT <16,35> +3VDS
KSI4 AB2A_CLK R240 1 2 0_0402_5% PCH_KBC_I2CLK
KSI5 24 KSI4 *GPIO22/I2C1_CLK0 90 KBC_PROC_HOT# PCH_KBC_I2CLK <16,35>
BAT54CW_SOT323-3 KBC_PROC_HOT# <24,5> CHARGER_DAT 1 2
KSI6 23 KSI5 *GPIO21/I2C2_DAT0 91 EC_MUTE# 20120908 Delete R241, R242 R243 10K_0402_5%
20120720 for HP's request EC_MUTE# <26> CHARGER_CLK 1 2
KSI7 22 KSI6 *GPIO20/I2C2_CLK0 92 MAIN_BAT_DET# R245 10K_0402_5%
+RTCVCC MAIN_BAT_DET# <41> ADP_EN 1 2
KSI7 *GPIO105/FAN_TACH1 101 TACH_FAN_IN R246 10K_0402_5%
*GPIO140/TACH2PWM_IN 102 A20GATE TACH_FAN_IN <24> KBRST# R247 1 @ 2 10K_0402_5%
20120713 Change by HP request TP_CLK 35 *GPIO45/A20M/PVT_CS#1 A20GATE <18> VCC1_PWRGD R248 1 2 10K_0402_5%
B <38> TP_CLK *IMCLK/GPIO51 B
103 KBD_CLK 8051TX_STBYLED# R1347 1 2 10K_0402_5%
SP_CLK 61 *GPIO53/PS2CLK 105 KBD_DATA KBD_CLK <33>
<38> SP_CLK SP_DATA 62 *GPIO50/KCLK *GPIO152/PS2DAT 4 ON/OFFBTN# KBD_DATA <33> TX_STBY_LED# R255 1 2 100K_0402_5%
1 <38> SP_DATA *GPIO65/KDAT *GPIO11/KSO16 ON/OFFBTN# <13,14,5> 20120725 HP's request 8051RX_CAPLED# R257 1 2 100K_0402_5%
PS2_CLK 66 74 ADP_PRES
<33> PS2_CLK PS2_DATA 67 *GPIO46/EMCLK *GPIO130 ADP_PRES <34,50> KBD_PWM_LED R259 1 2 10K_0402_5%
C188 <33> PS2_DATA *GPIO47/EMDAT KBC_PWR_ON R263 1 2 100K_0402_5%
1U_0402_6.3V6K
2
111 I2C_MAIN_DAT ON/OFFBTN_KBC# R268 1 2 10K_0402_5%
*I2C0_DATA0 112 I2C_MAIN_CLK
I2C_MAIN_DAT <41> CHRG_ADP_DET R439 1 2 10K_0402_5%
*I2C0_CLK0 I2C_MAIN_CLK <41> PCH_KBC_I2CDAT R440 1 2 10K_0402_5%
Access Bus Interface PCH_KBC_I2CLK R441 1 2 10K_0402_5%
PM_CLKRUN# 55 109 I2C_BAY_DAT
<14,28,32> PM_CLKRUN# SIRQ 57 CLKRUN# *I2C0_DATA1 110 I2C_BAY_CLK I2C_BAY_DAT <41> LID_SW# R442 1 2 10K_0402_5%
<16,28,32> SIRQ
CLK_PCI_KBC 54 SER_IRQ *I2C0_CLK1 I2C_BAY_CLK <41> MAIN_BAT_DET# R443 1 2 10K_0402_5%
EC_XCLK2 <15> CLK_PCI_KBC
EC_SCI# 76 PCI_CLK Power Mgmt/SIRQ 73 ON/OFFBTN_KBC# TRAVEL_BAT_DET# R444 1 2 10K_0402_5%
<18> EC_SCI# EC_SCI# *GPIO110 ON/OFFBTN_KBC# <33,38> TACH_FAN_IN R445 1 2 10K_0402_5%
EC_XCLK1
108 KSO17 20120912 Delete R249,R251 ON/OFFBTN# R295 1 2 100K_0402_5%
Y4 *GPIO12/KSO17 KSO17 <39>
LPC_LAD3 51 59 OCP_PWM_OUT
1 2 <16,25,28,32> LPC_LAD3 LAD[3] *ADC_TO_PWM_OUT/GPIO41 OCP_PWM_OUT <18> 8051_RECOVER#/_NUM_LOCK_LED# R493 1 2 100K_0402_5%
LPC_LAD2 50 75 KBC_DS3_EN
<16,25,28,32> LPC_LAD2 48 LAD[2] *GPIO13 60 KBC_DS3_EN <25,29,44,5,9> PVT_CS# R546 1 2 100K_0402_5%
LPC_LAD1 PM_PWROK
Miscellaneous
<16,25,28,32> LPC_LAD1 LPC_LAD0 46 LAD[1] *nRESET_OUT#/GPIO121 78 ADP_ID_CHK PM_PWROK <14,5>
132.768KHZ_12.5PF_FC-135 1 <16,25,28,32> LPC_LAD0 LAD[0] LPC *GPIO141/PWM3 ADP_ID_CHK <50> 20120719 Change to ADP_ID_CHK as HP's request 20120718 HP's request
77 VCC1_PWRGD 20120908 Delete R253
LPC_LFRAME# 52 Bus VCC1_RST# 38 EN_P1V5 20120912 Delete R256
VCC1_PWRGD <14>
C423 C424 <16,25,28,32> LPC_LFRAME# LFRAME# *ADC4/GPIO62 EN_P1V5 <33,39,44> +3VDS
KBC_SIO_RST# 53
10P_0402_25V8K 10P_0402_25V8K <18,32> KBC_SIO_RST# LRESET#
2 2 69 EC_XCLK2 R500 1 @ 2 0_0402_5%
*XTAL2 SUSCLK_KBC <14> 4.7K_0804_8P4R_5%
20120908 Delete R258/Uninstall R500 I2C_MAIN_CLK 1 8
70
EC_XCLK1 71 *VSS_VBAT 116 FET_B I2C_MAIN_DAT 2 7
20120908 HP's request *XTAL1 *GPIO163 113 FET_B <51> I2C_BAY_CLK 3 6
20120908 Delete R266 AMBER_BATLED#
20120908 Delete R264 &R262 *nBAT_LED#/GPIO154 115 TX_STBY_LED# AMBER_BATLED# <39> I2C_BAY_DAT 4 5
20120718 Uninstall R266 *nPWR_LED#/GPIO156
A_GND
2 2200P_0402_50V7K C189 1 114
2 1 *GPIO155 8051RX_CAPLED# <38> RP5
39
<42> VOLTAGE_ADC *ADC3/GPIO61 20120911 Resever for SUSACK#
<51> LATCHED_ALARM 300_0402_5% 1
R267
PVT_SCLK 2 *GPIO36 41 ADC_VREF_1126_C R1378 1 @ 2 0_0402_5%
*PVT_SCLK/GPIO153 *GPIO206 SUSACK# <14> CPPWR_EN R274 1 2 10K_0402_5%
PCH_SPI_CLK R437 1 2 33_0402_5% PCH_SPI_CLK_EC 3 42 R270 1 2 300_0402_5% PM_PWROK R275 1 2 10K_0402_5%
<16> PCH_SPI_CLK WLAN_DISABLE 30 *SHD_SCLK/GPIO122 *ADC2/GPIO60 65 TRAVEL_BAT_DET# ADP_A_ID <50>
<25> WLAN_DISABLE *GPIO31 GPIO33 TRAVEL_BAT_DET# <41> PM_RSMRST# R276 1 2 10K_0402_5%
31 64 LID_SW# ADP_ID_CHK R278 1 2 10K_0402_5%
<42> CHRG_ADP_DET 32 *GPIO127 *GPIO27 63 LID_SW# <22,39>
C 20120713 Change by HP request TP_DATA ADP_EN 20120908 Delete R271 FET_A R279 1 2 100K_0402_5% C
<38> TP_DATA WWAN_DISABLE 33 *IMDAT/GPIO52 GPIO35 40 ADP_EN <42>
<25> WWAN_DISABLE +3VDS FET_B R280 1 2 100K_0402_5%
*PWRGD
11
47
56
104
82
117
36
45
ADC_VREF_1126_C 1 2
A_GND +3VDS
PWR_GD 100P_0402_50V8J
<31,46,5> PWR_GD 8051TX_STBYLED# <33,38,39>
PCH_SPI_CLK_EC
1
20120912 Delete R277 20120711 Change C322 to 100pF as HP's request R269
6
20120810 HP's request 100K_0402_5%
1 A_GND
C365 20120923 HP's request
33P_0402_50V8J C190 1 2 2200P_0402_50V7K C191 1 2 2200P_0402_50V7K Q172A
2
@ 2
DMN66D0LDW-7_SOT363-6
2
C192 1 2 2200P_0402_50V7K 1 2
1
R281 0_0402_5%
Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise TX_STBY_LED# 5
20120718 EMI's request
Q172B
4
DMN66D0LDW-7_SOT363-6
SPI ROM (16MByte ) 20120725 HP's request
+3VDS
PVT ROM
20120713 Delete RH220
+3VDS UH5 CONN@
(IN)
8 4 +3VDS
2MB
20120713 Change power rail from +3V_SPI to +3VDS VCC VSS &UH1 45@ R282
PCH_SPI_WP# 3 1 2
@ RH222 1 2 PCH_SPI_CS0# W
D 3.3K_0402_5% 10K_0402_5% &UH2 45@ D
PCH_SPI_HOLD# 7 U18 CONN@
RH223 1 2 PCH_SPI_WP# HOLD 20mils 8 4
VCC VSS
0.1U_0402_16V4Z
3.3K_0402_5% PCH_SPI_CS0# 1 1
1 2 PCH_SPI_HOLD# S
C193
RH224 128M W25Q128FVSIG SOIC8P 3
3.3K_0402_5% PCH_SPI_CLK 6 W
C 1 R438 2 7
+3VDS
1
+3VDS +3VDS PCH_SPI_SI 5 2 PCH_SPI_SO_R_1 2 1 PCH_SPI_SO 2 10K_0402_5% HOLD 16M W25Q16CVSSIG SOIC 8P
R1343 D Q R283 4.99_0402_1% PVT_CS# 1
S
20mils 0_0402_5% 128M W25Q128FVSIG SOIC8P
1 1 1 @ PVT_SCLK 6
@ C
CH97 Security Classification Compal Secret Data Compal Electronics, Inc.
2
2
1 R285
C194 R284 1 2
1
40.2K_0402_1% 1M_0402_5%
3300P_0402_25V7K @ R286
2 +5VDS 10K_0402_5%
1
1 2 20120818 HP's request
2
+5VS
8
R288 76.8K_0402_1% U19A
1 2 1 2 3
P
+0.675VS +
R289 11.5K_0402_1% R290 10K_0402_5% 1 PWR_GD
1 2 1 2 2 O PWR_GD <30,46,5>
<49> 1.5VS_PG 1.07VREF
+3VL -
G
R1340 3.3K_0402_5% R291 57.6K_0402_1%
LM393DR2G_SO8
4
D41
R1337
1
1 2 2
<14,30,34,39,44,9> SLP_S3#
31.6K_0402_1% 1
3.3K_0402_5% C195
1
R292 1000P_0402_50V7K
R1338
PM_APWROK 1 2 3
2
2
3.3K_0402_5%
DAP202UGT106_SC70-3
R294
1 2
1M_0402_5%
1 2 +5VDS
+1.35VS
R1339 30.9K_0402_1%
8
U19B
1 2 1 2 5
P
+3VS +
R297 76.8K_0402_1% R296 10K_0402_5% 7
1.07VREF 6 O
-
G
1 2
+1.05VS
R293 24.3K_0402_1% LM393DR2G_SO8
4
1
1 20120711 HP's request
C196 R299
73.2K_0402_1% 20120718 HP's request
3300P_0402_25V7K 20120723 Change R286 to 10K as HP's request
2
46.4K_0402_1%
1 2
+3VL
R304
+3VDS
1
1000P_0402_50V7K
1 +3V_PCH
C197 35.7K_0402_1%
2
R306
2 R175
1
R309
2
3.3K_0402_5% RH236
1 2
1M_0402_5% 4.7K_0402_5%
1
+5VDS
2
R1379
R311
8
U20B 1 2
R310 1 2 20.5K_0402_1% 1 2 5
P
+3VM_LAN + 1M_0402_5%
7
<45> 1.05VM_PG R1341 1 2 3.3K_0402_5%
10K_0402_5% 6 O PM_APWROK <14,30>
- +5VDS
G
1
1 LM393DR2G_SO8
C199 20120923 HP's request
4
19.1K_0402_1%
1
8
D43 U20A
R1342 R313 3300P_0402_25V7K R307 3
P
1 2 2 2 <46> VGATE +
<14,30,45> SIO_SLP_A# 1K_0402_5% 1
2
2 O PCH_PWROK_R <14>
3.3K_0402_5% -
G
1
2
1 LM393DR2G_SO8
4
3 CH106
R301 0.1U_0402_16V4Z
1 2
1M_0402_5% 2
DAP202UGT106_SC70-3
C198
1 2
0.068U_0402_10V6K
20120913 Modify power ok circuit
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 31 of 53
1 2 3 4 5
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Parallel Port +5VS
2
TO LPC47N217N
D27
RB751V-40_SOD323-2
+3VS
1
DCD#1 R318 1 2 4.7K_0402_5%
A +5VS_PRN RI#1 1 2 A
R319 4.7K_0402_5%
LPTERR# R320 1 2 4.7K_0402_5% CTS#1 R321 1 2 4.7K_0402_5%
DSR#1 R322 1 2 4.7K_0402_5%
SERIAL I/F
<33> TXD1 DSR#1 56 TXD1 LAD3 LPC_LAD3 <16,25,28,30>
<33> DSR#1 RTS#1 1 DSR1# 14 LPC_LFRAME#
LPD3 1 2 <33> RTS#1 CTS#1 2 RTS1# LFRAME# 15 LPC_LDRQ0# LPC_LFRAME# <16,25,28,30>
R468 4.7K_0402_5%
LPD2 1 2 <33> CTS#1 DTR#1 3 CTS1# LDRQ# LPC_LDRQ0# <16>
R469 4.7K_0402_5% <33> DTR#1
LPC I/F
LPD1 R470 1 2 4.7K_0402_5% RI#1 4 DTR1# 16 KBC_SIO_RST#
<33> RI#1 RI1# PCI_RESET# KBC_SIO_RST# <18,30>
LPD0 R471 1 2 4.7K_0402_5% DCD#1 5 17 LPCPD#_SIO
<33> DCD#1 DCD1# LPCPD# +3VS
18 PM_CLKRUN#
CLKRUN# 19 CLK_PCI_SIO PM_CLKRUN# <14,28,30>
LPD7 1 2 LPTINIT# 35 PCI_CLK 20 SIRQ CLK_PCI_SIO <15>
R472 4.7K_0402_5% <33> LPTINIT# LPCPD#_SIO R325 1 2 4.7K_0402_5%
LPD6 1 2 LPTSLCTIN# 36 INIT# SER_IRQ 6 SIO_PME# 1 2 SIRQ <16,28,30>
R473 4.7K_0402_5% <33> LPTSLCTIN# +3VS
LPD5 R474 1 2 4.7K_0402_5% LPD0 37 SLCTIN# IO_PME# R324 10K_0402_5%
<33> LPD0 PD0
LPD4 R475 1 2 4.7K_0402_5% LPD1 39 8 CLK_SIO_14M
<33> LPD1 PD1 CLK14 CLK_SIO_14M <15>
LPD2 40 CLOCK
<33> LPD2 PD2
LPD3 41
<33> LPD3 PD3
LPD4 42 21 SIO_GPIO41
PARALLEL I/F
<33> LPD4 PD4 GPIO41
LPTINIT# R476 1 2 4.7K_0402_5% LPD5 43 22 SIO_GPIO42
<33> LPD5 PD5 GPIO42
LPTSTB# R477 1 2 4.7K_0402_5% LPD6 44 24 SIO_GPIO43
<33> LPD6 PD6 GPIO43
LPTAFD# R478 1 2 4.7K_0402_5% LPD7 45 25 SIO_GPIO44 CLK_PCI_SIO CLK_SIO_14M
GPIO
<33> LPD7 PD7 GPIO44
LPTSLCTIN# R479 1 2 4.7K_0402_5% LPTSLCT 47 26 SIO_GPIO45
<33> LPTSLCT SLCT GPIO45
1
LPTPE 48 27 SIO_GPIO46
B <33> LPTPE LPTBUSY 49 PE GPIO46 28 SER_SHD_GPIO47 B
<33> LPTBUSY R332 @ R333 @
LPTACK# 50 BUSY GPIO47 29 SIO_GPIO10
<33> LPTACK# 10_0402_5% 10_0402_5%
LPTERR# 51 ACK# GPIO10 30 SYSOPT
<33> LPTERR# ERROR# GPIO11/SYSOPT
1
LPTAFD# 52 31 SIO_GPIO12
<33> LPTAFD# ALF# GPIO12/IO_SMI#
2
LPTSTB# 53 32 SIO_IRQ
<33> LPTSTB# STROBE# GPIO13/IRQIN1 1 1
33 R327
GPIO14/IRQIN2 34 SIO_GPIO23 10K_0402_5% C205 @ C206 @
GPIO23
18P_0402_50V8J 10P_0402_25V8K
2
7 2 2
R482 1 2 4.7K_0402_5% SIO_GPIO44 +3VS VTR
10
R480 1 2 4.7K_0402_5% SIO_GPIO46 +3VS 23 VCC 57
VCC POWER EPAD
R481 1 2 4.7K_0402_5% SIO_GPIO45 38
46 VCC
R484 1 2 4.7K_0402_5% SIO_IRQ VCC
R485 1 2 4.7K_0402_5% SIO_GPIO12
C201
C202
C203
C204
R486 1 2 4.7K_0402_5% SIO_GPIO10 LPC47N217N-ABZJ_QFN56_8X8
1 1 1 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
+3VS 2 2 2 2
+3VS
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUPER I/O LPC47N217N-ABZJ
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 32 of 53
1 2 3 4 5
1 2 3 4 5
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DOCK CONN. 184PIN DOCKING CONNECT +5VS +3V_PCH
VA_ON#
1
C207
C209
(1) PCI Express x1 channels 1
(2) PS/2 Interfaces DOCK_ID R334 1 2 10K_0402_5%
(2) USB 2.channels +5VS ISO_PREP# R337 1 2 10K_0402_5% R335 C208
1 1
(2)
(2)
SATA Channels
Display Port Channels
VIN VA 1K_0402_5%
2
0.1U_0402_16V4Z
2
(1) Serial Port L27
(1) Parallel Port 2 2 HCB2012KF-121T50_0805 ON/OFFBTN_KBC#
C210
C211
C212
C213
(1) Line In 1 2 1
0.1U_0603_50V4Z
0.1U_0603_50V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
(1) Line Out C299
(1) RJ45 (10/100/1000) 1 1 1 1 0.01U_0402_16V7K
5A
1
(1) VGA L28
A (1) 2 LAN indicator LED's 2 A
D42 HCB2012KF-121T50_0805 20120911 Delete R336 as HP's request
(1) Power Button 1 2 2 2 2 2
(1) I2C interface L30ESD24VC3-2_SOT23-3
@ JDOCK1B
R168
100K_0402_5%
1 2 143 46
142 143 46 47
20120713 ESD's request 142 47
DPB_HPD 141 48 DCK1_HPD
VA <36> DPB_HPD 141 48 DCK1_HPD <35>
JDOCK1A 140 49 ON/OFFBTN_KBC#
2
<30,39,44> EN_P1V5 140 49 ON/OFFBTN_KBC# <30,38>
ADP_SIGNAL ADP_SIGNAL 139 50 VA_ON#
12A 190 189 DPB_AUX R339 1 2 0_0402_5% DPB_AUX_R 138 139 50 51 MXM_R_DCK_AUX R340 1 2 0_0402_5% MXM_DCK_AUX
P1 G1 DPB_AUX# R341 1 2 0_0402_5% DPB_AUX#_R 137 138 51 52 MXM_R_DCK_AUX# R342 1 2 0_0402_5% MXM_DCK_AUX#
136 137 52 53
135 136 53 54
188 1 134 135 54 55
187 188 1 2 133 134 55 56
<29> DOCK_MDO3+ 187 2 DOCK_MDO1+ <29> 133 56
186 3 132 57
<29> DOCK_MDO3- 186 3 DOCK_MDO1- <29> 132 57
185 4 <32> LPTSTB# LPTSTB# 131 58 D_DDCDATA
185 4 131 58 D_DDCDATA <36>
184 5 <32> LPTAFD# LPTAFD# 130 59 D_DDCCLK
<29> DOCK_MDO2+ 184 5 DOCK_MDO0+ <29> 130 59 D_DDCCLK <36>
183 6 <32> LPTERR# LPTERR# 129 60
<29> DOCK_MDO2- 183 6 DOCK_MDO0- <29> 129 60 D_VSYNC <36>
182 7 LPTACK# 128 61
182 7 <32> LPTACK# 128 61 D_HSYNC <36>
<32> LPTBUSY LPTBUSY 127 62
LPTPE 126 127 62 63 R_DOCK_RED
20120912 <32> LPTPE 126 63 R_DOCK_RED <36>
DETECT 181 8 <32> LPTSLCT LPTSLCT 125 64
181 8 DOCK_LED_LINK_LAN# <29> 125 64
180 9 LPD7 124 65 R_DOCK_GRN R_DOCK_GRN <36>
180 9 DOCK_LAN_ACT# <29> <32> LPD7 124 65
179 10 LPD6 123 66 R_DOCK_BLU
+5VS 179 10 +5VS <32> LPD6 123 66 R_DOCK_BLU <36>
178 11 20120912 LPD5 122 67
178 11 <32> LPD5 122 67
177 12 LPD4 121 68 DCD#1
177 12 <32> LPD4 121 68 DCD#1 <32>
176 13 USB3TN1 LPD3 120 69 RI#1
176 13 USB3TN1 <17> <32> LPD3 120 69 RI#1 <32>
175 14 USB3TP1 LPD2 119 70 DTR#1
175 14 USB3TP1 <17> <32> LPD2 119 70 DTR#1 <32>
174 15 LPD1 118 71 CTS#1
174 15 <32> LPD1 118 71 CTS#1 <32>
173 16 USB3RN1 LPD0 117 72 RTS#1
173 16 USB3RN1 <17> <32> LPD0 117 72 RTS#1 <32>
172 17 USB3RP1 LPTSLCTIN# 116 73 DSR#1
172 17 USB3RP1 <17> <32> LPTSLCTIN# 116 73 DSR#1 <32>
171 18 LPTINIT# 115 74 TXD1
171 18 <32> LPTINIT# 115 74 TXD1 <32>
170 19 STB_LED#_R 114 75 RXD1
B 170 19 USBP0- <17> 114 75 RXD1 <32> B
169 20 SATA_ACT# 113 76
169 20 USBP0+ <17> <13,39> SATA_ACT# 113 76
168 21 DOCK_ID 112 77
168 21 <29,36> DOCK_ID 112 77
167 22 ISO_PREP# 111 78
167 22 <13,36> ISO_PREP# 111 78
166 23 110 79
165 166 23 24 109 110 79 80
165 24 <13> SATA_PTX_DRX_P3 109 80
164 25 108 81 KBD_DATA
164 25 <13> SATA_PTX_DRX_N3 108 81 KBD_DATA <30>
163 26 107 82 KBD_CLK
163 26 107 82 KBD_CLK <30>
162 27 106 83 PS2_DATA
162 27 <13> SATA_PRX_DTX_P3 106 83 PS2_DATA <30>
161 28 105 84 PS2_CLK
161 28 <13> SATA_PRX_DTX_N3 105 84 PS2_CLK <30>
160 29 104 85
160 29 104 85 LINE_IN_SENSE <27>
159 30 USBP11- 103 86 DOCK_HPS#
159 30 <17> USBP11- 103 86 DOCK_HPS# <27>
<36> DPB_TXP0 158 31 USBP11+ 102 87
158 31 MXM_DCK_LANE_P0 <35> <17> USBP11+ 102 87
<36> DPB_TXN0 157 32 101 88
157 32 MXM_DCK_LANE_N0 <35> 101 88 DOCK_LINE_IN_L <27>
156 33 <13> SATA_PTX_DRX_P2 100 89
156 33 100 89 DOCK_LINE_IN_R <27>
<36> DPB_TXP1 155 34 <13> SATA_PTX_DRX_N2 99 90
155 34 MXM_DCK_LANE_P1 <35> 99 90
154 35 98 91 DLINE_OUT_L
<36> DPB_TXN1 154 35 MXM_DCK_LANE_N1 <35> 98 91 DLINE_OUT_L <27>
153 36 97 92 DLINE_OUT_R
Quick SW
<36> DPB_TXP2 152 153 36 37 GPU <13> SATA_PRX_DTX_P2
96 97 92 93
DLINE_OUT_R <27>
152 37 MXM_DCK_LANE_P2 <35> <13> SATA_PRX_DTX_N2 96 93
<36> DPB_TXN2 151 38 95 94 DETECT
151 38 MXM_DCK_LANE_N2 <35> 95 94
150 39
149 150 39 40 20120801 Change to Port 2 as HP's request
<36> DPB_TXP3 149 40 MXM_DCK_LANE_P3 <35>
<36> DPB_TXN3 148 41
148 41 MXM_DCK_LANE_N3 <35>
147 42
DPB_AUX 146 147 42 43 MXM_DCK_AUX 192 191
<36> DPB_AUX 146 43 MXM_DCK_AUX <35> G2 G1
DPB_AUX# 145 44 MXM_DCK_AUX# 194 193
<36> DPB_AUX# 145 44 MXM_DCK_AUX# <35> G4 G3
144 45 196 195
144 45 198 G6 G5 197
200 G8 G7 199
FOX_QL0094L-D26601-8H G10 G9
FOX_QL0094L-D26601-8H
C C
1
R346
10K_0402_5%
2
R_DOCK_RED C214 1 2 @ 0.1U_0402_16V4Z
STB_LED#_R R_DOCK_GRN C215 1 2 @ 0.1U_0402_16V4Z
R_DOCK_BLU C216 1 2 @ 0.1U_0402_16V4Z
1
D Q35
2 2N7002K_SOT23-3
<30,38,39> 8051TX_STBYLED#
G
S
3
20120718 HP's request
D D
IN NC<-->COM NO<-->COM Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
L ON OFF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
H OFF ON DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 33 of 53
1 2 3 4 5
A B C D E
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+3VALW TO +3VALW(PCH AUX Power) +5VALW to +5VS Transfer +3VALW to +3VS Transfer
Short J1 for PCH VCCSUS3.3 B+ +3VDS +3VS
+5VDS +5VS U25
U24 4.5A SI7326DN-T1-GE3_PAK1212-8-5 6.5A
+3VDS J1 @ +3V_PCH SI7326DN-T1-GE3_PAK1212-8-5 1
1
1 2 1 2
1 2
0.1U_0402_16V4Z
10U_0603_6.3V6M
3
0.1U_0402_16V4Z
2 1
C223
C219
JUMP_43X79 3 R354 5 1 1
C221
40mil 5 1 1 330K_0402_5% C218
1 C222 10U_0603_6.3V6M
4
1 10U_0805_10V4Z 2 1
4
3 1 Q40 C226 2 2
D
10U_0805_10V4Z 2 2 RUNON
2
AO3413L_SOT23-3 @ 2
1 1
1
10U_0603_6.3V6M
C225
1U_0603_25V6
C220
1
2
C224 R355 J2 R357
20120705 470_0603_5% RUNON SHORT PADS R356 0_0402_5%
6 2
1
10U_0603_6.3V6M 2 2 820K_0402_5%
1
2 R489
2
1K_0402_5% 1
Q9A C227
3
SLP_S3 2 0.01U_0402_16V7K
DMN66D0LDW-7_SOT363-6
2
+5VDS 2
3
5 KBC_PWR_ON#
<44,45> KBC_PWR_ON#
KBC_PWR_ON# 1 2
R455 100K_0402_5% Q18B +1.05VM to +1.05VS Transfer Q9B
4
DMN66D0LDW-7_SOT363-6 5
<30,50> ADP_PRES DMN66D0LDW-7_SOT363-6
+1.05VM +1.05VS
4
Q41
AO4430L_SO8 6A
8 1
6
Q67B
7 2
DMN66D0LDW-7_SOT363-6
6 3
2 5 5
C233
10U_0805_10V4Z
C234
0.1U_0402_16V4Z
C235
10U_0805_10V4Z
C232
330U_B2_2VM_R15M
KBC_PWR_ON <24,30> SIO_SLP_SUS# <14> 1
1
Q67A 1 1 1
4
+
1
DMN66D0LDW-7_SOT363-6 R456
100K_0402_5%
@
2 2 RUNON 1 R375 2 2 2
2 2
2
0_0402_5%
1
3 1
S
R363
0.1U_0402_16V4Z
4.7K_0402_5%
G
C230
1
1 2
2
AMT@ C229 HP requirement AMT@
R488 SLP_S3
1U_0402_6.3V6K 2 <49> SLP_S3
1K_0402_5%
2
1
D
2
SLP_LAN 2
<29> SLP_LAN <14,30,31,39,44,9> SLP_S3#
G
S
3
1
20120720 Delete C231 as HP's request Q39
2N7002KW_SOT323-3
R368
100K_0402_5%
3 3
2
20120711 HP's request
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
1 1 1 1 1 1 1 1 1
2
@ @ @ @ @ @ @ @ @
2
2 2
1
2 2 2 2 2 2 2
6
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 34 of 53
A B C D E
5 4 3 2 1
<4>
<4>
WWW.AliSaler.Com
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CRX_GTX_P[0..15]
<4> PEG_CRX_GTX_P[0..15]
PEG_CRX_GTX_N[0..15]
<4> PEG_CRX_GTX_N[0..15]
B+ B+
PCH_THERMTRIP#_R PCH_THERMTRIP#_R <18,5> PEX_RST
2
3 4 158 159
D PWR_SRC PWR_SRC GND GND D
2
5 6 160 161 CV1 1 2 0.22U_0402_6.3V6K PEG_CRX_GTX_N12
G
R137 PEG_CTX_GRX_N12 PEG_CRX_GTX_C_N12
7 PWR_SRC PWR_SRC 8 PEG_CTX_GRX_P12 162 PEX_TX3# PEX_RX3# 163 PEG_CRX_GTX_C_P12 CV2 1 2 0.22U_0402_6.3V6K PEG_CRX_GTX_P12
PWR_SRC PWR_SRC 2.2K_0402_5% PEX_TX3 PEX_RX3
9 10 3 1 AC_PRES_OUT 164 165
11 PWR_SRC PWR_SRC 12 166 GND GND 167
D
PWR_SRC PWR_SRC GND GND
1
13 14 PEG_CRX_GTX_N13 0.22U_0402_6.3V6K 1 2 CV3 PEG_CRX_GTX_C_N13 168 169 PEG_CTX_GRX_N13
15 PWR_SRC PWR_SRC 16 2N7002KW_SOT323-3 PEG_CRX_GTX_P13 0.22U_0402_6.3V6K 1 2 CV4 PEG_CRX_GTX_C_P13 170 PEX_RX2# PEX_TX2# 171 PEG_CTX_GRX_P13
17 PWR_SRC PWR_SRC 18 172 PEX_RX2 PEX_TX2 173
PWR_SRC PWR_SRC Q61 GND GND
19 20 PEG_CRX_GTX_N14 0.22U_0402_6.3V6K 1 2 CV5 PEG_CRX_GTX_C_N14 174 175 PEG_CTX_GRX_N14
21 PWR_SRC PWR_SRC 22 PEG_CRX_GTX_P14 0.22U_0402_6.3V6K 1 2 CV6 PEG_CRX_GTX_C_P14 176 PEX_RX1# PEX_TX1# 177 PEG_CTX_GRX_P14
23 GND GND 24 178 PEX_RX1 PEX_TX1 179
25 GND GND 26 PEG_CRX_GTX_N15 0.22U_0402_6.3V6K 1 2 CV7 PEG_CRX_GTX_C_N15 180 GND GND 181 PEG_CTX_GRX_N15
27 GND GND 28 PEG_CRX_GTX_P15 0.22U_0402_6.3V6K 1 2 CV8 PEG_CRX_GTX_C_P15 182 PEX_RX0# PEX_TX0# 183 PEG_CTX_GRX_P15
2
GND GND PEX_RX0 PEX_TX0
B
29 30 184 185
31 GND GND 32 186 GND GND 187
GND GND MXM_THERMTRIP# 3 1 PCH_THERMTRIP#_R <15> CLK_PCIE_VGA# PEX_REFCLK# PEX_CLK_REQ# PEG_CLK_REQ# <15>
33 34 188 189 PEX_RST
GND GND <15> CLK_PCIE_VGA PEX_REFCLK PEX_RST#
C
+5VS 35 36 MMBT3904_SOT23-3 190 191
GND GND Q62 GND VGA_DDC_DAT GPU_VGA_DDC_DAT <36>
37 38 192 193
GND GND RSVD VGA_DDC_CLK GPU_VGA_DDC_CLK <36>
39 40 194 195
GND GND RSVD VGA_VSYNC GPU_VGA_VSYNC <36>
41 42 DGPU_PRSNT# 196 197
5V PRSNT_R# DGPU_PRSNT# <13,18> RSVD VGA_HSYNC GPU_VGA_HSYNC <36>
43 44 198 199
45 5V WAKE# 46 DGPU_PWROK 200 RSVD GND 201
47 5V
5V
PWR_GOOD
PWR_EN
48 DGPU_PWR_EN
DGPU_PWROK
DGPU_PWR_EN
<18>
<14,15>
202 RSVD
LVDS_UCLK#
VGA_RED
VGA_GREEN
203
RED_R
GREEN_R
<36>
<36>
CRT
+3VS
49 50 204 205
5V RSVD LVDS_UCLK VGA_BLUE BLUE_R <36>
51 52 20120927 HP's request 206 207
53 GND RSVD 54 208 GND GND 209
GND RSVD 200K_0402_5% 1 2 R1382 LVDS_UTX3# LVDS_LCLK# U37
5
55 56 +3VS 210 211
57 GND RSVD 58 212 LVDS_UTX3 LVDS_LCLK 213 R93 R92 R91
VCC
59 GND PWR_LEVEL 60 214 GND GND 215 150_0402_1%150_0402_1% 150_0402_1% 1
PEX_STD_SW# TH_OVERT# LVDS_UTX2# LVDS_LTX3# IN1 DGPU_HOLD_RST# <14>
DGPU_PWR_EN R487 1 @ 2 4.7K_0402_5% 61 62 +5VS 216 217 4
VGA_DISABLE# TH_ALERT# 200K_0402_5% 1 2 R1383 +3VS LVDS_UTX2 LVDS_LTX3 OUT
ENAVDD_G 63 64 218 219 2
GND
PLT_RST# <13,14,25,28,29,30,37,39,5>
1
BL_EN_G 65 PNL_PWR_EN TH_PWM 66 200K_0402_5% 1 2R1384 220 GND GND 221 IN2
PNL_BL_EN GPIO0 +3VS PCH_KBC_I2CDAT <16,30> LVDS_UTX1# LVDS_LTX2#
2
BL_PWM_G 67 68 222 223
69 PNL_BL_PWM GPIO1 70 224 LVDS_UTX1 LVDS_LTX2 225 MC74VHC1G08DFT2G_SC70-5
3
71 HDMI_CEC GPIO2 72 MXM_PCH_KBC_I2CDAT 1 6 PCH_KBC_I2CLK <16,30> 226 GND GND 227
R63 2 1 100K_0402_5% 73 DVI_HPD SMB_DAT 74 MXM_PCH_KBC_I2CLK 228 LVDS_UTX0# LVDS_LTX1# 229
+3VS LVDS_DDC_DAT SMB_CLK Q60A +5VS LVDS_UTX0 LVDS_LTX1
75 76 230 231
77 LVDS_DDC_CLK GND 78 DMN66D0LDW-7_SOT363-6 232 GND GND 233 20120828 Change U37 to non OD part to solve MXM issue
GND OEM <36> MXM_SYS_LANE_N0 DP_C_L0# LVDS_LTX0#
5
C 79 80 Q60B 234 235 C
OEM OEM <36> MXM_SYS_LANE_P0 DP_C_L0 LVDS_LTX0
81 82 236 237
83 OEM OEM 84 4 3 238 GND GND 239 MXM_eDP_C_LANE_N0 C24 1 2 0.1U_0402_10V7K~D
OEM OEM <36> MXM_SYS_LANE_N1 DP_C_L1# DP_D_L0# MXM_eDP_LANE_N0 <36>
85 86 240 241 MXM_eDP_C_LANE_P0 C25 1 2 0.1U_0402_10V7K~D
OEM GND <36> MXM_SYS_LANE_P1 DP_C_L1 DP_D_L0 MXM_eDP_LANE_P0 <36>
87 88 PEG_CTX_GRX_N0 DMN66D0LDW-7_SOT363-6 242 243
PEG_CRX_GTX_N0 CV9 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N0 89 GND PEX_TX15# 90 PEG_CTX_GRX_P0 244 GND GND 245 MXM_eDP_C_LANE_N1 C26 1 2 0.1U_0402_10V7K~D
PEX_RX15# PEX_TX15 <36> MXM_SYS_LANE_N2 DP_C_L2# DP_D_L1# MXM_eDP_LANE_N1 <36>
CV10 2 1 0.22U_0402_6.3V6K 91 92 246 247 C27 1 2 0.1U_0402_10V7K~D
PEG_CRX_GTX_P0 PEG_CRX_GTX_C_P0
93 PEX_RX15
GND
GND
PEX_TX14#
94 PEG_CTX_GRX_N1 SWITCH <36> MXM_SYS_LANE_P2
248 DP_C_L2
GND
DP_D_L1
GND
249
MXM_eDP_C_LANE_P1
MXM_eDP_LANE_P1 <36>
PEG_CRX_GTX_N1 CV11 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N1 95 96 PEG_CTX_GRX_P1 250 251 MXM_eDP_C_LANE_N2 C28 1 2 0.1U_0402_10V7K~D
PEG_CRX_GTX_P1 CV12 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P1 97 PEX_RX14#
PEX_RX14
PEX_TX14
GND
98
<36>
<36>
MXM_SYS_LANE_N3
MXM_SYS_LANE_P3
252 DP_C_L3#
DP_C_L3
DP_D_L2#
DP_D_L2
253 MXM_eDP_C_LANE_P2 C29 1 2 0.1U_0402_10V7K~D
MXM_eDP_LANE_N2
MXM_eDP_LANE_P2
<36>
<36>
EDP
99 100 PEG_CTX_GRX_N2 254 255
PEG_CRX_GTX_N2 CV13 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N2 101 GND PEX_TX13# 102 PEG_CTX_GRX_P2 256 GND GND 257 MXM_eDP_C_LANE_N3 C30 1 2 0.1U_0402_10V7K~D
PEX_RX13# PEX_TX13 <36> MXM_SYS_AUX# DP_C_AUX# DP_D_L3# MXM_eDP_LANE_N3 <36>
PEG_CRX_GTX_P2 CV14 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P2 103 104 258 259 MXM_eDP_C_LANE_P3 C31 1 2 0.1U_0402_10V7K~D
PEX_RX13 GND <36> MXM_SYS_AUX DP_C_AUX DP_D_L3 MXM_eDP_LANE_P3 <36>
105 106 PEG_CTX_GRX_N3 260 261
PEG_CRX_GTX_N3 CV15 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N3 107 GND PEX_TX12# 108 PEG_CTX_GRX_P3 262 RSVD GND 263 GPU_C_AUX# C32 1 2 0.1U_0402_10V7K~D
PEX_RX12# PEX_TX12 20120710 RSVD DP_D_AUX# GPU_AUX# <36>
PEG_CRX_GTX_P3 CV16 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P3 109 110 264 265 GPU_C_AUX C33 1 2 0.1U_0402_10V7K~D
PEX_RX12 GND 20120717 Delete C354 to C363 RSVD DP_D_AUX GPU_AUX <36>
111 112 PEG_CTX_GRX_N4 266 267 R450 1 2 10K_0402_5% DCK1_SYS_HPD
GND PEX_TX11# RSVD DP_C_HPD DCK1_SYS_HPD <36>
PEG_CRX_GTX_N4 CV17 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N4 113 114 PEG_CTX_GRX_P4 268 269
PEX_RX11# PEX_TX11 RSVD DP_D_HPD GPU_HPD <36>
PEG_CRX_GTX_P4 CV18 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P4 115 116 270 271 20120709 HP's request
117 PEX_RX11 GND 118 PEG_CTX_GRX_N5 272 RSVD RSVD 273
PEG_CRX_GTX_N5 CV19 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N5 119 GND
PEX_RX10#
PEX_TX10#
PEX_TX10
120 PEG_CTX_GRX_P5 274 RSVD
RSVD
RSVD
RSVD
275 Thunder Bolt
PEG_CRX_GTX_P5 CV20 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P5 121 122 276 277
123 PEX_RX10 GND 124 PEG_CTX_GRX_N6 278 RSVD GND 279 MXM_TB_C_LANE_N0 C34 1 2 0.1U_0402_10V7K~D
GND PEX_TX9# RSVD DP_B_L0# MXM_TB_LANE_N0 <39>
PEG_CRX_GTX_N6 CV21 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N6 125 126 PEG_CTX_GRX_P6 280 281 MXM_TB_C_LANE_P0 C35 1 2 0.1U_0402_10V7K~D
PEX_RX9# PEX_TX9 RSVD DP_B_L0 MXM_TB_LANE_P0 <39>
PEG_CRX_GTX_P6 CV22 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P6 127 128 282 283
129 PEX_RX9 GND 130 PEG_CTX_GRX_N7 284 RSVD GND 285 MXM_TB_C_LANE_N1 C36 1 2 0.1U_0402_10V7K~D
GND PEX_TX8# GND DP_B_L1# MXM_TB_LANE_N1 <39>
PEG_CRX_GTX_N7 CV23 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N7 131 132 PEG_CTX_GRX_P7 286 287 MXM_TB_C_LANE_P1 C37 1 2 0.1U_0402_10V7K~D
PEX_RX8# PEX_TX8 <33> MXM_DCK_LANE_N0 DP_A_L0# DP_B_L1 MXM_TB_LANE_P1 <39>
PEG_CRX_GTX_P7 CV24 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P7 133 134 288 289
PEX_RX8 GND <33> MXM_DCK_LANE_P0 DP_A_L0 GND
135 136 PEG_CTX_GRX_N8 290 291 MXM_TB_C_LANE_N2 C38 1 2 0.1U_0402_10V7K~D
GND PEX_TX7# GND DP_B_L2# MXM_TB_LANE_N2 <39>
PEG_CRX_GTX_N8 CV25 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N8 137 138 PEG_CTX_GRX_P8 292 293 MXM_TB_C_LANE_P2 C39 1 2 0.1U_0402_10V7K~D
PEX_RX7# PEX_TX7 <33> MXM_DCK_LANE_N1 DP_A_L1# DP_B_L2 MXM_TB_LANE_P2 <39>
PEG_CRX_GTX_P8 CV26 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P8 139 140 294 295
PEX_RX7 GND <33> MXM_DCK_LANE_P1 DP_A_L1 GND
141 142 PEG_CTX_GRX_N9 296 297 MXM_TB_C_LANE_N3 C40 1 2 0.1U_0402_10V7K~D
PEG_CRX_GTX_N9 CV27 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N9 143 GND
PEX_RX6#
PEX_TX6#
PEX_TX6
144 PEG_CTX_GRX_P9 Dock <33> MXM_DCK_LANE_N2
298 GND
DP_A_L2#
DP_B_L3#
DP_B_L3
299 MXM_TB_C_LANE_P3 C67 1 2 0.1U_0402_10V7K~D
MXM_TB_LANE_N3
MXM_TB_LANE_P3
<39>
<39>
PEG_CRX_GTX_P9 CV28 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P9 145 146 300 301
PEX_RX6 GND <33> MXM_DCK_LANE_P2 DP_A_L2 GND
147 148 PEG_CTX_GRX_N10 302 303 MXM_TB_AUX#
GND PEX_TX5# GND DP_B_AUX# MXM_TB_AUX# <39>
PEG_CRX_GTX_N10 CV29 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N10 149 150 PEG_CTX_GRX_P10 304 305 MXM_TB_AUX
PEX_RX5# PEX_TX5 <33> MXM_DCK_LANE_N3 DP_A_L3# DP_B_AUX MXM_TB_AUX <39>
PEG_CRX_GTX_P10 CV30 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P10 151 152 306 307 R448 1 2 10K_0402_5% TB_HPD
PEX_RX5 GND <33> MXM_DCK_LANE_P3 DP_A_L3 DP_B_HPD TB_HPD <39>
153 154 PEG_CTX_GRX_N11 308 309 R449 1 2 10K_0402_5% DCK1_HPD
B GND PEX_TX4# GND DP_A_HPD DCK1_HPD <33> B
PEG_CRX_GTX_N11 CV31 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_N11 155 156 PEG_CTX_GRX_P11 310 311 +3VS
PEX_RX4# PEX_TX4 <33> MXM_DCK_AUX# DP_A_AUX# 3V3
PEG_CRX_GTX_P11 CV32 2 1 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P11 157 312 313
PEX_RX4 <33> MXM_DCK_AUX DP_A_AUX 3V3 20120709 HP's request
314 C347 C348 C349
316 PRSNT_L# 315
GND GND
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
318 317 1 1 1
JAE_MM70-314B2-1-R500 GND GND
20120709 HP's request JAE_MM70-314B2-1-R500
1
2 2 2
100K_0402_5%
R169
2
+3VS dGPU_HPD_INTR
<13,17> dGPU_HPD_INTR
U34
ENAVDD_G 3 5
1 Y0 VCC 4
<14> ENVDD_PCH Y1 Z 2 ENAVDD <22>
6
<14,36> DGPU_SELECT# S GND
74LVC1G3157GV_TSOP6
2N7002KW_SOT323-3
1
D D D
DCK1_SYS_HPD 2 TB_HPD 2 Q52 DCK1_HPD 2 Q53
Q51
G G G
1
1
S S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3
3
+3VS R451 R452 R453
U35 100K_0402_5% 100K_0402_5% 100K_0402_5%
BL_EN_G 3 5
1 Y0 VCC 4
<14> PANEL_BKEN_PCH ENABLT <22>
2
2
DGPU_SELECT# 6 Y1 Z 2
S GND
74LVC1G3157GV_TSOP6 S Z
A A
LO Y0
+3VS
U36
BL_PWM_G 3 5
<14> BKL_PWM_PCH
1 Y0
Y1
VCC
Z
4
INV_PWM <22> HI Y1
DGPU_SELECT# 6 2
S GND
74LVC1G3157GV_TSOP6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/06/11 Deciphered Date 2013/06/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 35 of 53
5 4 3 2 1
1 2 3 4 5
WWW.AliSaler.Com
eDP MUX +3VS
U42
DP Switch
CC72 1 2 0.1U_0402_16V4Z 54
CC73 1 2 0.01U_0402_16V7K_X7R 31 VDD 47 SEL
VDD SW_AUX
28
OUT_AUXp_SCL EDC_SW_AUX <22>
27
OUT_AUXn_SDA CC70 EDC_SW_AUX# <22> +3VS
IN2_PEQ 49
IN1_PEQ 50 IN2_PEQ/SDA_CTL 30 EDC_SW_C_AUX 1 2 0.1U_0402_16V4Z
IN1_AEQ# 3 IN1_PEQ/SCL_CTL AC_AUXp 29 EDC_SW_C_AUX# 1 2 0.1U_0402_16V4Z
IN2_AEQ# 51 IN1_AEQ# AC_AUXn CC71
IN2_AEQ# Place close to U42
C239
1U_0402_6.3V4Z
C240
0.1U_0402_16V4Z
C238
0.1U_0402_16V4Z
C241
0.1U_0402_16V4Z
37 I2C_CTL_EN 1 1 1 1
I2C_CTL_EN T145
A <7> EDP_CPU_LANE_P0 EDP_CPU_LANE_P0 52 A
EDP_CPU_LANE_N0 53 IN1_D0p
<7> EDP_CPU_LANE_N0 IN1_D0n
<7> EDP_CPU_LANE_P1 EDP_CPU_LANE_P1 55 34 CFG_OUTPUT 2 2 2 2
IN1_D1p CFG_OUTPUT U26
<7> EDP_CPU_LANE_N1 EDP_CPU_LANE_N1 56
IN1_D1n 12 42 DPA_TXN0 C324 1 2 0.1U_0402_16V7K
1 44 R516 1 2 1M_0402_5% VDD D0-A MB_DPA_TXN0 <39>
IN1_D2p CA_DET 21 41 DPA_TXP0 C323 1 2 0.1U_0402_16V7K
2 VDD D0+A MB_DPA_TXP0 <39>
IN1_D2n 34 40 DPA_TXN1 C326 1 2 0.1U_0402_16V7K
From CPU 4
5 IN1_D3p 42 EDP_SW_C_D0P CC75 1 2 0.1U_0402_16V4Z
VDD D1-A 39 DPA_TXP1 C325 1 2 0.1U_0402_16V7K
MB_DPA_TXN1
MB_DPA_TXP1
<39>
<39>
EDP_SW_D0P <22> D1+A 38 DPA_TXN2 C328 1 2 0.1U_0402_16V7K
IN1_D3n OUT_D0p 41 EDP_SW_C_D0N CC76 1 2 0.1U_0402_16V4Z MB_DPA_TXN2 <39>
EDP_SW_D0N <22> DPSW_SEL 2 D2-A 37 DPA_TXP2 C327 1 2 0.1U_0402_16V7K
EDP_CPU_AUX 24 OUT_D0n 39 EDP_SW_C_D1P CC77 1 2 0.1U_0402_16V4Z MB_DPA_TXP2 <39>
<7> EDP_CPU_AUX EDP_SW_D1P <22> 3 GPU_SEL D2+A 36 DPA_TXN3 C330 1 2 0.1U_0402_16V7K
<7> EDP_CPU_AUX#
EDP_CPU_AUX# 23
20
IN1_AUXp
IN1_AUXn
OUT_D1p
OUT_D1n
38
36
EDP_SW_C_D1N CC78 1 2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
EDP_SW_D1N <22>
<35> MXM_SYS_LANE_N0
4 D0- D3-A 35 DPA_TXP3 C329 1 2 0.1U_0402_16V7K
MB_DPA_TXN3 <39> M/B DP
EDP_SW_C_D2P CC79 1 <35> MXM_SYS_LANE_P0 D0+ D3+A MB_DPA_TXP3 <39>
IN1_SCL OUT2_D2p EDP_SW_D2P <22> 6 24
19 35 EDP_SW_C_D2N CC80 1 2 0.1U_0402_16V4Z <35> MXM_SYS_LANE_N1 D1- AUX-A MB_DPA_AUX# <39>
IN1_SDA OUT2_D2n EDP_SW_D2N <22> 7 23
33 EDP_SW_C_D3P CC81 1 2 0.1U_0402_16V4Z <35> MXM_SYS_LANE_P1 D1+ AUX+A MB_DPA_AUX <39>
OUT_D3p EDP_SW_D3P <22> 8 16
32 EDP_SW_C_D3N CC82 1 2 0.1U_0402_16V4Z <35> MXM_SYS_LANE_N2 D2- HPD_A MB_DP_HPD <39>
OUT_D3n EDP_SW_D3N <22> 9
<35> MXM_eDP_LANE_P0 MXM_eDP_LANE_P0 7 <35> MXM_SYS_LANE_P2 D2+
IN2_D0p 10 33
<35> MXM_eDP_LANE_N0 MXM_eDP_LANE_N0 8 <35> MXM_SYS_LANE_N3 D3- D0-B DPB_TXN0 <33>
IN2_D0n 11 32
<35> MXM_eDP_LANE_P1 MXM_eDP_LANE_P1 10 <35> MXM_SYS_LANE_P3 D3+ D0+B DPB_TXP0 <33>
IN2_D1p 31
<35> MXM_eDP_LANE_N1 MXM_eDP_LANE_N1 11 48 SEL D1-B DPB_TXN1 <33>
IN2_D1n SW_ML/I2C_ADDR 30
MXM_eDP_LANE_P2 13 D1+B DPB_TXP1 <33>
From GPU <35>
<35>
MXM_eDP_LANE_P2
MXM_eDP_LANE_N2 MXM_eDP_LANE_N2 14 IN2_D2p <35> MXM_SYS_AUX#
13
AUX- D2-B
29
DPB_TXN2 <33>
IN2_D2n 14 28
<35> MXM_eDP_LANE_P3 MXM_eDP_LANE_P3 15 46 CFG_HPD <35> MXM_SYS_AUX AUX+ D2+B DPB_TXP2 <33>
IN2_D3p CFG_HPD DPSW_SEL 5 27
<35> MXM_eDP_LANE_N3 MXM_eDP_LANE_N3 16 43 AUX_HPD_SEL D3-B DPB_TXN3 <33>
EDP_SW_HPD <22> 18 26
26
IN2_D3n OUT_HPD <35> DCK1_SYS_HPD HPD D3+B 19
DPB_TXP3
DPB_AUX#
<33>
<33>
Docking
GPU_AUX AUX-B
<35> GPU_AUX IN2_AUXp 1 20
GPU_AUX# 25 18 GND AUX+B DPB_AUX <33>
<35> GPU_AUX# IN2_AUXn REXT 17 15
22 17 GND HPD_B DPB_HPD <33>
IN2_SCL CEXT 22
21 GND
IN2_SDA 43 25 R503 1 2 10K_0402_5%
1
CC74 R505 HGND OE +3VS
1
2.2U_0402_6.3V6M
4.99K_0402_1%
45
GND PI3VDP12412ZHEX_TQFN42_9X3P5~D
<7> CPU_EDP_HPD# CPU_EDP_HPD# 6 12
GPU_HPD 9 IN1_HPD GND 57
<35> GPU_HPD IN2_HPD Epad 2
40 +3VS
2
PD
PS8321QFN56GTR-A0_QFN56_7X7
2
+3VS
R462
1
+3VS
B 10K_0402_5% B
R506 R507 R508 R509 R510 R511 100K_0402_5%
@R504
@ R504
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
SEL
1
R416
2
2N7002KW_SOT323-3 10K_0402_5%
1
D
<14,35> DGPU_SELECT# 2
2
G
2
@ @ @ @ @ @ S DPSW_SEL
3
Q63
IN1_AEQ#
IN2_AEQ# 2N7002KW_SOT323-3
1
D
IN1_PEQ
IN2_PEQ 2
ISO_PREP# <13,33>
CFG_HPD G
CFG_OUTPUT S
3
Q54
20120723
@R512
@R512 @ R513
@R513 @R514
@R514 @R515
@R515 SW_ML/SW_AUX
1
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
0 GPU
2
1 CPU
+5VS +RCRT_VCC
F1 +CRTVDD
C 1.1A_8VDC_FUSE D49 C
1 2 2
1
3 W=40mils
RB491D_SOT23-3 1
+3VS +5VS
C413
0.1U_0402_10V6K
VGA_DDCCLK R501 1 2 10K_0402_5% 10/17 HP 2
1 1 1 1 1 1
VGA_DDCDATA R502 1 2 10K_0402_5% JVGA1
L29 09/30 HP 6
CC60 CC61 CC62 CC63 CC64 CC65 39NH_CS0805-39NJ-S_5% L32110NH_CS0805-R11J-S_5% 11
U28 +3VS 2 2 2 2 2 2 1 2 1 2 R1363 1 2 R1364 1 2 0_0805_5% 1
VGA_RED DAC_RE DAC_R VGA_RE VGA_R
10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z L30 7 G 16
<14> PCH_CRT_RED 7
17 REDA
MAX14885E VCC
29 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VGA_GRN
39NH_CS0805-39NJ-S_5%
1 2 DAC_GR
L31110NH_CS0805-R11J-S_5%
1 2 DAC_G R1365 1
0_0805_5%
@ 10P_0402_50V8J
@ 10P_0402_50V8J
@ 10P_0402_50V8J
1 R1369
1 R1371
0.1U_0402_16V4Z 9
1 R1370
0_0805_5%
9 2
18P_0402_50V8J
18P_0402_50V8J
18P_0402_50V8J
<14> PCH_CRT_BLU 14
19 BLUA
C420
C421
C414
18P_0402_50V8J
18P_0402_50V8J
18P_0402_50V8J
C418
C415
C419
<35> BLUE_R 1 1 1 1 1 1 4
BLUB 33 VGA_RED
C422
C416
C417
1 1 1 10
5 RED1 24 R_DOCK_RED
<14> PCH_CRT_DDC_CLK R_DOCK_RED <33> 15
15 SCLA RED2
<35> GPU_VGA_DDC_CLK 10/17 HP 10/17 HP 5
SCLB 32 VGA_GRN 2 2 2 2 2 2
6 GRN1 23 R_DOCK_GRN 2 2 2
<14> PCH_CRT_DDC_DAT SDAA GRN2 R_DOCK_GRN <33> CONN@
150_0402_1% 2
150_0402_1% 2
150_0402_1% 2
<35> GPU_VGA_DDC_DAT 16
SDAB 31 VGA_BLU SUYIN_070915HR015M226ZR
R350 1 2 10K_0402_5% 2 BLU1 22 R_DOCK_BLU
+5VS EN BLU2 R_DOCK_BLU <33>
30 SCA00000U10 @ VGA_DDCDATA
GND
3
20 12 @
DGPU_SELECT# 2 10 GND NC
GND D46
VGA_B 3
QA2A <29,33> DOCK_ID 5 QA2B 41 Security Classification Compal Secret Data Compal Electronics, Inc.
1
DMN66D0LDW-7_SOT363-6 GPAD 1
DMN66D0LDW-7_SOT363-6 2 2012/06/11 2013/06/11 Title
MAX14885EETL+T_TQFN40_5X5~D Issued Date Deciphered Date
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Switch/MUX
20120723 YSLC05CH_SOT23-3 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SCA00000U10 Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P
@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 36 of 53
1 2 3 4 5
5 4 3 2 1
WWW.AliSaler.Com
+VCC_SM
1
R391
D 4.7K_0402_5% D
2
U30
SCardC8 1 28 XTAL_OUT
SCardC6 2 SCard0C8 XO 27 XTAL_IN CV33 18P_0402_50V8J
SCardFcb 3 SCard0C6 XI 26 PWRSV_SEL# XTAL_OUT
4 SCard0Fcb PWRSV_SEL 25 PWRSV_SEL# <14>
+5VS SMIO_5VPWR LEDCRD
1
SCardRst 5 24
SCard0Rst LEDPWR
2
SCardclk R395 2 1 0_0402_5% SCardclk_R 6 23
SCard0Clk RESET PLT_RST# <13,14,25,28,29,30,35,39,5>
SCardData R396 1 2 470_0402_5% 7 22 SSDA T93 PAD~D@ RH225 @ Y3
8 SCard0Data EEPDATA 21 SSCL T94 PAD~D@ +3VS_SM 1M_0402_5%
1 <17> USBP7- DM EEPCLK 12MHZ_18PF_X5H012000FI1H
9 20 EEPWP T95 PAD~D@
<17> USBP7+
1
10 DP P1(6) 19 20120920 HP's request
C252 +3VS_SM ICCInsertN
0.1U_0402_16V7K 11 AV33 ICCInsertN 18 XTAL_IN
2 +VCC_SM SCPWR0 VDDH
C253 12 17 C254
13 5VGND VDDP 16 +1.8VS_SM
1 CC68 +5VS 1 CV34 18P_0402_50V8J
5VInput VDD
0.1U_0402_16V7K
0.1U_0402_16V7K
2 14 15
+3VS_SM V33OUT V18OUT 20120709 Vendor's suggestion
1U_0402_6.3V6K
CC69 C257 C258 C259 AU9542B56-GBS-GR_SSOP28 C255
2 2
1 1 1 1 1 1 1 C256
1U_0402_6.3V6K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
1U_0402_6.3V6K
0.1U_0402_16V7K
2 2 2 2 2 2
J3
12
GND 11 +VCC_SM
GND
10
10 9 SCardRst
9 8 SCardclk C260 C261
8 7 SCardFcb
7 1 1
0.1U_0402_16V7K
0.1U_0402_16V7K
6
6 5 SCardC6 @
5 4 SCardData
4 3 SCardC8 2 2
3 2 ICCInsertN
2 1
1
C264 C265 C263 C262
ACES_51524-0100N-001
CONN@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1
@ @ @ @
20120705 Correct J3's footprint
2 2 2 2
B B
20120714 Correct J3's pin define
20120912 Modify J3's pin define
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Smart Card
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 37 of 53
5 4 3 2 1
5 4 3 2 1
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KSO12 @ C376
@C376 1 2 100P_0402_50V8J
KSI_D_9 @C377
@ C377 1 2 100P_0402_50V8J
KSI_D_13 @C378
@ C378 1 2 100P_0402_50V8J
+5VDS KSI_D_6 @C379
@ C379 1 2 100P_0402_50V8J
JPWR1
+5VDS 1 2
8051TX_STBYLED# 3 1 2 4
<30,33,39> 8051TX_STBYLED# 3 4 <30> KSI[0..7]
ON/OFFBTN_KBC# 5 6 KSI7
<30,33> ON/OFFBTN_KBC# 5 6
7 8 KSI6
7 8 KSI5 KSO1 @ C380
@C380 1 2 100P_0402_50V8J
D KSI4 CONN@ JKB1 KSO6 @C381
@ C381 1 2 100P_0402_50V8J D
ACES_50611-0040N-001 @C382
@ C382
KSI3 2 1 KSO4 1 2 100P_0402_50V8J
CONN@ <26> REC_MUTE_CTRL_KB 2 1 R400 KSO3 @C383
@ C383 1 2 100P_0402_50V8J
KSI2 +3VDS 4 3 360_0402_5% 2 1
4 3 8051RX_CAPLED# <30>
KSI1 KSO13 6 5 8051_RECOVER#/_NUM_LOCK_LED# <30>
20120917 Change JPWR1 to 4 pin KSI0 KSO9 8 6 5 7 KSO12
KSI_D_11 10 8 7 9 KSI_D_9
<30> KSO[0..13] 10 9
KSI7 12 11 KSI_D_13
KSI_D_5 14 12 11 13 KSI_D_6 KSI_D_1 @ C384
@C384 1 2 100P_0402_50V8J
KSO13 KSO10 16 14 13 15 KSO1 KSI_D_4 @C385
@ C385 1 2 100P_0402_50V8J
KSO12 KSO7 18 16 15 17 KSO6 KSI_D_10 @C386
@ C386 1 2 100P_0402_50V8J
KSO11 KSO8 20 18 17 19 KSO4 KSI_D_8 @C387
@ C387 1 2 100P_0402_50V8J
KSO10 KSI_D_3 22 20 19 21 KSO3
ON/OFFBTN_KBC# 22 21
KSO9 KSI_D_2 24 23 KSI_D_1
KSO8 KSI_D_0 26 24 23 25 KSI_D_4
2 KSO7 KSI_D_12 28 26 25 27 KSI_D_10
KSO6 KSI_D_14 30 28 27 29 KSI_D_8 KSO13 @ @C388
C388 1 2 100P_0402_50V8J
EMI cap C270 30 29 KSO9 @C389
@ C389 1 2 100P_0402_50V8J
KSO5 KSO2 32 31 KSO5
0.1U_0402_16V7K KSO4 KSO11 34 32 31 33 KSO0 KSI_D_11 @
@C390
C390 1 2 100P_0402_50V8J
1 @C391
@ C391
KSO3 34 33 KSI7 1 2 100P_0402_50V8J
KSO2 36 35
KSO1 38 GND GND 37
KSO0 GND GND
C C
20120927 HP's request
1
KSI_D_3 @ C396
@C396 1 2 100P_0402_50V8J
R407 KSI_D_2 @C397
@ C397 1 2 100P_0402_50V8J
Q47 100K_0402_5% KSI_D_0 @C398
@ C398 1 2 100P_0402_50V8J
+5VS_KBL @C399
@ C399
D36 KSI_D_12 1 2 100P_0402_50V8J
3
S
KB backlight Conn 2 2
R408
1 2
D33
2 KSI_D_0 KSI3 1
2 KSI_D_3 D39
2 KSI_D_6
G KSI_D_0 <39>
200K_0402_5% KSI0 1 3 KSI_D_11 KSI6 1
6
JP9 D 3 KSI_D_8 3 KSI_D_14
1
Q10A
KSI_D_1 <39>
ACES_50611-0040N-001 KSI1 1 3 KSI_D_12
2
CONN@ @ 3 KSI_D_9
DAP202UGT106_SOT323-3
DAP202UGT106_SOT323-3
D38
D35 2 KSI_D_5
20120926 Follow ME's request 2 KSI_D_2 KSI5 1
KBL_DET# <13,18>
KSI2 1 3 KSI_D_13
3 KSI_D_10
DAP202UGT106_SOT323-3
DAP202UGT106_SOT323-3 20120718 EMI's request
B B
TP/B TO M/B
Stick Point CONN
JTP1
1 2 JP13
3 1 2 4
SP_LEFT 5 3 4 6 +5VS 12
SP_MID 7 5 6 8 G4 11
SP_RIGHT 9 7 8 10 G3 10
DDR_XDP_WAN_SMBCLK 11 9 10 12 G2
<11,12,13,16,28,5> DDR_XDP_WAN_SMBCLK 9
DDR_XDP_WAN_SMBDAT 13 11 12 14 G1
<11,12,13,16,28,5> DDR_XDP_WAN_SMBDAT 13 14
TP_DATA 15 16 8
<30> TP_DATA 15 16 8 8
TP_CLK 17 18 7
<30> TP_CLK 17 18 7
19 20 6
+3VS 19 20 6 6
5
<30> SP_DATA 5
E-T_6900K-Q10N-00R 4
<30> SP_CLK 4 4
CONN@ SP_LEFT 3
SP_MID 2 3
20120907 Change JTP1's footprint & Delete JTP2 SP_RIGHT 1 2 2
2
C298 CONN@
1
D32 YSDA0502C C/A SOT-23
1
100P_0402_50V8J
2 +3VS
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/PWR CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 38 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
Function Board
D JFB1 D
1 2
+5VS
+3VDS 3 1
3
2
4
4 Thunderbolt
Function Key <38> KSI_D_0 KSI_D_0 5 6
KSI_D_1 7 5 6 8
MUTE <38> KSI_D_1 7 8 JTB1
<30> KSO17 KSO17 9 10
WIRELESS MUTE_LED_CNTR 11 9 10 12
<26> MUTE_LED_CNTR 11 12 1 2
WL/BT_LED# 13 14 <17> USB3TN6 1 2 MXM_TB_LANE_N3 <35>
13 14 3 4
LID_SW# 15 16 <17> USB3TP6 3 4 MXM_TB_LANE_P3 <35>
<22,30> LID_SW# 15 16 5 6
17 18 7 5 6 8
19 17 18 20 <17> USB3RN6 7 8 MXM_TB_LANE_N2 <35>
19 20 9 10
<17> USB3RP6 9 10 MXM_TB_LANE_P2 <35>
11 12
E-T_6900K-Q10N-00R 13 11 12 14
CONN@ <17> USBP5- 13 14 MXM_TB_LANE_N1 <35>
15 16
<17> USBP5+ 15 16 MXM_TB_LANE_P1 <35>
17 18
19 17 18 20
<36> MB_DPA_AUX# 19 20 MXM_TB_LANE_N0 <35>
21 22
<36> MB_DPA_AUX 21 22 MXM_TB_LANE_P0 <35>
20120715 Correct JFB1's footprint 23 24
25 23 24 26
20120912 Correct JFB1's footprint & Pin assignment <36> MB_DPA_TXP3 25 26 MXM_TB_AUX# <35>
<36> MB_DPA_TXN3 27 28
27 28 MXM_TB_AUX <35>
29 30
29 30 TB_HPD <35>
31 32
<36> MB_DPA_TXP2 31 32
<36> MB_DPA_TXN2 33 34
33 34 PCIE_PRX_DTX_N3 <17>
35 36
35 36 PCIE_PRX_DTX_P3 <17>
<36> MB_DPA_TXP1 37 38
39 37 38 40
<36> MB_DPA_TXN1 39 40 PCIE_PTX_C_DRX_N3 <17>
41 42
41 42 PCIE_PTX_C_DRX_P3 <17>
<36> MB_DPA_TXP0 43 44
45 43 44 46
<36> MB_DPA_TXN0 45 46 PCIE_PRX_DTX_N4 <17>
47 48
USB & Card Reader Board <36> MB_DP_HPD 49 47
49
48
50
50
PCIE_PRX_DTX_P4 <17>
51 52
C 51 52 PCIE_PTX_C_DRX_N4 <17> C
53 54
<17> USBP6- 53 54 PCIE_PTX_C_DRX_P4 <17>
55 56
+5VDS +3VS +5VDS +3VDS <17> USBP6+ 55 56
57 58
57 58 CLK_TB_REFCLK# <15>
<15> CLK_PCIE_EXP# 59 60
59 60 CLK_TB_REFCLK <15>
JCR1 61 62
<15> CLK_PCIE_EXP 61 62 TB_CLKREQ# <15>
63 64
<15> CLKREQ_EXP# 63 64
1 2 65 66
<17> USB3TN5 1 2 PCIE_PTX_C_DRX_P8 <17> 65 66 PCIE_PRX_DTX_N1 <17>
3 4 67 68
<17> USB3TP5 3 4 PCIE_PTX_C_DRX_N8 <17> <17> PCIE_PRX_EXPTX_N5 67 68 PCIE_PRX_DTX_P1 <17>
5 6 69 70
5 6 <17> PCIE_PRX_EXPTX_P5 69 70
7 8 71 72
<17> USB3RN5 7 8 PCIE_PRX_DTX_P8 <17> 71 72 PCIE_PTX_C_DRX_N1 <17>
9 10 <17> PCIE_PTX_EXPRX_N5 73 74
<17> USB3RP5 9 10 PCIE_PRX_DTX_N8 <17> 73 74 PCIE_PTX_C_DRX_P1 <17>
11 12 <17> PCIE_PTX_EXPRX_P5 75 76
13 11 12 14 77 75 76 78
<17> USBP4- 13 14 CLK_PCIE_CR <15> 77 78 USBP9- <17>
15 16 79 80
<17> USBP4+ 15 16 CLK_PCIE_CR# <15> <17> PCIE_PRX_DTX_N2 79 80 USBP9+ <17>
17 18 81 82
17 18 <17> PCIE_PRX_DTX_P2 81 82
19 20 83 84 HDD LED
<17> USB3TN2 19 20 83 84 SATA_ACT# <13,33>
21 22 85 86
<17> USB3TP2 21 22 <17> PCIE_PTX_C_DRX_N2 85 86 8051TX_STBYLED# <30,33,38>PWR_LED
23 24 PLT_RST# <17> PCIE_PTX_C_DRX_P2 87 88
23 24 87 88 AMBER_BATLED# <30>
25 26 89 90 Battery charger LED
<17> USB3RN2 25 26 CR_CLK_REQ# <15> 89 90 BAT_GRNLED# <13,30>
27 28 91 92 WIRELESS
<17> USB3RP2 27 28 <13,14,25,28,29,30,35,37,5> PLT_RST# 91 92 WL/BT_LED# <25>
29 30 +3VDS 93 94 HDD LED
29 30 EXT_MIC_L2 <27> 93 94 HDD_HALTLED <13>
31 32 95 96
<17> USBP1- 31 32 <30> CPPWR_EN 95 96 TB_HOT_PLUG# <17>
33 34 20120731 HP's request 97 98
<17> USBP1+ 33 34 HP_OUT_R <26> <14,30,31,34,44,9> SLP_S3# 97 98 CR_SX_WARN# <14>
35 36 99 100 +1.5VS
35 36 <30,33,44> EN_P1V5 99 100
37 38 101 102
PAD @
@T141
T141 37 38 HP_OUT_L <26> 101 102
<27> HP_SENSE# 39 40 103 104 +3VS
41 39 40 42 20120713 105 103 104 106
41 42 1 105 106
EN_P1V5 43 44 R1380 1 @ 2 0_0402_5% 107 108
43 44 PCH_PCIE_WAKE# <14,25> 107 108
45 46 C340 109 110
47 45 46 48 111 109 110 112
47 48 20120801 HP's request 0.01U_0402_16V7K_X7R 111 112
20120724 49 50 2 113 114
49 50 2012919 HP's request 113 114
51 52 115 116
B 53 51 52 54 117 115 116 118 B
53 54 117 118 +3VDS
55 56 +5VDS 119 120 +5VS
57 55 56 58 119 120
59 57 58 60
59 60 121
GND 122
61 GND
GND 62 FOX_QTS0120A-4121M-9H
GND 63 CONN@
GND 64
GND 65
GND 66
GND
20120911 Change JTB1's footprint
ACES_50121-06001-001
CONN@
+3VS_NFC
JNFC1
R1359
+3VS 1 2 +3VS_NFC 1 2 R358 @
3 1 2 4
0_0402_5% 3 4 NFC_RST# <16> 10K_0402_5%
5 6
<16> NFC_3S_SMBDAT 5 6 NFC_3S_SMBCLK <16>
7 8 NFC_SEL_R R1345
<18> NFC_INT
2
1 2 NFC_SW 9 7 8 10
<25> UIM_VPP @ NFC_SEL_R 1 2 NFC_SEL T151 PAD @
A 0_0402_5% 11 9 10 12 A
<30> NFC_UART_TX R1344 NFC_UART_RX <30>
11 12 0_0402_5%
1
13 14 R1346 @
1
15 GND GND 16
1
100K_0402_5% CONN@
2
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ADP_EN ACDRV
B+ +3VS
DC IN ACFET RBFET
D D
Jumper
RT8243AZQW +3VDSP +3VDS SY8032 +1.5VSP +1.5VS
Jumper
Main +5VDSP +5VDS
BATT B++ EN +3VS EN
ACDRV
Battery BATT
RBFET
Selector
+1.35VP +1.35V
+1.5VP Jumper
RT8207M +1.5V
2nd
BATT
+0.675VSP +0.675VS
Jumper
EN_P1V5 +0.75VSP +0.75VS
Charger SLP_S3# EN 7/19
C BQ24736 C
TPS51212 Jumper
+1.05VMP +1.05VM
SIO_SLP_A# EN
NCP81103 +CPU_CORE
B B
VR_ON EN
A A
5 4 3 2 1
5 4 3 2 1
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PD11
AZC099-04S.R7G SOT23 ESD
V I/O V I/O
3 2
PD10
L30ESD24VC3-2_SOT23-3
1
ADP_SIGNAL 5 2 3
V BUS Ground
6 1
V I/O V I/O
1
PL1 7/11 PC2 VMB_A PL4 BATT_A
PJP1 HCB2012KF-121T50_0805
VIN PJP2 0.1U_0603_50V7K HCB2012KF-121T50_0805
2
1 2 1 1 2
1 2 PL2 1 2
1 2 HCB2012KF-121T50_0805 2 3 I2C_MAIN_DAT-1 1 2
D D
3 4 ADPIN 1 2 3 4 I2C_MAIN_CLK-1 PL5
3 4 4
1
PL3 5 HCB2012KF-121T50_0805
5
1
5 6 HCB2012KF-121T50_0805 6 PC7
5 6 1 2 6 7 PC3 0.01U_0402_50V7K
100P_0402_50V8J
1000P_0402_50V7K
100P_0402_50V8J
1000P_0402_50V7K
2
7
1
7 8 8 1000P_0402_50V7K
2
7 8 8
1
9
PC1
PC4
PC5
PC6
@ PR1
GND
3
9 10 15K_0402_5% 10
9 10 GND
2
FOX_BP0208C-B24B1-9H
100P_0402_50V8J
100P_0402_50V8J
2
@ ACES_59012-0100N-002
1K_0402_5%
100_0402_5%
100_0402_5%
100_0402_5%
CONN@
1
1
1
PR2
PR3
PC8
PR4
PC9
PR5
PC10
100P_0402_50V8J
2
PD1
1
2
L30ESD24VC3-2_SOT23-3 @
C C
PD13 PD12
AZC099-04S.R7G SOT23 ESD L30ESD24VC3-2_SOT23-3
4 3 2
V I/O V I/O 1
5 2 3
V BUS Ground
6 1
V I/O V I/O
1
B B
7/11 PC11
0.1U_0603_50V7K VMB_B PL6 BATT_B
2
PJP3 HCB2012KF-121T50_0805
1 1 2
1 2
2 3 I2C_BAY_DAT-1 1 2
3 4 I2C_BAY_CLK-1 PL7
4
1
5 HCB2012KF-121T50_0805
5 6
6 7 PC12 PC13
2
7 8 1000P_0402_50V7K 0.01U_0402_50V7K
8
FOX_BR0208C-Z71H1-9H
CONN@
100P_0402_50V8J
100P_0402_50V8J
1K_0402_5%
100_0402_5%
100_0402_5%
100_0402_5%
1
1
1
1
PR6
PR7
PR8
PR9
PC14
PC15
PC16
100P_0402_50V8J
2
2
2
@
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VIN
7/30
P1 P2 B+
PQ107 AO4423L 1P SO8
1 8
2 7
3 6 to 5*5, 9/7
5 PQ102 8/8
MDU1512RH 1N POW ERDFN56-8
1 PR102 PL101
4
ACFET_CHG 2 0.005 +-1% 2512 100PPM/C 1UH_PCMB053T-1R0MS_7A_20%
3 5 1 4 1 2
PQ101 AO4423L 1P SO8
220K_0402_5%
220K_0402_5%
0.1U_0402_25V6
1 8 2 3
D D
1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2 7
68P_0402_50V8J
PC101
PR103
3 6
1
PC103
PC104
PC105
PC106
PC107
5
PC108
PC138
PC102
BAT54WS-7-F_SOD323-2~D
0.1U_0402_25V6
2
1 2
4.12K_0603_1%
4.12K_0603_1%
2
2
2
1
@ @ @
PD101
ACFET_CHG
PR104
PR105
0.1U_0402_25V6
0.1U_0402_25V6
6
1
PC109
PC110
PQ103A for RF request, 8/6
2 ME2N7002DKW -G 2N SOT363-6
2
1
ME2N7002DKW-G 2N SOT363-6
B+ P2 PQ105
5
AO4409L 1P SO8
CHRG_ADP_DET
ACDRV_CHG
CMSRC_CHG
ACP_CHG
ACN_CHG
3
100K_0402_5%
+3VDS PQ104 1
2
8
7
PQ103B
AON7408L_DFN8-5
PR107
3 6
5
1
PR108
2 4
P1 5
2
1
2.2_0402_1%
4
4
PU102 PR109
21
5
1
BQ24736RGRR_QFN20_3P5X3P5 10_1206_1%
ACPRES
ACDRV
CMSRC
ACP
ACN
PAD
3
2
1
PC111 BATT
2
ADP_EN <30> 1U_0603_25V6K
6 20 VCC_CHG 1 2
ACDET VCC PR110
PL102
C 0.02_1206_1% C
4.7U 20% VMPI0703AR-4R7M-Z01 5.5A
ICS 7 19 LX_CHG 1 2 CHG 1 4
PR127 IOUT PHASE
10 +-1% 0402 2 3
4.7_1206_5%
1
1 2 8 18 DH_CHG
<30> CHARGER_DAT
CSON1
SDA HIDRV
CSOP1
PR111
PR112 PC112
2.2_0402_1% 0.047U_0402_25V7K
1 2 9 17 BST_CHG 1 2BST_CHG-1 1 2
RB551V-30_SOD323-2
2200P_0402_50V7K
<30> CHARGER_CLK
10U_0805_25V6K
10U_0805_25V6K
0.01U_0402_50V7K
SCL BTST
5
PR128
0.1U_0402_25V6
0.1U_0402_25V6
1 SNB_CHG 2
1
4/12 10 +-1% 0402
AON7406L_DFN8-5
+3VDS
PC115
PC116
1
1
PC117
PC113
PC114
10 16
PD102
REGN_CHG
PC118
<50> SRSET ILIM REGN
LODRV
4/11 PD103
DLIM
GND
SRN
SRP
2
1
0.01U_0402_50V7K
RB751V-40_SOD323-2 4
2
PQ106
2 1
1
PC119
PR113
+5VS VIN
11
12
13
14
15
680P_0402_50V7K
22K_0402_1%
PC121
PC120
2
3
2
1
DL_CHG
1U_0603_25V6K
SRN_CHG
SRP_CHG
2
CHRG_ADP_DET <30>
1
4/12
PR114 PR115
18.2K_0402_1% 127K_0402_1% PR116 PR117
1M_0402_5% 10K_0402_5%
PD104 1 2
<50> V_3.9K
2
LL4148_LL34-2
2 1
0.01U_0402_50V7K
100P_0402_50V8J
1
PC123
PR120
1
PC122
0_0402_5%
B PR118 PR119 1 2 B
2
10K_0402_1% 20K_0402_1%
2
1
2
PR121 PC124
0_0402_5% 0.1U_0603_25V7K
2
1 2
PR122
0 +-5% 0402
1 2
CURRENT_ADC <30>
100P_0402_50V8J
1
1
PC125
@ PC126
0.22U_0402_6.3V6K
2
B+
VIN
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
6.8P_0402_50V8C
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
82P 50V J NPO 0402
1
PC130
PC129
PC131
PC133
PC132
PC134
PC136
PC135
PC137
PC143
PC142
PC144
PC147
PC146
PC148
PC151
PC150
PC152
PC139
PC140
PC141
PC145
PC149
PC153
PR124 PR125
49.9K_0402_1% 576K_0402_1%
1 2 1 2
2
2
VOLTAGE_ADC <30> @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
100P_0402_50V8J
A A
1
1
PC127
PR126 PC128
49.9K_0402_1% 0.22U_0402_6.3V6K
2
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D D
PC320
100P_0402_50V8J <1>5V=283KHz 3V=330KHz (Vin=6.5 ~ 12v)
1 2
<2>5V=321KHz 3V=375KHz (Vin=12 ~ 25v)
PR304 PR305 (By Rton= 68K ohm)
13.7K_0402_1% 30K_0402_1% +5VDSP
1 2 2 1
+3VDSP
68K_0603_5%
PR308 124K +-1% 0402
1
2 1 1 2
@ PL301
1UH_PCMB053T-1R0MS_7A_20%
1 2
PR310
2200P_0402_50V7K
2200P_0402_50V7K
68P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
82P 50V J NPO 0402
ENTRIP1 2
68P_0402_50V8J
10U_0805_25V6K
0.1U_0402_25V6
1
PC306
PC307
PC308
PC309
PC323
PC325
1
1
1 2
PC324
PC322
PC305
PC304
PC303
FB_3V
FB_5V
1
PQ301 PC321
2
5
SIS412DN-T1-GE3 1N POW ERPAK1212-8 1U_0402_10V6K @ @
2
5
@ PJP301 @ @
2
PAD-OPEN 1x3m @ PR311
1
0_0402_5% PU301
1 2
FB2
ENTRIP2
TON
ENTRIP1
FB1
4 21
C PG_3V_5V 6 PAD 4 C
PC310 PR313 PGOOD 20
for RF request, 8/6 0.1U_0603_25V7K 2.2_0603_5% BYP1 PR312 PC311 PQ302 for RF request, 8/6
2 1BST_3V-1 1 2 BST_3V 7 2.2_0603_5% 0.1U_0603_25V7K SIS412DN-T1-GE3 1N POW ERPAK1212-8
1
2
3
3
2
1
RT8243AZQW W QFN 20P BOOT1
PL303 UG_3V 8
4.7U 20% VMPI0703AR-4R7M-Z01 5.5A UGATE2 18 UG_5V PL302
1 2 UGATE1 2.2UH +-20% ETQP3W 2R2W FN 8.5A
+3VDSP +5VDSP
LX_3V 9 1 2
PHASE2 17 LX_5V
PHASE1
1
1
4.7_1206_5%
4.7_1206_5%
PR314
10
PR315
LG_3V
LGATE2
MDV1526URH 1N PDFN33-8
5
16 LG_5V
ENLDO
LGATE1
LDO5
LDO3
ENM
2200P_0402_50V7K
2200P_0402_50V7K
VIN
6.8P_0402_50V8C
6.8P_0402_50V8C
0.1U_0402_25V6
0.1U_0402_25V6
150U_B2_6.3VM_R35M
150U_UD_6.3VM_R15M
1 1
82P 50V J NPO 0402
2
4
1
1
PC326
PC327
PC328
PC330
PC331
PC332
+ +
PC329
PC314
PC315
PC333
11
12
13
14
15
1
1
PC313
PQ303 4
680P_0402_50V7K
680P_0402_50V7K
PQ304
PC312
AON7406L 1N DFN
2
2
@ @ @ @ 2 2 @ @ @ @
+3VLP
2
1
2
3
2
PR321 Typ: 175mA
3
2
1
1
499K_0402_1%
1 2 ENLDO_3V_5V PC302
B++
1
4.7U_0805_10V6K
2
1
100K_0402_1%
1U_0402_10V6K
0.1U_0603_25V7K
1
1
PC319
PC316
for RF request, 8/6
PR325
for RF request, 8/6
+5VLP
2
10K_0402_1% PR324
2
2
B
Typ: 225mA B
1
PC317
4.7U_0805_10V6K
2
+3VLP
PJP302
JUMP_43X118
+5VDSP 1
1 2
2 +5VDS
PJP303
+3VDSP JUMP_43X118
1 2
+3VDS
1 2
PJP306
JUMP_43X39
1 2
+3VLP 1 2 +3VL
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VDSP/5VDSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 15W 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 43 of 53
5 4 3 2 1
5 4 3 2 1
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B+ 1
PL401
HCB1608KF-121T30_0603
2 B+_1.35V
PC402
0.22U_0402_10V6K
1 2
PR418
2.2_0603_5%
1 2
68P_0402_50V8J
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
4.7U_0805_25V6-K
82P 50V J NPO 0402
PR402
1
0_0402_5%
PC419
PC401
PC403
PC404
PC405
PC406
1 2
+1.35VP
2
@ @
+0.675VSP
BST_1.35V
+0.675VSP
DH_1.35V
LX_1.35V
D D
+1.35VP
5
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
for RF request, 8/6
PC407
PC408
16
17
18
19
20
2
4 PU401
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PL402 PQ401 PAD
2.2UH_VMPI0703AR-2R2M-Z01_8A_20% SIS412DN-T1-GE3 1N POW ERPAK1212-8 DL_1.35V 15 1
1
2
3
LGATE VTTGND
1 2
+1.35VP 14
PGND VTTSNS
2
5
PR403
15.8K +-1% 0402
PR404 1 2 CS_1.35V 13 3
4.7_1206_5% CS RT8207MZQW _W QFN20_3X3 GND
330U_D2_2.5VY_R15M
1
2
4 12 4 VTTREF_0.675V
+ PR405 +5VDS VDDP VTTREF
PC409
1SNB_1.35V
5.1_0603_5%
1 2 VDD_1.35V 11 5 +1.35VP +1.35VP
2 +5VDS VDD VDDQ
PGOOD
680P_0603_50V7K PQ402
1
2
3
1
MDV1526URH 1N PDFN33-8
TON
PC411 PC412 PC413
PC410
FB
S5
S3
1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K
2
2
10
6
C PR419 C
@ 100K_0402_5%
TON_1.35V
FB_1.35V
S3_1.35V
+3VS 1 2
1.35V_PG PR406
10K_0402_1%
1 2 +1.35VP
7/11 PR407
887K_0402_1% @ PC414
B+_1.35V1 2 .1U_0402_16V7K
1 2
PR408
41.2K_0402_5%
1 D
D
3 1 1 2
2 PQ404
<34,45> KBC_PWR_ON#
G 2N7002KW 1N SOT323-3 PQ403
1
S 2N7002KW 1N SOT323-3
G
3
2
PC415
.1U_0402_16V7K
2
<30,33,39> EN_P1V5
1
PR411 +3VDS
10K_0402_1%
PR412
100_0402_5%
2
1
0_0402_5%
2
1 2 8/1
PR417
B <14,30,31,34,39,9> SLP_S3# B
PR416
4.7K +-5% 0402 PR413
10K_0402_1%
2
1
PR414
1
@ PC416 @ PC417 0 +-5% 0402
0.1U_0402_10V7K 0.1U_0402_10V7K 1 2
SLP_W LAN# <14,25>
2
1
1
PD401
1
BAT54CW _SOT323-3
PC418 @ PR415
.1U_0402_16V7K 10K_0402_5%
2
2
2
<14> SLP_S4# KBC_DS3_EN <25,29,30,5,9>
PJP401
JUMP_43X118
1 2
+1.35VP +1.35V
PJP402
JUMP_43X39
1 2
A +0.675VSP 1 2 +0.675VS A
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PL501
HCB2012KF-121T50_0805
B+_1.05V 1 2
B+
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
68P_0402_50V8J
0.1U_0402_25V6
D D
1
PC504
PC505
PC502
PC503
PC512
PC513
2
2
@ @
+3VS
5
1
for RF request, 8/6
@ PR511 PR502 PC506
100K_0402_5% 2.2_0603_5% 0.22U_0603_16V7K PQ501
<31> 1.05VM_PG 1 2BST_1.05V-1 1 2 4 SIS412DN-T1-GE3 1N POW ERPAK1212-8
2
7/17 PU501
PR503 1 10 BST_1.05V
3
2
1
86.6K +-1% 0402 PGOOD VBST
PR504 1 2 TRIP_1.05V 2 9 DH_1.05V PL502
100_0402_5% TRIP DRVH 2.2UH +-20% ETQP3W 2R2W FN 8.5A
,30,31> SIO_SLP_A#
1 2 EN_1.05V 3
EN SW
8 LX_1.05V 1 2
+1.05VMP
FB_1.05V 4 7
VFB V5IN
+5VDS 4/11
1
RF_1.05V 5 6 DL_1.05V
RF DRVL PR505
1
11 4.7_1206_5%
.1U_0402_16V7K
TP
1
5
C PC507 1 C
2
1
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M
PC508
2
PR506 + PC510
220U_B2_2.5VM_R15M
1SNB_1.05V
470K_0402_1%
2
@
2
4 2
PC511
3
2
1
680P_0603_50V7K
2
PQ502
AON7406L 1N DFN
PR508
5.11K_0402_1%
2 1
PQ503
2
2N7002KW 1N SOT323-3
D
1
2 PR510
4> KBC_PWR_ON# 10K_0402_1%
G
S
3
PJP501
JUMP_43X118
B 1 2 B
+1.05VMP +1.05VM
4/11
A A
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D D
PR202
143K_0603_1%
1 2 SWN3
PR203 PR204
220K_0402_5%_ERTJ0EV224J
165K_0402_1% 143K_0603_1%
1 2 1 2 SWN2
0.047U_0402_16V7K
CSREF
820P_0402_50V7K
75K_0402_1%
20K_0402_1%
220P_0402_50V8J
PR205
2
143K_0603_1%
1
PH201
PR201
PC239
PC240
PC241
@ PR206
1 2 SWN1
PR207
2
4.87K +-1% 0402
1
CSP3 2 1
SWN3 <47>
Place close to
1000P_0402_50V7K
0.047U_0402_16V7K
CSREF
phase 1 inductir
20K_0402_1%
2
2
PC242
PC243
@ PR208
1
PR209
2
4.87K +-1% 0402
CSREF <47>
1
CSP2 2 1
SWN2 <47>
CSP3
0.047U_0402_16V7K
CSREF
20K_0402_1%
CSP2
2
1
PC244
@ PR210
CSP1
CSSUM
C CPU_B+ C
PR211
DRON <47>
2
57W=75K 4.87K +-1% 0402
1
PR213 CSP1 2 1
75K +-1% 0402 47W=66.5K SWN1 <47>
2 CSCOMP 1 2
PR212
1K_0402_1%
57W=17.4K 81103_PWM <47>
47W=15.4K
1
2
0.01U_0402_25V7K
PC245 PC246
390P_0402_50V7K 10P_0402_25V8K
1 2 1 2 1 2 PR217 PR214
1
PC247
27
26
25
24
23
22
21
20
19
49.9_0402_1% 1 2 NCP81103MNTWG_QFN36_5X5 2.2_0603_5% 0.22U_0402_10V6K
1
1 2 1 2
CSSUM
CSREF
CSCOMP
PWM2/IMAX
DRON
CSP3
CSP2
CSP1
BST3
2
PC249
.1U_0402_16V7K
1 2 1 2 2 1 28 18
ILIM HG3 HG3 <47>
PR219 PR220 29 17
IOUT SW3 SW3 <47>
1K_0402_1% 7.5K_0402_1% 30 16 PC250
VRMP LG3 LG3 <47>
31 15 1 2 1 2
32 COMP PVCC 14 PR252 0_0402_5% 0_0402_5%
33 FB PGND 13 2.2U_0603_10V7K 1 PR253 2
1 2 1 2 34 DIFFOUT LG1 12
LG1 <47> +5VDS
VSN SW1 SW1 <47>
PR221 PR222 35 11
VSP HG1 HG1 <47>
0_0402_5% 1K_0402_5% 36 10
<10,9> VSSSENSE VCC BST1
1
VR_RDY
VRHOT#
INT_SEL
TSENSE
1 2
ALERT#
PC251 PR223 PC253
ROSC
1000P_0402_50V7K 37 2.2_0603_5% 0.22U_0402_10V6K
SCLK
SDIO
<9> VCCSENSE GND
PC252 1 2 1 2
EN
2
1 2 2200P_0402_50V7K
PR224
1
2
3
4
5
6
7
8
9
0_0402_5% PR225
B 1 2 45.3K_0402_1% B
+5VDS 1 2
TSENSE
2.2U_0603_10V7K
VR_RDY
2_0603_5% 0_0402_5%
ALERT#
2
PC254
1 2
SCLK
SDIO
<30,31,5> PWR_GD
2
1
PC255
1 2 .1U_0402_16V7K
1
PR228 TSENSE
<24,5> KBC_PROC_HOT_R
0_0402_5%
2
PR251
1
PR229 0_0402_5%
24.9K_0402_1%
1
+VCCIO_OUT
100K_0402_1%_TSM0B104F4251RZ
0_0402_5%
1
100 +-5% 0402
13K_0402_1%
PR233
PR234
2
PR230
PR231
PR232
PR235
PH202
2
PC256
1
.1U_0402_16V7K
1
1
1 2 SDIO
<9> VR_SVID_DAT
+3VS
PR236
22 +-5% 0402
VGATE
<31>
1 2 ALERT#
<9> VR_SVID_ALRT#
PR237
22 +-5% 0402 Place close to
A A
1 2 SCLK
<9> VR_SVID_CLK phase 1 MOSFET
PR238
22 +-5% 0402
Security Classification
2011/12/14
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QFKAA
Date: Friday, September 28, 2012 Sheet 46 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
D D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K
2200P_0402_50V7K
68P_0402_50V8J
5
1
1 2
PC211
PC212
PC213
PC214
PC215
PC264
PC267
AON7518 1N DFN
@ PL201
PR239 FBMA-L11-453215-800LMA90T_1812
2
2.2_0603_1% @ @
2 1 4
<46> HG1
PQ211
Place on MXM side, 8/7
+VCC_CORE
3
2
1
PL204
0.22UH 20% MMD-06DZNR22MEO1L 25A
1 4
<46> SW1
1
2 3
4.7_1206_5%
68P_0402_50V8J
220P_0402_25V8K
5
@ PC257
@ PC258
<46> LG1
1
PR240
SIR818DP-T1-GE3 1N POWERPAK SO8
V1N_CPU
CPU_B+ B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6K
5
4 2 1
100U_25V_M
100U_25V_M
1 1 1
68P_0402_50V8J
CSREF <46>
1SNUB_CPU1
100U_25V_M
1
1
AON7518 1N DFN
PR241 + + +
PC229
PC230
PC231
PC232
PC238
PC265
PC268
PC233
PC234
PC235
10_0402_1% PR242
680P_0402_50V7K
2.2_0603_1%
SWN1 <46>
3
2
1
2
2 1 4 @ @ 2 2 2
<46> HG3
@ @
PQ204
PC259
C C
2
3
2
1
PL203
0.22UH 20% MMD-06DZNR22MEO1L 25A
<46> SW3
1 4 +VCC_CORE
1
2 3
4.7_1206_5%
5
PR243
<46> LG3
2
PR244
4 V3N_CPU 2 1 CSREF
SNUB_CPU3
PQ205
10_0402_1%
SWN3 <46>
3
2
1
680P_0402_50V7K
1
PC260
2
for RF request, 8/6
CPU_B+
to 3*3, 9/7
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K
2200P_0402_50V7K
68P_0402_50V8J
1
2.2_0603_5%
PC204
PC205
PC206
PC207
PC203
PC266
PC269
B B
BSTA2 1 2 BSTA2_1
5
2
@ @
0.22U_0402_10V6K
AON7518 1N DFN
PC261
1
4
PQ203
2
1 9 PR246
+VCC_CORE
3
2
1
+5VDS 2 1 VCC_VCORE2 4 6 2 3
4.7_1206_5%
VCC GND
5
PR249
PR248 5 LG2
SIR818DP-T1-GE3 1N POWERPAK SO8
2.2U_0603_10V7K
0_0402_5% DRVL
PC262
1
PU202
2
NCP81151MNTBG_DFN8_2X2
4
2
PQ201
SNUB_CPU2
PR250
10_0402_1%
V2N_CPU 2 1 CSREF
3
2
1
680P_0402_50V7K
PC263
1
SWN2 <46>
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QFKAA
Date: Friday, September 28, 2012 Sheet 47 of 53
5 4 3 2 1
A
B
C
D
+VCC_CORE
+
2 1 2 1
2
1
PC2024 PC2013 PC2001
5
5
+
2 1
2
1
2
1
2 1
2
1
2
1
2 1
2
1
2
1
2 1 2 2 1
1
2 1 2 1
2
1
2 1 2 1
2
1
4
4
2 1 2 1
2
1
2 1 2 1
2
1
2 1 2 1 2 1
2 1 2 1 2 1
2 1 2 1
PC2035 PC2012
22U_0805_6.3V6M 22U_0805_6.3V6M
Issued Date
2 1
Security Classification
PC2036
22U_0805_6.3V6M
2 1
3
3
PC2037
22U_0805_6.3V6M
2 1
PC2038
22U_0805_6.3V6M
2012/04/03
Compal Secret Data
Deciphered Date
2
2
2014/12/31
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title
Date:
15W
Document Number
PROCESSOR DECOUPLING
Sheet
Compal Electronics, Inc.
of48
53
0.2
Rev
A
B
C
D
A B C D
WWW.AliSaler.Com
1 1
2
PC602
+3VS 680P_0402_50V7K
1 SNUB_+1.5V
7/17
1
PJP602
4.7_0402_1%
2
JUMP_43X39
PR601
@ 4X4
2
2 PU601
SY8032ABC_SOT23-6 PL602
1
0.47UH +-20% PCMC042T-R47MN 6A PJP601
4
IN LX
3 LX_1.5V 1 2
+1.5VSP +1.5VSP 2
2 1
1
+1.5VS
5 2 PR602 @ JUMP_43X39
PG GND 10K_0402_5%
150K_0402_1%
1
6 1 EN_1.5V 1 2
+3VS
22P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
FB EN
1
PR603
22U_0805_6.3VAM
1
@ PC603
PC604
1
0.1U_0402_10V7K
PC605
PC606
2
PC601
+1.5V_PCIEP
2 2
2
2
TDC=0.46A
Peak Current=0.66A
1
1.5VS_PG <31> PR604
100K_0402_1%
7/17
1
2
@ PR605
100K_0402_5% PQ601
2N7002KW 1N SOT323-3
D
1
2
2
<34> SLP_S3
G
S
3
+3VS
3 3
4 4
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+5VS
PR1101 PC1101
@ 665K_0402_1% @ 1U_0603_16V6K
1 2 1 2
PR1102
@ 200K_0402_1% +5VS
D D
1 2 1
0.01U_0402_16V7K
+IN
5
2 V+
V-
1
PR1103
PC1102
@ 118K_0402_1% 4
1 2 3 OUT
2
<41> OCP_MAIN# -IN
1
PR1104 @
1
@ 118K_0402_1% PU1101
1 2 @ LMV321AS5X_SOT23-5 PR1107
<41> OCP_TRAVEL# PR1105 PR1106 @ 2K_0402_5%
@ 200K_0402_1%@ 1M_0402_1%
2
2
2
PQ1101 +3VDS
PR1108 NDS0610_NL_SOT23-3
100_0402_5%
1
S
D
ADP_SIGNAL 1 2 3 1
PR1109
3
<42> V_3.9K 100K_0402_5%
1
1
G
2
+3VDS PR1111
2
PR1125 PR1110 0_0402_5% PD1101 SRSET <42>
C 13K_0402_1% 8.06K_0402_1% @ BAV70W _SOT323-3 C
2
B
PR1112
2
1
100K_0402_5% C
VIN
E
3 1 1 2 2 PQ1103
C
3
1
1
PR1114 PR1115
PR1113 220K_0402_5% 100_0402_5%
8.66K_0402_1%
2
2
1
PQ504 1
2N7002KW 1N SOT323-3 ADP_A_ID <30> OCP_A_IN <30>
D
1
PR1116 PC1103
2 3.9K_0402_5% 3900P_0402_50V7K
0> ADP_ID_CHK
1
1
G 2 +3VDS
3
E
S PR1117 PR1118
3
130K_0402_1%
B
45.3K_0402_1% @ PR1119 2 PQ1104
PD1102 0_0402_5% MMBT3906H_SOT23-3
C
GLZ4.7B_LL34-2
2
1
PR1120
274K_0402_1%
B P1 1 2 B
+3VDS
1
+5VDS
PR1121
200K_0402_1% PR1122
47K_0402_5%
8
2
3
P
+ 1
O ADP_PRES <30,34>
1
2
-
G
PR1123 PU1102A
86.6K_0402_1% LM393DR2G SO8
4
2
PR1124 @ PC1104
22K_0402_5% 0.01U_0402_16V7K
2
2
+3VL
A A
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1
PD1201
PR1202 BAV99W T1G_SC70-3
10K_0402_5%
1 3
MFET_B 1 2
PR1201
10K_0402_5%
BATT_A
2
D D
1
1
ME2N7002DKW-G 2N SOT363-6
ME2N7002DKW-G 2N SOT363-6
PD1202 PR1204
SX34H_SMA PR1203 470K_0402_5%
3
1 2 MFET_A 10K_0402_5%
PQ1201A
PQ1201B
2
2
LATCHED_ALARM 2 5
+3VDS
4
D
1
1
1
2 PQ1202
PR1205 PR1206 G 2N7002KW 1N SOT323-3
470K_0402_5% 220K_0402_5% S
3
4
4
5 5 <30> FET_A
2
2
3 6 6 3
2 7 7 2 BATT_A
1 8 8 1
BATT PQ1203 PQ1204
AO4409L 1P SO8 AO4409L 1P SO8
PQ1205 PQ1206
AO4409L 1P SO8 AO4409L 1P SO8
1 8 8 1
2 7 7 2 BATT_B
3 6 6 3
5 5
1
1
C C
PR1207 PR1208
4
470K_0402_5% 220K_0402_5%
2
2
1
PR1209
1 2 MFET_B 10K_0402_5%
PD1203
2
SX34H_SMA
BATT_B
1
1
ME2N7002DKW-G 2N SOT363-6
ME2N7002DKW-G 2N SOT363-6
PR1210
10K_0402_5% PR1211
6
470K_0402_5%
MFET_A 1 2
PQ1207B
PQ1207A
3 2
2
2
10K_0402_5% LATCHED_ALARM 5 2
PR1212
4 +3VDS
1
D
1
PD1204
BAV99W T1G_SC70-3 2 PQ1208
G 2N7002KW 1N SOT323-3
1
B B
S
3
<30> FET_B
PR1213
1M_0402_5%
1 2
+3VDS
4/11 +5VDS +3VDS
BATT 4/11 4/11
1
1
1
PR1214
1
2
8
PR1216
2
200K_0402_1% 5
P
+ 7 LATCHED_ALARM
LATCHED_ALARM <30>
2
6 O
-
G
PU1102B
1
LM393DR2G SO8
4
PR1217
64.9K_0402_1%
1
PR1218
1 2
A 137K_0402_1% D A
2
2
G
S PQ1209
3
2N7002KW 1N SOT323-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/03 Deciphered Date 2014/12/31 Title
Battery selector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 15W 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 51 of 53
5 4 3 2 1
5 4 3 2 1
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Version Change List ( P. I. R. List ) for HW Circuit
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D 1 30 KBC 08/18 HP The quad-mode does not require any GPIO from KBC Delete R1348 & R1349 and Add R541 and R542 0.2 D
2 31 PWR OK 08/18 HP Makes the power good circuit working. Non-install R284 0.2
3 26 MXM 08/28 Compal MXM Card can't be recognized in OS. Change U37 to MC74VHC1G08DFT2G (Non-OD type) 0.2
4 36 Switch/MUX 09/07 HP Move D-Sub connector on M/B Add VGA filter circuit and connector 0.2
5 30 KBC 09/08 HP SUSCLK is off during DS3 condition Add Y4, C423, C424 ; Delete R258, R264 0.2
6 30 KBC 09/08 HP Simplify the KBC solution for MEC1322 Delete R262,R266,R219,R216,R241,R242,R271,R253 0.2
9 39 NFC 09/10 HP Power rail option for NFC module Add +3VM_LAN (R1376) for NFC module 0.2
10 9 CPU 09/11 HP Remove RC102 and RC103 0.2
11 20 PCH 09/11 HP Connect PCH's pin AD12 to +3V_PCH directly Remove RH226 0.2
12 5 CPU 09/11 HP Connect CPU.AT26 pin to CPU_PLTRST# directly Remove RC66 0.2
13 5 CPU 09/11 HP Connect CPU.AL34 pin to H_CPUPWRGD directly Remove RC30 0.2
09/11 Simplify PCH solution for PCIE CLK Group Remove RH107,RH103,RH114,RH116,RH122
17 15 PCH HP 0.2
RH124,RH126,RH127,RH129,RH130
18 14 PCH 09/11 HP Reassignement GPIO for "BT_OFF" Change it from GPIO72 to GPIO61 0.2
19 30 KBC 09/11 HP Reserve for SUSACK# signal Uninstall R436 and add R1378 0.2
09/11 HP Reassigned BRD_ID4 to GPIO40 for CP support Connect RH180.1 to +3VS & RPH1.8 to GND 0.2
20 18 PCH
and update table for DB1-R
A
21 30 KBC 09/12 HP Simplify the KBC solution for MEC1322 Delete R249,R251,R256,R277 0.2 A
22 36 Switch/MUX 09/12 HP eDP trace length over Intel's specification Change solution to PS8321 0.2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/03 Deciphered Date 2014/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 52 of 53
5 4 3 2 1
5 4 3 2 1
WWW.AliSaler.Com
Version Change List ( P. I. R. List ) for HW Circuit
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D 23 29 LAN 09/12 HP Avoid IEEE failure with trace stub lines Add Lan switch solution PI3L500-AZFEX (U43) 0.2 D
24 39 I/O CONN 09/12 HP Move Hall sensor IC on Function board Add +3VDS & LID_SW# pin to JFB1 0.2
25 22 eDP 09/13 Compal Avoid LVDS Burn out Risk Rearrange pin assignment of JEDP1 0.2
26 31 POK CKT 09/13 HP Modify Power OK circuit Delete UH7, RH235 ; Add R1379 0.2
27 39 I/O CONN 09/19 HP Prevent Card Reader can't be recognized issue Add R1380 for PCH_PCIE_WAKE# 0.2
28 13 PCH 09/19 HP Disable the unlock of ME descriptor Change QH11 to P-MOSFET 0.2
29 37 Smart Card 09/20 HP RC delay is NOT good as reset Delete CC67,R393, then connect U30.23 to PLT_RST#. 0.2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9371P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 28, 2012 Sheet 53 of 53
5 4 3 2 1