PTN5100 PHY Programming Guide V0.1

PTN5100 PD PHY APPLICATION
PROGRAMMING GUIDE Ver. 0.1

1

Revision history
Rev Date Description
0.1 20150322 Initial version

2
Introduction
PTN5100 is a single port USB Type‐C Power Delivery PHY and Protocol IC that provides Type‐C configuration
channel interface and USB PD physical and protocol layer functions to a system PD port policy controller.
PTN5100 can support system realization of the following PD port roles – Provider (P) only, Provider/Consumer
(P/C), Consumer only (C) or Consumer/Provider (C/P). PTN5100 can be programmed to operation in Type‐C specific
UFP, DFP and DRP role.
PTN5100 can be programmed to operate with or without (autonomous) a policy controller. In autonomous mode,
PTN5100 does the following:
 Cable plug/unplug handling
 Determine plug orientation
 CC detection/indication scheme based on preprogrammed DRP, DFP or UFP role
 Handling (applying) of Rd or Rp depending on pre‐programmed port role
 Automatically closes the external power FETs

In non‐autonomous mode, PTN5100 works under the control of a policy controller and a system management
controller (SMC). Under the guidance of the policy controller and the system management controller through
SPI/I2C interface and hardware interrupt based, PTN5100 can be programmed to accomplish tasks such as power
contract negotiations, swaps power roles, swaps data roles, requests higher or lower power levels, initiates and
acknowledges DP Alternate mode. PTN5100 also supports Vender Defined Message.

PTN5100 uCONTROLLER EC
(PD PHY) SPI/I2C (PD PROTOCOL + PORT POLICY I2C (SYSTYEM POLICY
CONTROLLER) CONTROLLER)

Figure 1

PTN5100 EC
(PD PHY) SPI/I2C (PD PROTOCOL + PORT POLICY CONTROLLER +
SYSTYEM POLICY CONTROLLER)

Figure 2

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This application programming guide is intended to be used with NXP PTN5100 (PD port PHY). The port policy
controller is either a stand‐alone microcontroller (figure 1) or the port policy controller is absorbed into the EC
(figure 2). The stand‐alone microcontroller or the EC communicate with PTN5100 through a hardware SPI or an I2C
interface. The PTN5100 PD PHY functionalities can be programmed through a set of registers that the stand‐alone
or EC can assess through the SPI/I2C bus. The SPI interface requires a specific byte sequence and byte order and
will be described first. The I2C interface and the register interface will be described subsequently.

Programming steps needed to initialize the PTN5100, to send and to receive PD messages will be given and
describe in this programming guide as well.

I. SPI Interface
The PTN5100 SPI interface supports SPI modes 0 and 3. Each SPI access consists of a 16‐bit address follows by a
command byte to indicate a read access or a write access, auto address increment, and to start the internal
oscillator (if PTN5100 has been put into sleep mode).

SPI Command Byte [7:0] – command byte latched each SPI transaction and held stable until the next
transaction.
 Bit 7 – Access Direction
o ‘0’ – write
o ‘1’ – read
 Bit 6 – Clock Request
o ‘0’ – don’t request clock
o ‘1’ – request clock (start the internal oscillator)
 Bit [5:1] – Reserved
 Bit 0 – Address Auto Increment
o ‘0’ – Address Auto Increment Disable
o ‘1’ – Address Auto Increment Enable
To determine if the internal oscillator has started and has reached a stable frequency, a special register is provided
at address 0xFFFF. This special register indicates the status of the internal clock.
 Bits [7:1] – Reserved
 Bit 0 – Clock Status
o ‘0’ – internal clock is on and stable (clock is ready)
o ‘1’ – internal clock is off or not stable
The host processor (or EC) must first request the clock, then polling the special register bit 0 until bit 0 indicate
clock is ready before further SPI operations.
SPI Write
4
The following figure shows an example of burst SPI write and SPI clock is omitted for clarity.

Figure 3

SPI Read

The following figure shows an example of burst SPI read. Note that during SPI read, the first data should be taken
after the command byte is sent.

Figure 4

Multiple PTN5100 can be connected on the same SPI bus wherein each of them is selected by a dedicated SPI_CSN.
The interrupt outputs of PTN5100s can be wired‐OR into a single interrupt pin of EC or they can be separately
connected to dedicated pins of the EC.

II. I2C Interface

PTN5100 is an I2C slave to an I2C master, and its slave address can be selected by the SLV_ADDR pin.

The I2C interface is based on standard I2C specification. The read and write operation specifies by the standard
should be followed.

Each I2C transaction required a slave address, two‐byte register address (16‐bit), follows by data bytes.

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I2C Write
The following figure shows an example of an I2C write operation

Figure 4

I2C Read
The following figure shows a repeat start I2C read operation.

Figure 5

Bursts are allowed during I2C write or read. Bit15 of the offset register is auto address increment indication. If
bit 15 is a ‘0’ then auto‐increment is disabled, and it is a ‘1’ then auto‐increment is enabled.

III. Register Interface

The register interface is implemented and supports by the PTN5100. The register interface consist of a number
of 8‐bit registers. The list of these registers and the register bit (s) descriptions are listed in the last section of
this application programming guide. The functionality and behavior of the PTN5100 are depent on how these
registers are programmed. The power‐on or default register settings are programmed at the factory into the
non‐volatile flash memory (MTP – multi‐time programmable) inside the PTN5100. These pre‐programmed
parameters determine the initial behavior of the PTN5100 (for examples, the PTN5100 can behave as type C
DFP, or UFP or DRP upon power up. The PTN5100 can also be programmed to operate autonomously without a
host intervention, say during dead battery condition). Once the PTN5100 is up and running, the SMC (system
management controller) can always re‐program the PTN5100 through the register interface to change its
behavior, to request higher power or lower power from the remote provider, to request role swap if needed,
or to do Alternate modes.
Below are some samples flow charts to initialize PTN5100, to set up the PTN5100 to handle interrupt, to setup
PTN5100 to send a USB PD message as well as to receive a PD message.
a. PTN5100 Initialization
Before initializing other registers, the host must ensure that PTN5100’s internal oscillator is
stabled, and that the device has completed its power on reset sequence.
i. PTN5100 Internal Oscillator

The state of the PTN5100 internal oscillator can be read from the dummy_spi_register
(0xFFFF). Bit0 will be set to ‘1’ if the oscillator is stabled and ready.
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ii. PTN5100 Power On Reset
Once PTN5100 has completed its POR (power on reset) sequence, it will set bit0 of
pmu_status register to ‘1’.
iii. PTN5100 Sample Initialization Procedure

The flow chart below initialize the port to DFP role, pull up is a resistor type, type C
current set to standard USB (500mA), VCONN is enabled with forward and reverse
current protection.
PTN5100 POWER ON
READ 0xFFFF
N
BIT0 Set? Check for oscillator ready
READ 0x0048
N Check for PTN5100 POR
BIT0 Set? ready
WRITE 0x0041, 0x3B Un‐gate internal clocks
Disable power down &
WRITE 0x0042, 0x00 standby
READ PTN5100 INTERNAL
STATE AFTER POWER ON Check for VDD present
READ 0x0240
Check for VBUS present
READ 0x0241
Check orientation, VCONN
READ 0x0288 state, power role, SM state..
7
Check for default pull‐up type
READ 0x0289 – std USB, 1.5A, 3A
Check pull‐down on CC lines
READ 0x028A – Rd, Ra or both are on
CC1/CC2
READ 0x02C3 Check VCONN fault status
INITIALIZE PTN5100
Set TX slew rate, TX bias, RX
WRITE 0x0303, 0x1A bias
Select receive mask threshold
WRITE 0x0304, 0x23
Set Type‐C hardware state
WRITE 0x0280, 0x00 machine to disable
SRC SNK
SRC or SNK
Disable Disable
WRITE 0x0284, 0x00 WRITE 0x0285, 0x00 pull‐up
pull‐down
Enable pull‐up at Enable pull‐
STD USB limit
WRITE 0x0285, 0x09 WRITE 0x0284, 0x0A down
Enable Rd voltage
WRITE 0x0286, 0xC0 comparators
Enable Ra threshold
WRITE 0x0287, 0xC9 comparator at STD USB limit
Disable interrupts
WRITE 0x0003, 0xFF
Disable interrupts
WRITE 0x0004, 0xFF
WRITE 0x0005, 0xFF Disable interrupts
Select interrupt type – edge
or level
WRITE 0x000B, 0xFF
8
WRITE 0x000C, 0xFF or level
WRITE 0x000D, 0xFF or level
Select interrupt polarity –
WRITE 0x0012, 0xFF rising/falling, high/low
WRITE 0x0011, 0x01 Enable internal clock
Enable CC current stable, Role
WRITE 0x0003, 0x9A change, Detach, P/S interrupt
Enable RX, soft reset, hard reset, TX
WRITE 0x0004, 0x1B interrupt
WRITE 0x0005, 0xFE Enable POR interrupt
Enable forward and reverse
WRITE 0x02C0, 0x80
current protection on VCONN
Open all the FETs
WRITE 0x0242, 0x54
Select Rp type – resistor, or
WRITE 0x028C, 0x31 current source. Override MTP
default settings.
Disable hard reset reception
WRITE 0x0100, 0x00 (will enable later on TX or RX
messaging)
END INITIALIZATION
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b. Handling an Interrupt Event
Handling of an interrupt event are given in the two examples below. The selected interrupt
must be enabled during initialization of the PTN5100. There are two methods the software can
use to clear the interrupt. If the auto clear bits are set (0x0000, 0x0001, 0x0002), the interrupt
is automatically cleared once the interrupt status register has been read. If the auto clear bits
are not set, then the software must write to the corresponding bit in the status register to clear
the interrupt.
c. Sending a PD Message
The example given below is related to the type C cable insertion. The interrupt is generated if
there is an insertion occurs at the type C receptacle assuming that the role change interrupt is
enabled.
CABLE INSERTED
Read interrupt status 0 (role
READ 0x0008
change interrupt)
WRITE 0x0008, 0x20 Clear the interrupt
Read role status (power role,
READ 0x0288 CC orientation, VCONN status,
type C role (UFP, DFP))
READ 0x0289 Type C current (std USB,
Register Value Port Role CC1 State 1.5A, 3A)
‘bxx10_xxxx SRC SRC.Ra
‘b1001_xxxx SRC SRC.Open
‘b0101_xxxx SRC SRC.Rd READ 0x028A Determine if Rd/Ra connected
‘bxx10_xxxx SNK SNK.Open
‘bxx01_xxxx SNK SNK.Rp
Determine PTN5100 state
Register Value Port Role CC2 State READ 0x028B machine last state
‘bxxxx_xx10 SRC SRC.Ra
‘bxxxx_1001 SRC SRC.Open
‘bxxxx_0101 SRC SRC.Rd
Enable bias current, enable
‘bxxxx_xx10 SNK SNK.Open WRITE 0x0302, 0x09 RX (receiver)
‘bxxxx_xx01 SNK SNK.Rp
Enable hard reset receive,
WRITE 0x0100, 0x11 enable RX msg receive
10
WRITE 0x0242, 0xD6 Enable EN_USBSRC FET signal by
driving it to active low (5V onto VBUS)
5V on VBUS causes a power
READ 0x0008 change interrupt. Read int. status0
Read interrupt status1
READ 0x0009
READ 0x000A
Determine if VDD present on
READ 0x0240 VDD pin
Determine if VBUS present
READ 0x0241 on VBUS pin
Enable VSafe0 comparator
WRITE 0x0380, 0x02 Vref cell
Enable VSafe0 comparator (in
WRITE 0x0300, 0x02 case VBUS goes to 0V)
Set up SOP type, msg ID
WRITE 0x0107, 0x00 counter for TX transmission
Set up re‐try counter, PD msg
WRITE 0x0103, 0x13 role bit for TX transmission
Set up port role (source/sink for
WRITE 0x0104, 0x01 SOP msg) ‐ SOURCE
Set up data role ‐ DFP
WRITE 0x0105, 0x01
Reset PHY and protocol layer
WRITE 0x0040, 0x01
Clear PHY reset
WRITE 0x0040, 0x00
Enable SOP msg receiving
WRITE 0x010D, 0x01
11
Setup msg type and number of
WRITE 0x0106, 0A PDO being sent – SRC cap, 2 PDOs
WRITE 0x010B, 0x01 Enable TX message buffer
WRITE 0x0144 to Fill TX buffer (28 bytes) with PDOs. The
first 8 bytes would be the 2 PDOs, and the
0x015F with PDOs next 20 bytes are filled with zeros
Set TX message DONE bit
WRITE 0x0107, 0x02
Once PTN5100 has sent
TX message it will set TX
done interrupt
d. Receiving a PD Message
Once the PTN5100 has received a PD message it will set the msg_rcvd available interrupt. A
flow chart to read the PD message from the receive buffer is giving below.
MSG_RCVD INTERRUPT
READ 0x0008
Read interrupt status1 –
READ 0x0009 MSG_RCVD bit set
READ 0x000A
Find out which RX buffer has
READ 0x010F the received message
12
Find out how many PDOs and
READ 0x0110 message type received
Read PD message from RX
READ 0x183 to 0x019E buffer0.
MSG_RCVD DONE

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PTN5100 Register Table

Address Block/Register Dir POR Description
0x0000 int_control Internal Interrupt Control/Status
Control byte for the auto clear function of
interrupt controller

0x0000 int_auto_control0 RW 0x0000
When set the corresponding interrupt shall
automatically clear when the interrupt status
register has been read.


Control byte for the mask function of the

When set the corresponding interrupt is masked
and all activity on the interrupt source input shall
0x0003 int_mask0 RW 0x00ff be ignored. Setting this bit will cause an active
interrupt to cease asserting the interrupt outputs.

At POR all interrupts corresponding to Status0
register are masked.


0x0004 int_mask1 RW 0x00ff be ignored. Setting this bit will cause an active

At POR all interrupts corresponding to Status1
register are masked.


0x0005 int_mask2 RW 0x0006
be ignored. Setting this bit will cause an active

At POR we are unmasking the folloiwng interrupt:
Bit 0: por_complete
14
0x0006 –
Reserved ‐ 0x0000 Reserved
0x0007
Interrupt Status Register

When set the corresponding interrupt is asserted.
To clear the interrupt write a '1' to the
corresponding bit. If auto‐control is set for the
specific interrupt it shall be automatically cleared
when this register is read.

0x0008 int_status0 RWO 0x0000
Bit 7: cc2_stable_int
Bit 6: cc_cursns_stable_int
Bit 5: typec_role_change_int
Bit 4: typec_orient_found_int
Bit 3: typec_debug_found
Bit 2: typec_detach_int
Bit 1: GPIO Interrupt (OR of all GPIOs)
Bit 0: ps_stat_change_int

When set the corresponding interrupt is asserted.
To clear the interrupt write a '1' to the
corresponding bit. If auto‐control is set for the
specific interrupt it shall be automatically cleared
when this register is read.

0x0009 int_status1 RWO 0x0000
Bit 7: msg_rcvd_and_available
Bit 6: soft_rst_rcvd
Bit 5: hard_reset_rcvd
Bit 4: cable_reset_rcvd
Bit 3: other_reset_rcvd
Bit 2: tx_done
Bit 1: msg_rcvd
Bit 0: cc1_stable_int

Bits 7:3: Reserved
0x000A int_status2 RWO 0x0000 Bit 2: vconn_fault_fcl_int
Bit 1: vconn_fault_rcp_int
Bit 0: por_complete

Interrupt Edge Detection control register

When set the interrupt is Edge Triggered. When
Clear the interrupt is level sensitive.
0x000B int_edge0 RW 0x00ff

At POR all interrupts corresponding to Status0 are
edge sensitive.


0x000C int_edge1 RW 0x00ff

edge sensitive.

15

0x000D int_edge2 RW 0x0007

edge sensitive.

0x000E – Reserved
Reserved ‐ 0x0000
0x0010
Interrupt Source Clock Enable control register

0x0011 int_src_clkon RW 0x0000
When set the corresponding interrupt will enable
the system clock when asserted.
Interrupt Polarity control register

0x0012 int_polarity0 RW 0x00ff
When set the interrupt is active high, when clear
the interrupt is active low.

0x0013 int_polarity1 RW 0x00ff

0x0014 int_polarity2 RW 0x0007
Interrupt Output Polarity control register

0x0015 int_out_polarity_hi RW 0x0000
When set the output will be active high, when
clear the interrupt outputs are active low.
0x0016 –
0x003F
0x0040 pmu PMU
0x0040 pmu_reset_ctrl RW 0x0000 PMU reset control
0x0041 pmu_clk_ctrl0 RW 0x0000 PMU clock control0
0x0042 pmu_lowpower ‐ 0x0000 Enable Gating for low power
0x0043 –
0x0047
0x0048 pmu_status RO 0x0000 PMU Status Register
0x0049 i2c_clock_control_reg RW 0x0000 Control I2C clock
0x004A rev_id RO 0x00a0 Silicon's revision ID register
0x0080‐
0x00FF
0x0100 protocol_layer USB PD Protocol Layer
0x0100 sw_prot_rst_stat_ctrl RW 0x0010 USB PD Protocol Layer Reset and Control Register
16
0x0101 sw_usbpd_prot_pwrswap_reset RW 0x0001 USB PD Protocol Layer Reset and Control Register
0x0102 sw_prot_status_0 RO 0x0000 USB PD Protocol Layer Status Register
0x0103 sw_pd_info_0 RW 0x0013 USB PD Information for Message Transmission
0x0106 sw_usbpd_tx_pkt_ctrl_0 RW 0x0000 USB PD Protocol Layer Tx Packet Control Register
0x0107 sw_usbpd_tx_pkt_ctrl_1 RW 0x0000 USB PD Protocol Layer Tx Packet Control Register
USB PD Information for Message
0x0108 sw_pd_msg_hdr_rsvd RW 0x0000
Transmission ‐ Reserved bits in Msg header
0x0109 –
0x010A
0x010B sw_usbpd_tx_pkt_stat RO 0x0000 USB PD Protocol Layer Tx Packet Status Register
0x010C sw_usbpd_rx_pkt_ctrl_0 RW 0x0010 USB PD Protocol Layer Rx Packet Control Register
0x010D sw_usbpd_rx_pkt_ctrl_1 RW 0x0000 USB PD Protocol Layer Rx Packet Control Register
0x010E sw_usbpd_rx_pkt_ctrl_2 RW 0x0001 USB PD Protocol Layer Rx Packet Control Register
0x010F sw_usbpd_pend_rx_msg_global_stat RO 0x0000 USB PD Protocol Layer Pending Rx Message Status
USB PD Protocol Layer Rx Buf 0 Packet Status
Register. This contains status for recently received
0x0110 sw_usbpd_rx0_pkt_stat_0 RO 0x0000
message stored in Rx Message Buffer 0.



Register. This contains status for recently
received message stored in Rx Message Buffer 1.



0x0116 sw_bist_ctrl RW 0x0000 USB PD BIST Transmission Control
17
USB PD Bist Error Count Bits 15:8

Used in USB PD BIST Transmitter Mode. These bits
are used when Tahoe is in BIST Transmitter mode
sending PRBS frames to the test equipment. After
sending each PRBS frame the other side sends
back a BIST Test Message containing the Returned
Error Count. These are those bits.
0x0117 sw_rx_bist_errcnt_15_8 RO 0x0000

Note: We save bits 15:0 from the received BIST
Data Object for all incoming BIST Test Messages.
In the case of a returned error counter message
bits 15:0 contain the returned error count. In
other cases these bits are undefined. But they are
still stored and can be retrieved here.


Used in USB PD BIST Transmitter Mode. These bits
are used when Tahoe is in BIST Transmitter mode
sending PRBS frames to the test equipment. After
sending each PRBS frame the other side sends
back a BIST Test Message containing the Returned
Error Count. These are those bits.
0x0118 sw_rx_bist_errcnt_7_0 RO 0x0000

Note: We save bits 15:0 from the received BIST
Data Object for all incoming BIST Test Messages.
In the case of a returned error counter message
bits 15:0 contain the returned error count. In
other cases these bits are undefined. But they are
still stored and can be retrieved here.

0x0119 sw_bist_stat_0 RO 0x0000 USB PD Bist Message Status
0x011A –
Reserved ‐ 0x007d Reserved
0x013F
0x0140 usb_tx_msg_buf USB PD Message Buffer ‐ Tx Buffer
0x0140 usbpd_msg_buf_cfg RW 0x0000 Message Buffer Configuration
0x0141 –
0x0143
USB PD Message Tx Payload Data byte 0. First
0x0144 usbpd_msg_tx_buf_payload_0 RW 0x0000
byte sent after Message Header.
USB PD Message Tx Payload Data byte 1. 2nd byte
sent after Message Header.
USB PD Message Tx Payload Data byte 2. 3rd byte
USB PD Message Tx Payload Data byte 3. 4th byte
0x014A usbpd_msg_tx_buf_payload_6 RW 0x0000
18
0x014B usbpd_msg_tx_buf_payload_7 RW 0x0000
0x014C usbpd_msg_tx_buf_payload_8 RW 0x0000
USB PD Message Tx Payload Data byte 9. 1oth
0x014D usbpd_msg_tx_buf_payload_9 RW 0x0000
USB PD Message Tx Payload Data byte 10. 11th
0x014E usbpd_msg_tx_buf_payload_10 RW 0x0000
0x014F usbpd_msg_tx_buf_payload_11 RW 0x0000
USB PD Message Tx Payload Data byte 20. 21st
USB PD Message Tx Payload Data byte 21. 22nd
USB PD Message Tx Payload Data byte 22. 23rd
0x015A usbpd_msg_tx_buf_payload_22 RW 0x0000
0x015B usbpd_msg_tx_buf_payload_23 RW 0x0000
0x015C usbpd_msg_tx_buf_payload_24 RW 0x0000
0x015D usbpd_msg_tx_buf_payload_25 RW 0x0000
0x015E usbpd_msg_tx_buf_payload_26 RW 0x0000
0x015F usbpd_msg_tx_buf_payload_27 RW 0x0000
0x0180 usb_rx_msg_buf0 USB PD Message Buffer ‐ Rx Buffer 0
Not Used. This address is just reserved to allow Tx
0x0180 usbpd_msg_rx_buf0_control RO 0x0000 and Rx addresses in Message Buffer to be the
same.
0x0181 usbpd_msg_rx_buf0_hdr_0 RO 0x0000 USB PD Message Rx Buffer 0 Header bits [7:0]
0x0182 usbpd_msg_rx_buf0_hdr_1 RO 0x0000 USB PD Message Rx Buffer 0 Header bits [15:8]
19
USB PD Message Rx Buffer 0 Payload Data byte 0.
0x0183 usbpd_msg_rx_buf0_payload_0 RO 0x0000
First byte received after Message Header.
2nd byte received after Message Header.
3rd byte received after Message Header.
4th byte received after Message Header.
0x018A usbpd_msg_rx_buf0_payload_7 RO 0x0000
0x018B usbpd_msg_rx_buf0_payload_8 RO 0x0000
0x018C usbpd_msg_rx_buf0_payload_9 RO 0x0000
USB PD Message Rx Buffer 0 Payload Data byte
0x018D usbpd_msg_rx_buf0_payload_10 RO 0x0000
10. 11th byte received after Message Header.
0x018E usbpd_msg_rx_buf0_payload_11 RO 0x0000
0x018F usbpd_msg_rx_buf0_payload_12 RO 0x0000
20. 21st byte received after Message Header.
21. 22nd byte received after Message Header.
22. 23rd byte received after Message Header.
0x019A usbpd_msg_rx_buf0_payload_23 RO 0x0000
0x019B usbpd_msg_rx_buf0_payload_24 RO 0x0000
20
0x019C usbpd_msg_rx_buf0_payload_25 RO 0x0000
0x019D usbpd_msg_rx_buf0_payload_26 RO 0x0000
0x019E usbpd_msg_rx_buf0_payload_27 RO 0x0000
0x01C0 usb_rx_msg_buf1 USB PD Message Buffer ‐ Rx Buffer 1
Not Used. This address is just reserved to allow Tx
0x01C0 usbpd_msg_rx_buf1_control RO 0x0000 and Rx addresses in Message Buffer to be the
same.
0x01C1 usbpd_msg_rx_buf1_hdr_0 RO 0x0000 USB PD Message Rx Buffer 1 Header bits [7:0]
0x01C2 usbpd_msg_rx_buf1_hdr_1 RO 0x0000 USB PD Message Rx Buffer 1 Header bits [15:8]
0x01C3 usbpd_msg_rx_buf1_payload_0 RO 0x0000
First byte received after Message Header.
2nd byte received after Message Header.
3rd byte received after Message Header.
0x01CA usbpd_msg_rx_buf1_payload_7 RO 0x0000
0x01CB usbpd_msg_rx_buf1_payload_8 RO 0x0000
0x01CC usbpd_msg_rx_buf1_payload_9 RO 0x0000
0x01CD usbpd_msg_rx_buf1_payload_10 RO 0x0000
0x01CE usbpd_msg_rx_buf1_payload_11 RO 0x0000
0x01CF usbpd_msg_rx_buf1_payload_12 RO 0x0000
0x01D0 usbpd_msg_rx_buf1_payload_13 RO 0x0000
21
20. 21st byte received after Message Header.
21. 22nd byte received after Message Header.
22. 23rd byte received after Message Header.
0x01DA usbpd_msg_rx_buf1_payload_23 RO 0x0000
0x01DB usbpd_msg_rx_buf1_payload_24 RO 0x0000
0x01DC usbpd_msg_rx_buf1_payload_25 RO 0x0000
0x01DD usbpd_msg_rx_buf1_payload_26 RO 0x0000
0x01DE usbpd_msg_rx_buf1_payload_27 RO 0x0000
0x0200 phy_layer USB PD Digital PHY Layer
USB PD PHY Layer Data‐Rate and CLK‐Freq Config
0x0200 usbpd_phy_bist_ctrl RW 0x002c
Register
0x0201 –
Reserved RO 0x0000 Reserved
0x0205
USB PD PHY Layer Bitstream Behavior Control
0x0206 usbpd_phy_bitstream_ctrl RW 0x0008
Register
0x0207 –
Reserved RW 0x0024 Reserved
0x022D
During BIST Receive mode, this is the accumulated
0x022E usbpd_phy_bist_return_errcnt_15_8 RO 0x0000 Error‐Count value from PHY made available for
Read. This register contains bits 15:8
During BIST Receive mode, this is the accumulated
0x022F usbpd_phy_bist_return_errcnt_7_0 RO 0x0000 Error‐Count value from PHY made available for
Read. This register contains bits 7:0
Reserved Reserved
0x0232 RW 0x0000
0x0240 ps_status_fet_control Power Supply Status and FET Control
0x0240 pwr_supply_stat_0 RO 0x0000 Power Supply Status
0x0241 pwr_supply_stat_1 RO 0x0000 Power Supply Status
FET Control ‐ This allows S/W control of the FETs
0x0242 fet_ctrl_0 RW 0x0000 as well as setting up priority between V_ACDC and
Vbus in case H/W greedy mode is enabled.
0x0280 typec_condet Type‐C Controller
0x0280 control_sm_1 RW 0x0000
22
0x0281 control_sm_2 RW 0x0015
0x0282 control_sm_3 WO 0x0000
0x0283 control_vconn_comm RW 0x0000
0x0284 control_rd RW 0x0000
0x0285 control_rp RW 0x0000
0x0286 control_vrd RW 0x0000
0x0287 control_vra RW 0x0009
0x0288 status_role RO 0x0000
0x0289 status_cursns RO 0x0000
0x028A status_comp RO 0x0000
0x028B status_state RO 0x0000
0x028C config RW 0x0020
0x028D sw_taccdetect_10_8 RW 0x0000
Timer value for tAccDetect (Time before
0x028E sw_taccdetect_7_0 RW 0x00c7 Accessory Mode shall be entered). 50ms to 200ms
in increments of 256us. POR 50ms + ~10%
0x028F sw_tdrpswap_rp_10_8 RW 0x0000
Timer value for tDRPSwap (The length of a Rp
0x0290 sw_tdrpswap_rp_7_0 RW 0x003c cycle during the DRP advertisement). 15ms to
70ms in increments of 256us. POR 15ms + ~10%
0x0291 sw_tdrpswap_rd_10_8 RW 0x0000
Timer value for tDRPSwap (The length of a Rd
0x0292 sw_tdrpswap_rd_7_0 RW 0x00f6 cycle during the DRP advertisement). 15ms to
70ms in increments of 256us. POR 70ms ‐ ~10%
0x0293 sw_tdrphold_10_8 RW 0x0001
Timer value for tDRPHold (Wait time associated
0x0294 sw_tdrphold_7_0 RW 0x008e with the Attach.DFP.DRPWait state). 100ms to
150ms in increments of 256us. POR 100ms + ~10%
0x0295 sw_tdrplock_10_8 RW 0x0001
Timer value for tDRPLock (Wait time associated
0x0296 sw_tdrplock_7_0 RW 0x008e with the Lock.UFP state). 100ms to 150ms in
increments of 256us. POR 100ms + ~10%
0x0297 sw_tdrptry_10_8 RW 0x0006
Timer value for tDRPTry (Wait time associated
0x0298 sw_tdrptry_7_0 RW 0x0036
with the Try.DRP state). 400ms to 450ms in
23
0x0299 sw_terrorrecovery_10_8 RW 0x0000
Timer value for tErrorRecovery (Time a port shall
0x029A sw_terrorrecovery_7_0 RW 0x0064 remain in the ErrorRecovery state). 25ms min in
0x029B sw_tdfpidle_10_8 RW 0x0000
Timer value for tDFPIdle (Wait time associated
0x029C sw_tdfpidle_7_0 RW 0x00f6 with Unattached.DFP Idle state). 15ms to 524ms
in increments of 256us. POR 70ms ‐ ~10%
0x029D sw_tvbusdischarge_10_8 RW 0x0000
Timer value for VBUS discharge. 0ms to 524ms in
0x029E sw_tvbusdischarge_7_0 RW 0x00c7
Timer value for tCCDetectSkew (Allowance for
skew between debounced comparator outputs).
0x029F sw_tccdetectskew RW 0x00c7 5ms to 65ms in increments of 256 us. POR 50ms +
~10%.

Timer prescale divider, dividing 2MHz clock. The
time base for the timers is 0.5us Ã— 2 Ã—
0x02A0 sw_typec_clkdiv RW 0x00ff (sw_typec_clkdiv + 1). The timeout interval for a
timer is the time base Ã— (timer value + 1).

Debounce timer count value for detection on CC1.
0x02A1 sw_cc1_dbnc_cnt_15_8 RW 0x0029 10ms min at POR, adjustable from 0ms to 64ms in
steps of 256us. POR 10ms + ~2.5%
Debounce timer count value for detection on CC2.
0x02A2 sw_cc2_dbnc_cnt_15_8 RW 0x0029 10ms min at POR, adjustable from 0ms to 64ms in
Debounce timer count value for indication of
change in Vrd current limit voltage detection.
0x02A3 sw_cc_cursns_dbnc_cnt_15_8 RW 0x0029
10ms min at POR, adjustable from 0ms to 64ms in
0x02C0 vconn_switch_control Vconn Switch Control
0x02C0 vconn_fault_ctrl0 RW 0x0007 Vconn Control Register
0x02C1 vconn_fault_ctrl1 RW 0x0044 Vconn Switch Fault Control
0x02C2 vconn_fault_ctrl2 RW 0x0000 Vconn Switch Fault Control
0x02C3 vconn_fault_status RO 0x0000 Vconn Switch Fault Status
0x0300 ana_ctl Analog Control
0x0300 pwr_ctrl_0 RW 0x0000 Power Subsystem Control
0x0301 pwr_ctrl_1 RW 0x0001 Power Subsystem Control
0x0302 afe_ctrl_0 RW 0x0000 RX/TX Control 0
24
0x0305 product_id_byte0 RO 0x0000 Product ID Byte 0
0x0306 product_id_byte1 RO 0x0051 Product ID Byte 1
0x0307 –
Reserved RW 0x0000 Reserved
0x0343
0x0344 rxtx_tst_ctrl_1 ‐ 0x0000 RX/TX Test Control 1
0x0345 –
0x037F
0x0380 spare_regs Spare Registers
Spare Register (to Analog‐Top as
0x0380 spare_reg_0 RW 0x0000
dig_spare_in[7:0])
0x0381 Reserved ‐ 0x0000 Reserved
0x0382 Reserved ‐ 0x0000 Reserved
0xFFFF dummy_spi__registers SPI Internal Registers

0xFFFF spi_status RO 0x0000 SPI Status Register.

25

PTN5100 Register Description

int_control Block Register Definition ‐ Register int_auto_control0 (Offset: 0x0000)
Description: Control byte for the auto clear function of interrupt controllerWhen set the corresponding interrupt shall
automatically clear when the interrupt status register has been read.
R/W: RW
POR: 0x0000
Field Bits POR Description
int_auto_clr_cc2_stable_int 7 0x00 Auto Clear for CC2 Pin Stable Interrupt
int_auto_clr_cc_cursns_stable_int 6 0x00 Auto Clear for CC Current Sense Stable Interrupt
int_auto_clr_typec_role_change_int 5 0x00 Auto Clear for Type C Role Change Interrupt
int_auto_clr_typec_orient_found_int 4 0x00 Auto Clear for Type C Orient Found Interrupt
int_auto_clr_typec_debug_found 3 0x00 Auto Clear for Type C Debug Accessory Found Interrupt
int_auto_clr_typec_detach_int 2 0x00 Auto Clear for Type C Detach Interrupt
26
R/W: RW
POR: 0x0000
int_auto_clr_gpio_int 1 0x00 Auto Clear for GPIO Input Interrupt
int_auto_clr_ps_stat_change_int 0 0x00 Auto Clear for Power Supply Status Change Interrupt

R/W: RW
POR: 0x0000
int_auto_clr_msg_rcvd_and_availabl
7 0x00 Auto Clear for Message Received and Available Interrupt
e_int
int_auto_clr_soft_rst_rcvd_int 6 0x00 Auto Clear for Soft Reset Received Interrupt
int_auto_clr_hard_reset_rcvd_int 5 0x00 Auto Clear for Hard Reset Received Interrupt
int_auto_clr_cable_reset_rcvd_int 4 0x00 Auto Clear for Cable Reset Received Interrupt
int_auto_clr_other_reset_rcvd_int 3 0x00 Auto Clear for other_reset_rcvd_int
int_auto_clr_tx_done_int 2 0x00 Auto Clear for Message Tx Done Interrupt
int_auto_clr_msg_rcvd_int 1 0x00 Auto Clear for Message Received Interrupt
int_auto_clr_cc1_stable_int 0 0x00 Auto Clear for CC1 Pin Stable Interrupt

R/W: RW
POR: 0x0001
unused 7:3 0x00 Reserved
int_auto_clr_vconn_fault_fcl_int 2 0x00 Auto Clear for Vconn FCL Fault Interrupt
int_auto_clr_vconn_fault_rcp_int 1 0x00 Auto Clear for Vconn RCP Fault Interrupt
Auto Clear for PMU POR Complete Interrupt. At POR the por_complete
int_auto_clr_por_complete 0 0x01
interrupt is the only interrupt set to automatically
27

int_control Block Register Definition ‐ Register int_mask0 (Offset: 0x0003)
Description: Control byte for the mask function of the interrupt controllerWhen set the corresponding interrupt is masked
and all activity on the interrupt source input shall be ignored. Setting this bit will cause an active interrupt to cease
asserting the interrupt outputs.At POR all interrupts corresponding to Status0 register are masked.
R/W: RW
POR: 0x00ff
int_mask_cc2_stable_int 7 0x01 Mask for CC2 Pin Stable Interrupt
int_mask_cc_cursns_stable_int 6 0x01 Mask for CC Current Sense Stable Interrupt
int_mask_typec_role_change_int 5 0x01 Mask for Type C Role Change Interrupt
int_mask_typec_orient_found_int 4 0x01 Mask for Type C Orient Found Interrupt
int_mask_typec_debug_found 3 0x01 Mask for Type C Debug Accessory Found Interrupt
int_mask_typec_detach_int 2 0x01 Mask for Type C Detach Interrupt
int_mask_gpio_int 1 0x01 Mask for GPIO Input Interrupt
int_mask_ps_stat_change_int 0 0x01 Mask for Power Supply Status Change Interrupt

asserting the interrupt outputs.At POR all interrupts corresponding to Status1 register are masked.
R/W: RW
POR: 0x00ff
int_mask_msg_rcvd_and_available_i
7 0x01 Mask for Message Received and Available Interrupt
nt
int_mask_soft_rst_rcvd_int 6 0x01 Mask for Soft Reset Received Interrupt
int_mask_hard_reset_rcvd_int 5 0x01 Mask for Hard Reset Received Interrupt
int_mask_cable_reset_rcvd_int 4 0x01 Mask for Cable Reset Received Interrupt
int_mask_other_reset_rcvd_int 3 0x01 Mask for other_reset_rcvd_int
int_mask_tx_done_int 2 0x01 Mask for Message Tx Done Interrupt
int_mask_msg_rcvd_int 1 0x01 Mask for Message Received Interrupt
int_mask_cc1_stable_int 0 0x01 Mask for CC1 Pin Stable Interrupt
28

asserting the interrupt outputs.At POR we are unmasking the folloiwng interrupt: Bit 0: por_complete
R/W: RW
POR: 0x0006
int_mask_vconn_fault_fcl_int 2 0x01 Mask for Vconn FCL Fault Interrupt
int_mask_vconn_fault_rcp_int 1 0x01 Mask for Vconn RCP Fault Interrupt
Mask for PMU POR Complete Interrupt. At POR the por_complete
int_mask_por_complete 0 0x00
interrupt is the only interrupt set to automatically

int_control Block Register Definition ‐ Register int_rd_ahead_rsvd0 (Offset: 0x0006)
Description: Reserved
R/W: RO
POR: 0x0000

int_control Block Register Definition ‐ Register int_rd_ahead_rsvd1 (Offset: 0x0007)
Description: Reserved
R/W: RO
POR: 0x0000

int_control Block Register Definition ‐ Register int_status0 (Offset: 0x0008)
29
Description: Interrupt Status RegisterWhen set the corresponding interrupt is asserted. To clear the interrupt write a '1' to
the corresponding bit. If auto‐control is set for the specific interrupt it shall be automatically cleared when this register is
read.Bit 7: cc2_stable_intBit 6: cc_cursns_stable_intBit 5: typec_role_change_intBit 4: typec_orient_found_intBit 3:
typec_debug_foundBit 2: typec_detach_intBit 1: GPIO Interrupt (OR of all GPIOs)Bit 0: ps_stat_change_int (Or of all Power
Suppply Status Sub‐Interrupts)
R/W: RWO
POR: 0x0000
cc2_stable_int_stat 7 0x00 CC2 Pin Stable
cc_cursns_stable_int_stat 6 0x00 CC Current Sense Stable
typec_role_change_int_stat 5 0x00 Type C Role Change Indication
typec_orient_found_int_stat 4 0x00 Type C Orient Found Indication
typec_debug_found_stat 3 0x00 Type C Debug Accessory Found
typec_detach_int_stat 2 0x00 Type C Detach Indication
gpio_int_stat 1 0x00 GPIO Input Interrupt (OR of all GPIOs)
Power Supply Status Change (Or of all Power Suppply Status
Sub‐Interrupts)
vbus_present ‐ Interrupt asserted whenever vbus_present status
changes
vsys_present ‐ Interrupt asserted whenever vsys_present status
changes
vbus_eq_vsafe0v ‐ Interrupt asserted whenever vbus_eq_vsafe0v
ps_stat_change_int_stat 0 0x00
status is asserted (rising edge). This is meant to be used to
detect that Vbus discharge is complete.
vbus_eq_vsave5v ‐ Interrupt asserted whenever vbus_eq_vsafe5v
status changes. Usually used when first driving Vbus after a
connection to detect Vbus rising to VSafe5v (rising edge). But
may also be used when vbus is being discharged to detect
when Vbus has fallen back below VSafe5V (falling edge).

int_control Block Register Definition ‐ Register int_status1 (Offset: 0x0009)
read.Bit 7: msg_rcvd_and_availableBit 6: soft_rst_rcvdBit 5: hard_reset_rcvdBit 4: cable_reset_rcvdBit 3:
other_reset_rcvdBit 2: tx_doneBit 1: msg_rcvdBit 0: cc1_stable_int
R/W: RWO
POR: 0x0000
msg_rcvd_and_available_int_stat 7 0x00 USB PD Protocol Layer ‐ Message Received and Available
soft_rst_rcvd_int_stat 6 0x00 USB PD Protocol Layer ‐ Soft Reset Received
hard_reset_rcvd_int_stat 5 0x00 USB PD Protocol Layer ‐ Hard Reset Received
30
read.Bit 7: msg_rcvd_and_availableBit 6: soft_rst_rcvdBit 5: hard_reset_rcvdBit 4: cable_reset_rcvdBit 3:
other_reset_rcvdBit 2: tx_doneBit 1: msg_rcvdBit 0: cc1_stable_int
R/W: RWO
POR: 0x0000
cable_reset_rcvd_int_stat 4 0x00 USB PD Protocol Layer ‐ Cable Reset Received
USB PD Protocol Layer ‐ Other type of Hard/Cable Reset Received. This
other_reset_rcvd_int_stat 3 0x00 allows for new unforseen types of USB PD Reset signaling to be
detected.
tx_done_int_stat 2 0x00 USB PD Protocol Layer ‐ Message Tx Done
msg_rcvd_int_stat 1 0x00 USB PD PHY Layer ‐ Message Received.
cc1_stable_int_stat 0 0x00 CC1 Pin Stable

int_control Block Register Definition ‐ Register int_status2 (Offset: 0x000A)
Description: Interrupt Status RegisterBits 7:3: ReservedBit 2: vconn_fault_fcl_intBit 1: vconn_fault_rcp_intBit 0:
por_complete
R/W: RWO
POR: 0x0000
vconn_fault_fcl_int_stat 2 0x00 Vconn FCL Fault Interrupt
vconn_fault_rcp_int_stat 1 0x00 Vconn RCP Fault Interrupt
por_complete_int_stat 0 0x00 PMU POR Complete Interrupt

int_control Block Register Definition ‐ Register int_edge0 (Offset: 0x000B)
Description: Interrupt Edge Detection control registerWhen set the interrupt is Edge Triggered. When Clear the interrupt is
level sensitive.At POR all interrupts corresponding to Status0 are edge sensitive.
R/W: RW
POR: 0x00ff
int_edge_cc2_stable_int 7 0x01 Edge Control for CC2 Pin Stable Interrupt
int_edge_cc_cursns_stable_int 6 0x01 Edge Control for CC Current Sense Stable Interrupt
int_edge_typec_role_change_int 5 0x01 Edge Control for Type C Role Change Interrupt
31
R/W: RW
POR: 0x00ff
int_edge_typec_orient_found_int 4 0x01 Edge Control for Type C Orient Found Interrupt
int_edge_typec_debug_found 3 0x01 Edge Control for Type C Debug Accessory Found Interrupt
int_edge_typec_detach_int 2 0x01 Edge Control for Type C Detach Interrupt
int_edge_gpio_int 1 0x01 Edge Control for GPIO Input Interrupt
int_edge_ps_stat_change_int 0 0x01 Edge Control for Power Supply Status Change Interrupt

int_control Block Register Definition ‐ Register int_edge1 (Offset: 0x000C)
R/W: RW
POR: 0x00ff
int_edge_msg_rcvd_and_available_i
7 0x01 Edge Control for Message Received and Available Interrupt
nt
int_edge_soft_rst_rcvd_int 6 0x01 Edge Control for Soft Reset Received Interrupt
int_edge_hard_reset_rcvd_int 5 0x01 Edge Control for Hard Reset Received Interrupt
int_edge_cable_reset_rcvd_int 4 0x01 Edge Control for Cable Reset Received Interrupt
int_edge_other_reset_rcvd_int 3 0x01 Edge Control for other_reset_rcvd_int
int_edge_tx_done_int 2 0x01 Edge Control for Message Tx Done Interrupt
int_edge_msg_rcvd_int 1 0x01 Edge Control for Message Received Interrupt
int_edge_cc1_stable_int 0 0x01 Edge Control for CC1 Pin Stable Interrupt

int_control Block Register Definition ‐ Register int_edge2 (Offset: 0x000D)
R/W: RW
POR: 0x0007
32
R/W: RW
POR: 0x0007
int_edge_vconn_fault_fcl_int 2 0x01 Edge Control for Vconn FCL Fault Interrupt
int_edge_vconn_fault_rcp_int 1 0x01 Edge Control for Vconn RCP Fault Interrupt
Edge Control for PMU POR Complete Interrupt. At POR the
int_edge_por_complete 0 0x01
por_complete interrupt is the only interrupt set to automatically

int_control Block Register Definition ‐ Register int_manual0 (Offset: 0x000E)
Description: Interrupt Manual Assertion control registerWhen set the interrupt may be asserted by writing a '1' to the
interrupt status register for the corresponding interrupt bit.
R/W: RW
POR: 0x0000
Interrupt Manual Assertion control register

int_manual0 7:0 0x00
When set the interrupt may be asserted by writing a '1' to the interrupt
status register for the corresponding interrupt bit.

int_control Block Register Definition ‐ Register int_manual1 (Offset: 0x000F)
Description: Interrupt Manual Assertion control registerWhen set the interrupt may be asserted by writing a '1' to the
interrupt status register for the corresponding interrupt bit.
R/W: RW
POR: 0x0000


int_control Block Register Definition ‐ Register int_manual2 (Offset: 0x0010)
Description: Interrupt Manual Assertion control register
R/W: RW
POR: 0x0000

33

int_control Block Register Definition ‐ Register int_src_clkon (Offset: 0x0011)
Description: Interrupt Source Clock Enable control registerWhen set the corresponding interrupt will enable the system
clock when asserted.
R/W: RW
POR: 0x0000
Interrupt Source Clock Enable control register
int_src_clkon 0 0x00
When set the any interrupt will enable the system clock when asserted.

int_control Block Register Definition ‐ Register int_polarity0 (Offset: 0x0012)
Description: Interrupt Polarity control registerWhen set the interrupt is active high, when clear the interrupt is active low.
R/W: RW
POR: 0x00ff
int_pol_cc2_stable_int 7 0x01 Polarity Control for CC2 Pin Stable Interrupt
int_pol_cc_cursns_stable_int 6 0x01 Polarity Control for CC Current Sense Stable Interrupt
int_pol_typec_role_change_int 5 0x01 Polarity Control for Type C Role Change Interrupt
int_pol_typec_orient_found_int 4 0x01 Polarity Control for Type C Orient Found Interrupt
int_pol_typec_debug_found 3 0x01 Polarity Control for Type C Debug Accessory Found Interrupt
int_pol_typec_detach_int 2 0x01 Polarity Control for Type C Detach Interrupt
int_pol_gpio_int 1 0x01 Polarity Control for GPIO Input Interrupt
int_pol_ps_stat_change_int 0 0x01 Polarity Control for Power Supply Status Change Interrupt

R/W: RW
POR: 0x00ff
int_pol_msg_rcvd_and_available_int 7 0x01 Polarity Control for Message Received and Available Interrupt
int_pol_soft_rst_rcvd_int 6 0x01 Polarity Control for Soft Reset Received Interrupt
34
R/W: RW
POR: 0x00ff
int_pol_hard_reset_rcvd_int 5 0x01 Polarity Control for Hard Reset Received Interrupt
int_pol_cable_reset_rcvd_int 4 0x01 Polarity Control for Cable Reset Received Interrupt
int_pol_other_reset_rcvd_int 3 0x01 Polarity Control for other_reset_rcvd_int
int_pol_tx_done_int 2 0x01 Polarity Control for Message Tx Done Interrupt
int_pol_msg_rcvd_int 1 0x01 Polarity Control for Message Received Interrupt
int_pol_cc1_stable_int 0 0x01 Polarity Control for CC1 Pin Stable Interrupt

R/W: RW
POR: 0x0007
int_pol_vconn_fault_fcl_int 2 0x01 Polarity Control for Vconn FCL Fault Interrupt
int_pol_vconn_fault_rcp_int 1 0x01 Polarity Control for Vconn RCP Fault Interrupt
Polarity Control for PMU POR Complete Interrupt. At POR the
int_pol_por_complete 0 0x01
por_complete interrupt is the only interrupt set to automatically

int_control Block Register Definition ‐ Register int_out_polarity_hi (Offset: 0x0015)
Description: Interrupt Output Polarity control registerWhen set the output will be active high, when clear the interrupt
outputs are active low.
R/W: RW
POR: 0x0000
int_pin_polarity 1 0x00 The polarity for the primary interrupt output.
unused 0 0x00 Reserved

35

pmu Block Register Definition ‐ Register pmu_reset_ctrl (Offset: 0x0040)
Description: PMU reset control
R/W: RW
POR: 0x0000
sys_sw_rst 1 0x00 When '1', forces and asserts the reset to blocks getting sys_clk
Used to reset the Protocol and Digital PHY Layers.

PHY ‐ When '1', forces and asserts the reset to Serializer inside
Digital‐PHY‐TX block (which uses the phytx_gated_clk).
phy_prot_sw_rst 0 0x00
Protocol ‐ Used as a global reset. The Protocol layer is asynchronously
reset by a POR event or by S/W assertion (setting to '1') of this register
bit.

pmu Block Register Definition ‐ Register pmu_clk_ctrl0 (Offset: 0x0041)
Description: PMU clock control0
R/W: RW
POR: 0x0000
When '1', forces the dig_phy_fastclk to be ungated but will not start
dig_phy_fastclk_ungate 5 0x00
oscillator
When '1', forces the typec_2mhz_clk to be ungated but will not start
typec_2mhz_clk_ungate 4 0x00
oscillator
typec_clk_ungate 3 0x00 When '1', forces the typec_clk to be ungated but will not start oscillator
mtp_clk_ungate 2 0x00 When '1', forces the mtp_clk to be ungated but will not start oscillator
sys_clk_ungate 1 0x00 When '1', forces the sys_clk to be ungated but will not start oscillator
When '1', forces the dig_phy_prot_clk to be ungated but will not start
force_dig_phy_prot_clk_ungate 0 0x00
oscillator

36
pmu Block Register Definition ‐ Register pmu_lowpower (Offset: 0x0042)
Description: Enable Gating for low power
R/W: RW
POR: 0x0002
PMU Hibernate Mode

Default value 1. That keeps the FROâ€™s core always powered down
when not needed to conserve power when in autonomous mode in
disconnected state.

When set to 1, the hardware can powerdown the core of the FRO if
there is no block that needs a clock. When set to 0, the FRO is kept
powered up for fastest response time.

digosc_powerdown_if_idle 1 0x01
Set this bit to let Victoria be in deep‐low‐power‐mode. Regarding this
deep‐low‐power‐mode

‐ NOTE1: NO clock in the system, so even the external timers are off.
(I2C responds to incoming messages using SCL, so itâ€™s still awake.)
‐ NOTE2: StartÂ¬up time can get up to 50us. Typically a trimmed FRO
will be up within ~15us.
‐ NOTE3: Serial interfaces (SPI and I2C accesses) will create async_wake
pulse, and in turn remove clock gating on clocks.

PMU Sleep Mode Enable

Default value 0. That keeps the FROâ€™s output stage always ungated.

When set to 1, the hardware can gate the output buffer of the FRO, if
there is no block that needs a clock.

Processor will set this bit to let Victoria be in low‐power‐mode.
digosc_standby_if_idle 0 0x00
Regarding this low‐power‐mode :

‐ NOTE1: NO clock in the system, so even the external timers are off.
(I2C responds to incoming messages using SCL, so itâ€™s still awake.)
‐ NOTE2: StartÂ¬up time is only one clock.
‐ NOTE3: Serial interfaces (SPI and I2C accesses) will create async_wake
pulse, and in turn remove clock gating on clocks.

pmu Block Register Definition ‐ Register pmu_status (Offset: 0x0048)
Description: PMU Status Register
R/W: RO
POR: 0x0000
37
Description: PMU Status Register
R/W: RO
POR: 0x0000
When set the POR process has completed and the device is ready for
por_complete 0 0x00
operation

pmu Block Register Definition ‐ Register i2c_clock_control_reg (Offset: 0x0049)
Description: Control I2C clock
R/W: RW
POR: 0x0000
Setting this bit will disable the hardware function which stretches the
sw_dis_clk_stretch 1 0x00
SCL while waiting for the system oscillator to startup.
Selects between the two available sources for starting the system clock
when accessing via I2C.
sw_use_start_i2c 0 0x00
1: Enable the clock when a start is detected
0: Enable the clock when a valid slave address is received

pmu Block Register Definition ‐ Register rev_id (Offset: 0x004A)
Description: Tahoe silicon's revision ID register
R/W: RO
POR: 0x00a0
rev_id_base_layer 7:4 0x0a Upper 4 bits describe the Base layer. Tie this 4 bits to 4'hA
Lower 4 bits describe the metal layer. These 4 signals will be strapped
rev_id_metal_layer 3:0 0x00
to TIE_LOW cells

38

protocol_layer Block Register Definition ‐ Register sw_prot_rst_stat_ctrl (Offset: 0x0100)
Description: USB PD Protocol Layer Reset and Control Register
R/W: RW
POR: 0x0010
Allowed Hard Resets On Reception

Bit 0 => If this bit is 1 then Hard Reset Reception is enabled. Otherwise
it is disabled.
Bit 1 => If this bit is 1 then Cable Reset Reception is enabled. Otherwise
it is disabled.
Bit 2 => If this bit is 1 then RSVD Reset 2 is enabled. Otherwise it is
allowed_hrsts_on_rx 7:4 0x01
disabled.
Bit 3 => If this bit is 1 then RSVD Reset 3 is enabled. Otherwise it is
disabled.

Note: The protocol layer does not use this. It is just passed through to
the PHY layer.

sw_send_hard_reset 3 0x00 When high this tells the Protocol Layer to send a Hard Reset.
This tells the Protocol Layer which type of Hard Reset to send. This
information is passed to the Protocol Layer as well as being used to
manage the Message ID Counters.

sw_hard_reset_type 2:1 0x00 ''00'' => Hard Reset
''01'' => Cable Reset
''10'' => HR_RSVD2
''11'' => HR_RSVD3

Enable USB PD Protocol Layer Message Reception

0 => Disable message reception in USB PD Protocol layer. Incoming
sw_usbpd_protocol_enable_message
0 0x00 messages will be ignored. Hard Resets reception will still be handled.
rx
This is used when the Policy Layer enters its Source Disabled state,
during which Tahoe should ignore all incoming messages but should still
handle incoming Hard Resets.
39
R/W: RW
POR: 0x0010
1 => Enable message reception. This is normal operation.

protocol_layer Block Register Definition ‐ Register sw_usbpd_prot_pwrswap_reset (Offset: 0x0101)
R/W: RW
POR: 0x0001
Protocol Layer Power Role Swap Reset

This register allows S/W to reset the USB PD Protocol Layer after a
power role swap.

Any bits asserted creates an internal sw_usbpd_pwrswap_rst_n signal
in the Protocol Layer which resets all state machines, pending message
transmission, pending message reception (including ceasing to disable
incoming messages due to pending received message). This reset is a
single clock cycle wide (uses write notify).

The only things in the Protocol Layer which aren't globally reset by this
internal reset are the Tx Message ID counters, the Stored Rx Message ID
sw_usbpd_prot_pwrswap_reset 7:0 0x01 Counters, and the Rx ''First Message ID'' status.

The specific bit(s) asserted tells the design which message ID's to clear.
The POR is 0x01 meaning only clear Message ID [SOP], Stored Message
ID [SOP], first_id[SOP]
Bit 0 => SOP
Bit 1 => SOP'
Bit 2 => SOP''
Bit 3 => SOP' Debug
Bit 4 => SOP'' Debug
Bit 5 => SOP RSVD 5
Bit 6 => SOP RSVD 6
Bit 7 => SOP RSVD 7

protocol_layer Block Register Definition ‐ Register sw_prot_status_0 (Offset: 0x0102)
Description: USB PD Protocol Layer Status Register
R/W: RO
POR: 0x0000
Asserted by USB PD Protocol layer to tell S/W when S/W initiated Hard
usb_pd_hard_reset_sent 0 0x00 Reset has completed. This means the Hard Reset has been sent on
Vbus.
40

protocol_layer Block Register Definition ‐ Register sw_pd_info_0 (Offset: 0x0103)
Description: USB PD Information for Message Transmission
R/W: RW
POR: 0x001b
This tells the Protocol Layer the retry count to use when transmitting
messages. Normally S/W does not need to alter this. The POR is 3 to
match USB PD spec. If in cable application where retries are not
permitted, this may be changed to 0.

The committee just changed the value to 3. But were other discussions
to increase it further to avoid some collision issues after connection. To
allow for last second changes we'll increase this to a 4 bit counter to
allow up to 14 retries. The all 1's setting allows for infinite retries.
sw_usbpd_tx_retrycnt 6:3 0x03

0 => No Retries (Cable Application)
2 => 2 Retries. Current value for USB PD Spec Rev 2.0 Version 1.0
3 => 3 Retries. Expected upcoming change in USB PD Spec
4‐14 => 4‐14 Retries. Available to handle last second USB PD Spec
changes.
15 => Infinite Retries. Not sure if they would ever select this. But saw
hints in some of the presentations.

Used in USB PD Message Transmission. This needs to be sent with in the
Message Header.

0 => Rev 1.0
sw_our_spec_rev 2:1 0x01
1 => Rev 2.0
2 => Rsvd
3 => Rsvd

This tells the Protocol Layer what port role bit to use when sending
GoodCRC messages.

'0' => Don't use S/W's port role information. Instead use the inverse of
whatever was just received in the incoming message. For example, if
use_sw_port_role_in_good_crc 0 0x01
the incoming message had a port role of source then our outgoing
GoodCRC will have a port role of sink.
'1' => Use S/W's port role bit (sw_our_port_role) when sending
GoodCRC messages.

R/W: RW
POR: 0x0000
Used in USB PD Message Transmission. This needs to be sent with the
sw_our_port_role 7:0 0x00 Message Header. Each bit corresponds to a different SOP type. The
Protocol Layer uses whichever bit corresponds to the SOP type of the
41
R/W: RW
POR: 0x0000
current outgoing message.

For SOP type messages this corresponds to our current Power Role. A
'1' means Source and a '0' means Sink.

For SOP' and SOP'' type messages this corresponds to Cable Plug Info. A
'1' means that the message originated from the Cable Plug. A '0' means
that the message originated from the DFP or UFP.

For other SOP types this bit has no meaning.

Bit 7 => Rsvd. POR=0
Bit 4 => SOP'' Debug Type. POR=0
Bit 3 => SOP' Debug Type. POR=0
Bit 2 => SOP'' Type. POR=0 (DFP/UFP)
Bit 1 => SOP' Type. POR=0 (DFP/UFP)
Bit 0 => SOP Type. POR=0 (Sink).

R/W: RW
POR: 0x0000
Message Header. Each bit corresponds to a different SOP type. The
Protocol Layer uses whichever bit corresponds to the SOP type of the
current outgoing message.

For SOP type messages this corresponds to our current Data Role. A '1'
means DFP and a '0' means UFP.

For other SOP types this bit has no meaning and must be '0'
sw_our_data_role 7:0 0x00
Bit 4 => SOP'' Debug Type. POR=0
Bit 3 => SOP' Debug Type. POR=0
Bit 2 => SOP'' Type. POR=0.
Bit 1 => SOP' Type. POR=0.
Bit 0 => SOP Type. POR=0 (UFP).

42
protocol_layer Block Register Definition ‐ Register sw_usbpd_tx_pkt_ctrl_0 (Offset: 0x0106)
Description: USB PD Protocol Layer Tx Packet Control Register
R/W: RW
POR: 0x0000
Used in USB PD Message Transmission. This requests the protocol layer
sw_usbpd_tx_req 7 0x00 to send a USB PD Message defined by the other necessary fields. The
H/W uses the rising edge of this signal as a request indication.
sw_usbpd_msg_type 6:3 0x00 Message Header. This tells us what type of message is being sent. Refer
to USB PD Spec for more information.
Used in USB PD Message Transmission. This tells us how many 32 bit
sw_num_tx_pktdata_words 2:0 0x00
words after the Header will be sent in the current message.

protocol_layer Block Register Definition ‐ Register sw_usbpd_tx_pkt_ctrl_1 (Offset: 0x0107)
R/W: RW
POR: 0x0000
Enable GoodCRC SOP Checking

Normally when a message is sent and a GoodCRC is received, only the
Message ID is checked. If the output message ID matches the incoming
one in the GoodCRC message then message transmission is considered
successful and S/W is alerted with tx_done interrupt. This is what is
specified in the USB PD Spec. If the message IDs do not match then
S/W is alerted that an error occured (tx_done=1 and tx_error=1).

This bit allows S/W to tell H/W to also check the GoodCRC's SOP type
and make sure that matches the one used to transmit the previous
message. Therefore both the Message ID and SOP type of the outgoing
message and incoming GoodCRC message must match.
sw_en_goodcrc_sop_check 7 0x00
0 => (Default) Only consider Message ID when determining the success
of message transmission.
1 => Consider Message ID and SOP type when determining the success
of message transmission.

Note that there may be very good reason to keep the default setting
besides being compliant to the USB PD Spec. Retrying a message based
on SOP type mismatch may mean that we'll send the same message to
two different SOP types. If we don't check SOP in H/W then
mismatching SOP may result in H/W not retrying the message and
instead leaving it up to S/W. It may be better to leave the decision at a
higher level than H/W.

This tells the Protocol Layer which SOP to use when sending the current
message. This information is passed to the PHY as well as being used to
help manage the Message ID counters. This value should remain
constant during the entire duration of the message transmission. In
other words, it should only be changed right before asserting
sw_tx_sop 6:4 0x00
sw_tx_req.

0 => Send SOP
1 => Send SOP'
2 => Send SOP''
43
R/W: RW
POR: 0x0000
3 => Send SOP' Debug
4 => Send SOP'' Debug
5 => Send SOP_RSVD5
6 => Send SOP_ RSVD6
7 => Send SOP_ RSVD7

Forced Increment of Transmission Message ID

This allows S/W to force the protocol layer to increment the Message ID
for outgoing messages. If used this must be done while there are no
pending message transmissions.

'0' => POR value. When writing to this register this is normal value to
write to this bit if S/W does not wish to force the Protocol Layer to
increment the Message ID counter.
inc_msg_id 3 0x00

'1' => S/W writes a '1' to this bit if they wish to force the Protocol Layer
to increment the Message ID Counter. The H/W uses the write notify
feature so that it incrments the Message ID counter a single time with
each write to this register with the bit being high. Since H/W does use
the write notify feature, S/W does not have to explicitly write this bit to
'0' later. The next time S/W writes this register it can have this bit as a
'0'.

Always Increment Message ID Upon CRC Retry Timeout

Normally if a message is tried for the maximum number of retries
without receiving a valid GoodCRC in return then the message is
aborted by the protocol layer and the Message ID is not incremented.
But this bit allows F/W to alter the normal behavior.

'0' => Default value. Protocol Layer will not increment the Message ID
msg_tx_always_inc_msgid 2 0x00 counter if a message fails to transmit successfully for the maximum CRC
retry count. This matches the current USB PD Spec and the compliance
spec. But there may be changes in future revisions that require this
behavior to be different.

'1' => Protocol Layer will always increment the Message ID counter
after a message fails to transmit successfully for the maximum CRC
retry count.

Used in USB PD Message Transmission. When high this tells the H/W
sw_wr_msg_buf_done 1 0x00
that S/W had finished writing the payload data to the Message Buffer.
Used in USB PD Message Transmission. This requests the Protocol layer
sw_abort_tx 0 0x00
to abort the message transmission.

44
protocol_layer Block Register Definition ‐ Register sw_pd_msg_hdr_rsvd (Offset: 0x0108)
Description: USB PD Information for Message Transmission ‐ Reserved bits in Msg header
R/W: RW
POR: 0x0000
Bit 15 of USB PD Message Header is Reserved in USB PD Rev 0.5. This
sw_pd_msg_hdr_rsvd_15_tx 3 0x00
allows S/W to change it for message transmission initiated by S/W
sw_pd_msg_hdr_rsvd_15_rx 2 0x00 allows S/W to change it for message transmission initiated by the
Protocol Layer (Good CRC and Return Error Count Messaages).
sw_pd_msg_hdr_rsvd_4_tx 1 0x00
allows S/W to change it for message transmission initiated by S/W
sw_pd_msg_hdr_rsvd_4_rx 0 0x00 allows S/W to change it for message transmission initiated by the
Protocol Layer (Good CRC and Return Error Count Messaages).

protocol_layer Block Register Definition ‐ Register sw_usbpd_tx_pkt_stat (Offset: 0x010B)
Description: USB PD Protocol Layer Tx Packet Status Register
R/W: RO
POR: 0x0000
Used in USB PD Message Transmission. If '1' then there was an error in
usbpd_tx_error 1 0x00
Message Transmission.
Used in USB PD Message Transmission. Tells S/W that it may now write
enable_sw_msg_buf_wr 0 0x00
the payload data for the USB PD Message into the Message Buffer.

protocol_layer Block Register Definition ‐ Register sw_usbpd_rx_pkt_ctrl_0 (Offset: 0x010C)
Description: USB PD Protocol Layer Rx Packet Control Register
R/W: RW
POR: 0x0010
Message Transmission Discard Control

When '1' this tells the Protocol Layer to discard an outgoing message
when a message is received only if the SOP types of both messages
match. This matches the USB PD Spec definition.
sop_en_specific_sop_discard 4 0x01
When '0' this tells the Protocol layer to discard an outgoing message
when a message is received no matter the types of the Tx or Rx
messages. This is more like Tahoe behavior but does not match the
current USB PD Spec. This is only a backup option.

45
R/W: RW
POR: 0x0010
Controls H/W transmission of GoodCRC upon reception of a USB PD
Message.
‐ 00 => USB PD (Automatic transmission of GoodCRC upon message
reception),
‐ 01 => Wait for S/W before transmitting GoodCRC message.
‐ 10 => Reserved
‐ 11 => Don't Send GoodCRC
The default mode is '''0''' such that H/W sends the GoodCRC message
automatically upon message reception.

A special mode is introduced for other applications which allows S/W to
intervene and control H/W transmission of the GoodCRC.

‐ To hold off CRC transmission S/W sets usb_pd_goodcrc_mode = 01
(Wait for S/W). After processing an incoming messages S/W will either
tell H/W to 1) Send the GoodCRC, or 2) abort and do not send GoodCRC
message. In either case H/W will return to its ready state. In order to
sw_usbpd_goodcrc_mode 3:2 0x00 tell the H/W to send the GoodCRC message, S/W temporarily sets
usb_pd_goodcrc_mode back to 00 (Send CRC Immediately) and then
back to 01. In order to tell the H/W to abort transmission of GoodCRC
S/W temporarily sets usb_pd_goodcrc_mode to 11 (Don't Send CRC)
and then back to 01.

‐ To force H/W to never transmit GoodCRC messages, S/W can set
usb_pd_goodcrc_mode to '''11''' (Don't Send CRC). In this case H/W will
always abort GoodCRC transmission upon message reception.

Note that this bitfield does not affect how H/W asserts the
msg_rcvd_and_available interrupt if the settings are '''USB PD''' or
'''Don't Send GoodCRC'''. For '''Wait for S/W''' the design will assert the
interrupt upon reception of Soft Reset Message and incoming messages
with Message ID value matching our current stored value (i.e., duplicate
message which S/W doesn't normally need to see). Normally these last
two conditions do not result in assertion of the interrupt.

Used in USB PD Message Reception. When high this tells the H/W that
S/W has completed reading the payload data for the just received USB
PD Message from the Message Buffer.

sw_en_2rx_msgbuf = 0

In this case the Message Buffer only contains a single Rx Buffer, buffer
0. Sw_rd_msgbuf_1_done is not used in this case.

sw_rd_msgbuf_1_done 1 0x00 sw_en_2rx_msgbuf = 1

In this case the Message Buffer contains two Rx Buffers, buffer 0 and 1.
sw_rd_msgbuf_1_done corresponds to messages in buffer 1, which are
SOP prime messages (SOP', SOP'', SOP' Debug, SOP'' Debug, etc. . .).
S/W asserts sw_rd_msgbuf_1_done anytime it finishes reading the
payload data for the just received SOP ''Prime'' Message. SOP ''Prime''
Message reception and transmission is suspended until S/W asserts this
bit.

Used in USB PD Message Reception. When high this tells the H/W that
sw_rd_msgbuf_0_done 0 0x00 S/W has completed reading the payload data for the just received USB
PD Message from the Message Buffer.
46
R/W: RW
POR: 0x0010


In this case the Message Buffer only contains a single Rx Buffer, buffer
0. So S/W asserts sw_rd_msgbuf_0_done anytime it finishes reading the
payload data for the just received Message. Message reception and
transmission for all message types is suspended until S/W asserts this
bit.


In this case the Message Buffer contains two Rx Buffers, buffer 0 and 1.
sw_rd_msgbuf_0_done corresponds to messages in buffer 0, which are
SOP messages. S/W asserts sw_rd_msgbuf_0_done anytime it finishes
reading the payload data for the just received SOP Message. SOP
Message reception and transmission is suspended until S/W asserts this
bit.

protocol_layer Block Register Definition ‐ Register sw_usbpd_rx_pkt_ctrl_1 (Offset: 0x010D)
R/W: RW
POR: 0x0001
This identifies which SOPs are allowed to be received. A '1' in a bit
means that the corresponding SOP is allowed to be received and a
GoodCRC will be returned. A '0' in a bit means that the corresponding
SOP should be ignored and GoodCRC not returned.

Bit 0 => Corresponds to SOP
Bit 1 => Corresponds to SOP'
Bit 2 => Corresponds to SOP''
Bit 3 => Corresponds to SOP'‐debug
Bit 4 => Corresponds to SOP''‐debug
Bit 5 => Corresponds to SOP_RSVD5
allowed_sops_on_rx 7:0 0x01

Note: If S/W disables a particular SOP type after the reception of that
packet has already begun, then the remainder of the packet will be
received and S/W interrupted.

Note: The protocol layer does not use this input. It just passes it
through to the PHY. It was partitioned this way because S/W interfaces
to the protocol layer for message transmission and reception.

47
protocol_layer Block Register Definition ‐ Register sw_usbpd_rx_pkt_ctrl_2 (Offset: 0x010E)
R/W: RW
POR: 0x0001
This tells the Protocol Layer if the Message Buffer has one or two Rx
Buffers. If only one then all incoming messages are stored there. If
there are two buffers then SOP messages go in the first buffer and SOP
prime (SOP', SOP'', SOP'Debuf, SOP'' Debug, etc..) go into the second
buffer.
sw_en_2rx_msgbuf 0 0x01

0 => Only a single Rx Buffer is available in the message buffer
1 => Two Rx Buffers are available in the message buffer.

protocol_layer Block Register Definition ‐ Register sw_usbpd_pend_rx_msg_global_stat (Offset: 0x010F)
Description: USB PD Protocol Layer Pending Rx Message Status
R/W: RO
POR: 0x0000
This tells S/W that the incoming message for which
msg_rcvd_and_available was asserted was for a stale message. The
Message ID for this message matches that of the previous message
usb_pd_stale_rx_rcvd 2 0x00 received. Normally the msg_rcvd_and_available interrupt would not be
asserted in these cases. This is only true if sw_usbpd_goodcrc_mode is
set to ''Wait for S/W''. In this case the H/W must alert S/W.

Used in USB PD Message Reception. This tells S/W which Rx Message
Buffer has a pending Rx message.

sw_en_2rx_msgbuf=0

In this case there is only a single Rx Message Buffer. Therefore S/W
doesn't need to look at the status of usb_pd_rx_pend_msg.

sw_en_2rx_msgbuf=0

usb_pd_rx_pend_msg 1:0 0x00 In this case there are two Rx Message Buffers. S/W can look at each bit
to determine when each Rx Message Buffer has an available message.

Bit 0 => Rx Message Buffer 0. Buffer 0 contains all incoming SOP
messages. If this bit is set then there is an available SOP message in
buffer 0.

Bit 1 => Rx Message Buffer 1. Buffer 1 contains all incoming SOP
''prime'' messages. If this bit is set then there is an available SOP
''Prime'' message in buffer 1.

48

protocol_layer Block Register Definition ‐ Register sw_usbpd_rx0_pkt_stat_0 (Offset: 0x0110)
Description: USB PD Protocol Layer Rx Buf 0 Packet Status Register. This contains status for recently received message
stored in Rx Message Buffer 0.
R/W: RO
POR: 0x0000
Used in USB PD Message Reception. This tells S/W how many 32 bit
rx0_num_pktwords 6:4 0x00
words were received after the Message Header.
Used in USB PD Message Reception. These are the Message_Type bits
rx0_msg_type 3:0 0x00
from the received Message's Message Header.

R/W: RO
POR: 0x0000
Used in USB PD Message Reception. This tells S/W the SOP of the
rx0_sop 5:3 0x00
message currently available in Rx Message Buffer 0.
Used in USB PD Message Reception. This is the Port_Role bit from the
rx0_port_role 2 0x00
received Message's Message Header.
Used in USB PD Message Reception. These are the
rx0_spec_rev 1:0 0x00 Specification_Revision bits from the received Message's Message
Header.

R/W: RO
POR: 0x0000
Used in USB PD Message Reception. These are the MessageID bits from
rx0_msg_id 5:3 0x00
the received Message's Message Header.
Used in USB PD Message Reception. This is the reserved bit 15 from the
rx0_msg_hdr_rsvd_15 2 0x00
Used in USB PD Message Reception. This is the data role bitfield from
rx0_msg_hdr_data_role 1 0x00

49

R/W: RO
POR: 0x0000
Used in USB PD Message Reception. This tells S/W how many 32 bit
rx1_num_pktwords 6:4 0x00
words were received after the Message Header.
Used in USB PD Message Reception. These are the Message_Type bits
rx1_msg_type 3:0 0x00
from the received Message's Message Header.

R/W: RO
POR: 0x0000
Used in USB PD Message Reception. This tells S/W the SOP of the
rx1_sop 5:3 0x00
message currently available in Rx Message Buffer 1.
Used in USB PD Message Reception. This is the Port_Role bit from the
rx1_port_role 2 0x00
Used in USB PD Message Reception. These are the
rx1_spec_rev 1:0 0x00 Specification_Revision bits from the received Message's Message
Header.

R/W: RO
POR: 0x0000
Used in USB PD Message Reception. These are the MessageID bits from
rx1_msg_id 5:3 0x00
Used in USB PD Message Reception. This is the data role bitfield from
rx1_msg_hdr_data_role 1 0x00
50

protocol_layer Block Register Definition ‐ Register sw_bist_ctrl (Offset: 0x0116)
Description: USB PD BIST Transmission Control
R/W: RW
POR: 0x0000
Used during USB PD Bist Test Data Frame Reception. When high tells
the H/W to interrupt S/W upon reception of a BIST Test Data Frame
Message. When low tells H/W to not interrupt S/W. The normal
int_upon_bist_test_frame_rx 4 0x00
operation is to not tell S/W and ignore this message type. This is how
the USB PD Spec specifies the reception of this message type.

When high this requests the Protocol layer to perform a BIST command,
bist_req 3 0x00
defined by bist_cmd.
BIST Command for Protocol Layer to perform
‐ 000 => BIST Receive Mode. Receive one PRBS test frame.
‐ 001 => BIST Transmit Mode. Transmit one PRBS test frame.
‐ 010 => BIST Return Count (not used). This is automatically handled by
the H/W.
‐ 011 => BIST Carrier Mode 0. Transmit continuous 0's.
bist_cmd 2:0 0x00
‐ 100 => BIST Carrier Mode 1. Transmit continuous 1's.
‐ 101 => BIST Carrier Mode 2. Transmit alternating 1's and 0's.
‐ 110 => BIST Carrier Mode 3. Transmit continuous string of 16 1's
followed by 16 0's.
‐ 111 => BIST Eye Pattern. Transmit Continuous PRBS pattern.

protocol_layer Block Register Definition ‐ Register sw_rx_bist_errcnt_15_8 (Offset: 0x0117)
Description: USB PD Bist Error Count Bits 15:8Used in USB PD BIST Transmitter Mode. These bits are used when Tahoe is in
BIST Transmitter mode sending PRBS frames to the test equipment. After sending each PRBS frame the other side sends
back a BIST Test Message containing the Returned Error Count. These are those bits.Note: We save bits 15:0 from the
received BIST Data Object for all incoming BIST Test Messages. In the case of a returned error counter message bits 15:0
contain the returned error count. In other cases these bits are undefined. But they are still stored and can be retrieved
here.
R/W: RO
POR: 0x0000

Used in USB PD BIST Transmitter Mode. These bits are used when
Tahoe is in BIST Transmitter mode sending PRBS frames to the test
equipment. After sending each PRBS frame the other side sends back a
BIST Test Message containing the Returned Error Count. These are
sw_rx_bist_errcnt_15_8 7:0 0x00 those bits.

Note: We save bits 15:0 from the received BIST Data Object for all
incoming BIST Test Messages. In the case of a returned error counter
message bits 15:0 contain the returned error count. In other cases
these bits are undefined. But they are still stored and can be retrieved
here.
51
here.
R/W: RO
POR: 0x0000

protocol_layer Block Register Definition ‐ Register sw_rx_bist_errcnt_7_0 (Offset: 0x0118)
here.
R/W: RO
POR: 0x0000

Used in USB PD BIST Transmitter Mode. These bits are used when
Tahoe is in BIST Transmitter mode sending PRBS frames to the test
equipment. After sending each PRBS frame the other side sends back a
BIST Test Message containing the Returned Error Count. These are
those bits.
sw_rx_bist_errcnt_7_0 7:0 0x00

Note: We save bits 15:0 from the received BIST Data Object for all
incoming BIST Test Messages. In the case of a returned error counter
message bits 15:0 contain the returned error count. In other cases
these bits are undefined. But they are still stored and can be retrieved
here.

protocol_layer Block Register Definition ‐ Register sw_bist_stat_0 (Offset: 0x0119)
Description: USB PD Bist Message Status
R/W: RO
POR: 0x0000
Used in USB PD Message Reception. Whenever a BIST Test Message is
received, the Protocol layer retrieves the BIST Data object from the
usb_pd_rx_bist_type 3:0 0x00 Message Buffer. S/W may read it from the Message Buffer itself or just
read it from these register bits.

52

53
usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_buf_cfg (Offset: 0x0140)
Description: Message Buffer Configuration
R/W: RW
POR: 0x0000
If high, the message buffer will use the S/W header bytes. Otherwise it
will use the protocol layers header bytes (ctrl, header 0, header 1).
use_sw_header_info 0 0x00
The normal use is to have this bit stay at its POR value, '0'.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_0 (Offset: 0x0144)
Description: USB PD Message Tx Payload Data byte 0. First byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 0. First byte sent after Message
usbpd_msg_tx_buf_payload_0 7:0 0x00
Header.

Description: USB PD Message Tx Payload Data byte 1. 2nd byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 1. 2nd byte sent after Message
Header.

Description: USB PD Message Tx Payload Data byte 2. 3rd byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 2. 3rd byte sent after Message
Header.

54
Description: USB PD Message Tx Payload Data byte 3. 4th byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 3. 4th byte sent after Message
Header.

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_6 (Offset: 0x014A)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_7 (Offset: 0x014B)
R/W: RW
POR: 0x0000
Header.

55

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_8 (Offset: 0x014C)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_9 (Offset: 0x014D)
Description: USB PD Message Tx Payload Data byte 9. 1oth byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 9. 1oth byte sent after Message
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_10 (Offset: 0x014E)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_11 (Offset: 0x014F)
R/W: RW
POR: 0x0000
Header.

56
R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

57

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

R/W: RW
POR: 0x0000
Header.

Description: USB PD Message Tx Payload Data byte 20. 21st byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 20. 21st byte sent after Message
Header.

58
Description: USB PD Message Tx Payload Data byte 21. 22nd byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 21. 22nd byte sent after
Message Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_22 (Offset: 0x015A)
Description: USB PD Message Tx Payload Data byte 22. 23rd byte sent after Message Header.
R/W: RW
POR: 0x0000
USB PD Message Tx Payload Data byte 22. 23rd byte sent after Message
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_23 (Offset: 0x015B)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_24 (Offset: 0x015C)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_25 (Offset: 0x015D)
R/W: RW
POR: 0x0000
Header.

59

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_26 (Offset: 0x015E)
R/W: RW
POR: 0x0000
Header.

usb_tx_msg_buf Block Register Definition ‐ Register usbpd_msg_tx_buf_payload_27 (Offset: 0x015F)
R/W: RW
POR: 0x0000
Header.

60
usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_control (Offset: 0x0180)
Description: Not Used. This address is just reserved to allow Tx and Rx addresses in Message Buffer to be the same.
R/W: RO
POR: 0x0000
Not Used. This address is just reserved to allow Tx and Rx addresses in
usbpd_msg_rx_buf0_control 7:0 0x00
Message Buffer to be the same.

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_hdr_0 (Offset: 0x0181)
Description: USB PD Message Rx Buffer 0 Header bits [7:0]
R/W: RO
POR: 0x0000
usbpd_msg_rx_buf0_hdr_0 7:0 0x00 USB PD Message Rx Buffer 0 Header bits [7:0]

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_hdr_1 (Offset: 0x0182)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_0 (Offset: 0x0183)
Description: USB PD Message Rx Buffer 0 Payload Data byte 0. First byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 0 Payload Data byte 0. First byte received
usbpd_msg_rx_buf0_payload_0 7:0 0x00
after Message Header.

Description: USB PD Message Rx Buffer 0 Payload Data byte 1. 2nd byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 0 Payload Data byte 1. 2nd byte received

61

Description: USB PD Message Rx Buffer 0 Payload Data byte 2. 3rd byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 0 Payload Data byte 2. 3rd byte received

Description: USB PD Message Rx Buffer 0 Payload Data byte 3. 4th byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 0 Payload Data byte 3. 4th byte received

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

62
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_7 (Offset: 0x018A)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_8 (Offset: 0x018B)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_9 (Offset: 0x018C)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_10 (Offset: 0x018D)
R/W: RO
POR: 0x0000

63

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_11 (Offset: 0x018E)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_12 (Offset: 0x018F)
R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

64
R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

65

Description: USB PD Message Rx Buffer 0 Payload Data byte 20. 21st byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 0 Payload Data byte 20. 21st byte received

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_23 (Offset: 0x019A)
R/W: RO
POR: 0x0000

66
usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_24 (Offset: 0x019B)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_25 (Offset: 0x019C)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_26 (Offset: 0x019D)
R/W: RO
POR: 0x0000

usb_rx_msg_buf0 Block Register Definition ‐ Register usbpd_msg_rx_buf0_payload_27 (Offset: 0x019E)
R/W: RO
POR: 0x0000

67
usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_control (Offset: 0x01C0)
Description: Not Used. This address is just reserved to allow Tx and Rx addresses in Message Buffer to be the same.
R/W: RO
POR: 0x0000
Not Used. This address is just reserved to allow Tx and Rx addresses in
usbpd_msg_rx_buf1_control 7:0 0x00
Message Buffer to be the same.

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_hdr_0 (Offset: 0x01C1)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_hdr_1 (Offset: 0x01C2)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_0 (Offset: 0x01C3)
Description: USB PD Message Rx Buffer 1 Payload Data byte 0. First byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 1 Payload Data byte 0. First byte received

R/W: RO
POR: 0x0000

68

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

69
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_7 (Offset: 0x01CA)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_8 (Offset: 0x01CB)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_9 (Offset: 0x01CC)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_10 (Offset: 0x01CD)
R/W: RO
POR: 0x0000

70

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_11 (Offset: 0x01CE)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_12 (Offset: 0x01CF)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_13 (Offset: 0x01D0)
R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

71
R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

72

Description: USB PD Message Rx Buffer 1 Payload Data byte 20. 21st byte received after Message Header.
R/W: RO
POR: 0x0000
USB PD Message Rx Buffer 1 Payload Data byte 20. 21st byte received

R/W: RO
POR: 0x0000

R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_23 (Offset: 0x01DA)
R/W: RO
POR: 0x0000

73
usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_24 (Offset: 0x01DB)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_25 (Offset: 0x01DC)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_26 (Offset: 0x01DD)
R/W: RO
POR: 0x0000

usb_rx_msg_buf1 Block Register Definition ‐ Register usbpd_msg_rx_buf1_payload_27 (Offset: 0x01DE)
R/W: RO
POR: 0x0000

74

phy_layer Block Register Definition ‐ Register usbpd_phy_bist_ctrl (Offset: 0x0200)
Description: USB PD PHY Layer Data‐Rate and CLK‐Freq Config Register
R/W: RW
POR: 0x002c
All the data‐path related parameters inside the PHY will scale as per this
setting which tells PHY what's the data‐rate of the USBPD signaling it's
handling.
0x000 = 100Kbps+/‐10%
0x001 = 200Kbps+/‐10%
usbpd_data_rate 6:4 0x02 0x010 = 300Kbps+/‐10% (default)
0x011 = 350Kbps+/‐10%
0x100 = 400Kbps+/‐10%
0x101 = 500Kbps+/‐10%
0x110 = 600Kbps+/‐10%
0x111 = 700Kbps+/‐10%
All the timing related parameters inside the PHY will scale as per this
setting which tells PHY what's the frequency of the clk that it's getting.
0x000 = 1MHz
0x001 = 2.5MHz
0x010 = 5MHz
phy_prot_clk_freq 3:1 0x06
0x011 = 7.5MHz
0x100 = 10MHz
0x101 = 15MHz
0x110 = 30MHz (default)
0x111 = 50MHz
reset_prbs_pattern_gen 0 0x00 Used to reset the PHY layer's PRBS generator.

Table: phy_layer Block Register Definition ‐ Register usbpd_phy_bitstream_ctrl (Offset: 0x0206)
Description: USB PD PHY Layer Bitstream Behavior Control Register
R/W: RW
POR: 0x0008
This tells how many minimum preamble bits the PHY‐RX should wait
for, before asserting the preamble_detected signal.
0x000 = 8
0x001 = 16
0x010 = 32 (default)
min_preamble_bits 5:2 0x02
0x011 = 48
0x100 = 60
0x101 = 64
0x110 = 96 (out of current spec)
0x111 = 128 (out of current spec)
SW has decided that it's time for PHY‐RX to expect a bitstream. This
might be cause by (i) we're a default‐consumer, and are trying to
expect_bitstream 1 0x00
back‐power a dead‐battery provider, or (ii) part of cable marking
sequence, etc..
75
Description: USB PD PHY Layer Bitstream Behavior Control Register
R/W: RW
POR: 0x0008
(The default state of PHY‐RX is also to expect bit‐stream

SW has decided that it's time for PHY‐TX to send out a bitstream. This
send_bitstream 0 0x00 might be cause by (i) self dead battery scenario, and incoming Vsafe5DB
power, or (ii) part of cable marking sequence, etc..

Table: phy_layer Block Register Definition ‐ Register usbpd_phy_bist_return_errcnt_15_8 (Offset: 0x022E)
Description: During BIST Receive mode, this is the accumulated Error‐Count value from PHY made available for Read. This
register contains bits 15:8
R/W: RO
POR: 0x0000
During BIST Receive mode, this is the accumulated Error‐Count value
usbpd_phy_bist_return_errcnt_15_8 7:0 0x00
from PHY made available for Read. This register contains bits 15:8

Table: phy_layer Block Register Definition ‐ Register usbpd_phy_bist_return_errcnt_7_0 (Offset: 0x022F)
Description: During BIST Receive mode, this is the accumulated Error‐Count value from PHY made available for Read. This
register contains bits 7:0
R/W: RO
POR: 0x0000
During BIST Receive mode, this is the accumulated Error‐Count value
usbpd_phy_bist_return_errcnt_7_0 7:0 0x00
from PHY made available for Read. This register contains bits 7:0

76
ps_status_fet_control Block Register Definition ‐ Register pwr_supply_stat_0 (Offset: 0x0240)
Description: Power Supply Status
R/W: RO
POR: 0x0000
If high indicates that the Vsys supply is present and within limits for the
chip to operate from it (Vsys > 2.9V over debounce period).

Vsys is debounced by the Vsys detect circuitry. Debounce time is metal
vsys_present 0 0x00 programmable (See schematics) as follows: 100 us (default), 200 us, 300
us, 476 us. All numbers are typical timing.

Break time => always at 2 us.

ps_status_fet_control Block Register Definition ‐ Register pwr_supply_stat_1 (Offset: 0x0241)
Description: Power Supply Status
R/W: RO
POR: 0x0001
If high indicates that the Vbus supply is present and within limits for the
chip to operate from it.

Vbus is debounced by analog LDO. Debounce time is metal
programmable (See schematics) as follows:
vbus_present 2 0x00
Load Line ‐ 1 ms, 2 ms, 3 ms (default), 6 ms. All numbers are typical
timing.
No Load Line ‐ 3 ‐ 4.5 ms, 6.5 ‐ 7.5 ms, 13 ‐ 14.5 ms (default), 26 ‐ 27.5
ms.

If high indicates that the voltage on Vbus is above the VSafe5V limits
vbus_eq_vsafe5v 1 0x00
defined in the USB PD spec.
If high indicates that the voltage on Vbus is within the VSafe0V limits
defined in the USB PD spec.

Note that the analog pwr_ctrl_0.pwr_en_vsafe_comp register bit must
vbus_eq_vsafe0v 0 0x01
be asserted to enable the VSafe0V comparator. Be careful. If this
comparator is disabled then its output is high (lookling like Vbus is
within VSafe0V).

77
ps_status_fet_control Block Register Definition ‐ Register fet_ctrl_0 (Offset: 0x0242)
Description: FET Control ‐ This allows S/W control of the FETs as well as setting up priority between V_ACDC and Vbus in
case H/W greedy mode is enabled.
R/W: RW
POR: 0x0000
This allows S/W to force the FET controls as shown in sw_en_usbsrc,
sw_en_usbsnk1, and sw_en_usbsnk2 inputs, but with the provision that
H/W can override the FET controls if needed (via typec_sw_override).

'0' => If '0' then the FET control logic uses the sw_en_usbXXX[1:0]
sw_en_sw_override 7 0x00 settings as passed in via registers.

'1' => if '1' then the FET control logic uses the sw_en_usbXXX[1:0]
settings as passed in via registers. But if typec_sw_override is asserted
then the FET control logic assumes ''00'' settings for all
sw_en_usbXXX[1:0] inputs.
This controls the FET which allows us to either sink current from Vbus
or source current to Vbus (at 12V/20V).

'00' => H/W closes the FET as long as a dead battery condition is present
or if the Type C Controller is requesting the Sink1 FET to be closed. This
sw_en_usbsnk1 6:5 0x00
is the POR value. MTP bits allow this feature to be disabled.
'01' => H/W closes the FET as long as Vbus is present.
'10' => S/W forces FET open
'11' => S/W forces FET closed

This FET is only used in systems which employ a 5V to 12/20V Boost
Converter. The specific use of this FET is system specific.

'00' => Same as sw_en_usbsnk='00' setting except Sink2 FET is only
closed if mtp_assert_sink2_w_sink1 is asserted. This is the POR value.
sw_en_usbsnk2 4:3 0x00 '01' => Same as sw_en_usbsnk='01' setting except Sink2 FET is only
closed if mtp_assert_sink2_w_sink1 is asserted.

This controls the FET which allows us to source current onto Vbus at 5V.

'00' => Allow Type C Controller to open and close the FET. This is the
POR setting. MTP bits allow this feature to be disabled.
sw_en_usbsrc 2:1 0x00
'01' => Reserved

Tells the FET control logic when to ignore the presence of Vbus when
closing the USBSNK FETs. When high the logic must not consider
ignore_vbus_present_stat 0 0x00 vbus_present when closing the FETs. When low the logic will not close
the FETs if Vbus is not present.

78
typec_condet Block Register Definition ‐ Register control_sm_1 (Offset: 0x0280)
Description:
R/W: RW
POR: 0x0000
Select the Type‐C role for the Type‐C State Machine:
‐ 00 => Disabled
sw_typec_role 7:6 0x00 ‐ 01 => UFP
‐ 10 => DFP
‐ 11 => DRP
Controls discharge of VBUS to ground:
‐ 00 => Type‐C State Machine controls Vbus discharge enable/disable
sw_en_usb_vbus_discharge 5:4 0x00 ‐ 01 => Reserved
‐ 10 => Disable VBUS discharge circuit
‐ 11 => Enable VBUS discharge to ground
sw_en_usb_vbus_discharge_override 3 0x00 Allow hardware to override software control of VBUS discharge
sw_force_error_recovery 2 0x00 Direction to Type‐C State Machine to transition to ErrorRecovery state
Direction to Type‐C State Machine to transition to Unattached.UFP
sw_force_unattached_ufp 1 0x00
state
Direction to Type‐C State Machine to transition to Unattached.DFP
sw_force_unattached_dfp 0 0x00
state

Description:
R/W: RW
POR: 0x0015
Indication to Type‐C State Machine of failure to enter an Alternate
failed_to_enter_altmode 7 0x00
Mode
When this bit is 1, the Type‐C State Machine ignores vbus_present
negation when the port is an attached UFP or DFP Sink, but responds to
hard_reset_in_progress 6 0x00 disconnection when the port is an attached UFP or DFP Source. When
this bit is 0, detach occurs normally.

When this bit is 1, the Type‐C State Machine ignores vbus_present
negation when the port is an attached UFP or DFP Sink and ignores
power_role_swap_in_progress 5 0x00 disconnection when the port is an attached UFP or DFP Source. When
this bit is 0, detach occurs normally.

Enable DFP low power mode
sw_dfp_low_power 4 0x01

Select the source current limit for the Type‐C State Machine for use in
unattached states:
‐ 00 => Std USB
sw_unatt_rp_sel 3:2 0x01 ‐ 01 => 1.5A
‐ 10 => 3A
‐ 11 => Reserved

Select the source current limit for the Type‐C State Machine for use in
attached state:
sw_att_rp_sel 1:0 0x01
‐ 00 => Std USB
‐ 01 => 1.5A
79
Description:
R/W: RW
POR: 0x0015
‐ 10 => 3A
‐ 11 => Reserved

Description:
R/W: WO
POR: 0x0000

Writing 0 to this bit requests VCONN connection be disabled; writing 1
requests VCONN connection be enabled.

If the Type‐C State Machine is currently in an unattached state or an
accessory‐attached state, writing to this bit has no effect. Otherwise,
the VCONN connection state changes to the requested state.

vconn_en_change_req 5 0x00
If the Type C State Machiine is enabled to control the Vconn switch,
then it will close it upon initial connection if we are connected in a DFT
role and Ra was detected (Attached.DFP.Src state). Afterwards S/W can
cause it to change the Vconn switch enable via this bitfleid.

If the Type C State Machine is not enabled to control the Vconn switch,
then S/W will use sw_en_ccX_to_vconn bits to directly cortrol the
Vconn switch.
Writing 10 (Sink) to this bit requests a PD power role change to Sink
role; writing 11 (Source) requests a change to Source role. Writing other
values has no effect.
If the current PD power role is None or is the same as that requested, or
power_role_change_req 4:3 0x00
if the pd_swap_in_progress control bit is 0, writing to this bit has no
effect. Otherwise, the Type‐C State Machine changes to the requested
PD power role.

Writing 010 (UFP) to this bit requests a role change to UFP role; writing
001 (DFP) requests a change to DFP role. Writing other values has no
effect.

For a DRP in SM_UNATTACHED_UFP state, requesting UFP role has no
effect; and requesting DFP causes an immediate state change to
SM_UNATTACHED_DFP, resetting the tDRSwap timer. Similarly, for a
DRP in SM_UNATTACHED_DFP state, requesting DFP role has no effect;
typec_role_change_req 2:0 0x00 and requesting UFP causes an immediate state change to
SM_UNATTACHED_UFP, resetting the tDRSwap timer.

For a UFP in SM_UNATTACHED_UFP state, requesting UFP role has no
effect; and requesting DFP causes an immediate state change to
SM_UNATTACHED_ACCESSORY, resetting the tDRSwap timer. Similarly,
for a UFP in SM_UNATTACHED_ACCESSORY state, requesting DFP role
has no effect; and requesting UFP causes an immediate state change to
SM_UNATTACHED_UFP, resetting the tDRSwap timer.
80
Description:
R/W: WO
POR: 0x0000

For a DRP in SM_ATTACHED_UFP_ORIENT_DETECTED state, requesting
UFP role has no effect; and requesting DFP causes an immediate state
change to SM_ATTACHED_DFP. Similarly, for a DRP in
SM_ATTACHED_DFP state, requesting DFP role has no effect; and
requesting UFP causes an immediate state change to
SM_ATTACHED_UFP_ORIENT_DETECTED.
In all other cases, writing to these bits has no effect.

typec_condet Block Register Definition ‐ Register control_vconn_comm (Offset: 0x0283)
Description:
R/W: RW
POR: 0x0000
When 0, register bits (S/W) control the VCONN switch; when 1, the
Type‐C State Machine controls it.

Default is to let S/W Control Vconn switch and have it disabled. In
sw_sel_vconn_ctrl 5 0x00 autonomous systems without any S/W support, the Type C Controller
will not close the Vconn switch. In systems with S/W support, it is up to
that S/W to enable the Type C Controller to autonomously close the
Vconn Switch if appropriate.

sw_en_cc1_to_vconn 4 0x00 Enable VCONN_IN connection to CC1
sw_en_cc2_to_vconn 3 0x00 Enable VCONN_IN connection to CC2
Orientation of plug in receptacle is such that CC communication occurs
sw_cc_orient_on_cc1 2 0x00
on CC1
sw_en_cc1_comm 1 0x00 Enable CC communication switch to connect to CC1
sw_en_cc2_comm 0 0x00 Enable CC communication switch to connect to CC2

typec_condet Block Register Definition ‐ Register control_rd (Offset: 0x0284)
Description:
R/W: RW
POR: 0x0000
81
Description:
R/W: RW
POR: 0x0000
sw_rd_fine_cc1_en 3 0x00 Enable fine‐tolerance Rd pull‐down connection to CC1
sw_rd_coarse_cc1_en 2 0x00 Enable coarse‐tolerance Rd pull‐down connection to CC1
sw_rd_fine_cc2_en 1 0x00 Enable fine‐tolerance Rd pull‐down connection to CC2
sw_rd_coarse_cc2_en 0 0x00 Enable coarse‐tolerance Rd pull‐down connection to CC2

typec_condet Block Register Definition ‐ Register control_rp (Offset: 0x0285)
Description:
R/W: RW
POR: 0x0000
When 0, Type‐C State machine attached as Sink only detects
disconnection using vbus_present (when power‐role swap not in
progress); when 1, Type‐C State machine attached as Sink detects
sw_en_det_disconnect_as_sink 6 0x00
disconnection using vbus_present (when power‐role swap not in
progress) or partner's Rp being removed (regardless of power‐role
swap).
Enable for Rp current sources or resistors to CC1:
‐ 000 => none connected
sw_en_host_cc1_to_rp_1hot 5:3 0x00 ‐ 001 => Rp current/resistor for Std USB limit
‐ 010 => Rp current/resistor for 1.5A limit
‐ 100 => Rp current/resistor for 3A limit
Enable for Rp current sources or resistors to CC2:
‐ 000 => none connected
sw_en_host_cc2_to_rp_1hot 2:0 0x00 ‐ 001 => Rp current/resistor for Std USB limit
‐ 010 => Rp current/resistor for 1.5A limit
‐ 100 => Rp current/resistor for 3A limit

typec_condet Block Register Definition ‐ Register control_vrd (Offset: 0x0286)
Description:
R/W: RW
POR: 0x0000
sw_cc1_vrd_en 7 0x00 Enable for Vrd threshold comparator for CC1
sw_cc2_vrd_en 6 0x00 Enable for Vrd threshold comparator for CC2
sw_cc_vrd_stdusb_en 5 0x00 Enable Vrd comparator for Std USB current limit
82
Description:
R/W: RW
POR: 0x0000
sw_cc_vrd_1p5a_en 4 0x00 Enable Vrd comparator for 1.5A current limit
sw_vrd_stdusb_comp_on_cc1_en 3 0x00 Enable CC1 as input to Vrd comparator for Std USB current limit
sw_vrd_stdusb_comp_on_cc2_en 2 0x00 Enable CC2 as input to Vrd comparator for Std USB current limit
sw_vrd_1p5a_comp_on_cc1_en 1 0x00 Enable CC1 as input to Vrd comparator for 1.5A current limit
sw_vrd_1p5a_comp_on_cc2_en 0 0x00 Enable CC2 as input to Vrd comparator for 1.5A current limit

typec_condet Block Register Definition ‐ Register control_vra (Offset: 0x0287)
Description:
R/W: RW
POR: 0x0009
sw_cc1_vra_en 7 0x00 Enable for Vra threshold comparator for CC1
sw_cc2_vra_en 6 0x00 Enable for Vra threshold comparator for CC2
Reference select for Vra threshold comparator for CC1:
‐ 001 => threshold for Std USB limit
sw_cc1_vra_ref_sel_1hot 5:3 0x01 ‐ 010 => threshold for 1.5A limit
‐ 100 => threshold for 3A limi

Reference select for Vra threshold comparator for CC2:
‐ 001 => threshold for Std USB limit
sw_cc2_vra_ref_sel_1hot 2:0 0x01 ‐ 010 => threshold for 1.5A limit
‐ 100 => threshold for 3A limit

typec_condet Block Register Definition ‐ Register status_role (Offset: 0x0288)
Description:
R/W: RO
POR: 0x0000
Orientation of plug in receptacle is such that CC communication occurs
cc_orient_on_cc1 6 0x00
on CC2 (when 0) or CC1 (when 1).
From Type‐C State Machine, indicating current VCONN connection
cur_vconn_en 5 0x00
state: 0 => connection disabled, 1 => connection enabled
From Type‐C State Machine, indicating current USB PD power role:
cur_power_role 4:3 0x00
‐ 00 => None, or accessory attached
83
Description:
R/W: RO
POR: 0x0000
‐ 01 => Reserved
‐ 10 => Sink
‐ 11 => Source
From Type‐C State Machine, indicating current Type‐C role:
‐ 0 => None (Type‐C role not yet established)
‐ 1 => DFP
‐ 2 => UFP
cur_typec_role 2:0 0x00 ‐ 3 => Reserved
‐ 4 => Reserved
‐ 5 => Audio Accessory
‐ 6 => Debug Accessory
‐ 7 => Powered Accessory

typec_condet Block Register Definition ‐ Register status_cursns (Offset: 0x0289)
Description:
R/W: RO
POR: 0x0000
Debounced encoded value of sensed current limit
‐ 00 => Not enabled
cc_cursns_dbncd 1:0 0x00 ‐ 01 => Std USB
‐ 10 => 1.5A
‐ 11 => 3A

typec_condet Block Register Definition ‐ Register status_comp (Offset: 0x028A)
Description:
R/W: RO
POR: 0x0000
cc1_vrd_open_dbncd 7 0x00 Debounced voltage detection that Rd is open on CC1
cc1_vrd_present_dbncd 6 0x00 Debounced voltage detection that Rd is present on CC1
cc1_ra_present_dbncd 5 0x00 Debounced voltage detection that Ra is present on CC1
cc1_ra_disconnect_dbncd 4 0x00 Debounced voltage detection that Ra is disconnected on CC1
cc2_vrd_open_dbncd 3 0x00 Debounced voltage detection that Rd is open on CC2
cc2_vrd_present_dbncd 2 0x00 Debounced voltage detection that Rd is present on CC2
cc2_ra_present_dbncd 1 0x00 Debounced voltage detection that Ra is present on CC2
84
Description:
R/W: RO
POR: 0x0000
cc2_ra_disconnect_dbncd 0 0x00 Debounced voltage detection that Ra is disconnected on CC2

typec_condet Block Register Definition ‐ Register status_state (Offset: 0x028B)
Description:
R/W: RO
POR: 0x0000
From Type‐C State Machine, indicating the port role that was in effect
on the last attachment
typec_role_on_attachment 5 0x00 ‐ 0 => UFP, set on transition to SM_UNATTACHED_UFP, SM_LOCK_UFP.
‐ 1 => DFP, set on transition to SM_UNATTACHED_DFP, SM_TRY_DFP,
SM_ATTACH_DFP_DRPWAIT
Current state of Type‐C State Machine, for debugging purposes.
sm_cur_state 4:0 0x00
Encoding TBD.

typec_condet Block Register Definition ‐ Register config (Offset: 0x028C)
Description:
R/W: RW
POR: 0x0020
When 1, the sw_resistor_rp_ok register bits are used to select between
sw_sel_resistor_rp_ok 7 0x00 current source or resistor for pull‐up; when 0, the mtp_resistor_rp_ok
MTP bits are used.
Controls selection of current source or resistor for pull‐up. For each bit,
0 indicates use of current source, and 1 indicates use of resistor.

sw_resistor_rp_ok 6:5 0x01 Bit [0] controls selection for a pull‐up advertising StdUSB current limit.
Bit [1] controls selection for pull‐ups advertising 1.5A and 3A current
limits. This bit is now reserved as analog only has current source pullups
for 1.5A and 3A advertisement.
When 1, register bits override MTP bits; when 0, MTP bits are used. This
affects the following bits:
‐ sw_typec_role
‐ sw_unatt_rp_sel
typec_sel_reg_mtp_n 4 0x00 ‐ sw_att_rp_sel
‐ sw_prefer_dfp_role
‐ sw_support_accessories
‐ sw_dfp_low_power
‐ sw_cc_orient_on_cc1_invert
Select preference for DFP role for Type‐C State Machine: 0 => don't
sw_prefer_dfp_role 3 0x00
prefer DFP; 1 => prefer DFP or don't support PD operation
Select whether accessories are supported for Type‐C State Machine: 0
sw_support_accessories 2 0x00
=> don't support; 1 => support
85
Description:
R/W: RW
POR: 0x0020
Select make‐before‐break transition from coarse‐ to fine‐tolerance Rd
sw_rd_make_b4_brk 1 0x00
pull‐down
When 0, typec_cc_orient_on_cc1 output is active high (0 => CC on CC2,
1 => CC on CC1); when 1, typec_cc_orient_on_cc1 output is inverted to
sw_cc_orient_on_cc1_invert 0 0x00
active low (0 => CC on CC1, 1 => CC on CC2). The sense of the software
status bit cc_orient_on_cc1 is not affected.

typec_condet Block Register Definition ‐ Register sw_taccdetect_10_8 (Offset: 0x028D)
Description:
R/W: RW
POR: 0x0000
Timer value for tAccDetect (Time before Accessory Mode shall be
sw_taccdetect_10_8 2:0 0x00 entered). 50ms to 200ms in increments of prescaled timebase. POR
50ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_taccdetect_7_0 (Offset: 0x028E)
Description: Timer value for tAccDetect (Time before Accessory Mode shall be entered). 50ms to 200ms in increments of
prescaled timebase. POR 50ms + ~7.5%
R/W: RW
POR: 0x00d2
Timer value for tAccDetect (Time before Accessory Mode shall be
sw_taccdetect_7_0 7:0 0xd2 entered). 50ms to 200ms in increments of prescaled timebase. POR
50ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrpswap_rp_10_8 (Offset: 0x028F)
Description:
R/W: RW
POR: 0x0000
Timer value for tDRPSwap_Rp (The length of a Rp cycle during the DRP
sw_tdrpswap_rp_10_8 2:0 0x00 advertisement). 15ms to 70ms in increments of prescaled timebase.
POR 24.7ms + ~7.5%

86
typec_condet Block Register Definition ‐ Register sw_tdrpswap_rp_7_0 (Offset: 0x0290)
Description: Timer value for tDRPSwap_Rp (The length of a Rp cycle during the DRP advertisement). 15ms to 70ms in
increments of prescaled timebase. POR 24.7ms + ~7.5%
R/W: RW
POR: 0x0068
Timer value for tDRPSwap_Rp (The length of a Rp cycle during the DRP
sw_tdrpswap_rp_7_0 7:0 0x68 advertisement). 15ms to 70ms in increments of prescaled timebase.
POR 24.7ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrpswap_rd_10_8 (Offset: 0x0291)
Description:
R/W: RW
POR: 0x0000
Timer value for tDRPSwap_Rd (The length of a Rd cycle during the DRP
sw_tdrpswap_rd_10_8 2:0 0x00 advertisement). 15ms to 70ms in increments of prescaled timebase.
POR 57ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrpswap_rd_7_0 (Offset: 0x0292)
Description: Timer value for tDRPSwap_Rd (The length of a Rd cycle during the DRP advertisement). 15ms to 70ms in
increments of prescaled timebase. POR 57ms + ~7.5%
R/W: RW
POR: 0x00f0
Timer value for tDRPSwap_Rd (The length of a Rd cycle during the DRP
sw_tdrpswap_rd_7_0 7:0 0xf0 advertisement). 15ms to 70ms in increments of prescaled timebase.
POR 57ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrphold_10_8 (Offset: 0x0293)
Description:
R/W: RW
POR: 0x0001
Timer value for tDRPHold (Wait time associated with the
sw_tdrphold_10_8 2:0 0x01 Attach.DFP.DRPWait state). 100ms to 150ms in increments of prescaled
timebase. POR 100ms + ~7.5%

87
typec_condet Block Register Definition ‐ Register sw_tdrphold_7_0 (Offset: 0x0294)
Description: Timer value for tDRPHold (Wait time associated with the Attach.DFP.DRPWait state). 100ms to 150ms in
increments of prescaled timebase. POR 100ms + ~7.5%
R/W: RW
POR: 0x00a4
Timer value for tDRPHold (Wait time associated with the
sw_tdrphold_7_0 7:0 0xa4 Attach.DFP.DRPWait state). 100ms to 150ms in increments of prescaled
timebase. POR 100ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrplock_10_8 (Offset: 0x0295)
Description:
R/W: RW
POR: 0x0001
Timer value for tDRPLock (Wait time associated with the Lock.UFP
sw_tdrplock_10_8 2:0 0x01 state). 100ms to 150ms in increments of prescaled timebase. POR
100ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrplock_7_0 (Offset: 0x0296)
Description: Timer value for tDRPLock (Wait time associated with the Lock.UFP state). 100ms to 150ms in increments of
R/W: RW
POR: 0x00a4
Timer value for tDRPLock (Wait time associated with the Lock.UFP
sw_tdrplock_7_0 7:0 0xa4 state). 100ms to 150ms in increments of prescaled timebase. POR
100ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tdrptry_10_8 (Offset: 0x0297)
Description:
R/W: RW
POR: 0x0006
Timer value for tDRPTry (Wait time associated with the Try.DRP state).
sw_tdrptry_10_8 2:0 0x06 400ms to 450ms in increments of prescaled timebase. POR 400ms +
~7.5%

88
typec_condet Block Register Definition ‐ Register sw_tdrptry_7_0 (Offset: 0x0298)
Description: Timer value for tDRPTry (Wait time associated with the Try.DRP state). 400ms to 450ms in increments of
R/W: RW
POR: 0x0090
Timer value for tDRPTry (Wait time associated with the Try.DRP state).
sw_tdrptry_7_0 7:0 0x90 400ms to 450ms in increments of prescaled timebase. POR 400ms +
~7.5%

typec_condet Block Register Definition ‐ Register sw_terrorrecovery_10_8 (Offset: 0x0299)
Description:
R/W: RW
POR: 0x0000
Timer value for tErrorRecovery (Time a port shall remain in the
sw_terrorrecovery_10_8 2:0 0x00 ErrorRecovery state). 25ms min in increments of prescaled timebase.
POR 25ms + ~7.50%

typec_condet Block Register Definition ‐ Register sw_terrorrecovery_7_0 (Offset: 0x029A)
Description: Timer value for tErrorRecovery (Time a port shall remain in the ErrorRecovery state). 25ms min in increments
of prescaled timebase. POR 25ms + ~7.50%
R/W: RW
POR: 0x0069
Timer value for tErrorRecovery (Time a port shall remain in the
sw_terrorrecovery_7_0 7:0 0x69 ErrorRecovery state). 25ms min in increments of prescaled timebase.
POR 25ms + ~7.50%

typec_condet Block Register Definition ‐ Register sw_tdfpidle_10_8 (Offset: 0x029B)
Description:
R/W: RW
POR: 0x0000
Timer value for tDFPIdle (Wait time associated with Unattached.DFP
sw_tdfpidle_10_8 2:0 0x00 Idle state). 15ms to 524ms in increments of prescaled timebase. POR
57ms + ~7.5%

89
typec_condet Block Register Definition ‐ Register sw_tdfpidle_7_0 (Offset: 0x029C)
Description: Timer value for tDFPIdle (Wait time associated with Unattached.DFP Idle state). 15ms to 524ms in increments
of prescaled timebase. POR 57ms + ~7.5%
R/W: RW
POR: 0x00f0
Timer value for tDFPIdle (Wait time associated with Unattached.DFP
sw_tdfpidle_7_0 7:0 0xf0 Idle state). 15ms to 524ms in increments of prescaled timebase. POR
57ms + ~7.5%

typec_condet Block Register Definition ‐ Register sw_tvbusdischarge_10_8 (Offset: 0x029D)
Description:
R/W: RW
POR: 0x0000
Timer value for VBUS discharge. 0ms to 524ms in increments of
sw_tvbusdischarge_10_8 2:0 0x00

typec_condet Block Register Definition ‐ Register sw_tvbusdischarge_7_0 (Offset: 0x029E)
Description: Timer value for VBUS discharge. 0ms to 524ms in increments of prescaled timebase. POR 50ms + ~7.5%
R/W: RW
POR: 0x00d2
Timer value for VBUS discharge. 0ms to 524ms in increments of
sw_tvbusdischarge_7_0 7:0 0xd2

typec_condet Block Register Definition ‐ Register sw_tccdetectskew (Offset: 0x029F)
Description: Timer value for tCCDetectSkew (Allowance for skew between debounced comparator outputs). 5ms to 65ms in
increments of prescaled timebase. POR 50ms + ~7.5%.
R/W: RW
POR: 0x00d2
Timer value for tCCDetectSkew (Allowance for skew between
debounced comparator outputs). 5ms to 65ms in increments of
sw_tccdetectskew 7:0 0xd2
prescaled timebase. POR 50ms + ~7.5%.

90
typec_condet Block Register Definition ‐ Register sw_typec_clkdiv (Offset: 0x02A0)
Description: Timer prescale divider, dividing 2MHz clock. The time base for the timers is 0.5us Ã— 2 Ã— (sw_typec_clkdiv +
1). The timeout interval for a timer is the time base Ã— timer value.
R/W: RW
POR: 0x00ff
Timer prescale divider, dividing 2MHz clock. The time base for the
timers is 0.5us Ã— 2 Ã— (sw_typec_clkdiv + 1). The timeout interval for
sw_typec_clkdiv 7:0 0xff
a timer is the time base Ã— timer value.

typec_condet Block Register Definition ‐ Register sw_cc1_dbnc_cnt_15_8 (Offset: 0x02A1)
Description: Debounce timer count value for detection on CC1. 10ms min at POR, adjustable from 0ms to 64ms in steps of
256us. POR 10ms + ~2.5%
R/W: RW
POR: 0x0029
Debounce timer count value for detection on CC1. 10ms min at POR,
sw_cc1_dbnc_cnt_15_8 7:0 0x29
adjustable from 0ms to 64ms in steps of 256us. POR 10ms + ~2.5%

typec_condet Block Register Definition ‐ Register sw_cc2_dbnc_cnt_15_8 (Offset: 0x02A2)
Description: Debounce timer count value for detection on CC2. 10ms min at POR, adjustable from 0ms to 64ms in steps of
256us. POR 10ms + ~2.5%
R/W: RW
POR: 0x0029
Debounce timer count value for detection on CC2. 10ms min at POR,
sw_cc2_dbnc_cnt_15_8 7:0 0x29

typec_condet Block Register Definition ‐ Register sw_cc_cursns_dbnc_cnt_15_8 (Offset: 0x02A3)
Description: Debounce timer count value for indication of change in Vrd current limit voltage detection. 10ms min at POR,
R/W: RW
POR: 0x0029
Debounce timer count value for indication of change in Vrd current limit
sw_cc_cursns_dbnc_cnt_15_8 7:0 0x29 voltage detection. 10ms min at POR, adjustable from 0ms to 64ms in

91
vconn_switch_control Block Register Definition ‐ Register vconn_fault_ctrl0 (Offset: 0x02C0)
Description: Vconn Control Register
R/W: RW
POR: 0x0007
Enable Type C Controller Vconn Fault Clear

'0' => Only S/W can clear Vconn Faults.

'1' => S/W can clear the Vconn Faults (vconn_fcl_fault_clr and
vconn_rcp_fault_clr) as well as the Type C Controller. The Type C
Controller will clear RCP and FCL faults whenever it deasserts both of its
sw_en_typec_clr_vconn_flt 7 0x00 en_cc1_to_vconn and en_cc2_to_vconn outputs. It does this whenver
it's not closing the Vconn switch. Note that S/W also controls the Vconn
switch through the Type C Controller. Therefore if S/W disables the
Type C Controller and disables the Vconn switch on both CC lines, then
the fault will be cleared. If the Type C Controller is enabled and it
deasserts Vconn switch from both CC lines (disconnect condition,
connect but not driving Vconn) then the faults wilil be cleared.

This bit allows host firmware to clear a Vconn switch reverse current
fault condition. When vconn_rcp_fault_stat is set, indicating a fault,
host firmware can write a '1' to vconn_rcp_fault_clr to clear the fault
vconn_rcp_fault_clr 6 0x00
condition and reclose the Vconn switch.

This bit allows host firmware to clear a Vconn switch forward current
fault condition. When vconn_fcl_fault_stat bit is set, indicating a fault,
host firmware can write a '1' to vconn_fcl_fault_clr bit to clear the fault
vconn_fcl_fault_clr 5 0x00
condition and reclose the Vconn switch.

Reverse Current Fault Switch Disconnect Control

This bit controls disconnection of Vconn swtich when a reverse current
fault condition occurs. The Fault interrupt is generated only if the
corresponding interrupt bit is not masked.
sw_rcp_disable_vconn_disconnect 4 0x00

0 => Vconn switch is disconnected when a fault occurs..
1 => Vconn switch disconnection is disabled even if fault occurs.. Fault
interrupt is still generated.

Forward Current Fault Switch Disconnect Control

This bit controls disconnection of Vconn swtich when a reverse current
fault condition occurs. The Fault interrupt is generated only if the
corresponding interrupt bit is not masked.
sw_fcl_disable_vconn_disconnect 3 0x00

0 => Vconn switch is disconnected when a fault occurs..
1 => Vconn switch disconnection is disabled even if fault occurs.. Fault
interrupt is still generated.

This bit is used to enable forward current protection caused by
overvoltage on the CC1 and CC2 pins when connected to Vconn_in .
This bit goes to the digital logic. The actual enable to the analog
switches is generated by the digital Vconn logic.
sw_en_vconn_fcl 2 0x01

0 => CC1 and CC2 are not protected from forward current (over
voltage). vconnx_fault in the vconn_fault_status register will not be set
if a fault is detected.
92
Description: Vconn Control Register
R/W: RW
POR: 0x0007

1 => CC1 and CC2 are protected from forward current (over voltage).
vconnx_fault bit will be set in the vconn_fault_status register if a fault
condition is detected.

This bit is used to enable reverse current protection caused by
overvoltage on the CC1 and CC2 pins when connected to Vconn_in .
This bit goes to the digital logic. The actual enable to the analog
switches is generated by the digital Vconn logic.

0 => CC1 and CC2 are not protected from reverse current (over voltage).
sw_en_vconn_rcp 1 0x01 vconnx_fault in the vconn_fault_status register will not be set if a fault
is detected.

1 => CC1 and CC2 are protected from reverse current (over voltage).
vconnx_fault bit will be set in the vconn_fault_status register if a fault
condition is detected.

Select between S/W and MTP for Vconn Switches Fault Control

0 => Select S/W Control
1 => Select MTP Control

This affects the following bits:
sw_sel_vconn_reg_set 0 0x01
sw_en_vconn_fcl
sw_en_vconn_rcp
sw_fcl_disable_vconn_disconnect
sw_rcp_disable_vconn_disconnect
sw_sel_fcl_threshold

Description: Vconn Switch Fault Control
R/W: RW
POR: 0x0044
Length of digital deglitch for fault condition. If fault persists for more
than this time then a fault is declared.

0000 => No deglitch
0001 => ~12 us
0010 => ~36 us
0011 => ~60 us
0100 => ~100 us (Default)
fcl_deglitch 7:4 0x04
0101 => ~200 us
0110 => ~500 us
0111 => ~1000 us
1000 => ~2 ms
1001 => ~5 ms
1010 => ~10 ms
1011 => ~20 ms
11xx => ~50 ms
93
R/W: RW
POR: 0x0044
Length of digital deglitch for fault condition. If fault persists for more
than this time then a fault is declared.

0000 => No deglitch
0001 => ~12 us
0010 => ~36 us
0011 => ~60 us
0100 => ~100 us (Default)
rcp_deglitch 3:0 0x04 0101 => ~200 us
0110 => ~500 us
0111 => ~1000 us
1000 => ~2 ms
1001 => ~5 ms
1010 => ~10 ms
1011 => ~20 ms
11xx => ~50 ms

R/W: RW
POR: 0x0000
Vconn Forward Current Limiting Threshold

00 => 250 mA
sw_sel_fcl_threshold 1:0 0x00 01 => 500 mA
10 => 1000 mA
11 => Reserved

vconn_switch_control Block Register Definition ‐ Register vconn_fault_status (Offset: 0x02C3)
Description: Vconn Switch Fault Status
R/W: RO
POR: 0x0000
This bit indicates a forward current fault condition has been sensed on
CC1 or CC2 and these switches have been opened (if
vconn_fcl_fault_stat 3 0x00
sw_fcl_disable_vconn_disconnect is cleared).

94
Description: Vconn Switch Fault Status
R/W: RO
POR: 0x0000
This bit is set when sw_en_vconn_fcl is a 1 and a fault is sensed on CC1
or CC2. This bit is reset when a '1' is written to the vconn_fcl_fault_clr
bit. It is also reset when fault detection/protection is disabled via
sw_en_vconn_fcl=0.

This bit indicates a reverse current fault condition has been sensed on
CC1 or CC2 and these switches have been opened (if
sw_rcp_disable_vconn_disconnect is cleared).

vconn_rcp_fault_stat 2 0x00 This bit is set when sw_en_vconn_rcp is a 1 and a fault is sensed on CC1
or CC2. This bit is reset when a '1' is written to the vconn_rcp_fault_clr
bit. It is also reset when fault detection/protection is disabled via
sw_en_vconn_rcp=0.

This bit indicates the state/result of the comparator used for Vconn
forward current protection scheme.

0 => No forward current limiting fault is present
1 => Forward current limiting fault is present

fcl_comp_out_sync 1 0x00
When the sw_en_vconn_fcl bit is set, sw_fcl_disable_vconn_disconnect
is cleared, and a forward current condition occurs, the Vconn switch is
opened and the vconn_fcl_fault_stat bit field is set So if the host
firmware reads this register after a fault event, the bit fields will read as
zero.

This bit indicates the state/result of the comparator used for Vconn
reverse current protection scheme.

0 => No reverse current is flowing through the Vconn switch
1 => Reverse current is flowing through the Vconn switch

rcp_comp_out_sync 0 0x00
When the sw_en_vconn_rcp bit is set,
sw_rcp_disable_vconn_disconnect is cleared, and a reverse current
condition occurs, the Vconn switch is opened and the
vconn_rcp_fault_stat bit field is set So if the host firmware reads this
register after a fault event, the bit fields will read as zero.

95
ana_ctl Block Register Definition ‐ Register pwr_ctrl_0 (Offset: 0x0300)
Description: Power Subsystem Control
R/W: RW
POR: 0x0000
When '1' allows the pwr_lp_mode bit to affect the VDD1V8 power
pwr_en_lpmode 6 0x00 supply ‐ will power down the LDO1V8 and only the crude‐regulator will
hold up VDD1V8
When '1', allows the crude regulator to be powered down in normal
pwr_allow_dis_crudreg 5 0x00
mode
pwr_pd_bias 4 0x00 Powerdown for the bias generator
Affects the bias block and the LDO1V8 (if pwr_en_lpmode permits). In
pwr_lp_mode 3 0x00 the bias, it shuts down the generation of the 2 uA and 5 uA biases to
save IQQ ‐ idea being that only the 0.5 uA for the CC_DET is needed
In the bias, it shuts down the generation of the 2 uA and 5 uA biases to
pwr_en_vbus_discharge 2 0x00
save IQQ ‐ idea being that only the 0.5 uA for the CC_DET is needed
Set to '1' to enable the comparator generating the pwr_vbus_vsafe0v
signal

Note: This comparator is powered by Vsys (VDD). If we are in a dead
battery scenario then S/W may not use the vbus_eq_vsafe0v status.
pwr_en_vsafe_comp 1 0x00
Note: This comparator requires its Vref cell to be enabled and stable
prior to use. Otherwise the VSafe0V status will be unstable for a short
time. Refer to the SPARE_REG_0.pwr_en_sys_iref bit definition for
more info.

HI will enable the comparators that generate PGOOD info for those
pwr_en_ccconq_pgcmps 0 0x00 internal rails. When this signal is '0', the podas for those 2 rails will be
'0'

ana_ctl Block Register Definition ‐ Register pwr_ctrl_1 (Offset: 0x0301)
R/W: RW
POR: 0x000a
Just in case we find out that ESD structures need the Charge‐Pump to
stay ON, then we'll tell SW to enable this bit forever. Till then, it stays 0.
This bit doesn't need to be set/reset while enabling/disabling the
sw_en_cp6p0v 5 0x00 VCONN switches.

Those switches will enable the CP automatically.

Similar to RX, the TX of AFE needs a control bit from Power‐Subsystem's
pwr_bias_tx_ref_select 4 0x00
BIAS circuit.
Defines the voltage thresholds used in AFE Rx. Together the Vref_high
and Vref_low help define the Rx Mask. See rx_vref_slct bit for more
pwr_bias_rx_ref_select 3:0 0x0a
information.

96
R/W: RW
POR: 0x000a
Bits 3:2 ‐ Vref_high ‐ Sets the high voltage threshold in the Rx Mask
00 => 560 mV
01 => 685 mV
10 => 600 mV (Default)
11 => 810 mV

Bits 1:0 ‐ Vref_low ‐ Sets the low voltage threshold in the Rx mask
00 => 290 mV
01 => 415 mV
10 => 500 mV (Default)
11 => 540 mV

Intersection of all masks ‐ Used by default unless we find problems.
Actual PD Thresholds = 430 mV, 550 mV, 670 mV
Programmed Thresholds (0b1010): Vref_low= 500 mV, Vref_high =
600 mV

Intersection of Sink & Neutral masks ‐ Used when Power Sink
Programmed Thresholds (0b1000): Vref_low = 290 mV, Vref_high =
600 mV

Intersection of Src & Neutral masks ‐ Used when Power Source
810 mV.

Neutral Mask ‐ Used when in cable
810 mV

ana_ctl Block Register Definition ‐ Register afe_ctrl_0 (Offset: 0x0302)
Description: RX/TX Control 0
R/W: RW
POR: 0x0000
This bit has nothing to do with ICAL trim being done. It actually controls
a bias current generated inside CC_ICAL and used in number of modes:
cc_ical_trim_done_sw 3 0x00 RX, TX, CC termination, VCONN FCL, ICAL trim. See VCT145 for details.
0 ‐ cc_ical_trim_done controlled by TYPEC hardware,
1 ‐ cc_ical_trim_done force enabled
0 ‐ cc_vrefs_en controlled by TYPEC hardware, 1 ‐ cc_vrefs_en force
cc_vrefs_en_sw 2 0x00
enabled
tx_en_sw 1 0x00 0 ‐ TX controlled by PHY hardware, 1 ‐ TX force enabled
rx_en 0 0x00 0 ‐ RX disabled, 1 ‐ RX enabled
97

R/W: RW
POR: 0x0000
Select different slew rate options in TX ( 3 different way, trade of
sr_blk_slct 7:6 0x00
between accuracy and current)
tx_sr_ctrl 5:3 0x00
tx_ictrl 2:0 0x00

R/W: RW
POR: 0x0000
rx_ictrl 6:4 0x00
BMC Rx Mask Reference Select.

0 => Default. Use 2 thresholds to define Rx mask. The design uses an
rx_vref_slct 3 0x00 upper and lower voltage threshold.
1 =>:Use 1 threshold to define Rx mask. The design uses a single
midpoint voltage threshold of 550 mV.

rx_fc_ctrl 2:0 0x00

ana_ctl Block Register Definition ‐ Register product_id_byte0 (Offset: 0x0305)
Description: Product ID Byte 0
R/W: RO
POR: 0x0000
product_id_byte0 7:0 0x00 Product ID Byte 0

98
ana_ctl Block Register Definition ‐ Register product_id_byte1 (Offset: 0x0306)
Description: Product ID Byte 1
R/W: RO
POR: 0x0051
product_id_byte1 7:0 0x51 Product ID Byte 1

ana_ctl Block Register Definition ‐ Register clk_tst_ctrl (Offset: 0x0307)
Description: Clock test control
R/W: RW
POR: 0x0000
fro_clk_req_tst 1 0x00 Request to keep FRO running
lposc_req_tst 0 0x00 Request to keep 2MHz oscillator running

99
spare_regs Block Register Definition ‐ Register spare_reg_0 (Offset: 0x0380)
Description: Spare Register (to Analog‐Top as dig_spare_in[7:0])
R/W: RW
POR: 0x0000
Spare Register (to Analog‐Top as dig_spare_in[7:0])

Bits 7:2 => Reserved

Bit 1 => pwr_en_sys_iref ‐ Enables Vref cell required by the VSafe0V
comparator. VRef must be stable before enabling the VSafe0V
comparator or glitches on the VSafe0V status may be present. 0 =>
Disable the VRef cell (default). 1 => Enable the Vref cell. This must be
done at least 100 us prior to enabling the VSafe0V comparator via
pwr_en_vsafe_comp bit.

dig_spare_in_lsb 7:0 0x00
Bit 0 => vsafe0v_thr_sel ‐ Select VSafe0V detection threshold for
vbus_eq_vsafe0v analog status. 0 => Select VSave0V Discharge
Threshold, 1 => Select USB PD VSafe0V Threshold. '0' is used when
Victoria is actively discharging Vbus. '1' is used only when S/W needs to
check Vbus level while not discharging it.

Note: S/W needs to set the VSafe0V detection threshold to Discharge at
all times except when it really requires monitoring Vbus while not
discharging it. This is required because the Type C Controller needs the
discharge threshold during a disconnect when it is discharging Vbus.

Description: Spare Register (to Analog‐Top as dig_spare_in[15:8])
R/W: RW
POR: 0x0000
Spare Register (to Analog‐Top as dig_spare_in[15:8])

dig_spare_in_msb 7:0 0x00
Bits 7:0 => Reserved

Description: Spare Register (from Analog‐Top as dig_spare_out[7:0])
R/W: RO
POR: 0x0000
dig_spare_out 7:0 0x00 Spare Register (from Analog‐Top as dig_spare_out[7:0])

100
dummy_spi__registers Block Register Definition ‐ Register spi_status (Offset: 0xFFFF)
Description: SPI Status Register.The SPI Block contains this internal register for aiding clock status checking during SPI
accesses. It is not an actual MMIO register. The resulting MMIO registers generated from the Perl script will not be used as
the register is coded into the actual SPI Slave.
R/W: RO
POR: 0x0000
clk_valid 0 0x00 System Clock is valid when '1'

101

102

103

PTN5100 PHY Programming Guide V0.1

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PTN5100 PHY Programming Guide V0.1

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PTN5100 PD PHY APPLICATION

PROGRAMMING GUIDE Ver. 0.1

II. I2C Interface

III. Register Interface

i. PTN5100 Internal Oscillator

iii. PTN5100 Sample Initialization Procedure

0x0000 int_control Internal Interrupt Control/Status

0x0040 pmu PMU

0x0040 pmu_reset_ctrl RW 0x0000 PMU reset control

0x0041 pmu_clk_ctrl0 RW 0x0000 PMU clock control0

0x0042 pmu_lowpower ‐ 0x0000 Enable Gating for low power

0x0048 pmu_status RO 0x0000 PMU Status Register

0x0049 i2c_clock_control_reg RW 0x0000 Control I2C clock

0x004A rev_id RO 0x00a0 Silicon's revision ID register

0x0100 protocol_layer USB PD Protocol Layer

0x0100 sw_prot_rst_stat_ctrl RW 0x0010 USB PD Protocol Layer Reset and Control Register

0x0101 sw_usbpd_prot_pwrswap_reset RW 0x0001 USB PD Protocol Layer Reset and Control Register

0x0102 sw_prot_status_0 RO 0x0000 USB PD Protocol Layer Status Register

0x0103 sw_pd_info_0 RW 0x0013 USB PD Information for Message Transmission

0x0104 sw_pd_info_1 RW 0x0000 USB PD Information for Message Transmission

0x0105 sw_pd_info_2 RW 0x0000 USB PD Information for Message Transmission

0x0106 sw_usbpd_tx_pkt_ctrl_0 RW 0x0000 USB PD Protocol Layer Tx Packet Control Register

0x0107 sw_usbpd_tx_pkt_ctrl_1 RW 0x0000 USB PD Protocol Layer Tx Packet Control Register

0x010B sw_usbpd_tx_pkt_stat RO 0x0000 USB PD Protocol Layer Tx Packet Status Register

0x010C sw_usbpd_rx_pkt_ctrl_0 RW 0x0010 USB PD Protocol Layer Rx Packet Control Register

0x010D sw_usbpd_rx_pkt_ctrl_1 RW 0x0000 USB PD Protocol Layer Rx Packet Control Register

0x010E sw_usbpd_rx_pkt_ctrl_2 RW 0x0001 USB PD Protocol Layer Rx Packet Control Register

0x010F sw_usbpd_pend_rx_msg_global_stat RO 0x0000 USB PD Protocol Layer Pending Rx Message Status

0x0116 sw_bist_ctrl RW 0x0000 USB PD BIST Transmission Control

0x0119 sw_bist_stat_0 RO 0x0000 USB PD Bist Message Status

0x0140 usb_tx_msg_buf USB PD Message Buffer ‐ Tx Buffer

0x0140 usbpd_msg_buf_cfg RW 0x0000 Message Buffer Configuration

0x0180 usb_rx_msg_buf0 USB PD Message Buffer ‐ Rx Buffer 0

0x0181 usbpd_msg_rx_buf0_hdr_0 RO 0x0000 USB PD Message Rx Buffer 0 Header bits [7:0]

0x0182 usbpd_msg_rx_buf0_hdr_1 RO 0x0000 USB PD Message Rx Buffer 0 Header bits [15:8]

0x01C0 usb_rx_msg_buf1 USB PD Message Buffer ‐ Rx Buffer 1

0x01C1 usbpd_msg_rx_buf1_hdr_0 RO 0x0000 USB PD Message Rx Buffer 1 Header bits [7:0]

0x01C2 usbpd_msg_rx_buf1_hdr_1 RO 0x0000 USB PD Message Rx Buffer 1 Header bits [15:8]

0x0200 phy_layer USB PD Digital PHY Layer

0x0240 ps_status_fet_control Power Supply Status and FET Control

0x0240 pwr_supply_stat_0 RO 0x0000 Power Supply Status

0x0241 pwr_supply_stat_1 RO 0x0000 Power Supply Status

0x0280 typec_condet Type‐C Controller

0x0280 control_sm_1 RW 0x0000

0x0281 control_sm_2 RW 0x0015

0x0282 control_sm_3 WO 0x0000

0x0283 control_vconn_comm RW 0x0000

0x0284 control_rd RW 0x0000

0x0285 control_rp RW 0x0000

0x0286 control_vrd RW 0x0000

0x0287 control_vra RW 0x0009

0x0288 status_role RO 0x0000

0x0289 status_cursns RO 0x0000

0x028A status_comp RO 0x0000

0x028B status_state RO 0x0000

0x028C config RW 0x0020

0x028D sw_taccdetect_10_8 RW 0x0000

0x028F sw_tdrpswap_rp_10_8 RW 0x0000

0x0291 sw_tdrpswap_rd_10_8 RW 0x0000

0x0293 sw_tdrphold_10_8 RW 0x0001

0x0295 sw_tdrplock_10_8 RW 0x0001

0x0297 sw_tdrptry_10_8 RW 0x0006

0x0299 sw_terrorrecovery_10_8 RW 0x0000