Unit-3

Q1. Write Verilog HDL code to determine the factorial of any natural
number.

Q2. Write Verilog HDL for JK Flip-flop using Behavioral level architecture and use to implement a 4 bit
counter (should count all the state from 0000 to 1111) with the following constraints: a. all transition
should take place at the positive edge of the clock, b. When reset bit is low, the counter should start from
the state 0000.

Q3. Define 1 bit full adder as task or function, Use it to implement a 4 bit ripple carry adder circuit use
behavioral modeling.

Q4. For the following finite state machine shown in Fig 1, write the Verilog HDL code with the following
constraints: a. All transitions should take place at the positive edge of the clock, b. when reset is low,
system should enter S0 state.

Q5.Write dataflow modeling of given negative edge triggered d flipflop for fig shown below and design T
flipflop using this d flipflop.

fig.2 D flipflop
Q6. (A) Design and write Verilog code for 2:1 multiplexer using bufif0 and bufif1gates as shown below:

The delay specification for gates b1 and b2 are as follows.

Q7. Design and write Verilog code for 8*1 mux using 2*1 mux instantiation use any modeling

Q8. Design and write Verilog code for Sequence detector (non-overlapping) which can detect 1101
pattern, whenever pattern detects output should be high else output should be zero.

Q9.(a) Explain the difference between task and function.

(b) state describe any five Verilog system tasks.

Q10. Design and write Verilog code for 4-bit magnitude comparator A magnitude comparator checks if
one number is greater than or equal to or less than another number. A 4-bit magnitude comparator takes
two 4-bit numbers, A and B, as input. We write the bits in A and B as follows. Leftmost bit is the most
significant bit

A = A[3] A[2] A[1] A[0]

B = B[3] B[2] B[1] B[0]